rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_13 : input clock : Clock input reset : Reset output io : { req : { flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}}, resp : { `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<13> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 11, 11) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_plaInput, 1, 1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput, 2, 2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_plaInput, 3, 3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 11, 11) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_lo = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_2 = orr(_decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_1 = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 1, 0) node _decoded_T_1 = bits(_decoded_T, 0, 0) node _decoded_T_2 = bits(_decoded_T, 1, 1) node _decoded_T_3 = cat(_decoded_T_1, _decoded_T_2) node _decoded_T_4 = bits(decoded_plaOutput, 3, 2) node _decoded_T_5 = bits(_decoded_T_4, 0, 0) node _decoded_T_6 = bits(_decoded_T_4, 1, 1) node _decoded_T_7 = cat(_decoded_T_5, _decoded_T_6) node decoded = cat(_decoded_T_3, _decoded_T_7) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<13> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<4> node _decoded_orMatrixOutputs_T_3 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 3, 3) node decoded_invMatrixOutputs_lo_1 = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_1 = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_8 = bits(decoded_plaOutput_1, 1, 0) node _decoded_T_9 = bits(_decoded_T_8, 0, 0) node _decoded_T_10 = bits(_decoded_T_8, 1, 1) node _decoded_T_11 = cat(_decoded_T_9, _decoded_T_10) node _decoded_T_12 = bits(decoded_plaOutput_1, 3, 2) node _decoded_T_13 = bits(_decoded_T_12, 0, 0) node _decoded_T_14 = bits(_decoded_T_12, 1, 1) node _decoded_T_15 = cat(_decoded_T_13, _decoded_T_14) node decoded_1 = cat(_decoded_T_11, _decoded_T_15) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_31 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_13( // @[RouteComputer.scala:29:7] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_3 // @[RouteComputer.scala:40:14] ); wire [11:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] assign io_resp_0_vc_sel_0_2 = \|{&{decoded_invInputs[0], decoded_invInputs[11]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[0]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_3 = &{decoded_invInputs[0], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_341 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_85 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_341( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_85 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_126 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_140 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_126( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_140 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<4>(0h8)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_141 = shr(io.in.a.bits.source, 2) node _T_142 = eq(_T_141, UInt<4>(0h8)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<4>(0h8)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<27>(0h4000000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<4>(0h8)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<2>(0h2)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<27>(0h4000000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_347 = shr(io.in.a.bits.source, 2) node _T_348 = eq(_T_347, UInt<4>(0h8)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<2>(0h2)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<27>(0h4000000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<4>(0h8)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<2>(0h2)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<27>(0h4000000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<4>(0h8)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<2>(0h2)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_549 = and(_T_547, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<27>(0h4000000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_556) node _T_558 = and(_T_546, _T_557) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_558, UInt<1>(0h1), "") : assert_26 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(source_ok, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(is_aligned, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_568, UInt<1>(0h1), "") : assert_29 node _T_572 = eq(io.in.a.bits.mask, mask) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_572, UInt<1>(0h1), "") : assert_30 node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_576 : node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_35) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<1>(0h1)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_36) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_593 = shr(io.in.a.bits.source, 2) node _T_594 = eq(_T_593, UInt<2>(0h2)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_37) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_598 = and(_T_596, _T_597) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_599 = shr(io.in.a.bits.source, 2) node _T_600 = eq(_T_599, UInt<2>(0h3)) node _T_601 = leq(UInt<1>(0h0), uncommonBits_38) node _T_602 = and(_T_600, _T_601) node _T_603 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_604 = and(_T_602, _T_603) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_605 = shr(io.in.a.bits.source, 2) node _T_606 = eq(_T_605, UInt<4>(0h8)) node _T_607 = leq(UInt<1>(0h0), uncommonBits_39) node _T_608 = and(_T_606, _T_607) node _T_609 = leq(uncommonBits_39, UInt<2>(0h2)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_614 = or(_T_580, _T_586) node _T_615 = or(_T_614, _T_592) node _T_616 = or(_T_615, _T_598) node _T_617 = or(_T_616, _T_604) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_579, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<27>(0h4000000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = and(_T_627, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_635, UInt<1>(0h1), "") : assert_31 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(source_ok, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(is_aligned, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_645, UInt<1>(0h1), "") : assert_34 node _T_649 = not(mask) node _T_650 = and(io.in.a.bits.mask, _T_649) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_651, UInt<1>(0h1), "") : assert_35 node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_655 : node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_40) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h1)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_41) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h2)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_42) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h3)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_43) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_684 = shr(io.in.a.bits.source, 2) node _T_685 = eq(_T_684, UInt<4>(0h8)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_44) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_44, UInt<2>(0h2)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_693 = or(_T_659, _T_665) node _T_694 = or(_T_693, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = and(_T_658, _T_700) node _T_702 = or(UInt<1>(0h0), _T_701) node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_705 = cvt(_T_704) node _T_706 = and(_T_705, asSInt(UInt<27>(0h4000000))) node _T_707 = asSInt(_T_706) node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0))) node _T_709 = and(_T_703, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = and(_T_702, _T_710) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_711, UInt<1>(0h1), "") : assert_36 node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(source_ok, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(is_aligned, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_721, UInt<1>(0h1), "") : assert_39 node _T_725 = eq(io.in.a.bits.mask, mask) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_725, UInt<1>(0h1), "") : assert_40 node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_729 : node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_45) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<1>(0h1)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_46) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<2>(0h2)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_47) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<2>(0h3)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_48) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_757 = and(_T_755, _T_756) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<4>(0h8)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_49) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_49, UInt<2>(0h2)) node _T_763 = and(_T_761, _T_762) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_767 = or(_T_733, _T_739) node _T_768 = or(_T_767, _T_745) node _T_769 = or(_T_768, _T_751) node _T_770 = or(_T_769, _T_757) node _T_771 = or(_T_770, _T_763) node _T_772 = or(_T_771, _T_764) node _T_773 = or(_T_772, _T_765) node _T_774 = or(_T_773, _T_766) node _T_775 = and(_T_732, _T_774) node _T_776 = or(UInt<1>(0h0), _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<27>(0h4000000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_783) node _T_785 = and(_T_776, _T_784) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_785, UInt<1>(0h1), "") : assert_41 node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(source_ok, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(is_aligned, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_795, UInt<1>(0h1), "") : assert_44 node _T_799 = eq(io.in.a.bits.mask, mask) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_799, UInt<1>(0h1), "") : assert_45 node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_803 : node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_806 = and(_T_804, _T_805) node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<1>(0h0)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_50) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<1>(0h1)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_51) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<2>(0h2)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_52) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<2>(0h3)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_53) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<4>(0h8)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_54) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_54, UInt<2>(0h2)) node _T_837 = and(_T_835, _T_836) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_841 = or(_T_807, _T_813) node _T_842 = or(_T_841, _T_819) node _T_843 = or(_T_842, _T_825) node _T_844 = or(_T_843, _T_831) node _T_845 = or(_T_844, _T_837) node _T_846 = or(_T_845, _T_838) node _T_847 = or(_T_846, _T_839) node _T_848 = or(_T_847, _T_840) node _T_849 = and(_T_806, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_852 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_853 = cvt(_T_852) node _T_854 = and(_T_853, asSInt(UInt<27>(0h4000000))) node _T_855 = asSInt(_T_854) node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0))) node _T_857 = and(_T_851, _T_856) node _T_858 = or(UInt<1>(0h0), _T_857) node _T_859 = and(_T_850, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_859, UInt<1>(0h1), "") : assert_46 node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(source_ok, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(is_aligned, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_869, UInt<1>(0h1), "") : assert_49 node _T_873 = eq(io.in.a.bits.mask, mask) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_873, UInt<1>(0h1), "") : assert_50 node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_877, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_881, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 2) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_885 : node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok_1, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_889, UInt<1>(0h1), "") : assert_54 node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_893, UInt<1>(0h1), "") : assert_55 node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_897, UInt<1>(0h1), "") : assert_56 node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_901, UInt<1>(0h1), "") : assert_57 node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_905 : node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok_1, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(sink_ok, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_912, UInt<1>(0h1), "") : assert_60 node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_916, UInt<1>(0h1), "") : assert_61 node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_920, UInt<1>(0h1), "") : assert_62 node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_924, UInt<1>(0h1), "") : assert_63 node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_929 = or(UInt<1>(0h0), _T_928) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_929, UInt<1>(0h1), "") : assert_64 node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_933 : node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(source_ok_1, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(sink_ok, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_940, UInt<1>(0h1), "") : assert_67 node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_944, UInt<1>(0h1), "") : assert_68 node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_948, UInt<1>(0h1), "") : assert_69 node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_953 = or(_T_952, io.in.d.bits.corrupt) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_953, UInt<1>(0h1), "") : assert_70 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = or(UInt<1>(0h0), _T_957) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_958, UInt<1>(0h1), "") : assert_71 node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_962 : node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(source_ok_1, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_966, UInt<1>(0h1), "") : assert_73 node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_970, UInt<1>(0h1), "") : assert_74 node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_975, UInt<1>(0h1), "") : assert_75 node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_979 : node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok_1, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_983, UInt<1>(0h1), "") : assert_77 node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_988 = or(_T_987, io.in.d.bits.corrupt) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_988, UInt<1>(0h1), "") : assert_78 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(UInt<1>(0h0), _T_992) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_993, UInt<1>(0h1), "") : assert_79 node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_997 : node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(source_ok_1, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81 node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82 node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1010 = or(UInt<1>(0h0), _T_1009) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<28>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1026 = eq(a_first, UInt<1>(0h0)) node _T_1027 = and(io.in.a.valid, _T_1026) when _T_1027 : node _T_1028 = eq(io.in.a.bits.opcode, opcode) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87 node _T_1032 = eq(io.in.a.bits.param, param) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88 node _T_1036 = eq(io.in.a.bits.size, size) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89 node _T_1040 = eq(io.in.a.bits.source, source) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90 node _T_1044 = eq(io.in.a.bits.address, address) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91 node _T_1048 = and(io.in.a.ready, io.in.a.valid) node _T_1049 = and(_T_1048, a_first) when _T_1049 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1050 = eq(d_first, UInt<1>(0h0)) node _T_1051 = and(io.in.d.valid, _T_1050) when _T_1051 : node _T_1052 = eq(io.in.d.bits.opcode, opcode_1) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92 node _T_1056 = eq(io.in.d.bits.param, param_1) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93 node _T_1060 = eq(io.in.d.bits.size, size_1) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94 node _T_1064 = eq(io.in.d.bits.source, source_1) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95 node _T_1068 = eq(io.in.d.bits.sink, sink) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96 node _T_1072 = eq(io.in.d.bits.denied, denied) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97 node _T_1076 = and(io.in.d.ready, io.in.d.valid) node _T_1077 = and(_T_1076, d_first) when _T_1077 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1078 = and(io.in.a.valid, a_first_1) node _T_1079 = and(_T_1078, UInt<1>(0h1)) when _T_1079 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1080 = and(io.in.a.ready, io.in.a.valid) node _T_1081 = and(_T_1080, a_first_1) node _T_1082 = and(_T_1081, UInt<1>(0h1)) when _T_1082 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1083 = dshr(inflight, io.in.a.bits.source) node _T_1084 = bits(_T_1083, 0, 0) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(_T_1085, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1089 = and(io.in.d.valid, d_first_1) node _T_1090 = and(_T_1089, UInt<1>(0h1)) node _T_1091 = eq(d_release_ack, UInt<1>(0h0)) node _T_1092 = and(_T_1090, _T_1091) when _T_1092 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1093 = and(io.in.d.ready, io.in.d.valid) node _T_1094 = and(_T_1093, d_first_1) node _T_1095 = and(_T_1094, UInt<1>(0h1)) node _T_1096 = eq(d_release_ack, UInt<1>(0h0)) node _T_1097 = and(_T_1095, _T_1096) when _T_1097 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1098 = and(io.in.d.valid, d_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) node _T_1100 = eq(d_release_ack, UInt<1>(0h0)) node _T_1101 = and(_T_1099, _T_1100) when _T_1101 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1102 = dshr(inflight, io.in.d.bits.source) node _T_1103 = bits(_T_1102, 0, 0) node _T_1104 = or(_T_1103, same_cycle_resp) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1110 = or(_T_1108, _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100 node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101 else : node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1120 = or(_T_1118, _T_1119) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102 node _T_1124 = eq(io.in.d.bits.size, a_size_lookup) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103 node _T_1128 = and(io.in.d.valid, d_first_1) node _T_1129 = and(_T_1128, a_first_1) node _T_1130 = and(_T_1129, io.in.a.valid) node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1132 = and(_T_1130, _T_1131) node _T_1133 = eq(d_release_ack, UInt<1>(0h0)) node _T_1134 = and(_T_1132, _T_1133) when _T_1134 : node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.a.ready) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104 node _T_1140 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1141 = orr(a_set_wo_ready) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) node _T_1143 = or(_T_1140, _T_1142) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_48 node _T_1147 = orr(inflight) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) node _T_1149 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1150 = or(_T_1148, _T_1149) node _T_1151 = lt(watchdog, plusarg_reader.out) node _T_1152 = or(_T_1150, _T_1151) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1156 = and(io.in.a.ready, io.in.a.valid) node _T_1157 = and(io.in.d.ready, io.in.d.valid) node _T_1158 = or(_T_1156, _T_1157) when _T_1158 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1159 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1160 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1161 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = and(_T_1159, _T_1162) when _T_1163 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1164 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1165 = and(_T_1164, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1166 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1167 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = and(_T_1165, _T_1168) when _T_1169 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1170 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1171 = bits(_T_1170, 0, 0) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1176 = and(io.in.d.valid, d_first_2) node _T_1177 = and(_T_1176, UInt<1>(0h1)) node _T_1178 = and(_T_1177, d_release_ack_1) when _T_1178 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1179 = and(io.in.d.ready, io.in.d.valid) node _T_1180 = and(_T_1179, d_first_2) node _T_1181 = and(_T_1180, UInt<1>(0h1)) node _T_1182 = and(_T_1181, d_release_ack_1) when _T_1182 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1183 = and(io.in.d.valid, d_first_2) node _T_1184 = and(_T_1183, UInt<1>(0h1)) node _T_1185 = and(_T_1184, d_release_ack_1) when _T_1185 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1186 = dshr(inflight_1, io.in.d.bits.source) node _T_1187 = bits(_T_1186, 0, 0) node _T_1188 = or(_T_1187, same_cycle_resp_1) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1192 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_109 else : node _T_1196 = eq(io.in.d.bits.size, c_size_lookup) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_110 node _T_1200 = and(io.in.d.valid, d_first_2) node _T_1201 = and(_T_1200, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1202 = and(_T_1201, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1203 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = and(_T_1204, d_release_ack_1) node _T_1206 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : node _T_1208 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<28>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1209 = or(_T_1208, _WIRE_27.ready) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_111 node _T_1213 = orr(c_set_wo_ready) when _T_1213 : node _T_1214 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_49 node _T_1218 = orr(inflight_1) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) node _T_1220 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = lt(watchdog_1, plusarg_reader_1.out) node _T_1223 = or(_T_1221, _T_1222) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<28>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1227 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1228 = and(io.in.d.ready, io.in.d.valid) node _T_1229 = or(_T_1227, _T_1228) when _T_1229 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_24( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1156 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1156; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1156; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1229 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1229; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1229; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1229; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1082 = _T_1156 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1097 = _T_1229 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1200 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1200 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1182 = _T_1229 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1182 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1182 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1182 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_306 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_50 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_306( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_50 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_123 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_124 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_194 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_194( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[12]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of ConstellationSystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst tile_prci_domain_1 of TilePRCIDomain_1 inst tile_prci_domain_2 of TilePRCIDomain_2 inst tile_prci_domain_3 of TilePRCIDomain_3 inst tile_prci_domain_4 of TilePRCIDomain_4 inst tile_prci_domain_5 of TilePRCIDomain_5 inst tile_prci_domain_6 of TilePRCIDomain_6 inst tile_prci_domain_7 of TilePRCIDomain_7 inst tile_prci_domain_8 of TilePRCIDomain_8 inst tile_prci_domain_9 of TilePRCIDomain_9 inst tile_prci_domain_10 of TilePRCIDomain_10 inst tile_prci_domain_11 of TilePRCIDomain_11 inst xbar of IntXbar_i12_o1 inst xbar_1 of IntXbar_i12_o1_1 inst xbar_2 of IntXbar_i12_o1_2 inst tileHartIdNexusNode of BundleBridgeNexus_UInt4_12 inst broadcast of BundleBridgeNexus_UInt32_12 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst nexus_2 of BundleBridgeNexus_TraceBundle_1 inst nexus_3 of BundleBridgeNexus_TraceCoreInterface_1 inst nexus_4 of BundleBridgeNexus_TraceBundle_2 inst nexus_5 of BundleBridgeNexus_TraceCoreInterface_2 inst nexus_6 of BundleBridgeNexus_TraceBundle_3 inst nexus_7 of BundleBridgeNexus_TraceCoreInterface_3 inst nexus_8 of BundleBridgeNexus_TraceBundle_4 inst nexus_9 of BundleBridgeNexus_TraceCoreInterface_4 inst nexus_10 of BundleBridgeNexus_TraceBundle_5 inst nexus_11 of BundleBridgeNexus_TraceCoreInterface_5 inst nexus_12 of BundleBridgeNexus_TraceBundle_6 inst nexus_13 of BundleBridgeNexus_TraceCoreInterface_6 inst nexus_14 of BundleBridgeNexus_TraceBundle_7 inst nexus_15 of BundleBridgeNexus_TraceCoreInterface_7 inst nexus_16 of BundleBridgeNexus_TraceBundle_8 inst nexus_17 of BundleBridgeNexus_TraceCoreInterface_8 inst nexus_18 of BundleBridgeNexus_TraceBundle_9 inst nexus_19 of BundleBridgeNexus_TraceCoreInterface_9 inst nexus_20 of BundleBridgeNexus_TraceBundle_10 inst nexus_21 of BundleBridgeNexus_TraceCoreInterface_10 inst nexus_22 of BundleBridgeNexus_TraceBundle_11 inst nexus_23 of BundleBridgeNexus_TraceCoreInterface_11 inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_60 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_1 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_30 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[12] invalidate tileHaltSinkNodeIn[0] invalidate tileHaltSinkNodeIn[1] invalidate tileHaltSinkNodeIn[2] invalidate tileHaltSinkNodeIn[3] invalidate tileHaltSinkNodeIn[4] invalidate tileHaltSinkNodeIn[5] invalidate tileHaltSinkNodeIn[6] invalidate tileHaltSinkNodeIn[7] invalidate tileHaltSinkNodeIn[8] invalidate tileHaltSinkNodeIn[9] invalidate tileHaltSinkNodeIn[10] invalidate tileHaltSinkNodeIn[11] wire tileWFISinkNodeIn : UInt<1>[12] invalidate tileWFISinkNodeIn[0] invalidate tileWFISinkNodeIn[1] invalidate tileWFISinkNodeIn[2] invalidate tileWFISinkNodeIn[3] invalidate tileWFISinkNodeIn[4] invalidate tileWFISinkNodeIn[5] invalidate tileWFISinkNodeIn[6] invalidate tileWFISinkNodeIn[7] invalidate tileWFISinkNodeIn[8] invalidate tileWFISinkNodeIn[9] invalidate tileWFISinkNodeIn[10] invalidate tileWFISinkNodeIn[11] wire tileCeaseSinkNodeIn : UInt<1>[12] invalidate tileCeaseSinkNodeIn[0] invalidate tileCeaseSinkNodeIn[1] invalidate tileCeaseSinkNodeIn[2] invalidate tileCeaseSinkNodeIn[3] invalidate tileCeaseSinkNodeIn[4] invalidate tileCeaseSinkNodeIn[5] invalidate tileCeaseSinkNodeIn[6] invalidate tileCeaseSinkNodeIn[7] invalidate tileCeaseSinkNodeIn[8] invalidate tileCeaseSinkNodeIn[9] invalidate tileCeaseSinkNodeIn[10] invalidate tileCeaseSinkNodeIn[11] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire debugNodesOut_1 : { sync : UInt<1>[1]} invalidate debugNodesOut_1.sync[0] wire debugNodesIn_1 : { sync : UInt<1>[1]} invalidate debugNodesIn_1.sync[0] connect debugNodesOut_1, debugNodesIn_1 wire debugNodesOut_2 : { sync : UInt<1>[1]} invalidate debugNodesOut_2.sync[0] wire debugNodesIn_2 : { sync : UInt<1>[1]} invalidate debugNodesIn_2.sync[0] connect debugNodesOut_2, debugNodesIn_2 wire debugNodesOut_3 : { sync : UInt<1>[1]} invalidate debugNodesOut_3.sync[0] wire debugNodesIn_3 : { sync : UInt<1>[1]} invalidate debugNodesIn_3.sync[0] connect debugNodesOut_3, debugNodesIn_3 wire debugNodesOut_4 : { sync : UInt<1>[1]} invalidate debugNodesOut_4.sync[0] wire debugNodesIn_4 : { sync : UInt<1>[1]} invalidate debugNodesIn_4.sync[0] connect debugNodesOut_4, debugNodesIn_4 wire debugNodesOut_5 : { sync : UInt<1>[1]} invalidate debugNodesOut_5.sync[0] wire debugNodesIn_5 : { sync : UInt<1>[1]} invalidate debugNodesIn_5.sync[0] connect debugNodesOut_5, debugNodesIn_5 wire debugNodesOut_6 : { sync : UInt<1>[1]} invalidate debugNodesOut_6.sync[0] wire debugNodesIn_6 : { sync : UInt<1>[1]} invalidate debugNodesIn_6.sync[0] connect debugNodesOut_6, debugNodesIn_6 wire debugNodesOut_7 : { sync : UInt<1>[1]} invalidate debugNodesOut_7.sync[0] wire debugNodesIn_7 : { sync : UInt<1>[1]} invalidate debugNodesIn_7.sync[0] connect debugNodesOut_7, debugNodesIn_7 wire debugNodesOut_8 : { sync : UInt<1>[1]} invalidate debugNodesOut_8.sync[0] wire debugNodesIn_8 : { sync : UInt<1>[1]} invalidate debugNodesIn_8.sync[0] connect debugNodesOut_8, debugNodesIn_8 wire debugNodesOut_9 : { sync : UInt<1>[1]} invalidate debugNodesOut_9.sync[0] wire debugNodesIn_9 : { sync : UInt<1>[1]} invalidate debugNodesIn_9.sync[0] connect debugNodesOut_9, debugNodesIn_9 wire debugNodesOut_10 : { sync : UInt<1>[1]} invalidate debugNodesOut_10.sync[0] wire debugNodesIn_10 : { sync : UInt<1>[1]} invalidate debugNodesIn_10.sync[0] connect debugNodesOut_10, debugNodesIn_10 wire debugNodesOut_11 : { sync : UInt<1>[1]} invalidate debugNodesOut_11.sync[0] wire debugNodesIn_11 : { sync : UInt<1>[1]} invalidate debugNodesIn_11.sync[0] connect debugNodesOut_11, debugNodesIn_11 wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceCoreNodesIn_1 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_1.cause invalidate traceCoreNodesIn_1.tval invalidate traceCoreNodesIn_1.priv invalidate traceCoreNodesIn_1.group[0].ilastsize invalidate traceCoreNodesIn_1.group[0].itype invalidate traceCoreNodesIn_1.group[0].iaddr invalidate traceCoreNodesIn_1.group[0].iretire wire traceCoreNodesIn_2 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_2.cause invalidate traceCoreNodesIn_2.tval invalidate traceCoreNodesIn_2.priv invalidate traceCoreNodesIn_2.group[0].ilastsize invalidate traceCoreNodesIn_2.group[0].itype invalidate traceCoreNodesIn_2.group[0].iaddr invalidate traceCoreNodesIn_2.group[0].iretire wire traceCoreNodesIn_3 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_3.cause invalidate traceCoreNodesIn_3.tval invalidate traceCoreNodesIn_3.priv invalidate traceCoreNodesIn_3.group[0].ilastsize invalidate traceCoreNodesIn_3.group[0].itype invalidate traceCoreNodesIn_3.group[0].iaddr invalidate traceCoreNodesIn_3.group[0].iretire wire traceCoreNodesIn_4 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_4.cause invalidate traceCoreNodesIn_4.tval invalidate traceCoreNodesIn_4.priv invalidate traceCoreNodesIn_4.group[0].ilastsize invalidate traceCoreNodesIn_4.group[0].itype invalidate traceCoreNodesIn_4.group[0].iaddr invalidate traceCoreNodesIn_4.group[0].iretire wire traceCoreNodesIn_5 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_5.cause invalidate traceCoreNodesIn_5.tval invalidate traceCoreNodesIn_5.priv invalidate traceCoreNodesIn_5.group[0].ilastsize invalidate traceCoreNodesIn_5.group[0].itype invalidate traceCoreNodesIn_5.group[0].iaddr invalidate traceCoreNodesIn_5.group[0].iretire wire traceCoreNodesIn_6 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_6.cause invalidate traceCoreNodesIn_6.tval invalidate traceCoreNodesIn_6.priv invalidate traceCoreNodesIn_6.group[0].ilastsize invalidate traceCoreNodesIn_6.group[0].itype invalidate traceCoreNodesIn_6.group[0].iaddr invalidate traceCoreNodesIn_6.group[0].iretire wire traceCoreNodesIn_7 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_7.cause invalidate traceCoreNodesIn_7.tval invalidate traceCoreNodesIn_7.priv invalidate traceCoreNodesIn_7.group[0].ilastsize invalidate traceCoreNodesIn_7.group[0].itype invalidate traceCoreNodesIn_7.group[0].iaddr invalidate traceCoreNodesIn_7.group[0].iretire wire traceCoreNodesIn_8 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_8.cause invalidate traceCoreNodesIn_8.tval invalidate traceCoreNodesIn_8.priv invalidate traceCoreNodesIn_8.group[0].ilastsize invalidate traceCoreNodesIn_8.group[0].itype invalidate traceCoreNodesIn_8.group[0].iaddr invalidate traceCoreNodesIn_8.group[0].iretire wire traceCoreNodesIn_9 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_9.cause invalidate traceCoreNodesIn_9.tval invalidate traceCoreNodesIn_9.priv invalidate traceCoreNodesIn_9.group[0].ilastsize invalidate traceCoreNodesIn_9.group[0].itype invalidate traceCoreNodesIn_9.group[0].iaddr invalidate traceCoreNodesIn_9.group[0].iretire wire traceCoreNodesIn_10 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_10.cause invalidate traceCoreNodesIn_10.tval invalidate traceCoreNodesIn_10.priv invalidate traceCoreNodesIn_10.group[0].ilastsize invalidate traceCoreNodesIn_10.group[0].itype invalidate traceCoreNodesIn_10.group[0].iaddr invalidate traceCoreNodesIn_10.group[0].iretire wire traceCoreNodesIn_11 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_11.cause invalidate traceCoreNodesIn_11.tval invalidate traceCoreNodesIn_11.priv invalidate traceCoreNodesIn_11.group[0].ilastsize invalidate traceCoreNodesIn_11.group[0].itype invalidate traceCoreNodesIn_11.group[0].iaddr invalidate traceCoreNodesIn_11.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid wire traceNodesIn_1 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_1.time invalidate traceNodesIn_1.insns[0].tval invalidate traceNodesIn_1.insns[0].cause invalidate traceNodesIn_1.insns[0].interrupt invalidate traceNodesIn_1.insns[0].exception invalidate traceNodesIn_1.insns[0].priv invalidate traceNodesIn_1.insns[0].insn invalidate traceNodesIn_1.insns[0].iaddr invalidate traceNodesIn_1.insns[0].valid wire traceNodesIn_2 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_2.time invalidate traceNodesIn_2.insns[0].tval invalidate traceNodesIn_2.insns[0].cause invalidate traceNodesIn_2.insns[0].interrupt invalidate traceNodesIn_2.insns[0].exception invalidate traceNodesIn_2.insns[0].priv invalidate traceNodesIn_2.insns[0].insn invalidate traceNodesIn_2.insns[0].iaddr invalidate traceNodesIn_2.insns[0].valid wire traceNodesIn_3 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_3.time invalidate traceNodesIn_3.insns[0].tval invalidate traceNodesIn_3.insns[0].cause invalidate traceNodesIn_3.insns[0].interrupt invalidate traceNodesIn_3.insns[0].exception invalidate traceNodesIn_3.insns[0].priv invalidate traceNodesIn_3.insns[0].insn invalidate traceNodesIn_3.insns[0].iaddr invalidate traceNodesIn_3.insns[0].valid wire traceNodesIn_4 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_4.time invalidate traceNodesIn_4.insns[0].tval invalidate traceNodesIn_4.insns[0].cause invalidate traceNodesIn_4.insns[0].interrupt invalidate traceNodesIn_4.insns[0].exception invalidate traceNodesIn_4.insns[0].priv invalidate traceNodesIn_4.insns[0].insn invalidate traceNodesIn_4.insns[0].iaddr invalidate traceNodesIn_4.insns[0].valid wire traceNodesIn_5 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_5.time invalidate traceNodesIn_5.insns[0].tval invalidate traceNodesIn_5.insns[0].cause invalidate traceNodesIn_5.insns[0].interrupt invalidate traceNodesIn_5.insns[0].exception invalidate traceNodesIn_5.insns[0].priv invalidate traceNodesIn_5.insns[0].insn invalidate traceNodesIn_5.insns[0].iaddr invalidate traceNodesIn_5.insns[0].valid wire traceNodesIn_6 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_6.time invalidate traceNodesIn_6.insns[0].tval invalidate traceNodesIn_6.insns[0].cause invalidate traceNodesIn_6.insns[0].interrupt invalidate traceNodesIn_6.insns[0].exception invalidate traceNodesIn_6.insns[0].priv invalidate traceNodesIn_6.insns[0].insn invalidate traceNodesIn_6.insns[0].iaddr invalidate traceNodesIn_6.insns[0].valid wire traceNodesIn_7 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_7.time invalidate traceNodesIn_7.insns[0].tval invalidate traceNodesIn_7.insns[0].cause invalidate traceNodesIn_7.insns[0].interrupt invalidate traceNodesIn_7.insns[0].exception invalidate traceNodesIn_7.insns[0].priv invalidate traceNodesIn_7.insns[0].insn invalidate traceNodesIn_7.insns[0].iaddr invalidate traceNodesIn_7.insns[0].valid wire traceNodesIn_8 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_8.time invalidate traceNodesIn_8.insns[0].tval invalidate traceNodesIn_8.insns[0].cause invalidate traceNodesIn_8.insns[0].interrupt invalidate traceNodesIn_8.insns[0].exception invalidate traceNodesIn_8.insns[0].priv invalidate traceNodesIn_8.insns[0].insn invalidate traceNodesIn_8.insns[0].iaddr invalidate traceNodesIn_8.insns[0].valid wire traceNodesIn_9 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_9.time invalidate traceNodesIn_9.insns[0].tval invalidate traceNodesIn_9.insns[0].cause invalidate traceNodesIn_9.insns[0].interrupt invalidate traceNodesIn_9.insns[0].exception invalidate traceNodesIn_9.insns[0].priv invalidate traceNodesIn_9.insns[0].insn invalidate traceNodesIn_9.insns[0].iaddr invalidate traceNodesIn_9.insns[0].valid wire traceNodesIn_10 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_10.time invalidate traceNodesIn_10.insns[0].tval invalidate traceNodesIn_10.insns[0].cause invalidate traceNodesIn_10.insns[0].interrupt invalidate traceNodesIn_10.insns[0].exception invalidate traceNodesIn_10.insns[0].priv invalidate traceNodesIn_10.insns[0].insn invalidate traceNodesIn_10.insns[0].iaddr invalidate traceNodesIn_10.insns[0].valid wire traceNodesIn_11 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_11.time invalidate traceNodesIn_11.insns[0].tval invalidate traceNodesIn_11.insns[0].cause invalidate traceNodesIn_11.insns[0].interrupt invalidate traceNodesIn_11.insns[0].exception invalidate traceNodesIn_11.insns[0].priv invalidate traceNodesIn_11.insns[0].insn invalidate traceNodesIn_11.insns[0].iaddr invalidate traceNodesIn_11.insns[0].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect tile_prci_domain_1.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_2 connect tile_prci_domain_2.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_3 connect tile_prci_domain_3.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_4 connect tile_prci_domain_4.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_5 connect tile_prci_domain_5.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_6 connect tile_prci_domain_6.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_7 connect tile_prci_domain_7.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_8 connect tile_prci_domain_8.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_9 connect tile_prci_domain_9.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_10 connect tile_prci_domain_10.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_11 connect tile_prci_domain_11.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_12 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_13 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in_0, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_0 connect coh_wrapper.auto.coherent_jbar_anon_in_1, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_1 connect coh_wrapper.auto.coherent_jbar_anon_in_2, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_2 connect coh_wrapper.auto.coherent_jbar_anon_in_3, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_3 connect mbus.auto.bus_xing_in_0, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_0 connect mbus.auto.bus_xing_in_1, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_1 connect mbus.auto.bus_xing_in_2, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_2 connect mbus.auto.bus_xing_in_3, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_3 connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_2.auto.in, tile_prci_domain_1.auto.element_reset_domain_rockettile_trace_source_out connect nexus_3.auto.in, tile_prci_domain_1.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_4.auto.in, tile_prci_domain_2.auto.element_reset_domain_rockettile_trace_source_out connect nexus_5.auto.in, tile_prci_domain_2.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_6.auto.in, tile_prci_domain_3.auto.element_reset_domain_rockettile_trace_source_out connect nexus_7.auto.in, tile_prci_domain_3.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_8.auto.in, tile_prci_domain_4.auto.element_reset_domain_rockettile_trace_source_out connect nexus_9.auto.in, tile_prci_domain_4.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_10.auto.in, tile_prci_domain_5.auto.element_reset_domain_rockettile_trace_source_out connect nexus_11.auto.in, tile_prci_domain_5.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_12.auto.in, tile_prci_domain_6.auto.element_reset_domain_rockettile_trace_source_out connect nexus_13.auto.in, tile_prci_domain_6.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_14.auto.in, tile_prci_domain_7.auto.element_reset_domain_rockettile_trace_source_out connect nexus_15.auto.in, tile_prci_domain_7.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_16.auto.in, tile_prci_domain_8.auto.element_reset_domain_rockettile_trace_source_out connect nexus_17.auto.in, tile_prci_domain_8.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_18.auto.in, tile_prci_domain_9.auto.element_reset_domain_rockettile_trace_source_out connect nexus_19.auto.in, tile_prci_domain_9.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_20.auto.in, tile_prci_domain_10.auto.element_reset_domain_rockettile_trace_source_out connect nexus_21.auto.in, tile_prci_domain_10.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_22.auto.in, tile_prci_domain_11.auto.element_reset_domain_rockettile_trace_source_out connect nexus_23.auto.in, tile_prci_domain_11.auto.element_reset_domain_rockettile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_0 connect tile_prci_domain_1.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_1 connect tile_prci_domain_2.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_2 connect tile_prci_domain_3.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_3 connect tile_prci_domain_4.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_4 connect tile_prci_domain_5.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_5 connect tile_prci_domain_6.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_6 connect tile_prci_domain_7.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_7 connect tile_prci_domain_8.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_8 connect tile_prci_domain_9.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_9 connect tile_prci_domain_10.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_10 connect tile_prci_domain_11.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_11 connect tile_prci_domain.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_0 connect tile_prci_domain_1.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_1 connect tile_prci_domain_2.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_2 connect tile_prci_domain_3.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_3 connect tile_prci_domain_4.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_4 connect tile_prci_domain_5.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_5 connect tile_prci_domain_6.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_6 connect tile_prci_domain_7.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_7 connect tile_prci_domain_8.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_8 connect tile_prci_domain_9.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_9 connect tile_prci_domain_10.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_10 connect tile_prci_domain_11.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_11 connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out_0 connect debugNodesIn_1, tlDM.auto.dmOuter_int_out_1 connect debugNodesIn_2, tlDM.auto.dmOuter_int_out_2 connect debugNodesIn_3, tlDM.auto.dmOuter_int_out_3 connect debugNodesIn_4, tlDM.auto.dmOuter_int_out_4 connect debugNodesIn_5, tlDM.auto.dmOuter_int_out_5 connect debugNodesIn_6, tlDM.auto.dmOuter_int_out_6 connect debugNodesIn_7, tlDM.auto.dmOuter_int_out_7 connect debugNodesIn_8, tlDM.auto.dmOuter_int_out_8 connect debugNodesIn_9, tlDM.auto.dmOuter_int_out_9 connect debugNodesIn_10, tlDM.auto.dmOuter_int_out_10 connect debugNodesIn_11, tlDM.auto.dmOuter_int_out_11 connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect tile_prci_domain_1.auto.intsink_in.sync[0], debugNodesOut_1.sync[0] connect tile_prci_domain_2.auto.intsink_in.sync[0], debugNodesOut_2.sync[0] connect tile_prci_domain_3.auto.intsink_in.sync[0], debugNodesOut_3.sync[0] connect tile_prci_domain_4.auto.intsink_in.sync[0], debugNodesOut_4.sync[0] connect tile_prci_domain_5.auto.intsink_in.sync[0], debugNodesOut_5.sync[0] connect tile_prci_domain_6.auto.intsink_in.sync[0], debugNodesOut_6.sync[0] connect tile_prci_domain_7.auto.intsink_in.sync[0], debugNodesOut_7.sync[0] connect tile_prci_domain_8.auto.intsink_in.sync[0], debugNodesOut_8.sync[0] connect tile_prci_domain_9.auto.intsink_in.sync[0], debugNodesOut_9.sync[0] connect tile_prci_domain_10.auto.intsink_in.sync[0], debugNodesOut_10.sync[0] connect tile_prci_domain_11.auto.intsink_in.sync[0], debugNodesOut_11.sync[0] connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_0, tile_prci_domain.auto.tl_master_clock_xing_out connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_0.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in_0[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_0[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_0[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_1, tile_prci_domain_1.auto.tl_master_clock_xing_out connect tile_prci_domain_1.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_1.sync[0] connect tile_prci_domain_1.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_1.sync[1] connect tile_prci_domain_1.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_2.sync[0] connect tile_prci_domain_1.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_3.sync[0] connect xbar.auto.anon_in_1[0], tile_prci_domain_1.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_1[0], tile_prci_domain_1.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_1[0], tile_prci_domain_1.auto.intsink_out_2[0] connect traceNodesIn_1, nexus_2.auto.out connect traceCoreNodesIn_1, nexus_3.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_2, tile_prci_domain_2.auto.tl_master_clock_xing_out connect tile_prci_domain_2.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_2.sync[0] connect tile_prci_domain_2.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_2.sync[1] connect tile_prci_domain_2.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_4.sync[0] connect tile_prci_domain_2.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_5.sync[0] connect xbar.auto.anon_in_2[0], tile_prci_domain_2.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_2[0], tile_prci_domain_2.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_2[0], tile_prci_domain_2.auto.intsink_out_2[0] connect traceNodesIn_2, nexus_4.auto.out connect traceCoreNodesIn_2, nexus_5.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_3, tile_prci_domain_3.auto.tl_master_clock_xing_out connect tile_prci_domain_3.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_3.sync[0] connect tile_prci_domain_3.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_3.sync[1] connect tile_prci_domain_3.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_6.sync[0] connect tile_prci_domain_3.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_7.sync[0] connect xbar.auto.anon_in_3[0], tile_prci_domain_3.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_3[0], tile_prci_domain_3.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_3[0], tile_prci_domain_3.auto.intsink_out_2[0] connect traceNodesIn_3, nexus_6.auto.out connect traceCoreNodesIn_3, nexus_7.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_4, tile_prci_domain_4.auto.tl_master_clock_xing_out connect tile_prci_domain_4.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_4.sync[0] connect tile_prci_domain_4.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_4.sync[1] connect tile_prci_domain_4.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_8.sync[0] connect tile_prci_domain_4.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_9.sync[0] connect xbar.auto.anon_in_4[0], tile_prci_domain_4.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_4[0], tile_prci_domain_4.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_4[0], tile_prci_domain_4.auto.intsink_out_2[0] connect traceNodesIn_4, nexus_8.auto.out connect traceCoreNodesIn_4, nexus_9.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_5, tile_prci_domain_5.auto.tl_master_clock_xing_out connect tile_prci_domain_5.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_5.sync[0] connect tile_prci_domain_5.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_5.sync[1] connect tile_prci_domain_5.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_10.sync[0] connect tile_prci_domain_5.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_11.sync[0] connect xbar.auto.anon_in_5[0], tile_prci_domain_5.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_5[0], tile_prci_domain_5.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_5[0], tile_prci_domain_5.auto.intsink_out_2[0] connect traceNodesIn_5, nexus_10.auto.out connect traceCoreNodesIn_5, nexus_11.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_6, tile_prci_domain_6.auto.tl_master_clock_xing_out connect tile_prci_domain_6.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_6.sync[0] connect tile_prci_domain_6.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_6.sync[1] connect tile_prci_domain_6.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_12.sync[0] connect tile_prci_domain_6.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_13.sync[0] connect xbar.auto.anon_in_6[0], tile_prci_domain_6.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_6[0], tile_prci_domain_6.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_6[0], tile_prci_domain_6.auto.intsink_out_2[0] connect traceNodesIn_6, nexus_12.auto.out connect traceCoreNodesIn_6, nexus_13.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_7, tile_prci_domain_7.auto.tl_master_clock_xing_out connect tile_prci_domain_7.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_7.sync[0] connect tile_prci_domain_7.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_7.sync[1] connect tile_prci_domain_7.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_14.sync[0] connect tile_prci_domain_7.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_15.sync[0] connect xbar.auto.anon_in_7[0], tile_prci_domain_7.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_7[0], tile_prci_domain_7.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_7[0], tile_prci_domain_7.auto.intsink_out_2[0] connect traceNodesIn_7, nexus_14.auto.out connect traceCoreNodesIn_7, nexus_15.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_8, tile_prci_domain_8.auto.tl_master_clock_xing_out connect tile_prci_domain_8.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_8.sync[0] connect tile_prci_domain_8.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_8.sync[1] connect tile_prci_domain_8.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_16.sync[0] connect tile_prci_domain_8.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_17.sync[0] connect xbar.auto.anon_in_8[0], tile_prci_domain_8.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_8[0], tile_prci_domain_8.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_8[0], tile_prci_domain_8.auto.intsink_out_2[0] connect traceNodesIn_8, nexus_16.auto.out connect traceCoreNodesIn_8, nexus_17.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_9, tile_prci_domain_9.auto.tl_master_clock_xing_out connect tile_prci_domain_9.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_9.sync[0] connect tile_prci_domain_9.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_9.sync[1] connect tile_prci_domain_9.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_18.sync[0] connect tile_prci_domain_9.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_19.sync[0] connect xbar.auto.anon_in_9[0], tile_prci_domain_9.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_9[0], tile_prci_domain_9.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_9[0], tile_prci_domain_9.auto.intsink_out_2[0] connect traceNodesIn_9, nexus_18.auto.out connect traceCoreNodesIn_9, nexus_19.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_10, tile_prci_domain_10.auto.tl_master_clock_xing_out connect tile_prci_domain_10.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_10.sync[0] connect tile_prci_domain_10.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_10.sync[1] connect tile_prci_domain_10.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_20.sync[0] connect tile_prci_domain_10.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_21.sync[0] connect xbar.auto.anon_in_10[0], tile_prci_domain_10.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_10[0], tile_prci_domain_10.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_10[0], tile_prci_domain_10.auto.intsink_out_2[0] connect traceNodesIn_10, nexus_20.auto.out connect traceCoreNodesIn_10, nexus_21.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_11, tile_prci_domain_11.auto.tl_master_clock_xing_out connect tile_prci_domain_11.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_11.sync[0] connect tile_prci_domain_11.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_11.sync[1] connect tile_prci_domain_11.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_22.sync[0] connect tile_prci_domain_11.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_23.sync[0] connect xbar.auto.anon_in_11[0], tile_prci_domain_11.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_11[0], tile_prci_domain_11.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_11[0], tile_prci_domain_11.auto.intsink_out_2[0] connect traceNodesIn_11, nexus_22.auto.out connect traceCoreNodesIn_11, nexus_23.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.hartIsInReset[1], resetctrl.hartIsInReset[1] connect tlDM.io.hartIsInReset[2], resetctrl.hartIsInReset[2] connect tlDM.io.hartIsInReset[3], resetctrl.hartIsInReset[3] connect tlDM.io.hartIsInReset[4], resetctrl.hartIsInReset[4] connect tlDM.io.hartIsInReset[5], resetctrl.hartIsInReset[5] connect tlDM.io.hartIsInReset[6], resetctrl.hartIsInReset[6] connect tlDM.io.hartIsInReset[7], resetctrl.hartIsInReset[7] connect tlDM.io.hartIsInReset[8], resetctrl.hartIsInReset[8] connect tlDM.io.hartIsInReset[9], resetctrl.hartIsInReset[9] connect tlDM.io.hartIsInReset[10], resetctrl.hartIsInReset[10] connect tlDM.io.hartIsInReset[11], resetctrl.hartIsInReset[11] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[1], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[2], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[3], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[4], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[5], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[6], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[7], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[8], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[9], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[10], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[11], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell	module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_1, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_2, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_3, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_4, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_5, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_6, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_7, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_8, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_9, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_10, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_11, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [7:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _intsink_auto_out_0; // @[Crossing.scala:109:29] wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [11:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [6:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [11:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_11_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_10_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_9_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_8_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_7_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_6_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_5_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_4_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_3_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_2_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_1_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_0_sync_0; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_23_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_22_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_21_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_20_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_19_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_18_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_17_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_16_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_15_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_14_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_13_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_12_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_11_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_10_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_9_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_8_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_7_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_6_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_5_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_4_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_3_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_2_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_11_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_11_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_10_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_10_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_9_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_9_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_8_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_8_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_7_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_7_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_6_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_6_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_5_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_5_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_4_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_4_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_3_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_3_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_2_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_2_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_1_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_0_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire [3:0] _tileHartIdNexusNode_auto_out_11; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_10; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_9; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_8; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_7; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_6; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_5; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_4; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_3; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_2; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_1; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_0; // @[HasTiles.scala:75:39] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [11:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [6:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_3_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_3_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_3_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_3_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_3_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_2_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_2_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_2_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_2_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_2_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_1_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_1_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_1_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_1_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_1_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_0_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_0_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_0_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_0_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_0_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [5:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [5:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size; // @[LazyScope.scala:98:27] wire [4:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address; // @[LazyScope.scala:98:27] wire [15:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [127:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[LazyScope.scala:98:27] wire [4:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[LazyScope.scala:98:27] wire [5:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [127:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[LazyScope.scala:98:27] wire [28:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[LazyScope.scala:98:27] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_e_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_2_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_2_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_2_flit_bits_tail; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_ingress_width_widget_in_2_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_ingress_width_widget_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_ingress_width_widget_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_d_ready; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_5; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_6; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_5; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_6; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_3_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_3_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_3_flit_bits_tail; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_4_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_3_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_2_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_fixedClockNode_auto_anon_out_13_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_13_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_12_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_12_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_11_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_11_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_10_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_10_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_9_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_9_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_8_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_8_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_7_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_7_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_6_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_6_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_5_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_5_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_4_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_4_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_3_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_3_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_2_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_2_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27] reg [63:0] sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr; // @[NoC.scala:163:37] reg [63:0] sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:164:37] wire [63:0] sbus_system_bus_noc_acd_noc_noc_debug_any_stall_ctr = sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr + sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50] reg [63:0] sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr; // @[NoC.scala:163:37] reg [63:0] sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:164:37] wire [63:0] sbus_system_bus_noc_be_noc_noc_debug_any_stall_ctr = sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr + sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] always @(posedge _sbus_fixedClockNode_auto_anon_out_0_clock) begin // @[ClockGroup.scala:115:114] if (_sbus_fixedClockNode_auto_anon_out_0_reset) begin // @[ClockGroup.scala:115:114] sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37] sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37] sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37] sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37] end else begin // @[ClockGroup.scala:115:114] sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr <= sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr + {62'h0, _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_5 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_6 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_2}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}] sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr <= sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr + {62'h0, _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_5 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_6 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_2}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}] sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr <= sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr + {63'h0, _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}] sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr <= sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr + {63'h0, _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}] end always @(posedge) always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module ScalePipe : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}, out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}} wire out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}} connect out.bits.index, io.in.bits.index connect out.bits.id, io.in.bits.id connect out.bits.scale.bits, io.in.bits.scale.bits connect out.bits.data, io.in.bits.data connect out.valid, io.in.valid wire _out_bits_data_WIRE : { bits : UInt<32>} wire _out_bits_data_WIRE_1 : UInt<32> connect _out_bits_data_WIRE_1, io.in.bits.scale.bits node _out_bits_data_T = bits(_out_bits_data_WIRE_1, 31, 0) connect _out_bits_data_WIRE.bits, _out_bits_data_T node out_bits_data_f_rec_rawIn_sign = bits(_out_bits_data_WIRE.bits, 31, 31) node out_bits_data_f_rec_rawIn_expIn = bits(_out_bits_data_WIRE.bits, 30, 23) node out_bits_data_f_rec_rawIn_fractIn = bits(_out_bits_data_WIRE.bits, 22, 0) node out_bits_data_f_rec_rawIn_isZeroExpIn = eq(out_bits_data_f_rec_rawIn_expIn, UInt<1>(0h0)) node out_bits_data_f_rec_rawIn_isZeroFractIn = eq(out_bits_data_f_rec_rawIn_fractIn, UInt<1>(0h0)) node _out_bits_data_f_rec_rawIn_normDist_T = bits(out_bits_data_f_rec_rawIn_fractIn, 0, 0) node _out_bits_data_f_rec_rawIn_normDist_T_1 = bits(out_bits_data_f_rec_rawIn_fractIn, 1, 1) node _out_bits_data_f_rec_rawIn_normDist_T_2 = bits(out_bits_data_f_rec_rawIn_fractIn, 2, 2) node _out_bits_data_f_rec_rawIn_normDist_T_3 = bits(out_bits_data_f_rec_rawIn_fractIn, 3, 3) node _out_bits_data_f_rec_rawIn_normDist_T_4 = bits(out_bits_data_f_rec_rawIn_fractIn, 4, 4) node _out_bits_data_f_rec_rawIn_normDist_T_5 = bits(out_bits_data_f_rec_rawIn_fractIn, 5, 5) node _out_bits_data_f_rec_rawIn_normDist_T_6 = bits(out_bits_data_f_rec_rawIn_fractIn, 6, 6) node _out_bits_data_f_rec_rawIn_normDist_T_7 = bits(out_bits_data_f_rec_rawIn_fractIn, 7, 7) node _out_bits_data_f_rec_rawIn_normDist_T_8 = bits(out_bits_data_f_rec_rawIn_fractIn, 8, 8) node _out_bits_data_f_rec_rawIn_normDist_T_9 = bits(out_bits_data_f_rec_rawIn_fractIn, 9, 9) node _out_bits_data_f_rec_rawIn_normDist_T_10 = bits(out_bits_data_f_rec_rawIn_fractIn, 10, 10) node _out_bits_data_f_rec_rawIn_normDist_T_11 = bits(out_bits_data_f_rec_rawIn_fractIn, 11, 11) node _out_bits_data_f_rec_rawIn_normDist_T_12 = bits(out_bits_data_f_rec_rawIn_fractIn, 12, 12) node _out_bits_data_f_rec_rawIn_normDist_T_13 = bits(out_bits_data_f_rec_rawIn_fractIn, 13, 13) node _out_bits_data_f_rec_rawIn_normDist_T_14 = bits(out_bits_data_f_rec_rawIn_fractIn, 14, 14) node _out_bits_data_f_rec_rawIn_normDist_T_15 = bits(out_bits_data_f_rec_rawIn_fractIn, 15, 15) node _out_bits_data_f_rec_rawIn_normDist_T_16 = bits(out_bits_data_f_rec_rawIn_fractIn, 16, 16) node _out_bits_data_f_rec_rawIn_normDist_T_17 = bits(out_bits_data_f_rec_rawIn_fractIn, 17, 17) node _out_bits_data_f_rec_rawIn_normDist_T_18 = bits(out_bits_data_f_rec_rawIn_fractIn, 18, 18) node _out_bits_data_f_rec_rawIn_normDist_T_19 = bits(out_bits_data_f_rec_rawIn_fractIn, 19, 19) node _out_bits_data_f_rec_rawIn_normDist_T_20 = bits(out_bits_data_f_rec_rawIn_fractIn, 20, 20) node _out_bits_data_f_rec_rawIn_normDist_T_21 = bits(out_bits_data_f_rec_rawIn_fractIn, 21, 21) node _out_bits_data_f_rec_rawIn_normDist_T_22 = bits(out_bits_data_f_rec_rawIn_fractIn, 22, 22) node _out_bits_data_f_rec_rawIn_normDist_T_23 = mux(_out_bits_data_f_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _out_bits_data_f_rec_rawIn_normDist_T_24 = mux(_out_bits_data_f_rec_rawIn_normDist_T_2, UInt<5>(0h14), _out_bits_data_f_rec_rawIn_normDist_T_23) node _out_bits_data_f_rec_rawIn_normDist_T_25 = mux(_out_bits_data_f_rec_rawIn_normDist_T_3, UInt<5>(0h13), _out_bits_data_f_rec_rawIn_normDist_T_24) node _out_bits_data_f_rec_rawIn_normDist_T_26 = mux(_out_bits_data_f_rec_rawIn_normDist_T_4, UInt<5>(0h12), _out_bits_data_f_rec_rawIn_normDist_T_25) node _out_bits_data_f_rec_rawIn_normDist_T_27 = mux(_out_bits_data_f_rec_rawIn_normDist_T_5, UInt<5>(0h11), _out_bits_data_f_rec_rawIn_normDist_T_26) node _out_bits_data_f_rec_rawIn_normDist_T_28 = mux(_out_bits_data_f_rec_rawIn_normDist_T_6, UInt<5>(0h10), _out_bits_data_f_rec_rawIn_normDist_T_27) node _out_bits_data_f_rec_rawIn_normDist_T_29 = mux(_out_bits_data_f_rec_rawIn_normDist_T_7, UInt<4>(0hf), _out_bits_data_f_rec_rawIn_normDist_T_28) node _out_bits_data_f_rec_rawIn_normDist_T_30 = mux(_out_bits_data_f_rec_rawIn_normDist_T_8, UInt<4>(0he), _out_bits_data_f_rec_rawIn_normDist_T_29) node _out_bits_data_f_rec_rawIn_normDist_T_31 = mux(_out_bits_data_f_rec_rawIn_normDist_T_9, UInt<4>(0hd), _out_bits_data_f_rec_rawIn_normDist_T_30) node _out_bits_data_f_rec_rawIn_normDist_T_32 = mux(_out_bits_data_f_rec_rawIn_normDist_T_10, UInt<4>(0hc), _out_bits_data_f_rec_rawIn_normDist_T_31) node _out_bits_data_f_rec_rawIn_normDist_T_33 = mux(_out_bits_data_f_rec_rawIn_normDist_T_11, UInt<4>(0hb), _out_bits_data_f_rec_rawIn_normDist_T_32) node _out_bits_data_f_rec_rawIn_normDist_T_34 = mux(_out_bits_data_f_rec_rawIn_normDist_T_12, UInt<4>(0ha), _out_bits_data_f_rec_rawIn_normDist_T_33) node _out_bits_data_f_rec_rawIn_normDist_T_35 = mux(_out_bits_data_f_rec_rawIn_normDist_T_13, UInt<4>(0h9), _out_bits_data_f_rec_rawIn_normDist_T_34) node _out_bits_data_f_rec_rawIn_normDist_T_36 = mux(_out_bits_data_f_rec_rawIn_normDist_T_14, UInt<4>(0h8), _out_bits_data_f_rec_rawIn_normDist_T_35) node _out_bits_data_f_rec_rawIn_normDist_T_37 = mux(_out_bits_data_f_rec_rawIn_normDist_T_15, UInt<3>(0h7), _out_bits_data_f_rec_rawIn_normDist_T_36) node _out_bits_data_f_rec_rawIn_normDist_T_38 = mux(_out_bits_data_f_rec_rawIn_normDist_T_16, UInt<3>(0h6), _out_bits_data_f_rec_rawIn_normDist_T_37) node _out_bits_data_f_rec_rawIn_normDist_T_39 = mux(_out_bits_data_f_rec_rawIn_normDist_T_17, UInt<3>(0h5), _out_bits_data_f_rec_rawIn_normDist_T_38) node _out_bits_data_f_rec_rawIn_normDist_T_40 = mux(_out_bits_data_f_rec_rawIn_normDist_T_18, UInt<3>(0h4), _out_bits_data_f_rec_rawIn_normDist_T_39) node _out_bits_data_f_rec_rawIn_normDist_T_41 = mux(_out_bits_data_f_rec_rawIn_normDist_T_19, UInt<2>(0h3), _out_bits_data_f_rec_rawIn_normDist_T_40) node _out_bits_data_f_rec_rawIn_normDist_T_42 = mux(_out_bits_data_f_rec_rawIn_normDist_T_20, UInt<2>(0h2), _out_bits_data_f_rec_rawIn_normDist_T_41) node _out_bits_data_f_rec_rawIn_normDist_T_43 = mux(_out_bits_data_f_rec_rawIn_normDist_T_21, UInt<1>(0h1), _out_bits_data_f_rec_rawIn_normDist_T_42) node out_bits_data_f_rec_rawIn_normDist = mux(_out_bits_data_f_rec_rawIn_normDist_T_22, UInt<1>(0h0), _out_bits_data_f_rec_rawIn_normDist_T_43) node _out_bits_data_f_rec_rawIn_subnormFract_T = dshl(out_bits_data_f_rec_rawIn_fractIn, out_bits_data_f_rec_rawIn_normDist) node _out_bits_data_f_rec_rawIn_subnormFract_T_1 = bits(_out_bits_data_f_rec_rawIn_subnormFract_T, 21, 0) node out_bits_data_f_rec_rawIn_subnormFract = shl(_out_bits_data_f_rec_rawIn_subnormFract_T_1, 1) node _out_bits_data_f_rec_rawIn_adjustedExp_T = xor(out_bits_data_f_rec_rawIn_normDist, UInt<9>(0h1ff)) node _out_bits_data_f_rec_rawIn_adjustedExp_T_1 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, _out_bits_data_f_rec_rawIn_adjustedExp_T, out_bits_data_f_rec_rawIn_expIn) node _out_bits_data_f_rec_rawIn_adjustedExp_T_2 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _out_bits_data_f_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _out_bits_data_f_rec_rawIn_adjustedExp_T_2) node _out_bits_data_f_rec_rawIn_adjustedExp_T_4 = add(_out_bits_data_f_rec_rawIn_adjustedExp_T_1, _out_bits_data_f_rec_rawIn_adjustedExp_T_3) node out_bits_data_f_rec_rawIn_adjustedExp = tail(_out_bits_data_f_rec_rawIn_adjustedExp_T_4, 1) node out_bits_data_f_rec_rawIn_isZero = and(out_bits_data_f_rec_rawIn_isZeroExpIn, out_bits_data_f_rec_rawIn_isZeroFractIn) node _out_bits_data_f_rec_rawIn_isSpecial_T = bits(out_bits_data_f_rec_rawIn_adjustedExp, 8, 7) node out_bits_data_f_rec_rawIn_isSpecial = eq(_out_bits_data_f_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire out_bits_data_f_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_data_f_rec_rawIn_out_isNaN_T = eq(out_bits_data_f_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _out_bits_data_f_rec_rawIn_out_isNaN_T_1 = and(out_bits_data_f_rec_rawIn_isSpecial, _out_bits_data_f_rec_rawIn_out_isNaN_T) connect out_bits_data_f_rec_rawIn.isNaN, _out_bits_data_f_rec_rawIn_out_isNaN_T_1 node _out_bits_data_f_rec_rawIn_out_isInf_T = and(out_bits_data_f_rec_rawIn_isSpecial, out_bits_data_f_rec_rawIn_isZeroFractIn) connect out_bits_data_f_rec_rawIn.isInf, _out_bits_data_f_rec_rawIn_out_isInf_T connect out_bits_data_f_rec_rawIn.isZero, out_bits_data_f_rec_rawIn_isZero connect out_bits_data_f_rec_rawIn.sign, out_bits_data_f_rec_rawIn_sign node _out_bits_data_f_rec_rawIn_out_sExp_T = bits(out_bits_data_f_rec_rawIn_adjustedExp, 8, 0) node _out_bits_data_f_rec_rawIn_out_sExp_T_1 = cvt(_out_bits_data_f_rec_rawIn_out_sExp_T) connect out_bits_data_f_rec_rawIn.sExp, _out_bits_data_f_rec_rawIn_out_sExp_T_1 node _out_bits_data_f_rec_rawIn_out_sig_T = eq(out_bits_data_f_rec_rawIn_isZero, UInt<1>(0h0)) node _out_bits_data_f_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_data_f_rec_rawIn_out_sig_T) node _out_bits_data_f_rec_rawIn_out_sig_T_2 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, out_bits_data_f_rec_rawIn_subnormFract, out_bits_data_f_rec_rawIn_fractIn) node _out_bits_data_f_rec_rawIn_out_sig_T_3 = cat(_out_bits_data_f_rec_rawIn_out_sig_T_1, _out_bits_data_f_rec_rawIn_out_sig_T_2) connect out_bits_data_f_rec_rawIn.sig, _out_bits_data_f_rec_rawIn_out_sig_T_3 node _out_bits_data_f_rec_T = bits(out_bits_data_f_rec_rawIn.sExp, 8, 6) node _out_bits_data_f_rec_T_1 = mux(out_bits_data_f_rec_rawIn.isZero, UInt<3>(0h0), _out_bits_data_f_rec_T) node _out_bits_data_f_rec_T_2 = mux(out_bits_data_f_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _out_bits_data_f_rec_T_3 = or(_out_bits_data_f_rec_T_1, _out_bits_data_f_rec_T_2) node _out_bits_data_f_rec_T_4 = cat(out_bits_data_f_rec_rawIn.sign, _out_bits_data_f_rec_T_3) node _out_bits_data_f_rec_T_5 = bits(out_bits_data_f_rec_rawIn.sExp, 5, 0) node _out_bits_data_f_rec_T_6 = cat(_out_bits_data_f_rec_T_4, _out_bits_data_f_rec_T_5) node _out_bits_data_f_rec_T_7 = bits(out_bits_data_f_rec_rawIn.sig, 22, 0) node out_bits_data_f_rec = cat(_out_bits_data_f_rec_T_6, _out_bits_data_f_rec_T_7) inst out_bits_data_in_to_rec_fn of INToRecFN_i8_e8_s24 connect out_bits_data_in_to_rec_fn.io.signedIn, UInt<1>(0h1) wire _out_bits_data_in_to_rec_fn_io_in_WIRE : UInt<8> node _out_bits_data_in_to_rec_fn_io_in_T = asUInt(io.in.bits.data) connect _out_bits_data_in_to_rec_fn_io_in_WIRE, _out_bits_data_in_to_rec_fn_io_in_T connect out_bits_data_in_to_rec_fn.io.in, _out_bits_data_in_to_rec_fn_io_in_WIRE connect out_bits_data_in_to_rec_fn.io.roundingMode, UInt<3>(0h0) connect out_bits_data_in_to_rec_fn.io.detectTininess, UInt<1>(0h1) inst out_bits_data_muladder of MulAddRecFN_e8_s24 connect out_bits_data_muladder.io.op, UInt<1>(0h0) connect out_bits_data_muladder.io.roundingMode, UInt<3>(0h0) connect out_bits_data_muladder.io.detectTininess, UInt<1>(0h1) connect out_bits_data_muladder.io.a, out_bits_data_in_to_rec_fn.io.out connect out_bits_data_muladder.io.b, out_bits_data_f_rec connect out_bits_data_muladder.io.c, UInt<1>(0h0) inst out_bits_data_rec_fn_to_in of RecFNToIN_e8_s24_i8 connect out_bits_data_rec_fn_to_in.clock, clock connect out_bits_data_rec_fn_to_in.reset, reset connect out_bits_data_rec_fn_to_in.io.in, out_bits_data_muladder.io.out connect out_bits_data_rec_fn_to_in.io.roundingMode, UInt<3>(0h0) connect out_bits_data_rec_fn_to_in.io.signedOut, UInt<1>(0h1) node out_bits_data_overflow = bits(out_bits_data_rec_fn_to_in.io.intExceptionFlags, 1, 1) node out_bits_data_sign_exp = bits(out_bits_data_rec_fn_to_in.io.in, 31, 23) node _out_bits_data_sign_isZero_T = bits(out_bits_data_sign_exp, 8, 6) node out_bits_data_sign_isZero = eq(_out_bits_data_sign_isZero_T, UInt<1>(0h0)) node _out_bits_data_sign_isSpecial_T = bits(out_bits_data_sign_exp, 8, 7) node out_bits_data_sign_isSpecial = eq(_out_bits_data_sign_isSpecial_T, UInt<2>(0h3)) wire out_bits_data_sign_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_data_sign_out_isNaN_T = bits(out_bits_data_sign_exp, 6, 6) node _out_bits_data_sign_out_isNaN_T_1 = and(out_bits_data_sign_isSpecial, _out_bits_data_sign_out_isNaN_T) connect out_bits_data_sign_out.isNaN, _out_bits_data_sign_out_isNaN_T_1 node _out_bits_data_sign_out_isInf_T = bits(out_bits_data_sign_exp, 6, 6) node _out_bits_data_sign_out_isInf_T_1 = eq(_out_bits_data_sign_out_isInf_T, UInt<1>(0h0)) node _out_bits_data_sign_out_isInf_T_2 = and(out_bits_data_sign_isSpecial, _out_bits_data_sign_out_isInf_T_1) connect out_bits_data_sign_out.isInf, _out_bits_data_sign_out_isInf_T_2 connect out_bits_data_sign_out.isZero, out_bits_data_sign_isZero node _out_bits_data_sign_out_sign_T = bits(out_bits_data_rec_fn_to_in.io.in, 32, 32) connect out_bits_data_sign_out.sign, _out_bits_data_sign_out_sign_T node _out_bits_data_sign_out_sExp_T = cvt(out_bits_data_sign_exp) connect out_bits_data_sign_out.sExp, _out_bits_data_sign_out_sExp_T node _out_bits_data_sign_out_sig_T = eq(out_bits_data_sign_isZero, UInt<1>(0h0)) node _out_bits_data_sign_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_data_sign_out_sig_T) node _out_bits_data_sign_out_sig_T_2 = bits(out_bits_data_rec_fn_to_in.io.in, 22, 0) node _out_bits_data_sign_out_sig_T_3 = cat(_out_bits_data_sign_out_sig_T_1, _out_bits_data_sign_out_sig_T_2) connect out_bits_data_sign_out.sig, _out_bits_data_sign_out_sig_T_3 node out_bits_data_sat = mux(out_bits_data_sign_out.sign, asSInt(UInt<8>(0h80)), asSInt(UInt<8>(0h7f))) wire _out_bits_data_WIRE_2 : SInt<8> node _out_bits_data_T_1 = asSInt(out_bits_data_rec_fn_to_in.io.out) connect _out_bits_data_WIRE_2, _out_bits_data_T_1 node _out_bits_data_T_2 = mux(out_bits_data_overflow, out_bits_data_sat, _out_bits_data_WIRE_2) connect out.bits.data, _out_bits_data_T_2 regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_v, out.valid reg io_out_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when out.valid : connect io_out_pipe_b, out.bits regreset io_out_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_pipe_v, io_out_pipe_v reg io_out_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when io_out_pipe_v : connect io_out_pipe_pipe_b, io_out_pipe_b regreset io_out_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_pipe_pipe_v, io_out_pipe_pipe_v reg io_out_pipe_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when io_out_pipe_pipe_v : connect io_out_pipe_pipe_pipe_b, io_out_pipe_pipe_b regreset io_out_pipe_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_pipe_pipe_pipe_v, io_out_pipe_pipe_pipe_v reg io_out_pipe_pipe_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when io_out_pipe_pipe_pipe_v : connect io_out_pipe_pipe_pipe_pipe_b, io_out_pipe_pipe_pipe_b wire io_out_pipe_pipe_pipe_pipe_out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}} connect io_out_pipe_pipe_pipe_pipe_out.valid, io_out_pipe_pipe_pipe_pipe_v connect io_out_pipe_pipe_pipe_pipe_out.bits, io_out_pipe_pipe_pipe_pipe_b connect io.out, io_out_pipe_pipe_pipe_pipe_out	module ScalePipe( // @[VectorScalarMultiplier.scala:33:7] input clock, // @[VectorScalarMultiplier.scala:33:7] input reset, // @[VectorScalarMultiplier.scala:33:7] input io_in_valid, // @[VectorScalarMultiplier.scala:35:14] input [7:0] io_in_bits_data, // @[VectorScalarMultiplier.scala:35:14] input [31:0] io_in_bits_scale_bits, // @[VectorScalarMultiplier.scala:35:14] input [1:0] io_in_bits_id, // @[VectorScalarMultiplier.scala:35:14] input [3:0] io_in_bits_index, // @[VectorScalarMultiplier.scala:35:14] output io_out_valid, // @[VectorScalarMultiplier.scala:35:14] output [7:0] io_out_bits_data, // @[VectorScalarMultiplier.scala:35:14] output [1:0] io_out_bits_id, // @[VectorScalarMultiplier.scala:35:14] output [3:0] io_out_bits_index // @[VectorScalarMultiplier.scala:35:14] ); wire out_bits_data_f_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [2:0] _out_bits_data_rec_fn_to_in_io_intExceptionFlags; // @[Configs.scala:93:34] wire [32:0] _out_bits_data_muladder_io_out; // @[Configs.scala:84:30] wire [32:0] _out_bits_data_in_to_rec_fn_io_out; // @[Configs.scala:76:34] wire io_in_valid_0 = io_in_valid; // @[VectorScalarMultiplier.scala:33:7] wire [7:0] io_in_bits_data_0 = io_in_bits_data; // @[VectorScalarMultiplier.scala:33:7] wire [31:0] io_in_bits_scale_bits_0 = io_in_bits_scale_bits; // @[VectorScalarMultiplier.scala:33:7] wire [1:0] io_in_bits_id_0 = io_in_bits_id; // @[VectorScalarMultiplier.scala:33:7] wire [3:0] io_in_bits_index_0 = io_in_bits_index; // @[VectorScalarMultiplier.scala:33:7] wire out_valid = io_in_valid_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire [7:0] _out_bits_data_in_to_rec_fn_io_in_T = io_in_bits_data_0; // @[VectorScalarMultiplier.scala:33:7] wire [31:0] out_bits_scale_bits = io_in_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire [31:0] _out_bits_data_WIRE_1 = io_in_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:33:7, :41:89] wire [1:0] out_bits_id = io_in_bits_id_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire [3:0] out_bits_index = io_in_bits_index_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire io_out_pipe_pipe_pipe_pipe_out_valid; // @[Valid.scala:135:21] wire [7:0] io_out_pipe_pipe_pipe_pipe_out_bits_data; // @[Valid.scala:135:21] wire [31:0] io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits; // @[Valid.scala:135:21] wire [1:0] io_out_pipe_pipe_pipe_pipe_out_bits_id; // @[Valid.scala:135:21] wire [3:0] io_out_pipe_pipe_pipe_pipe_out_bits_index; // @[Valid.scala:135:21] wire [31:0] io_out_bits_scale_bits; // @[VectorScalarMultiplier.scala:33:7] wire [7:0] io_out_bits_data_0; // @[VectorScalarMultiplier.scala:33:7] wire [1:0] io_out_bits_id_0; // @[VectorScalarMultiplier.scala:33:7] wire [3:0] io_out_bits_index_0; // @[VectorScalarMultiplier.scala:33:7] wire io_out_valid_0; // @[VectorScalarMultiplier.scala:33:7] wire [7:0] _out_bits_data_T_2; // @[Configs.scala:104:12] wire [7:0] out_bits_data; // @[VectorScalarMultiplier.scala:40:21] wire [31:0] _out_bits_data_T; // @[VectorScalarMultiplier.scala:41:89] assign _out_bits_data_T = _out_bits_data_WIRE_1; // @[VectorScalarMultiplier.scala:41:89] wire [31:0] _out_bits_data_WIRE_bits = _out_bits_data_T; // @[VectorScalarMultiplier.scala:41:89] wire out_bits_data_f_rec_rawIn_sign = _out_bits_data_WIRE_bits[31]; // @[rawFloatFromFN.scala:44:18] wire out_bits_data_f_rec_rawIn_sign_0 = out_bits_data_f_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] out_bits_data_f_rec_rawIn_expIn = _out_bits_data_WIRE_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] out_bits_data_f_rec_rawIn_fractIn = _out_bits_data_WIRE_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire out_bits_data_f_rec_rawIn_isZeroExpIn = out_bits_data_f_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire out_bits_data_f_rec_rawIn_isZeroFractIn = out_bits_data_f_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _out_bits_data_f_rec_rawIn_normDist_T = out_bits_data_f_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_1 = out_bits_data_f_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_2 = out_bits_data_f_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_3 = out_bits_data_f_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_4 = out_bits_data_f_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_5 = out_bits_data_f_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_6 = out_bits_data_f_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_7 = out_bits_data_f_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_8 = out_bits_data_f_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_9 = out_bits_data_f_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_10 = out_bits_data_f_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_11 = out_bits_data_f_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_12 = out_bits_data_f_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_13 = out_bits_data_f_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_14 = out_bits_data_f_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_15 = out_bits_data_f_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_16 = out_bits_data_f_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_17 = out_bits_data_f_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_18 = out_bits_data_f_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_19 = out_bits_data_f_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_20 = out_bits_data_f_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_21 = out_bits_data_f_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_22 = out_bits_data_f_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_23 = _out_bits_data_f_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_24 = _out_bits_data_f_rec_rawIn_normDist_T_2 ? 5'h14 : _out_bits_data_f_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_25 = _out_bits_data_f_rec_rawIn_normDist_T_3 ? 5'h13 : _out_bits_data_f_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_26 = _out_bits_data_f_rec_rawIn_normDist_T_4 ? 5'h12 : _out_bits_data_f_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_27 = _out_bits_data_f_rec_rawIn_normDist_T_5 ? 5'h11 : _out_bits_data_f_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_28 = _out_bits_data_f_rec_rawIn_normDist_T_6 ? 5'h10 : _out_bits_data_f_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_29 = _out_bits_data_f_rec_rawIn_normDist_T_7 ? 5'hF : _out_bits_data_f_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_30 = _out_bits_data_f_rec_rawIn_normDist_T_8 ? 5'hE : _out_bits_data_f_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_31 = _out_bits_data_f_rec_rawIn_normDist_T_9 ? 5'hD : _out_bits_data_f_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_32 = _out_bits_data_f_rec_rawIn_normDist_T_10 ? 5'hC : _out_bits_data_f_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_33 = _out_bits_data_f_rec_rawIn_normDist_T_11 ? 5'hB : _out_bits_data_f_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_34 = _out_bits_data_f_rec_rawIn_normDist_T_12 ? 5'hA : _out_bits_data_f_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_35 = _out_bits_data_f_rec_rawIn_normDist_T_13 ? 5'h9 : _out_bits_data_f_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_36 = _out_bits_data_f_rec_rawIn_normDist_T_14 ? 5'h8 : _out_bits_data_f_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_37 = _out_bits_data_f_rec_rawIn_normDist_T_15 ? 5'h7 : _out_bits_data_f_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_38 = _out_bits_data_f_rec_rawIn_normDist_T_16 ? 5'h6 : _out_bits_data_f_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_39 = _out_bits_data_f_rec_rawIn_normDist_T_17 ? 5'h5 : _out_bits_data_f_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_40 = _out_bits_data_f_rec_rawIn_normDist_T_18 ? 5'h4 : _out_bits_data_f_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_41 = _out_bits_data_f_rec_rawIn_normDist_T_19 ? 5'h3 : _out_bits_data_f_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_42 = _out_bits_data_f_rec_rawIn_normDist_T_20 ? 5'h2 : _out_bits_data_f_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_43 = _out_bits_data_f_rec_rawIn_normDist_T_21 ? 5'h1 : _out_bits_data_f_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] out_bits_data_f_rec_rawIn_normDist = _out_bits_data_f_rec_rawIn_normDist_T_22 ? 5'h0 : _out_bits_data_f_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _out_bits_data_f_rec_rawIn_subnormFract_T = {31'h0, out_bits_data_f_rec_rawIn_fractIn} << out_bits_data_f_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _out_bits_data_f_rec_rawIn_subnormFract_T_1 = _out_bits_data_f_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] out_bits_data_f_rec_rawIn_subnormFract = {_out_bits_data_f_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _out_bits_data_f_rec_rawIn_adjustedExp_T = {4'hF, ~out_bits_data_f_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_1 = out_bits_data_f_rec_rawIn_isZeroExpIn ? _out_bits_data_f_rec_rawIn_adjustedExp_T : {1'h0, out_bits_data_f_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_2 = out_bits_data_f_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_3 = {6'h20, _out_bits_data_f_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_4 = {1'h0, _out_bits_data_f_rec_rawIn_adjustedExp_T_1} + {2'h0, _out_bits_data_f_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] out_bits_data_f_rec_rawIn_adjustedExp = _out_bits_data_f_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _out_bits_data_f_rec_rawIn_out_sExp_T = out_bits_data_f_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire out_bits_data_f_rec_rawIn_isZero = out_bits_data_f_rec_rawIn_isZeroExpIn & out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire out_bits_data_f_rec_rawIn_isZero_0 = out_bits_data_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _out_bits_data_f_rec_rawIn_isSpecial_T = out_bits_data_f_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire out_bits_data_f_rec_rawIn_isSpecial = &_out_bits_data_f_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _out_bits_data_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _out_bits_data_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _out_bits_data_f_rec_T_2 = out_bits_data_f_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _out_bits_data_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _out_bits_data_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire out_bits_data_f_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] out_bits_data_f_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] out_bits_data_f_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _out_bits_data_f_rec_rawIn_out_isNaN_T = ~out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _out_bits_data_f_rec_rawIn_out_isNaN_T_1 = out_bits_data_f_rec_rawIn_isSpecial & _out_bits_data_f_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign out_bits_data_f_rec_rawIn_isNaN = _out_bits_data_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _out_bits_data_f_rec_rawIn_out_isInf_T = out_bits_data_f_rec_rawIn_isSpecial & out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign out_bits_data_f_rec_rawIn_isInf = _out_bits_data_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _out_bits_data_f_rec_rawIn_out_sExp_T_1 = {1'h0, _out_bits_data_f_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign out_bits_data_f_rec_rawIn_sExp = _out_bits_data_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _out_bits_data_f_rec_rawIn_out_sig_T = ~out_bits_data_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _out_bits_data_f_rec_rawIn_out_sig_T_1 = {1'h0, _out_bits_data_f_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _out_bits_data_f_rec_rawIn_out_sig_T_2 = out_bits_data_f_rec_rawIn_isZeroExpIn ? out_bits_data_f_rec_rawIn_subnormFract : out_bits_data_f_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _out_bits_data_f_rec_rawIn_out_sig_T_3 = {_out_bits_data_f_rec_rawIn_out_sig_T_1, _out_bits_data_f_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign out_bits_data_f_rec_rawIn_sig = _out_bits_data_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _out_bits_data_f_rec_T = out_bits_data_f_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _out_bits_data_f_rec_T_1 = out_bits_data_f_rec_rawIn_isZero_0 ? 3'h0 : _out_bits_data_f_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _out_bits_data_f_rec_T_3 = {_out_bits_data_f_rec_T_1[2:1], _out_bits_data_f_rec_T_1[0] \| _out_bits_data_f_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _out_bits_data_f_rec_T_4 = {out_bits_data_f_rec_rawIn_sign_0, _out_bits_data_f_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _out_bits_data_f_rec_T_5 = out_bits_data_f_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _out_bits_data_f_rec_T_6 = {_out_bits_data_f_rec_T_4, _out_bits_data_f_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _out_bits_data_f_rec_T_7 = out_bits_data_f_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] out_bits_data_f_rec = {_out_bits_data_f_rec_T_6, _out_bits_data_f_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] _out_bits_data_in_to_rec_fn_io_in_WIRE = _out_bits_data_in_to_rec_fn_io_in_T; // @[Configs.scala:78:41] wire out_bits_data_overflow = _out_bits_data_rec_fn_to_in_io_intExceptionFlags[1]; // @[Configs.scala:93:34, :98:57] wire [8:0] out_bits_data_sign_exp = _out_bits_data_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_data_sign_isZero_T = out_bits_data_sign_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_data_sign_isZero = _out_bits_data_sign_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_data_sign_out_isZero = out_bits_data_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_data_sign_isSpecial_T = out_bits_data_sign_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_data_sign_isSpecial = &_out_bits_data_sign_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_data_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_data_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_data_sign_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_data_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_data_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_data_sign_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_data_sign_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_data_sign_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_data_sign_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_data_sign_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_data_sign_out_isNaN_T = out_bits_data_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_data_sign_out_isInf_T = out_bits_data_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_data_sign_out_isNaN_T_1 = out_bits_data_sign_isSpecial & _out_bits_data_sign_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_data_sign_out_isNaN = _out_bits_data_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_data_sign_out_isInf_T_1 = ~_out_bits_data_sign_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_data_sign_out_isInf_T_2 = out_bits_data_sign_isSpecial & _out_bits_data_sign_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_data_sign_out_isInf = _out_bits_data_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_data_sign_out_sign_T = _out_bits_data_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_data_sign_out_sign = _out_bits_data_sign_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_data_sign_out_sExp_T = {1'h0, out_bits_data_sign_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_data_sign_out_sExp = _out_bits_data_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_data_sign_out_sig_T = ~out_bits_data_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_data_sign_out_sig_T_1 = {1'h0, _out_bits_data_sign_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_data_sign_out_sig_T_2 = _out_bits_data_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_data_sign_out_sig_T_3 = {_out_bits_data_sign_out_sig_T_1, _out_bits_data_sign_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_data_sign_out_sig = _out_bits_data_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [7:0] out_bits_data_sat = out_bits_data_sign_out_sign ? 8'h80 : 8'h7F; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_data_T_1; // @[Configs.scala:104:56] wire [7:0] _out_bits_data_WIRE_2 = _out_bits_data_T_1; // @[Configs.scala:104:56] assign _out_bits_data_T_2 = out_bits_data_overflow ? out_bits_data_sat : _out_bits_data_WIRE_2; // @[Configs.scala:98:57, :102:22, :104:{12,56}] assign out_bits_data = _out_bits_data_T_2; // @[VectorScalarMultiplier.scala:40:21] reg io_out_pipe_v; // @[Valid.scala:141:24] reg [7:0] io_out_pipe_b_data; // @[Valid.scala:142:26] reg [31:0] io_out_pipe_b_scale_bits; // @[Valid.scala:142:26] reg [1:0] io_out_pipe_b_id; // @[Valid.scala:142:26] reg [3:0] io_out_pipe_b_index; // @[Valid.scala:142:26] reg io_out_pipe_pipe_v; // @[Valid.scala:141:24] reg [7:0] io_out_pipe_pipe_b_data; // @[Valid.scala:142:26] reg [31:0] io_out_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] reg [1:0] io_out_pipe_pipe_b_id; // @[Valid.scala:142:26] reg [3:0] io_out_pipe_pipe_b_index; // @[Valid.scala:142:26] reg io_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24] reg [7:0] io_out_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26] reg [31:0] io_out_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] reg [1:0] io_out_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26] reg [3:0] io_out_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26] reg io_out_pipe_pipe_pipe_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_pipe_pipe_pipe_out_valid = io_out_pipe_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg [7:0] io_out_pipe_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_data = io_out_pipe_pipe_pipe_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [31:0] io_out_pipe_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits = io_out_pipe_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:135:21, :142:26] reg [1:0] io_out_pipe_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_id = io_out_pipe_pipe_pipe_pipe_b_id; // @[Valid.scala:135:21, :142:26] reg [3:0] io_out_pipe_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_index = io_out_pipe_pipe_pipe_pipe_b_index; // @[Valid.scala:135:21, :142:26] assign io_out_valid_0 = io_out_pipe_pipe_pipe_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_pipe_pipe_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_scale_bits = io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits; // @[Valid.scala:135:21] assign io_out_bits_id_0 = io_out_pipe_pipe_pipe_pipe_out_bits_id; // @[Valid.scala:135:21] assign io_out_bits_index_0 = io_out_pipe_pipe_pipe_pipe_out_bits_index; // @[Valid.scala:135:21] always @(posedge clock) begin // @[VectorScalarMultiplier.scala:33:7] if (reset) begin // @[VectorScalarMultiplier.scala:33:7] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[VectorScalarMultiplier.scala:33:7] io_out_pipe_v <= out_valid; // @[Valid.scala:141:24] io_out_pipe_pipe_v <= io_out_pipe_v; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_v <= io_out_pipe_pipe_v; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_pipe_v <= io_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24] end if (out_valid) begin // @[VectorScalarMultiplier.scala:40:21] io_out_pipe_b_data <= out_bits_data; // @[Valid.scala:142:26] io_out_pipe_b_scale_bits <= out_bits_scale_bits; // @[Valid.scala:142:26] io_out_pipe_b_id <= out_bits_id; // @[Valid.scala:142:26] io_out_pipe_b_index <= out_bits_index; // @[Valid.scala:142:26] end if (io_out_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_pipe_b_data <= io_out_pipe_b_data; // @[Valid.scala:142:26] io_out_pipe_pipe_b_scale_bits <= io_out_pipe_b_scale_bits; // @[Valid.scala:142:26] io_out_pipe_pipe_b_id <= io_out_pipe_b_id; // @[Valid.scala:142:26] io_out_pipe_pipe_b_index <= io_out_pipe_b_index; // @[Valid.scala:142:26] end if (io_out_pipe_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_b_data; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_b_scale_bits <= io_out_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_b_id <= io_out_pipe_pipe_b_id; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_b_index <= io_out_pipe_pipe_b_index; // @[Valid.scala:142:26] end if (io_out_pipe_pipe_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_pipe_b_scale_bits <= io_out_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_pipe_b_id <= io_out_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_pipe_b_index <= io_out_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26] end always @(posedge) INToRecFN_i8_e8_s24 out_bits_data_in_to_rec_fn ( // @[Configs.scala:76:34] .io_in (_out_bits_data_in_to_rec_fn_io_in_WIRE), // @[Configs.scala:78:41] .io_out (_out_bits_data_in_to_rec_fn_io_out) ); // @[Configs.scala:76:34] MulAddRecFN_e8_s24 out_bits_data_muladder ( // @[Configs.scala:84:30] .io_a (_out_bits_data_in_to_rec_fn_io_out), // @[Configs.scala:76:34] .io_b (out_bits_data_f_rec), // @[recFNFromFN.scala:50:41] .io_out (_out_bits_data_muladder_io_out) ); // @[Configs.scala:84:30] RecFNToIN_e8_s24_i8 out_bits_data_rec_fn_to_in ( // @[Configs.scala:93:34] .clock (clock), .reset (reset), .io_in (_out_bits_data_muladder_io_out), // @[Configs.scala:84:30] .io_out (_out_bits_data_T_1), .io_intExceptionFlags (_out_bits_data_rec_fn_to_in_io_intExceptionFlags) ); // @[Configs.scala:93:34] assign io_out_valid = io_out_valid_0; // @[VectorScalarMultiplier.scala:33:7] assign io_out_bits_data = io_out_bits_data_0; // @[VectorScalarMultiplier.scala:33:7] assign io_out_bits_id = io_out_bits_id_0; // @[VectorScalarMultiplier.scala:33:7] assign io_out_bits_index = io_out_bits_index_0; // @[VectorScalarMultiplier.scala:33:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_2 : input clock : Clock input reset : Reset output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<4>(0hf)) when _T : connect doing_reset, UInt<1>(0h0) reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0)) node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0) wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect f2_entry, entries[_f2_entry_T_1] node _T_1 = eq(io.update_idx, io.f2_req_idx) node _T_2 = and(io.update_repair, _T_1) when _T_2 : connect f2_entry.s_cnt, io.update_meta.s_cnt else : node _T_3 = eq(io.update_idx, io.f2_req_idx) node _T_4 = and(io.update_mispredict, _T_3) when _T_4 : connect f2_entry.s_cnt, UInt<1>(0h0) reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f3_entry, f2_entry reg f3_scnt_REG : UInt, clock connect f3_scnt_REG, io.f2_req_idx node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) node _f3_tag_T = bits(io.f2_req_idx, 13, 4) reg f3_tag : UInt, clock connect f3_tag, _f3_tag_T connect io.f3_pred, io.f3_pred_in connect io.f3_meta.s_cnt, f3_scnt node _T_5 = eq(f3_entry.tag, f3_tag) when _T_5 : node _T_6 = eq(f3_scnt, f3_entry.p_cnt) node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) connect io.f3_pred, _io_f3_pred_T reg f4_fire : UInt<1>, clock connect f4_fire, io.f3_req_fire reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f4_entry, f3_entry reg f4_tag : UInt, clock connect f4_tag, f3_tag reg f4_scnt : UInt, clock connect f4_scnt, f3_scnt reg f4_idx_REG : UInt, clock connect f4_idx_REG, io.f2_req_idx reg f4_idx : UInt, clock connect f4_idx, f4_idx_REG when f4_fire : node _T_9 = eq(f4_entry.tag, f4_tag) when _T_9 : node _T_10 = eq(f4_scnt, f4_entry.p_cnt) node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _T_13 = or(f4_idx, UInt<4>(0h0)) node _T_14 = bits(_T_13, 3, 0) connect entries[_T_14].age, UInt<3>(0h7) node _T_15 = or(f4_idx, UInt<4>(0h0)) node _T_16 = bits(_T_15, 3, 0) connect entries[_T_16].s_cnt, UInt<1>(0h0) else : node _T_17 = or(f4_idx, UInt<4>(0h0)) node _T_18 = bits(_T_17, 3, 0) node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 node _T_19 = or(f4_idx, UInt<4>(0h0)) node _T_20 = bits(_T_19, 3, 0) node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) node _entries_age_T_2 = tail(_entries_age_T_1, 1) node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) connect entries[_T_20].age, _entries_age_T_3 node _entry_T = or(io.update_idx, UInt<4>(0h0)) node _entry_T_1 = bits(_entry_T, 3, 0) node tag = bits(io.update_idx, 13, 4) node tag_match = eq(entries[_entry_T_1].tag, tag) node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect wentry, entries[_entry_T_1] node _T_21 = eq(doing_reset, UInt<1>(0h0)) node _T_22 = and(io.update_mispredict, _T_21) when _T_22 : node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_24 = and(_T_23, tag_match) when _T_24 : connect wentry.s_cnt, UInt<1>(0h0) connect wentry.conf, UInt<1>(0h0) else : node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_26 = eq(tag_match, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : skip else : node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_29 = and(_T_28, tag_match) node _T_30 = and(_T_29, ctr_match) when _T_30 : node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) connect wentry.conf, _wentry_conf_T_1 connect wentry.s_cnt, UInt<1>(0h0) else : node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_32 = and(_T_31, tag_match) node _T_33 = eq(ctr_match, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) when _T_34 : connect wentry.conf, UInt<1>(0h0) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_36 = eq(tag_match, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_41 = eq(tag_match, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) when _T_44 : node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) node _wentry_age_T_1 = tail(_wentry_age_T, 1) connect wentry.age, _wentry_age_T_1 else : node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_46 = and(_T_45, tag_match) node _T_47 = and(_T_46, ctr_match) when _T_47 : connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_49 = and(_T_48, tag_match) node _T_50 = eq(ctr_match, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect wentry.p_cnt, io.update_meta.s_cnt connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_53 = eq(tag_match, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt node _T_55 = or(io.update_idx, UInt<4>(0h0)) node _T_56 = bits(_T_55, 3, 0) connect entries[_T_56], wentry else : node _T_57 = eq(doing_reset, UInt<1>(0h0)) node _T_58 = and(io.update_repair, _T_57) when _T_58 : node _T_59 = eq(io.update_idx, f4_idx) node _T_60 = and(f4_fire, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(tag_match, _T_61) when _T_62 : connect wentry.s_cnt, io.update_meta.s_cnt node _T_63 = or(io.update_idx, UInt<4>(0h0)) node _T_64 = bits(_T_63, 3, 0) connect entries[_T_64], wentry when doing_reset : wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect _entries_WIRE.s_cnt, UInt<10>(0h0) connect _entries_WIRE.p_cnt, UInt<10>(0h0) connect _entries_WIRE.age, UInt<3>(0h0) connect _entries_WIRE.conf, UInt<3>(0h0) connect _entries_WIRE.tag, UInt<10>(0h0) connect entries[reset_idx], _entries_WIRE	module LoopBranchPredictorColumn_2( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [36:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [36:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [36:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [36:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [36:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [36:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [36:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [36:0] f4_idx_REG; // @[loop.scala:92:35] reg [36:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (\|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (\|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (\|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (\|_GEN_0[_entry_T_1]) & ~tag_match & (\|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 \| _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 \| _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 \| _T_24 \| _T_27 \| _GEN_5 \| ~(_T_39 \| ~(_T_44 \| _GEN_4 \| ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 \| ~(_T_44 \| ~(_T_47 \| ~(_T_51 \| ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 \| _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 \| _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 \| _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| ~(_GEN_7 \| ~(_T_44 \| _T_47 \| ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 \| ~(_T_27 \| ~(_GEN_5 \| _T_39 \| ~(_T_44 \| ~(_GEN_4 \| _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_1 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_1 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T	module IntSyncCrossingSource_n1x1_1( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_1 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_77 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} inst input_buffer of InputBuffer_77 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) inst route_arbiter of Arbiter2_RouteComputerReq_31 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2] wire vcalloc_vals : UInt<1>[2] node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0)) node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11) node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_18 = and(io.router_req.ready, io.router_req.valid) when _T_18 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1]) when _T_19 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = bits(vcalloc_sel, 0, 0) node _mask_T_6 = bits(vcalloc_sel, 1, 1) node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_7, _mask_T_8) wire _mask_WIRE : UInt<2> connect _mask_WIRE, _mask_T_9 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2] node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10 connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2] node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1] node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_14 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_15 : UInt<2> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_14.egress_node_id, _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_16 : UInt<4> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_14.egress_node, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_34 connect _io_vcalloc_req_bits_WIRE_14.ingress_node_id, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_18 : UInt<4> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_14.ingress_node, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_14.vnet_id, _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_14 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_20 = bits(vcalloc_sel, 1, 1) node _T_21 = and(vcalloc_vals[1], _T_20) node _T_22 = and(_T_21, io.vcalloc_req.ready) when _T_22 : connect states[1].g, UInt<3>(0h3) node _T_23 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_23 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready) node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1) connect io.debug.va_stall, _io_debug_va_stall_T_3 node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_24 : node _T_25 = bits(vcalloc_sel, 0, 0) when _T_25 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_26 = bits(vcalloc_sel, 1, 1) when _T_26 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_190 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] node _credit_available_T = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node _credit_available_T_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node _credit_available_T_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi = cat(states[1].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi, credit_available_lo) node _credit_available_T_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _credit_available_T_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node _credit_available_T_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_1 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_27 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_28 = and(_T_27, input_buffer.io.deq[1].bits.tail) when _T_28 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_5 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5 node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_7 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1) connect salloc_outs[0].vid, _salloc_outs_0_vid_T node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _vc_sel_WIRE : UInt<1>[2] node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_4 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_7 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_3 : UInt<1>[2] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_10 connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4 node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_13 connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5 connect vc_sel.`1`, _vc_sel_WIRE_3 wire _vc_sel_WIRE_6 : UInt<1>[2] node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_16 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_19 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 connect vc_sel.`2`, _vc_sel_WIRE_6 wire _vc_sel_WIRE_9 : UInt<1>[1] node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_22 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 connect vc_sel.`3`, _vc_sel_WIRE_9 node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1) node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0)) node _virt_channel_T_7 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0)) node _virt_channel_T_8 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = or(_virt_channel_T_6, _virt_channel_T_7) node _virt_channel_T_11 = or(_virt_channel_T_10, _virt_channel_T_8) node _virt_channel_T_12 = or(_virt_channel_T_11, _virt_channel_T_9) wire virt_channel : UInt<1> connect virt_channel, _virt_channel_T_12 node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_29 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3) wire _salloc_outs_0_flit_payload_WIRE : UInt<37> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`3`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) node _T_30 = asUInt(reset) when _T_30 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0)	module InputUnit_77( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_2_1; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire _GEN_1 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_62 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_62( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_434 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_178 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_434( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_178 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_34 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_68 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_34 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0he) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0he)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_18 = eq(UInt<5>(0h10), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(UInt<5>(0h11), io.in.bits.egress_id) when _T_19 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_21 = and(route_q.io.enq.valid, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_22, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_69 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_34 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_27 = and(vcalloc_q.io.enq.valid, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_34( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h1E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h1B; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_12 = {1'h0, {1'h0, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T}}} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h5 : 3'h0)} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hA : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'h9 : 4'h0); // @[Mux.scala:30:73] wire [2:0] _GEN_0 = _route_buffer_io_enq_bits_flow_egress_node_T_12[2:0] \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h6 : 3'h0); // @[Mux.scala:30:73] wire [3:0] _GEN_1 = {_route_buffer_io_enq_bits_flow_egress_node_T_12[3], _GEN_0}; // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_1 == 4'hE; // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_1 != 4'hE; // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 connect _source_ok_WIRE[9], _source_ok_T_44 node _source_ok_T_45 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[2]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[3]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[4]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[5]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[6]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[7]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_52, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h3)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<2>(0h2)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<4>(0h8)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_112 = eq(_T_111, UInt<1>(0h0)) node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_114 = cvt(_T_113) node _T_115 = and(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = asSInt(_T_115) node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0))) node _T_118 = or(_T_112, _T_117) node _T_119 = and(_T_11, _T_24) node _T_120 = and(_T_119, _T_37) node _T_121 = and(_T_120, _T_50) node _T_122 = and(_T_121, _T_63) node _T_123 = and(_T_122, _T_76) node _T_124 = and(_T_123, _T_89) node _T_125 = and(_T_124, _T_102) node _T_126 = and(_T_125, _T_110) node _T_127 = and(_T_126, _T_118) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_127, UInt<1>(0h1), "") : assert_1 node _T_131 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_131 : node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_136 = shr(io.in.a.bits.source, 2) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = leq(UInt<1>(0h0), uncommonBits_7) node _T_139 = and(_T_137, _T_138) node _T_140 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_141 = and(_T_139, _T_140) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_142 = shr(io.in.a.bits.source, 2) node _T_143 = eq(_T_142, UInt<1>(0h1)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_8) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_147 = and(_T_145, _T_146) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_148 = shr(io.in.a.bits.source, 2) node _T_149 = eq(_T_148, UInt<2>(0h2)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_9) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_154 = shr(io.in.a.bits.source, 2) node _T_155 = eq(_T_154, UInt<2>(0h3)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_10) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_159 = and(_T_157, _T_158) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_160 = shr(io.in.a.bits.source, 3) node _T_161 = eq(_T_160, UInt<2>(0h3)) node _T_162 = leq(UInt<1>(0h0), uncommonBits_11) node _T_163 = and(_T_161, _T_162) node _T_164 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_165 = and(_T_163, _T_164) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_166 = shr(io.in.a.bits.source, 3) node _T_167 = eq(_T_166, UInt<2>(0h2)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_12) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_172 = shr(io.in.a.bits.source, 3) node _T_173 = eq(_T_172, UInt<4>(0h8)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_13) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_179 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_180 = or(_T_135, _T_141) node _T_181 = or(_T_180, _T_147) node _T_182 = or(_T_181, _T_153) node _T_183 = or(_T_182, _T_159) node _T_184 = or(_T_183, _T_165) node _T_185 = or(_T_184, _T_171) node _T_186 = or(_T_185, _T_177) node _T_187 = or(_T_186, _T_178) node _T_188 = or(_T_187, _T_179) node _T_189 = and(_T_134, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_192 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<14>(0h2000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<13>(0h1000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<17>(0h10000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<18>(0h2f000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<17>(0h10000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<13>(0h1000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<27>(0h4000000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<13>(0h1000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_196, _T_201) node _T_238 = or(_T_237, _T_206) node _T_239 = or(_T_238, _T_211) node _T_240 = or(_T_239, _T_216) node _T_241 = or(_T_240, _T_221) node _T_242 = or(_T_241, _T_226) node _T_243 = or(_T_242, _T_231) node _T_244 = or(_T_243, _T_236) node _T_245 = and(_T_191, _T_244) node _T_246 = or(UInt<1>(0h0), _T_245) node _T_247 = and(_T_190, _T_246) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_247, UInt<1>(0h1), "") : assert_2 node _T_251 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_14) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_15) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_16) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_17) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_276 = shr(io.in.a.bits.source, 3) node _T_277 = eq(_T_276, UInt<2>(0h3)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_18) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_281 = and(_T_279, _T_280) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_282 = shr(io.in.a.bits.source, 3) node _T_283 = eq(_T_282, UInt<2>(0h2)) node _T_284 = leq(UInt<1>(0h0), uncommonBits_19) node _T_285 = and(_T_283, _T_284) node _T_286 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_287 = and(_T_285, _T_286) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_288 = shr(io.in.a.bits.source, 3) node _T_289 = eq(_T_288, UInt<4>(0h8)) node _T_290 = leq(UInt<1>(0h0), uncommonBits_20) node _T_291 = and(_T_289, _T_290) node _T_292 = leq(uncommonBits_20, UInt<3>(0h4)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_295 = eq(io.in.a.bits.source, UInt<7>(0h48)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_251 connect _WIRE[1], _T_257 connect _WIRE[2], _T_263 connect _WIRE[3], _T_269 connect _WIRE[4], _T_275 connect _WIRE[5], _T_281 connect _WIRE[6], _T_287 connect _WIRE[7], _T_293 connect _WIRE[8], _T_294 connect _WIRE[9], _T_295 node _T_296 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_297 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_298 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_299 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_302 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_304 = mux(_WIRE[7], _T_296, UInt<1>(0h0)) node _T_305 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_306 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_307 = or(_T_297, _T_298) node _T_308 = or(_T_307, _T_299) node _T_309 = or(_T_308, _T_300) node _T_310 = or(_T_309, _T_301) node _T_311 = or(_T_310, _T_302) node _T_312 = or(_T_311, _T_303) node _T_313 = or(_T_312, _T_304) node _T_314 = or(_T_313, _T_305) node _T_315 = or(_T_314, _T_306) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_315 node _T_316 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_317 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_318 = and(_T_316, _T_317) node _T_319 = or(UInt<1>(0h0), _T_318) node _T_320 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<14>(0h2000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<13>(0h1000))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_324, _T_329) node _T_366 = or(_T_365, _T_334) node _T_367 = or(_T_366, _T_339) node _T_368 = or(_T_367, _T_344) node _T_369 = or(_T_368, _T_349) node _T_370 = or(_T_369, _T_354) node _T_371 = or(_T_370, _T_359) node _T_372 = or(_T_371, _T_364) node _T_373 = and(_T_319, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_WIRE_1, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_375, UInt<1>(0h1), "") : assert_3 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(source_ok, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_382 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_382, UInt<1>(0h1), "") : assert_5 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(is_aligned, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_389 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_389, UInt<1>(0h1), "") : assert_7 node _T_393 = not(io.in.a.bits.mask) node _T_394 = eq(_T_393, UInt<1>(0h0)) node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_T_394, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_394, UInt<1>(0h1), "") : assert_8 node _T_398 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_398, UInt<1>(0h1), "") : assert_9 node _T_402 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_402 : node _T_403 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_404 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_21) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<1>(0h1)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_22) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_419 = shr(io.in.a.bits.source, 2) node _T_420 = eq(_T_419, UInt<2>(0h2)) node _T_421 = leq(UInt<1>(0h0), uncommonBits_23) node _T_422 = and(_T_420, _T_421) node _T_423 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_424 = and(_T_422, _T_423) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_425 = shr(io.in.a.bits.source, 2) node _T_426 = eq(_T_425, UInt<2>(0h3)) node _T_427 = leq(UInt<1>(0h0), uncommonBits_24) node _T_428 = and(_T_426, _T_427) node _T_429 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_430 = and(_T_428, _T_429) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_431 = shr(io.in.a.bits.source, 3) node _T_432 = eq(_T_431, UInt<2>(0h3)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_25) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_436 = and(_T_434, _T_435) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_437 = shr(io.in.a.bits.source, 3) node _T_438 = eq(_T_437, UInt<2>(0h2)) node _T_439 = leq(UInt<1>(0h0), uncommonBits_26) node _T_440 = and(_T_438, _T_439) node _T_441 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_442 = and(_T_440, _T_441) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_443 = shr(io.in.a.bits.source, 3) node _T_444 = eq(_T_443, UInt<4>(0h8)) node _T_445 = leq(UInt<1>(0h0), uncommonBits_27) node _T_446 = and(_T_444, _T_445) node _T_447 = leq(uncommonBits_27, UInt<3>(0h4)) node _T_448 = and(_T_446, _T_447) node _T_449 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_450 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_451 = or(_T_406, _T_412) node _T_452 = or(_T_451, _T_418) node _T_453 = or(_T_452, _T_424) node _T_454 = or(_T_453, _T_430) node _T_455 = or(_T_454, _T_436) node _T_456 = or(_T_455, _T_442) node _T_457 = or(_T_456, _T_448) node _T_458 = or(_T_457, _T_449) node _T_459 = or(_T_458, _T_450) node _T_460 = and(_T_405, _T_459) node _T_461 = or(UInt<1>(0h0), _T_460) node _T_462 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_464 = cvt(_T_463) node _T_465 = and(_T_464, asSInt(UInt<14>(0h2000))) node _T_466 = asSInt(_T_465) node _T_467 = eq(_T_466, asSInt(UInt<1>(0h0))) node _T_468 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_469 = cvt(_T_468) node _T_470 = and(_T_469, asSInt(UInt<13>(0h1000))) node _T_471 = asSInt(_T_470) node _T_472 = eq(_T_471, asSInt(UInt<1>(0h0))) node _T_473 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_474 = cvt(_T_473) node _T_475 = and(_T_474, asSInt(UInt<17>(0h10000))) node _T_476 = asSInt(_T_475) node _T_477 = eq(_T_476, asSInt(UInt<1>(0h0))) node _T_478 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_479 = cvt(_T_478) node _T_480 = and(_T_479, asSInt(UInt<18>(0h2f000))) node _T_481 = asSInt(_T_480) node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0))) node _T_483 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_484 = cvt(_T_483) node _T_485 = and(_T_484, asSInt(UInt<17>(0h10000))) node _T_486 = asSInt(_T_485) node _T_487 = eq(_T_486, asSInt(UInt<1>(0h0))) node _T_488 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_489 = cvt(_T_488) node _T_490 = and(_T_489, asSInt(UInt<13>(0h1000))) node _T_491 = asSInt(_T_490) node _T_492 = eq(_T_491, asSInt(UInt<1>(0h0))) node _T_493 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_494 = cvt(_T_493) node _T_495 = and(_T_494, asSInt(UInt<27>(0h4000000))) node _T_496 = asSInt(_T_495) node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0))) node _T_498 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_499 = cvt(_T_498) node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000))) node _T_501 = asSInt(_T_500) node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0))) node _T_503 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<13>(0h1000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = or(_T_467, _T_472) node _T_509 = or(_T_508, _T_477) node _T_510 = or(_T_509, _T_482) node _T_511 = or(_T_510, _T_487) node _T_512 = or(_T_511, _T_492) node _T_513 = or(_T_512, _T_497) node _T_514 = or(_T_513, _T_502) node _T_515 = or(_T_514, _T_507) node _T_516 = and(_T_462, _T_515) node _T_517 = or(UInt<1>(0h0), _T_516) node _T_518 = and(_T_461, _T_517) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_518, UInt<1>(0h1), "") : assert_10 node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_523 = shr(io.in.a.bits.source, 2) node _T_524 = eq(_T_523, UInt<1>(0h0)) node _T_525 = leq(UInt<1>(0h0), uncommonBits_28) node _T_526 = and(_T_524, _T_525) node _T_527 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_528 = and(_T_526, _T_527) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_529 = shr(io.in.a.bits.source, 2) node _T_530 = eq(_T_529, UInt<1>(0h1)) node _T_531 = leq(UInt<1>(0h0), uncommonBits_29) node _T_532 = and(_T_530, _T_531) node _T_533 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_534 = and(_T_532, _T_533) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_535 = shr(io.in.a.bits.source, 2) node _T_536 = eq(_T_535, UInt<2>(0h2)) node _T_537 = leq(UInt<1>(0h0), uncommonBits_30) node _T_538 = and(_T_536, _T_537) node _T_539 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_540 = and(_T_538, _T_539) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_541 = shr(io.in.a.bits.source, 2) node _T_542 = eq(_T_541, UInt<2>(0h3)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_31) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_547 = shr(io.in.a.bits.source, 3) node _T_548 = eq(_T_547, UInt<2>(0h3)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_32) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_553 = shr(io.in.a.bits.source, 3) node _T_554 = eq(_T_553, UInt<2>(0h2)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_33) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_559 = shr(io.in.a.bits.source, 3) node _T_560 = eq(_T_559, UInt<4>(0h8)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_34) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_564 = and(_T_562, _T_563) node _T_565 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_566 = eq(io.in.a.bits.source, UInt<7>(0h48)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_522 connect _WIRE_2[1], _T_528 connect _WIRE_2[2], _T_534 connect _WIRE_2[3], _T_540 connect _WIRE_2[4], _T_546 connect _WIRE_2[5], _T_552 connect _WIRE_2[6], _T_558 connect _WIRE_2[7], _T_564 connect _WIRE_2[8], _T_565 connect _WIRE_2[9], _T_566 node _T_567 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_568 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_569 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_570 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_572 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_573 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_574 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_575 = mux(_WIRE_2[7], _T_567, UInt<1>(0h0)) node _T_576 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_577 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = or(_T_568, _T_569) node _T_579 = or(_T_578, _T_570) node _T_580 = or(_T_579, _T_571) node _T_581 = or(_T_580, _T_572) node _T_582 = or(_T_581, _T_573) node _T_583 = or(_T_582, _T_574) node _T_584 = or(_T_583, _T_575) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_577) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_586 node _T_587 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_588 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_589 = and(_T_587, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<14>(0h2000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<13>(0h1000))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_602 = cvt(_T_601) node _T_603 = and(_T_602, asSInt(UInt<17>(0h10000))) node _T_604 = asSInt(_T_603) node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0))) node _T_606 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_607 = cvt(_T_606) node _T_608 = and(_T_607, asSInt(UInt<18>(0h2f000))) node _T_609 = asSInt(_T_608) node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0))) node _T_611 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_612 = cvt(_T_611) node _T_613 = and(_T_612, asSInt(UInt<17>(0h10000))) node _T_614 = asSInt(_T_613) node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0))) node _T_616 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<13>(0h1000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_622 = cvt(_T_621) node _T_623 = and(_T_622, asSInt(UInt<27>(0h4000000))) node _T_624 = asSInt(_T_623) node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0))) node _T_626 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_627 = cvt(_T_626) node _T_628 = and(_T_627, asSInt(UInt<13>(0h1000))) node _T_629 = asSInt(_T_628) node _T_630 = eq(_T_629, asSInt(UInt<1>(0h0))) node _T_631 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_632 = cvt(_T_631) node _T_633 = and(_T_632, asSInt(UInt<13>(0h1000))) node _T_634 = asSInt(_T_633) node _T_635 = eq(_T_634, asSInt(UInt<1>(0h0))) node _T_636 = or(_T_595, _T_600) node _T_637 = or(_T_636, _T_605) node _T_638 = or(_T_637, _T_610) node _T_639 = or(_T_638, _T_615) node _T_640 = or(_T_639, _T_620) node _T_641 = or(_T_640, _T_625) node _T_642 = or(_T_641, _T_630) node _T_643 = or(_T_642, _T_635) node _T_644 = and(_T_590, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = and(_WIRE_3, _T_645) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_646, UInt<1>(0h1), "") : assert_11 node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(source_ok, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_653 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_653, UInt<1>(0h1), "") : assert_13 node _T_657 = asUInt(reset) node _T_658 = eq(_T_657, UInt<1>(0h0)) when _T_658 : node _T_659 = eq(is_aligned, UInt<1>(0h0)) when _T_659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_660 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_660, UInt<1>(0h1), "") : assert_15 node _T_664 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(_T_664, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_664, UInt<1>(0h1), "") : assert_16 node _T_668 = not(io.in.a.bits.mask) node _T_669 = eq(_T_668, UInt<1>(0h0)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_669, UInt<1>(0h1), "") : assert_17 node _T_673 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_673, UInt<1>(0h1), "") : assert_18 node _T_677 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_677 : node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<1>(0h0)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_35) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_688 = shr(io.in.a.bits.source, 2) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_36) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_694 = shr(io.in.a.bits.source, 2) node _T_695 = eq(_T_694, UInt<2>(0h2)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_37) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_699 = and(_T_697, _T_698) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_700 = shr(io.in.a.bits.source, 2) node _T_701 = eq(_T_700, UInt<2>(0h3)) node _T_702 = leq(UInt<1>(0h0), uncommonBits_38) node _T_703 = and(_T_701, _T_702) node _T_704 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_706 = shr(io.in.a.bits.source, 3) node _T_707 = eq(_T_706, UInt<2>(0h3)) node _T_708 = leq(UInt<1>(0h0), uncommonBits_39) node _T_709 = and(_T_707, _T_708) node _T_710 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_711 = and(_T_709, _T_710) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_712 = shr(io.in.a.bits.source, 3) node _T_713 = eq(_T_712, UInt<2>(0h2)) node _T_714 = leq(UInt<1>(0h0), uncommonBits_40) node _T_715 = and(_T_713, _T_714) node _T_716 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_717 = and(_T_715, _T_716) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_718 = shr(io.in.a.bits.source, 3) node _T_719 = eq(_T_718, UInt<4>(0h8)) node _T_720 = leq(UInt<1>(0h0), uncommonBits_41) node _T_721 = and(_T_719, _T_720) node _T_722 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_726 = or(_T_681, _T_687) node _T_727 = or(_T_726, _T_693) node _T_728 = or(_T_727, _T_699) node _T_729 = or(_T_728, _T_705) node _T_730 = or(_T_729, _T_711) node _T_731 = or(_T_730, _T_717) node _T_732 = or(_T_731, _T_723) node _T_733 = or(_T_732, _T_724) node _T_734 = or(_T_733, _T_725) node _T_735 = and(_T_680, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_736, UInt<1>(0h1), "") : assert_19 node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_742 = and(_T_740, _T_741) node _T_743 = or(UInt<1>(0h0), _T_742) node _T_744 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_745 = cvt(_T_744) node _T_746 = and(_T_745, asSInt(UInt<13>(0h1000))) node _T_747 = asSInt(_T_746) node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0))) node _T_749 = and(_T_743, _T_748) node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_752 = and(_T_750, _T_751) node _T_753 = or(UInt<1>(0h0), _T_752) node _T_754 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<14>(0h2000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<18>(0h2f000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<17>(0h10000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<13>(0h1000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_780 = cvt(_T_779) node _T_781 = and(_T_780, asSInt(UInt<27>(0h4000000))) node _T_782 = asSInt(_T_781) node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0))) node _T_784 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_785 = cvt(_T_784) node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000))) node _T_787 = asSInt(_T_786) node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0))) node _T_789 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_790 = cvt(_T_789) node _T_791 = and(_T_790, asSInt(UInt<13>(0h1000))) node _T_792 = asSInt(_T_791) node _T_793 = eq(_T_792, asSInt(UInt<1>(0h0))) node _T_794 = or(_T_758, _T_763) node _T_795 = or(_T_794, _T_768) node _T_796 = or(_T_795, _T_773) node _T_797 = or(_T_796, _T_778) node _T_798 = or(_T_797, _T_783) node _T_799 = or(_T_798, _T_788) node _T_800 = or(_T_799, _T_793) node _T_801 = and(_T_753, _T_800) node _T_802 = or(UInt<1>(0h0), _T_749) node _T_803 = or(_T_802, _T_801) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_803, UInt<1>(0h1), "") : assert_20 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(source_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(is_aligned, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_813 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_813, UInt<1>(0h1), "") : assert_23 node _T_817 = eq(io.in.a.bits.mask, mask) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_817, UInt<1>(0h1), "") : assert_24 node _T_821 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_821, UInt<1>(0h1), "") : assert_25 node _T_825 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_825 : node _T_826 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_827 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_828 = and(_T_826, _T_827) node _T_829 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_830 = shr(io.in.a.bits.source, 2) node _T_831 = eq(_T_830, UInt<1>(0h0)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_42) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_835 = and(_T_833, _T_834) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_836 = shr(io.in.a.bits.source, 2) node _T_837 = eq(_T_836, UInt<1>(0h1)) node _T_838 = leq(UInt<1>(0h0), uncommonBits_43) node _T_839 = and(_T_837, _T_838) node _T_840 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_841 = and(_T_839, _T_840) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<2>(0h2)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_44) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<2>(0h3)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_45) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_854 = shr(io.in.a.bits.source, 3) node _T_855 = eq(_T_854, UInt<2>(0h3)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_46) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_860 = shr(io.in.a.bits.source, 3) node _T_861 = eq(_T_860, UInt<2>(0h2)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_47) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_865 = and(_T_863, _T_864) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_866 = shr(io.in.a.bits.source, 3) node _T_867 = eq(_T_866, UInt<4>(0h8)) node _T_868 = leq(UInt<1>(0h0), uncommonBits_48) node _T_869 = and(_T_867, _T_868) node _T_870 = leq(uncommonBits_48, UInt<3>(0h4)) node _T_871 = and(_T_869, _T_870) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_874 = or(_T_829, _T_835) node _T_875 = or(_T_874, _T_841) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_853) node _T_878 = or(_T_877, _T_859) node _T_879 = or(_T_878, _T_865) node _T_880 = or(_T_879, _T_871) node _T_881 = or(_T_880, _T_872) node _T_882 = or(_T_881, _T_873) node _T_883 = and(_T_828, _T_882) node _T_884 = or(UInt<1>(0h0), _T_883) node _T_885 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_886 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_887 = and(_T_885, _T_886) node _T_888 = or(UInt<1>(0h0), _T_887) node _T_889 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = and(_T_888, _T_893) node _T_895 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_896 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_897 = and(_T_895, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<18>(0h2f000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<17>(0h10000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<13>(0h1000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<27>(0h4000000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<13>(0h1000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_942 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<17>(0h10000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = and(_T_941, _T_946) node _T_948 = or(UInt<1>(0h0), _T_894) node _T_949 = or(_T_948, _T_940) node _T_950 = or(_T_949, _T_947) node _T_951 = and(_T_884, _T_950) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_951, UInt<1>(0h1), "") : assert_26 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(source_ok, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(is_aligned, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_961 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_961, UInt<1>(0h1), "") : assert_29 node _T_965 = eq(io.in.a.bits.mask, mask) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_965, UInt<1>(0h1), "") : assert_30 node _T_969 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_969 : node _T_970 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_971 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_972 = and(_T_970, _T_971) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_974 = shr(io.in.a.bits.source, 2) node _T_975 = eq(_T_974, UInt<1>(0h0)) node _T_976 = leq(UInt<1>(0h0), uncommonBits_49) node _T_977 = and(_T_975, _T_976) node _T_978 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_979 = and(_T_977, _T_978) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_980 = shr(io.in.a.bits.source, 2) node _T_981 = eq(_T_980, UInt<1>(0h1)) node _T_982 = leq(UInt<1>(0h0), uncommonBits_50) node _T_983 = and(_T_981, _T_982) node _T_984 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_985 = and(_T_983, _T_984) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_986 = shr(io.in.a.bits.source, 2) node _T_987 = eq(_T_986, UInt<2>(0h2)) node _T_988 = leq(UInt<1>(0h0), uncommonBits_51) node _T_989 = and(_T_987, _T_988) node _T_990 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_991 = and(_T_989, _T_990) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_992 = shr(io.in.a.bits.source, 2) node _T_993 = eq(_T_992, UInt<2>(0h3)) node _T_994 = leq(UInt<1>(0h0), uncommonBits_52) node _T_995 = and(_T_993, _T_994) node _T_996 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_997 = and(_T_995, _T_996) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_998 = shr(io.in.a.bits.source, 3) node _T_999 = eq(_T_998, UInt<2>(0h3)) node _T_1000 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_1003 = and(_T_1001, _T_1002) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_1004 = shr(io.in.a.bits.source, 3) node _T_1005 = eq(_T_1004, UInt<2>(0h2)) node _T_1006 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1007 = and(_T_1005, _T_1006) node _T_1008 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_1009 = and(_T_1007, _T_1008) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_1010 = shr(io.in.a.bits.source, 3) node _T_1011 = eq(_T_1010, UInt<4>(0h8)) node _T_1012 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1013 = and(_T_1011, _T_1012) node _T_1014 = leq(uncommonBits_55, UInt<3>(0h4)) node _T_1015 = and(_T_1013, _T_1014) node _T_1016 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1017 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1018 = or(_T_973, _T_979) node _T_1019 = or(_T_1018, _T_985) node _T_1020 = or(_T_1019, _T_991) node _T_1021 = or(_T_1020, _T_997) node _T_1022 = or(_T_1021, _T_1003) node _T_1023 = or(_T_1022, _T_1009) node _T_1024 = or(_T_1023, _T_1015) node _T_1025 = or(_T_1024, _T_1016) node _T_1026 = or(_T_1025, _T_1017) node _T_1027 = and(_T_972, _T_1026) node _T_1028 = or(UInt<1>(0h0), _T_1027) node _T_1029 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1030 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1034 = cvt(_T_1033) node _T_1035 = and(_T_1034, asSInt(UInt<13>(0h1000))) node _T_1036 = asSInt(_T_1035) node _T_1037 = eq(_T_1036, asSInt(UInt<1>(0h0))) node _T_1038 = and(_T_1032, _T_1037) node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1040 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = or(UInt<1>(0h0), _T_1041) node _T_1043 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1044 = cvt(_T_1043) node _T_1045 = and(_T_1044, asSInt(UInt<14>(0h2000))) node _T_1046 = asSInt(_T_1045) node _T_1047 = eq(_T_1046, asSInt(UInt<1>(0h0))) node _T_1048 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1049 = cvt(_T_1048) node _T_1050 = and(_T_1049, asSInt(UInt<18>(0h2f000))) node _T_1051 = asSInt(_T_1050) node _T_1052 = eq(_T_1051, asSInt(UInt<1>(0h0))) node _T_1053 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1054 = cvt(_T_1053) node _T_1055 = and(_T_1054, asSInt(UInt<17>(0h10000))) node _T_1056 = asSInt(_T_1055) node _T_1057 = eq(_T_1056, asSInt(UInt<1>(0h0))) node _T_1058 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1059 = cvt(_T_1058) node _T_1060 = and(_T_1059, asSInt(UInt<13>(0h1000))) node _T_1061 = asSInt(_T_1060) node _T_1062 = eq(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<27>(0h4000000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1069 = cvt(_T_1068) node _T_1070 = and(_T_1069, asSInt(UInt<13>(0h1000))) node _T_1071 = asSInt(_T_1070) node _T_1072 = eq(_T_1071, asSInt(UInt<1>(0h0))) node _T_1073 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<13>(0h1000))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = or(_T_1047, _T_1052) node _T_1079 = or(_T_1078, _T_1057) node _T_1080 = or(_T_1079, _T_1062) node _T_1081 = or(_T_1080, _T_1067) node _T_1082 = or(_T_1081, _T_1072) node _T_1083 = or(_T_1082, _T_1077) node _T_1084 = and(_T_1042, _T_1083) node _T_1085 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1086 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<17>(0h10000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = and(_T_1085, _T_1090) node _T_1092 = or(UInt<1>(0h0), _T_1038) node _T_1093 = or(_T_1092, _T_1084) node _T_1094 = or(_T_1093, _T_1091) node _T_1095 = and(_T_1028, _T_1094) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_31 node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(source_ok, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(is_aligned, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1105 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_34 node _T_1109 = not(mask) node _T_1110 = and(io.in.a.bits.mask, _T_1109) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_35 node _T_1115 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1115 : node _T_1116 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1117 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1120 = shr(io.in.a.bits.source, 2) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) node _T_1122 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1125 = and(_T_1123, _T_1124) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1126 = shr(io.in.a.bits.source, 2) node _T_1127 = eq(_T_1126, UInt<1>(0h1)) node _T_1128 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1131 = and(_T_1129, _T_1130) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1132 = shr(io.in.a.bits.source, 2) node _T_1133 = eq(_T_1132, UInt<2>(0h2)) node _T_1134 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1135 = and(_T_1133, _T_1134) node _T_1136 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1137 = and(_T_1135, _T_1136) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1138 = shr(io.in.a.bits.source, 2) node _T_1139 = eq(_T_1138, UInt<2>(0h3)) node _T_1140 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1141 = and(_T_1139, _T_1140) node _T_1142 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1143 = and(_T_1141, _T_1142) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_1144 = shr(io.in.a.bits.source, 3) node _T_1145 = eq(_T_1144, UInt<2>(0h3)) node _T_1146 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1147 = and(_T_1145, _T_1146) node _T_1148 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_1149 = and(_T_1147, _T_1148) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_1150 = shr(io.in.a.bits.source, 3) node _T_1151 = eq(_T_1150, UInt<2>(0h2)) node _T_1152 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_1155 = and(_T_1153, _T_1154) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_1156 = shr(io.in.a.bits.source, 3) node _T_1157 = eq(_T_1156, UInt<4>(0h8)) node _T_1158 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1159 = and(_T_1157, _T_1158) node _T_1160 = leq(uncommonBits_62, UInt<3>(0h4)) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1163 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1164 = or(_T_1119, _T_1125) node _T_1165 = or(_T_1164, _T_1131) node _T_1166 = or(_T_1165, _T_1137) node _T_1167 = or(_T_1166, _T_1143) node _T_1168 = or(_T_1167, _T_1149) node _T_1169 = or(_T_1168, _T_1155) node _T_1170 = or(_T_1169, _T_1161) node _T_1171 = or(_T_1170, _T_1162) node _T_1172 = or(_T_1171, _T_1163) node _T_1173 = and(_T_1118, _T_1172) node _T_1174 = or(UInt<1>(0h0), _T_1173) node _T_1175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1176 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _T_1178 = or(UInt<1>(0h0), _T_1177) node _T_1179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1180 = cvt(_T_1179) node _T_1181 = and(_T_1180, asSInt(UInt<14>(0h2000))) node _T_1182 = asSInt(_T_1181) node _T_1183 = eq(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1185 = cvt(_T_1184) node _T_1186 = and(_T_1185, asSInt(UInt<13>(0h1000))) node _T_1187 = asSInt(_T_1186) node _T_1188 = eq(_T_1187, asSInt(UInt<1>(0h0))) node _T_1189 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1190 = cvt(_T_1189) node _T_1191 = and(_T_1190, asSInt(UInt<18>(0h2f000))) node _T_1192 = asSInt(_T_1191) node _T_1193 = eq(_T_1192, asSInt(UInt<1>(0h0))) node _T_1194 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1195 = cvt(_T_1194) node _T_1196 = and(_T_1195, asSInt(UInt<17>(0h10000))) node _T_1197 = asSInt(_T_1196) node _T_1198 = eq(_T_1197, asSInt(UInt<1>(0h0))) node _T_1199 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1200 = cvt(_T_1199) node _T_1201 = and(_T_1200, asSInt(UInt<13>(0h1000))) node _T_1202 = asSInt(_T_1201) node _T_1203 = eq(_T_1202, asSInt(UInt<1>(0h0))) node _T_1204 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1205 = cvt(_T_1204) node _T_1206 = and(_T_1205, asSInt(UInt<27>(0h4000000))) node _T_1207 = asSInt(_T_1206) node _T_1208 = eq(_T_1207, asSInt(UInt<1>(0h0))) node _T_1209 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1210 = cvt(_T_1209) node _T_1211 = and(_T_1210, asSInt(UInt<13>(0h1000))) node _T_1212 = asSInt(_T_1211) node _T_1213 = eq(_T_1212, asSInt(UInt<1>(0h0))) node _T_1214 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<13>(0h1000))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = or(_T_1183, _T_1188) node _T_1220 = or(_T_1219, _T_1193) node _T_1221 = or(_T_1220, _T_1198) node _T_1222 = or(_T_1221, _T_1203) node _T_1223 = or(_T_1222, _T_1208) node _T_1224 = or(_T_1223, _T_1213) node _T_1225 = or(_T_1224, _T_1218) node _T_1226 = and(_T_1178, _T_1225) node _T_1227 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1228 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1229 = cvt(_T_1228) node _T_1230 = and(_T_1229, asSInt(UInt<17>(0h10000))) node _T_1231 = asSInt(_T_1230) node _T_1232 = eq(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = and(_T_1227, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1226) node _T_1235 = or(_T_1234, _T_1233) node _T_1236 = and(_T_1174, _T_1235) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_36 node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(source_ok, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(is_aligned, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1246 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_39 node _T_1250 = eq(io.in.a.bits.mask, mask) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_40 node _T_1254 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1254 : node _T_1255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1256 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1259 = shr(io.in.a.bits.source, 2) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) node _T_1261 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1264 = and(_T_1262, _T_1263) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_1265 = shr(io.in.a.bits.source, 2) node _T_1266 = eq(_T_1265, UInt<1>(0h1)) node _T_1267 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1268 = and(_T_1266, _T_1267) node _T_1269 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_1270 = and(_T_1268, _T_1269) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1271 = shr(io.in.a.bits.source, 2) node _T_1272 = eq(_T_1271, UInt<2>(0h2)) node _T_1273 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1276 = and(_T_1274, _T_1275) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1277 = shr(io.in.a.bits.source, 2) node _T_1278 = eq(_T_1277, UInt<2>(0h3)) node _T_1279 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1280 = and(_T_1278, _T_1279) node _T_1281 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1282 = and(_T_1280, _T_1281) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_1283 = shr(io.in.a.bits.source, 3) node _T_1284 = eq(_T_1283, UInt<2>(0h3)) node _T_1285 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1286 = and(_T_1284, _T_1285) node _T_1287 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_1288 = and(_T_1286, _T_1287) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_1289 = shr(io.in.a.bits.source, 3) node _T_1290 = eq(_T_1289, UInt<2>(0h2)) node _T_1291 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1292 = and(_T_1290, _T_1291) node _T_1293 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_1294 = and(_T_1292, _T_1293) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1295 = shr(io.in.a.bits.source, 3) node _T_1296 = eq(_T_1295, UInt<4>(0h8)) node _T_1297 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1298 = and(_T_1296, _T_1297) node _T_1299 = leq(uncommonBits_69, UInt<3>(0h4)) node _T_1300 = and(_T_1298, _T_1299) node _T_1301 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1302 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1303 = or(_T_1258, _T_1264) node _T_1304 = or(_T_1303, _T_1270) node _T_1305 = or(_T_1304, _T_1276) node _T_1306 = or(_T_1305, _T_1282) node _T_1307 = or(_T_1306, _T_1288) node _T_1308 = or(_T_1307, _T_1294) node _T_1309 = or(_T_1308, _T_1300) node _T_1310 = or(_T_1309, _T_1301) node _T_1311 = or(_T_1310, _T_1302) node _T_1312 = and(_T_1257, _T_1311) node _T_1313 = or(UInt<1>(0h0), _T_1312) node _T_1314 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1315 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1316 = and(_T_1314, _T_1315) node _T_1317 = or(UInt<1>(0h0), _T_1316) node _T_1318 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<14>(0h2000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<13>(0h1000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<18>(0h2f000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<17>(0h10000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<13>(0h1000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<27>(0h4000000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<13>(0h1000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1354 = cvt(_T_1353) node _T_1355 = and(_T_1354, asSInt(UInt<13>(0h1000))) node _T_1356 = asSInt(_T_1355) node _T_1357 = eq(_T_1356, asSInt(UInt<1>(0h0))) node _T_1358 = or(_T_1322, _T_1327) node _T_1359 = or(_T_1358, _T_1332) node _T_1360 = or(_T_1359, _T_1337) node _T_1361 = or(_T_1360, _T_1342) node _T_1362 = or(_T_1361, _T_1347) node _T_1363 = or(_T_1362, _T_1352) node _T_1364 = or(_T_1363, _T_1357) node _T_1365 = and(_T_1317, _T_1364) node _T_1366 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1367 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<17>(0h10000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = and(_T_1366, _T_1371) node _T_1373 = or(UInt<1>(0h0), _T_1365) node _T_1374 = or(_T_1373, _T_1372) node _T_1375 = and(_T_1313, _T_1374) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_41 node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(source_ok, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(is_aligned, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1385 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_44 node _T_1389 = eq(io.in.a.bits.mask, mask) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_45 node _T_1393 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1393 : node _T_1394 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1395 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1398 = shr(io.in.a.bits.source, 2) node _T_1399 = eq(_T_1398, UInt<1>(0h0)) node _T_1400 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1401 = and(_T_1399, _T_1400) node _T_1402 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1403 = and(_T_1401, _T_1402) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1404 = shr(io.in.a.bits.source, 2) node _T_1405 = eq(_T_1404, UInt<1>(0h1)) node _T_1406 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1409 = and(_T_1407, _T_1408) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1410 = shr(io.in.a.bits.source, 2) node _T_1411 = eq(_T_1410, UInt<2>(0h2)) node _T_1412 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1413 = and(_T_1411, _T_1412) node _T_1414 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1415 = and(_T_1413, _T_1414) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1416 = shr(io.in.a.bits.source, 2) node _T_1417 = eq(_T_1416, UInt<2>(0h3)) node _T_1418 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1421 = and(_T_1419, _T_1420) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1422 = shr(io.in.a.bits.source, 3) node _T_1423 = eq(_T_1422, UInt<2>(0h3)) node _T_1424 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1425 = and(_T_1423, _T_1424) node _T_1426 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1427 = and(_T_1425, _T_1426) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_1428 = shr(io.in.a.bits.source, 3) node _T_1429 = eq(_T_1428, UInt<2>(0h2)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1433 = and(_T_1431, _T_1432) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1434 = shr(io.in.a.bits.source, 3) node _T_1435 = eq(_T_1434, UInt<4>(0h8)) node _T_1436 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1437 = and(_T_1435, _T_1436) node _T_1438 = leq(uncommonBits_76, UInt<3>(0h4)) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1441 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1442 = or(_T_1397, _T_1403) node _T_1443 = or(_T_1442, _T_1409) node _T_1444 = or(_T_1443, _T_1415) node _T_1445 = or(_T_1444, _T_1421) node _T_1446 = or(_T_1445, _T_1427) node _T_1447 = or(_T_1446, _T_1433) node _T_1448 = or(_T_1447, _T_1439) node _T_1449 = or(_T_1448, _T_1440) node _T_1450 = or(_T_1449, _T_1441) node _T_1451 = and(_T_1396, _T_1450) node _T_1452 = or(UInt<1>(0h0), _T_1451) node _T_1453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = or(UInt<1>(0h0), _T_1455) node _T_1457 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = and(_T_1456, _T_1461) node _T_1463 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1464 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<14>(0h2000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<17>(0h10000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<18>(0h2f000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<17>(0h10000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<13>(0h1000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<13>(0h1000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1468, _T_1473) node _T_1505 = or(_T_1504, _T_1478) node _T_1506 = or(_T_1505, _T_1483) node _T_1507 = or(_T_1506, _T_1488) node _T_1508 = or(_T_1507, _T_1493) node _T_1509 = or(_T_1508, _T_1498) node _T_1510 = or(_T_1509, _T_1503) node _T_1511 = and(_T_1463, _T_1510) node _T_1512 = or(UInt<1>(0h0), _T_1462) node _T_1513 = or(_T_1512, _T_1511) node _T_1514 = and(_T_1452, _T_1513) node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(_T_1514, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1514, UInt<1>(0h1), "") : assert_46 node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(source_ok, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(is_aligned, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1524 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_49 node _T_1528 = eq(io.in.a.bits.mask, mask) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_50 node _T_1532 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1536 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1537 = asUInt(reset) node _T_1538 = eq(_T_1537, UInt<1>(0h0)) when _T_1538 : node _T_1539 = eq(_T_1536, UInt<1>(0h0)) when _T_1539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1536, UInt<1>(0h1), "") : assert_52 node _source_ok_T_53 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<1>(0h0)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<1>(0h1)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 2) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<2>(0h2)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 2) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<2>(0h3)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 3) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<2>(0h3)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 3) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<2>(0h2)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 3) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<4>(0h8)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_13, UInt<3>(0h4)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h48)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_53 connect _source_ok_WIRE_1[1], _source_ok_T_59 connect _source_ok_WIRE_1[2], _source_ok_T_65 connect _source_ok_WIRE_1[3], _source_ok_T_71 connect _source_ok_WIRE_1[4], _source_ok_T_77 connect _source_ok_WIRE_1[5], _source_ok_T_83 connect _source_ok_WIRE_1[6], _source_ok_T_89 connect _source_ok_WIRE_1[7], _source_ok_T_95 connect _source_ok_WIRE_1[8], _source_ok_T_96 connect _source_ok_WIRE_1[9], _source_ok_T_97 node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_105, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1540 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1540 : node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(source_ok_1, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1544 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_54 node _T_1548 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_55 node _T_1552 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_56 node _T_1556 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_57 node _T_1560 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1560 : node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(source_ok_1, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(sink_ok, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1567 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_60 node _T_1571 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_61 node _T_1575 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_62 node _T_1579 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_63 node _T_1583 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1584 = or(UInt<1>(0h1), _T_1583) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_64 node _T_1588 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1588 : node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(source_ok_1, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(sink_ok, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1595 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_67 node _T_1599 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_68 node _T_1603 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_69 node _T_1607 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1608 = or(_T_1607, io.in.d.bits.corrupt) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_70 node _T_1612 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1613 = or(UInt<1>(0h1), _T_1612) node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(_T_1613, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1613, UInt<1>(0h1), "") : assert_71 node _T_1617 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1617 : node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(source_ok_1, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1621 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_73 node _T_1625 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1626 = asUInt(reset) node _T_1627 = eq(_T_1626, UInt<1>(0h0)) when _T_1627 : node _T_1628 = eq(_T_1625, UInt<1>(0h0)) when _T_1628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1625, UInt<1>(0h1), "") : assert_74 node _T_1629 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1630 = or(UInt<1>(0h1), _T_1629) node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(_T_1630, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1630, UInt<1>(0h1), "") : assert_75 node _T_1634 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1634 : node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(source_ok_1, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1638 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1639 = asUInt(reset) node _T_1640 = eq(_T_1639, UInt<1>(0h0)) when _T_1640 : node _T_1641 = eq(_T_1638, UInt<1>(0h0)) when _T_1641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1638, UInt<1>(0h1), "") : assert_77 node _T_1642 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1643 = or(_T_1642, io.in.d.bits.corrupt) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_78 node _T_1647 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1648 = or(UInt<1>(0h1), _T_1647) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_79 node _T_1652 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1652 : node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(source_ok_1, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1656 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_81 node _T_1660 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_82 node _T_1664 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1665 = or(UInt<1>(0h1), _T_1664) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.mask, UInt<16>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1669 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1673 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1677 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1678 = asUInt(reset) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) when _T_1679 : node _T_1680 = eq(_T_1677, UInt<1>(0h0)) when _T_1680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1677, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1681 = eq(a_first, UInt<1>(0h0)) node _T_1682 = and(io.in.a.valid, _T_1681) when _T_1682 : node _T_1683 = eq(io.in.a.bits.opcode, opcode) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_87 node _T_1687 = eq(io.in.a.bits.param, param) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_88 node _T_1691 = eq(io.in.a.bits.size, size) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_89 node _T_1695 = eq(io.in.a.bits.source, source) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_90 node _T_1699 = eq(io.in.a.bits.address, address) node _T_1700 = asUInt(reset) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) when _T_1701 : node _T_1702 = eq(_T_1699, UInt<1>(0h0)) when _T_1702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1699, UInt<1>(0h1), "") : assert_91 node _T_1703 = and(io.in.a.ready, io.in.a.valid) node _T_1704 = and(_T_1703, a_first) when _T_1704 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1705 = eq(d_first, UInt<1>(0h0)) node _T_1706 = and(io.in.d.valid, _T_1705) when _T_1706 : node _T_1707 = eq(io.in.d.bits.opcode, opcode_1) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_92 node _T_1711 = eq(io.in.d.bits.param, param_1) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_93 node _T_1715 = eq(io.in.d.bits.size, size_1) node _T_1716 = asUInt(reset) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) when _T_1717 : node _T_1718 = eq(_T_1715, UInt<1>(0h0)) when _T_1718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1715, UInt<1>(0h1), "") : assert_94 node _T_1719 = eq(io.in.d.bits.source, source_1) node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(_T_1719, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1719, UInt<1>(0h1), "") : assert_95 node _T_1723 = eq(io.in.d.bits.sink, sink) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_96 node _T_1727 = eq(io.in.d.bits.denied, denied) node _T_1728 = asUInt(reset) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) when _T_1729 : node _T_1730 = eq(_T_1727, UInt<1>(0h0)) when _T_1730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1727, UInt<1>(0h1), "") : assert_97 node _T_1731 = and(io.in.d.ready, io.in.d.valid) node _T_1732 = and(_T_1731, d_first) when _T_1732 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<73>, clock, reset, UInt<73>(0h0) regreset inflight_opcodes : UInt<292>, clock, reset, UInt<292>(0h0) regreset inflight_sizes : UInt<584>, clock, reset, UInt<584>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<73> connect a_set, UInt<73>(0h0) wire a_set_wo_ready : UInt<73> connect a_set_wo_ready, UInt<73>(0h0) wire a_opcodes_set : UInt<292> connect a_opcodes_set, UInt<292>(0h0) wire a_sizes_set : UInt<584> connect a_sizes_set, UInt<584>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1733 = and(io.in.a.valid, a_first_1) node _T_1734 = and(_T_1733, UInt<1>(0h1)) when _T_1734 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1735 = and(io.in.a.ready, io.in.a.valid) node _T_1736 = and(_T_1735, a_first_1) node _T_1737 = and(_T_1736, UInt<1>(0h1)) when _T_1737 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1738 = dshr(inflight, io.in.a.bits.source) node _T_1739 = bits(_T_1738, 0, 0) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) node _T_1741 = asUInt(reset) node _T_1742 = eq(_T_1741, UInt<1>(0h0)) when _T_1742 : node _T_1743 = eq(_T_1740, UInt<1>(0h0)) when _T_1743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1740, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<73> connect d_clr, UInt<73>(0h0) wire d_clr_wo_ready : UInt<73> connect d_clr_wo_ready, UInt<73>(0h0) wire d_opcodes_clr : UInt<292> connect d_opcodes_clr, UInt<292>(0h0) wire d_sizes_clr : UInt<584> connect d_sizes_clr, UInt<584>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1744 = and(io.in.d.valid, d_first_1) node _T_1745 = and(_T_1744, UInt<1>(0h1)) node _T_1746 = eq(d_release_ack, UInt<1>(0h0)) node _T_1747 = and(_T_1745, _T_1746) when _T_1747 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1748 = and(io.in.d.ready, io.in.d.valid) node _T_1749 = and(_T_1748, d_first_1) node _T_1750 = and(_T_1749, UInt<1>(0h1)) node _T_1751 = eq(d_release_ack, UInt<1>(0h0)) node _T_1752 = and(_T_1750, _T_1751) when _T_1752 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1753 = and(io.in.d.valid, d_first_1) node _T_1754 = and(_T_1753, UInt<1>(0h1)) node _T_1755 = eq(d_release_ack, UInt<1>(0h0)) node _T_1756 = and(_T_1754, _T_1755) when _T_1756 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1757 = dshr(inflight, io.in.d.bits.source) node _T_1758 = bits(_T_1757, 0, 0) node _T_1759 = or(_T_1758, same_cycle_resp) node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(_T_1759, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1759, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1763 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1764 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1765 = or(_T_1763, _T_1764) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_100 node _T_1769 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_101 else : node _T_1773 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1774 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1775 = or(_T_1773, _T_1774) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_102 node _T_1779 = eq(io.in.d.bits.size, a_size_lookup) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_103 node _T_1783 = and(io.in.d.valid, d_first_1) node _T_1784 = and(_T_1783, a_first_1) node _T_1785 = and(_T_1784, io.in.a.valid) node _T_1786 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = eq(d_release_ack, UInt<1>(0h0)) node _T_1789 = and(_T_1787, _T_1788) when _T_1789 : node _T_1790 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1791 = or(_T_1790, io.in.a.ready) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_104 node _T_1795 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1796 = orr(a_set_wo_ready) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) node _T_1798 = or(_T_1795, _T_1797) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_1802 = orr(inflight) node _T_1803 = eq(_T_1802, UInt<1>(0h0)) node _T_1804 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1805 = or(_T_1803, _T_1804) node _T_1806 = lt(watchdog, plusarg_reader.out) node _T_1807 = or(_T_1805, _T_1806) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1811 = and(io.in.a.ready, io.in.a.valid) node _T_1812 = and(io.in.d.ready, io.in.d.valid) node _T_1813 = or(_T_1811, _T_1812) when _T_1813 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<73>, clock, reset, UInt<73>(0h0) regreset inflight_opcodes_1 : UInt<292>, clock, reset, UInt<292>(0h0) regreset inflight_sizes_1 : UInt<584>, clock, reset, UInt<584>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<73> connect c_set, UInt<73>(0h0) wire c_set_wo_ready : UInt<73> connect c_set_wo_ready, UInt<73>(0h0) wire c_opcodes_set : UInt<292> connect c_opcodes_set, UInt<292>(0h0) wire c_sizes_set : UInt<584> connect c_sizes_set, UInt<584>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1814 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1815 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1816 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = and(_T_1814, _T_1817) when _T_1818 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1819 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1820 = and(_T_1819, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1821 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1822 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = and(_T_1820, _T_1823) when _T_1824 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1825 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1826 = bits(_T_1825, 0, 0) node _T_1827 = eq(_T_1826, UInt<1>(0h0)) node _T_1828 = asUInt(reset) node _T_1829 = eq(_T_1828, UInt<1>(0h0)) when _T_1829 : node _T_1830 = eq(_T_1827, UInt<1>(0h0)) when _T_1830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1827, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<73> connect d_clr_1, UInt<73>(0h0) wire d_clr_wo_ready_1 : UInt<73> connect d_clr_wo_ready_1, UInt<73>(0h0) wire d_opcodes_clr_1 : UInt<292> connect d_opcodes_clr_1, UInt<292>(0h0) wire d_sizes_clr_1 : UInt<584> connect d_sizes_clr_1, UInt<584>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1831 = and(io.in.d.valid, d_first_2) node _T_1832 = and(_T_1831, UInt<1>(0h1)) node _T_1833 = and(_T_1832, d_release_ack_1) when _T_1833 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1834 = and(io.in.d.ready, io.in.d.valid) node _T_1835 = and(_T_1834, d_first_2) node _T_1836 = and(_T_1835, UInt<1>(0h1)) node _T_1837 = and(_T_1836, d_release_ack_1) when _T_1837 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1838 = and(io.in.d.valid, d_first_2) node _T_1839 = and(_T_1838, UInt<1>(0h1)) node _T_1840 = and(_T_1839, d_release_ack_1) when _T_1840 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1841 = dshr(inflight_1, io.in.d.bits.source) node _T_1842 = bits(_T_1841, 0, 0) node _T_1843 = or(_T_1842, same_cycle_resp_1) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1847 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1848 = asUInt(reset) node _T_1849 = eq(_T_1848, UInt<1>(0h0)) when _T_1849 : node _T_1850 = eq(_T_1847, UInt<1>(0h0)) when _T_1850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1847, UInt<1>(0h1), "") : assert_109 else : node _T_1851 = eq(io.in.d.bits.size, c_size_lookup) node _T_1852 = asUInt(reset) node _T_1853 = eq(_T_1852, UInt<1>(0h0)) when _T_1853 : node _T_1854 = eq(_T_1851, UInt<1>(0h0)) when _T_1854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1851, UInt<1>(0h1), "") : assert_110 node _T_1855 = and(io.in.d.valid, d_first_2) node _T_1856 = and(_T_1855, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1857 = and(_T_1856, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1858 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = and(_T_1859, d_release_ack_1) node _T_1861 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1862 = and(_T_1860, _T_1861) when _T_1862 : node _T_1863 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<128>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1864 = or(_T_1863, _WIRE_27.ready) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_111 node _T_1868 = orr(c_set_wo_ready) when _T_1868 : node _T_1869 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1870 = asUInt(reset) node _T_1871 = eq(_T_1870, UInt<1>(0h0)) when _T_1871 : node _T_1872 = eq(_T_1869, UInt<1>(0h0)) when _T_1872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1869, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1873 = orr(inflight_1) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) node _T_1875 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1876 = or(_T_1874, _T_1875) node _T_1877 = lt(watchdog_1, plusarg_reader_1.out) node _T_1878 = or(_T_1876, _T_1877) node _T_1879 = asUInt(reset) node _T_1880 = eq(_T_1879, UInt<1>(0h0)) when _T_1880 : node _T_1881 = eq(_T_1878, UInt<1>(0h0)) when _T_1881 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1878, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<128>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1882 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1883 = and(io.in.d.ready, io.in.d.valid) node _T_1884 = or(_T_1882, _T_1883) when _T_1884 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [583:0] c_sizes_set = 584'h0; // @[Monitor.scala:741:34] wire [291:0] c_opcodes_set = 292'h0; // @[Monitor.scala:740:34] wire [72:0] c_set = 73'h0; // @[Monitor.scala:738:34] wire [72:0] c_set_wo_ready = 73'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_52 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_72 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_55 = _source_ok_T_54 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_73 = _source_ok_T_72 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_78 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_84 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_90 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_79 = _source_ok_T_78 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_85 = _source_ok_T_84 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_91 = _source_ok_T_90 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_94 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_105 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1811 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1811; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1811; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1884 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1884; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1884; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1884; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [72:0] inflight; // @[Monitor.scala:614:27] reg [291:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [583:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [72:0] a_set; // @[Monitor.scala:626:34] wire [72:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [291:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [583:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [291:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [291:0] _a_opcode_lookup_T_6 = {288'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [291:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [583:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [583:0] _a_size_lookup_T_6 = {576'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [583:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[583:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire _T_1737 = _T_1811 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1737 ? _a_set_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1737 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1737 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1737 ? _a_opcodes_set_T_1[291:0] : 292'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1737 ? _a_sizes_set_T_1[583:0] : 584'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [72:0] d_clr; // @[Monitor.scala:664:34] wire [72:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [291:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [583:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1783 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1783 & ~d_release_ack ? _d_clr_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire _T_1752 = _T_1884 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1752 ? _d_clr_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1752 ? _d_opcodes_clr_T_5[291:0] : 292'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1752 ? _d_sizes_clr_T_5[583:0] : 584'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [72:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [72:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [72:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [291:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [291:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [291:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [583:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [583:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [583:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [72:0] inflight_1; // @[Monitor.scala:726:35] wire [72:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [291:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [291:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [583:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [583:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [291:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [291:0] _c_opcode_lookup_T_6 = {288'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [291:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [583:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [583:0] _c_size_lookup_T_6 = {576'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [583:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[583:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [72:0] d_clr_1; // @[Monitor.scala:774:34] wire [72:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [291:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [583:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1855 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1855 & d_release_ack_1 ? _d_clr_wo_ready_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35] wire _T_1837 = _T_1884 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1837 ? _d_clr_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1837 ? _d_opcodes_clr_T_11[291:0] : 292'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1837 ? _d_sizes_clr_T_11[583:0] : 584'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [72:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [72:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [291:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [291:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [583:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [583:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.user.amba_prot.fetch invalidate anonIn.a.bits.user.amba_prot.secure invalidate anonIn.a.bits.user.amba_prot.privileged invalidate anonIn.a.bits.user.amba_prot.writealloc invalidate anonIn.a.bits.user.amba_prot.readalloc invalidate anonIn.a.bits.user.amba_prot.modifiable invalidate anonIn.a.bits.user.amba_prot.bufferable invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.user.amba_prot.fetch invalidate anonIn_1.a.bits.user.amba_prot.secure invalidate anonIn_1.a.bits.user.amba_prot.privileged invalidate anonIn_1.a.bits.user.amba_prot.writealloc invalidate anonIn_1.a.bits.user.amba_prot.readalloc invalidate anonIn_1.a.bits.user.amba_prot.modifiable invalidate anonIn_1.a.bits.user.amba_prot.bufferable invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_35 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_36 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch connect monitor_1.io.in.a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure connect monitor_1.io.in.a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged connect monitor_1.io.in.a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc connect monitor_1.io.in.a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc connect monitor_1.io.in.a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable connect monitor_1.io.in.a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.user.amba_prot.fetch invalidate anonOut.a.bits.user.amba_prot.secure invalidate anonOut.a.bits.user.amba_prot.privileged invalidate anonOut.a.bits.user.amba_prot.writealloc invalidate anonOut.a.bits.user.amba_prot.readalloc invalidate anonOut.a.bits.user.amba_prot.modifiable invalidate anonOut.a.bits.user.amba_prot.bufferable invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] invalidate in[0].a.bits.user.amba_prot.fetch invalidate in[0].a.bits.user.amba_prot.secure invalidate in[0].a.bits.user.amba_prot.privileged invalidate in[0].a.bits.user.amba_prot.writealloc invalidate in[0].a.bits.user.amba_prot.readalloc invalidate in[0].a.bits.user.amba_prot.modifiable invalidate in[0].a.bits.user.amba_prot.bufferable connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h1)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<1>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.user.amba_prot.fetch invalidate _WIRE_9.bits.user.amba_prot.secure invalidate _WIRE_9.bits.user.amba_prot.privileged invalidate _WIRE_9.bits.user.amba_prot.writealloc invalidate _WIRE_9.bits.user.amba_prot.readalloc invalidate _WIRE_9.bits.user.amba_prot.modifiable invalidate _WIRE_9.bits.user.amba_prot.bufferable invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.user.amba_prot.fetch invalidate _WIRE_11.bits.user.amba_prot.secure invalidate _WIRE_11.bits.user.amba_prot.privileged invalidate _WIRE_11.bits.user.amba_prot.writealloc invalidate _WIRE_11.bits.user.amba_prot.readalloc invalidate _WIRE_11.bits.user.amba_prot.modifiable invalidate _WIRE_11.bits.user.amba_prot.bufferable invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready connect anonIn.d.bits.source, UInt<1>(0h0) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) invalidate in[1].a.bits.user.amba_prot.fetch invalidate in[1].a.bits.user.amba_prot.secure invalidate in[1].a.bits.user.amba_prot.privileged invalidate in[1].a.bits.user.amba_prot.writealloc invalidate in[1].a.bits.user.amba_prot.readalloc invalidate in[1].a.bits.user.amba_prot.modifiable invalidate in[1].a.bits.user.amba_prot.bufferable connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch connect in[1].a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure connect in[1].a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged connect in[1].a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc connect in[1].a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc connect in[1].a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable connect in[1].a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0)) connect in[1].a.bits.source, _in_1_a_bits_source_T wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<1>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.valid, UInt<1>(0h0) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.user.amba_prot.fetch invalidate _WIRE_33.bits.user.amba_prot.secure invalidate _WIRE_33.bits.user.amba_prot.privileged invalidate _WIRE_33.bits.user.amba_prot.writealloc invalidate _WIRE_33.bits.user.amba_prot.readalloc invalidate _WIRE_33.bits.user.amba_prot.modifiable invalidate _WIRE_33.bits.user.amba_prot.bufferable invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<1>(0h0) connect _WIRE_34.bits.size, UInt<4>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.user.amba_prot.fetch invalidate _WIRE_35.bits.user.amba_prot.secure invalidate _WIRE_35.bits.user.amba_prot.privileged invalidate _WIRE_35.bits.user.amba_prot.writealloc invalidate _WIRE_35.bits.user.amba_prot.readalloc invalidate _WIRE_35.bits.user.amba_prot.modifiable invalidate _WIRE_35.bits.user.amba_prot.bufferable invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<1>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.valid, UInt<1>(0h0) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<1>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready connect anonIn_1.d.bits.source, UInt<1>(0h0) wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.valid, UInt<1>(0h0) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] invalidate out[0].a.bits.user.amba_prot.fetch invalidate out[0].a.bits.user.amba_prot.secure invalidate out[0].a.bits.user.amba_prot.privileged invalidate out[0].a.bits.user.amba_prot.writealloc invalidate out[0].a.bits.user.amba_prot.readalloc invalidate out[0].a.bits.user.amba_prot.modifiable invalidate out[0].a.bits.user.amba_prot.bufferable connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<1>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<32>(0h0) connect _WIRE_50.bits.source, UInt<1>(0h0) connect _WIRE_50.bits.size, UInt<4>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<1>(0h0) connect _WIRE_52.bits.size, UInt<4>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<32>(0h0) connect _WIRE_54.bits.source, UInt<1>(0h0) connect _WIRE_54.bits.size, UInt<4>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<1>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.user.amba_prot.fetch invalidate _WIRE_57.bits.user.amba_prot.secure invalidate _WIRE_57.bits.user.amba_prot.privileged invalidate _WIRE_57.bits.user.amba_prot.writealloc invalidate _WIRE_57.bits.user.amba_prot.readalloc invalidate _WIRE_57.bits.user.amba_prot.modifiable invalidate _WIRE_57.bits.user.amba_prot.bufferable invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_58.bits.address, UInt<32>(0h0) connect _WIRE_58.bits.source, UInt<1>(0h0) connect _WIRE_58.bits.size, UInt<4>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.user.amba_prot.fetch invalidate _WIRE_59.bits.user.amba_prot.secure invalidate _WIRE_59.bits.user.amba_prot.privileged invalidate _WIRE_59.bits.user.amba_prot.writealloc invalidate _WIRE_59.bits.user.amba_prot.readalloc invalidate _WIRE_59.bits.user.amba_prot.modifiable invalidate _WIRE_59.bits.user.amba_prot.bufferable invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<1>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_62.bits.address, UInt<32>(0h0) connect _WIRE_62.bits.source, UInt<1>(0h0) connect _WIRE_62.bits.size, UInt<4>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<1>(0h0) connect _addressC_WIRE.bits.size, UInt<4>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE_2.bits.data, UInt<64>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) connect _addressC_WIRE_2.bits.source, UInt<1>(0h0) connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE_2.valid, UInt<1>(0h0) connect _addressC_WIRE_2.ready, UInt<1>(0h0) wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<1>(0h0) connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<1>(0h1)) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<1>(0h0)) node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<1>(0h1)) node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<1>(0h0)) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<1>(0h0) connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<1>(0h0) connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.source, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect in[0].a.ready, portsAOI_filtered[0].ready wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect in[1].a.ready, portsAOI_filtered_1[0].ready wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<1>(0h0) connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) wire _portsBIO_WIRE_2 : UInt<1> connect _portsBIO_WIRE_2, _portsBIO_T_2 connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<1>(0h0) connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE_2.bits.source, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_7 : UInt<1> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_8 : UInt<1> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_9 : UInt<1> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_10 : UInt<1> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_11 : UInt<1> connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11 node _out_0_a_bits_T_24 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_0_a_bits_T_25 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_25) wire _out_0_a_bits_WIRE_12 : UInt<1> connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_26 connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12 node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28) wire _out_0_a_bits_WIRE_13 : UInt<1> connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_29 connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13 connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6 connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31) wire _out_0_a_bits_WIRE_14 : UInt<32> connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_32 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14 node _out_0_a_bits_T_33 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_34 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_34) wire _out_0_a_bits_WIRE_15 : UInt<1> connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_35 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15 node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37) wire _out_0_a_bits_WIRE_16 : UInt<4> connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_38 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16 node _out_0_a_bits_T_39 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_40 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_40) wire _out_0_a_bits_WIRE_17 : UInt<3> connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_41 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17 node _out_0_a_bits_T_42 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_43 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_43) wire _out_0_a_bits_WIRE_18 : UInt<3> connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_44 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<1>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.user.amba_prot.fetch invalidate _WIRE_73.bits.user.amba_prot.secure invalidate _WIRE_73.bits.user.amba_prot.privileged invalidate _WIRE_73.bits.user.amba_prot.writealloc invalidate _WIRE_73.bits.user.amba_prot.readalloc invalidate _WIRE_73.bits.user.amba_prot.modifiable invalidate _WIRE_73.bits.user.amba_prot.bufferable invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.mask, UInt<8>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<1>(0h0) connect _WIRE_76.bits.size, UInt<4>(0h0) connect _WIRE_76.bits.param, UInt<2>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.mask invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode connect in[0].d, portsDIO_filtered[0] connect portsBIO_filtered[0].ready, UInt<1>(0h0) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<64>(0h0) connect _WIRE_78.bits.mask, UInt<8>(0h0) connect _WIRE_78.bits.address, UInt<32>(0h0) connect _WIRE_78.bits.source, UInt<1>(0h0) connect _WIRE_78.bits.size, UInt<4>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.corrupt invalidate _WIRE_79.bits.data invalidate _WIRE_79.bits.mask invalidate _WIRE_79.bits.address invalidate _WIRE_79.bits.source invalidate _WIRE_79.bits.size invalidate _WIRE_79.bits.param invalidate _WIRE_79.bits.opcode connect in[1].d, portsDIO_filtered[1] connect portsBIO_filtered[1].ready, UInt<1>(0h0)	module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_0_d_bits_sink; // @[Xbar.scala:216:19] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_privileged_0 = auto_anon_in_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire auto_anon_in_1_a_bits_user_amba_prot_bufferable = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_modifiable = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_fetch = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_secure = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_bufferable = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_modifiable = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_privileged = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_secure = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_fetch = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_0_a_bits_source = 1'h1; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_bufferable = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_modifiable = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_fetch = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _in_0_a_bits_source_T = 1'h1; // @[Xbar.scala:166:55] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire requestBOI_0_1 = 1'h1; // @[Parameters.scala:46:9] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire portsAOI_filtered_0_bits_source = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:352:24] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire portsAOI_filtered_1_0_bits_user_amba_prot_bufferable = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_modifiable = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_fetch = 1'h1; // @[Xbar.scala:352:24] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_40 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_user_amba_prot_fetch = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_source = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire _in_1_a_bits_source_T = 1'h0; // @[Xbar.scala:166:55] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:46:9] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsAOI_filtered_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_34 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [63:0] auto_anon_in_1_a_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] in_1_a_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _out_0_a_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [8:0] beatsAI_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_user_amba_prot_readalloc = auto_anon_in_1_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_user_amba_prot_writealloc = auto_anon_in_1_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_bufferable = auto_anon_in_0_a_bits_user_amba_prot_bufferable_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_modifiable = auto_anon_in_0_a_bits_user_amba_prot_modifiable_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_readalloc = auto_anon_in_0_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_writealloc = auto_anon_in_0_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_privileged = auto_anon_in_0_a_bits_user_amba_prot_privileged_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_bufferable_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_modifiable_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_privileged_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_secure_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_fetch_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_bufferable = anonIn_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_modifiable = anonIn_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_readalloc = anonIn_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_writealloc = anonIn_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_privileged = anonIn_a_bits_user_amba_prot_privileged; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_readalloc = anonIn_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_writealloc = anonIn_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_bufferable_0 = anonOut_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_modifiable_0 = anonOut_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_readalloc_0 = anonOut_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_writealloc_0 = anonOut_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_privileged_0 = anonOut_a_bits_user_amba_prot_privileged; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_secure; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_secure_0 = anonOut_a_bits_user_amba_prot_secure; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_fetch; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_fetch_0 = anonOut_a_bits_user_amba_prot_fetch; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_bufferable = in_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_modifiable = in_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_readalloc = in_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_writealloc = in_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_privileged = in_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_readalloc = in_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_writealloc = in_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_bits_source; // @[Xbar.scala:159:18] wire in_1_d_bits_source; // @[Xbar.scala:159:18] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_bufferable; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_bufferable = out_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_modifiable; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_modifiable = out_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_readalloc; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_readalloc = out_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_writealloc; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_writealloc = out_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_privileged; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_privileged = out_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_secure; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_secure = out_0_a_bits_user_amba_prot_secure; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_fetch; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_fetch = out_0_a_bits_user_amba_prot_fetch; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire requestDOI_0_0 = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = ~out_0_d_bits_source; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module Tile_53 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_309 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_53( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_309 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IDPool : input clock : Clock input reset : Reset output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}} regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff) regreset select : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid : UInt<1>, clock, reset, UInt<1>(0h1) connect io.alloc.valid, valid connect io.alloc.bits, select node taken_shiftAmount = bits(io.alloc.bits, 2, 0) node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount) node _taken_T_1 = bits(_taken_T, 7, 0) node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0)) node allocated_shiftAmount = bits(io.free.bits, 2, 0) node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount) node _allocated_T_1 = bits(_allocated_T, 7, 0) node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0)) node _bitmap1_T = not(taken) node _bitmap1_T_1 = and(bitmap, _bitmap1_T) node bitmap1 = or(_bitmap1_T_1, allocated) node _select1_T = bits(bitmap1, 0, 0) node _select1_T_1 = bits(bitmap1, 1, 1) node _select1_T_2 = bits(bitmap1, 2, 2) node _select1_T_3 = bits(bitmap1, 3, 3) node _select1_T_4 = bits(bitmap1, 4, 4) node _select1_T_5 = bits(bitmap1, 5, 5) node _select1_T_6 = bits(bitmap1, 6, 6) node _select1_T_7 = bits(bitmap1, 7, 7) node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8) node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9) node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10) node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11) node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12) node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13) node _valid1_T = orr(bitmap) node _valid1_T_1 = bits(bitmap, 0, 0) node _valid1_T_2 = bits(bitmap, 1, 1) node _valid1_T_3 = bits(bitmap, 2, 2) node _valid1_T_4 = bits(bitmap, 3, 3) node _valid1_T_5 = bits(bitmap, 4, 4) node _valid1_T_6 = bits(bitmap, 5, 5) node _valid1_T_7 = bits(bitmap, 6, 6) node _valid1_T_8 = bits(bitmap, 7, 7) node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2) node _valid1_T_10 = bits(_valid1_T_9, 1, 0) node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4) node _valid1_T_12 = bits(_valid1_T_11, 1, 0) node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12) node _valid1_T_14 = bits(_valid1_T_13, 2, 0) node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6) node _valid1_T_16 = bits(_valid1_T_15, 1, 0) node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8) node _valid1_T_18 = bits(_valid1_T_17, 1, 0) node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18) node _valid1_T_20 = bits(_valid1_T_19, 2, 0) node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20) node _valid1_T_22 = bits(_valid1_T_21, 3, 0) node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1)) node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready) node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0)) node _valid1_T_26 = and(_valid1_T, _valid1_T_25) node valid1 = or(_valid1_T_26, io.free.valid) node _T = or(io.alloc.ready, io.free.valid) when _T : connect bitmap, bitmap1 connect valid, valid1 node _T_1 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_2 = and(_T_1, io.free.valid) node _T_3 = or(io.alloc.ready, _T_2) when _T_3 : connect select, select1 node _T_4 = eq(io.free.valid, UInt<1>(0h0)) node _T_5 = not(taken) node _T_6 = and(bitmap, _T_5) node _T_7 = dshr(_T_6, io.free.bits) node _T_8 = bits(_T_7, 0, 0) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_4, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid \|\| !(bitmap & ~taken)(io.free.bits))\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = orr(bitmap) node _T_15 = eq(valid, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node _T_19 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_20 = and(_T_19, io.free.valid) node _T_21 = or(io.alloc.ready, _T_20) reg REG : UInt<1>, clock connect REG, _T_21 node _T_22 = and(io.alloc.valid, REG) when _T_22 : node _T_23 = bits(bitmap, 0, 0) node _T_24 = bits(bitmap, 1, 1) node _T_25 = bits(bitmap, 2, 2) node _T_26 = bits(bitmap, 3, 3) node _T_27 = bits(bitmap, 4, 4) node _T_28 = bits(bitmap, 5, 5) node _T_29 = bits(bitmap, 6, 6) node _T_30 = bits(bitmap, 7, 7) node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7)) node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31) node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32) node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33) node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34) node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35) node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36) node _T_38 = eq(select, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2 assert(clock, _T_38, UInt<1>(0h1), "") : assert_2	module IDPool( // @[IDPool.scala:8:7] input clock, // @[IDPool.scala:8:7] input reset, // @[IDPool.scala:8:7] input io_free_valid, // @[IDPool.scala:12:14] input [2:0] io_free_bits, // @[IDPool.scala:12:14] input io_alloc_ready, // @[IDPool.scala:12:14] output io_alloc_valid, // @[IDPool.scala:12:14] output [2:0] io_alloc_bits // @[IDPool.scala:12:14] ); wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7] wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7] wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7] wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7] wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49] wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49] wire io_alloc_valid_0; // @[IDPool.scala:8:7] reg [7:0] bitmap; // @[IDPool.scala:18:23] reg [2:0] select; // @[IDPool.scala:19:23] assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23] reg valid; // @[IDPool.scala:20:23] assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23] wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}] wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}] wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27] wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}] wire [7:0] bitmap1 = _bitmap1_T_1 \| allocated; // @[IDPool.scala:26:22, :27:{25,35}] wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45] wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45] wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45] wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45] wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45] wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45] wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45] wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45] wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45] wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45] wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45] wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45] wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45] wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45] wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45] wire _valid1_T = \|bitmap; // @[IDPool.scala:18:23, :29:28] wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46] wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46] wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}] wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}] wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}] wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}] wire valid1 = _valid1_T_26 \| io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17] reg REG; // @[IDPool.scala:51:36]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h13)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h13)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_86 = shr(io.in.a.bits.source, 5) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<5>(0h13)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<5>(0h13)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_199 = shr(io.in.a.bits.source, 5) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<5>(0h13)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_240 = shr(io.in.a.bits.source, 5) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<5>(0h13)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_283 = shr(io.in.a.bits.source, 5) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<5>(0h13)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_321 = shr(io.in.a.bits.source, 5) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<5>(0h13)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_359 = shr(io.in.a.bits.source, 5) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<5>(0h13)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<20> connect a_set, UInt<20>(0h0) wire a_set_wo_ready : UInt<20> connect a_set_wo_ready, UInt<20>(0h0) wire a_opcodes_set : UInt<80> connect a_opcodes_set, UInt<80>(0h0) wire a_sizes_set : UInt<80> connect a_sizes_set, UInt<80>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<20> connect d_clr, UInt<20>(0h0) wire d_clr_wo_ready : UInt<20> connect d_clr_wo_ready, UInt<20>(0h0) wire d_opcodes_clr : UInt<80> connect d_opcodes_clr, UInt<80>(0h0) wire d_sizes_clr : UInt<80> connect d_sizes_clr, UInt<80>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_110 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<20> connect c_set, UInt<20>(0h0) wire c_set_wo_ready : UInt<20> connect c_set_wo_ready, UInt<20>(0h0) wire c_opcodes_set : UInt<80> connect c_opcodes_set, UInt<80>(0h0) wire c_sizes_set : UInt<80> connect c_sizes_set, UInt<80>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<20> connect d_clr_1, UInt<20>(0h0) wire d_clr_wo_ready_1 : UInt<20> connect d_clr_wo_ready_1, UInt<20>(0h0) wire d_opcodes_clr_1 : UInt<80> connect d_opcodes_clr_1, UInt<80>(0h0) wire d_sizes_clr_1 : UInt<80> connect d_sizes_clr_1, UInt<80>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_111 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_14 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_148 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_149 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_150 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_14( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_148 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_149 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_150 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_48 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_99 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_100 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = \|flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset \| next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_48 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorBank_1 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid inst columns_0 of LoopBranchPredictorColumn_4 connect columns_0.clock, clock connect columns_0.reset, reset inst columns_1 of LoopBranchPredictorColumn_5 connect columns_1.clock, clock connect columns_1.reset, reset inst columns_2 of LoopBranchPredictorColumn_6 connect columns_2.clock, clock connect columns_2.reset, reset inst columns_3 of LoopBranchPredictorColumn_7 connect columns_3.clock, clock connect columns_3.reset, reset wire f3_meta : { s_cnt : UInt<10>}[4] node lo = cat(f3_meta[1].s_cnt, f3_meta[0].s_cnt) node hi = cat(f3_meta[3].s_cnt, f3_meta[2].s_cnt) node _T = cat(hi, lo) wire update_meta : { s_cnt : UInt<10>}[4] wire _update_meta_WIRE : UInt<40> connect _update_meta_WIRE, s1_update.bits.meta node _update_meta_T = bits(_update_meta_WIRE, 9, 0) connect update_meta[0].s_cnt, _update_meta_T node _update_meta_T_1 = bits(_update_meta_WIRE, 19, 10) connect update_meta[1].s_cnt, _update_meta_T_1 node _update_meta_T_2 = bits(_update_meta_WIRE, 29, 20) connect update_meta[2].s_cnt, _update_meta_T_2 node _update_meta_T_3 = bits(_update_meta_WIRE, 39, 30) connect update_meta[3].s_cnt, _update_meta_T_3 connect columns_0.io.f2_req_valid, s2_valid connect columns_0.io.f2_req_idx, s2_idx node _columns_0_io_f3_req_fire_T = bits(s3_mask, 0, 0) node _columns_0_io_f3_req_fire_T_1 = and(s3_valid, _columns_0_io_f3_req_fire_T) node _columns_0_io_f3_req_fire_T_2 = and(_columns_0_io_f3_req_fire_T_1, io.f3_fire) node _columns_0_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].is_br) reg columns_0_io_f3_req_fire_REG : UInt<1>, clock connect columns_0_io_f3_req_fire_REG, _columns_0_io_f3_req_fire_T_3 node _columns_0_io_f3_req_fire_T_4 = and(_columns_0_io_f3_req_fire_T_2, columns_0_io_f3_req_fire_REG) connect columns_0.io.f3_req_fire, _columns_0_io_f3_req_fire_T_4 connect columns_0.io.f3_pred_in, io.resp_in[0].f3[0].taken connect io.resp.f3[0].taken, columns_0.io.f3_pred node _columns_0_io_update_mispredict_T = bits(s1_update.bits.br_mask, 0, 0) node _columns_0_io_update_mispredict_T_1 = and(s1_update.valid, _columns_0_io_update_mispredict_T) node _columns_0_io_update_mispredict_T_2 = and(_columns_0_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_0_io_update_mispredict_T_3 = and(_columns_0_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_0.io.update_mispredict, _columns_0_io_update_mispredict_T_3 node _columns_0_io_update_repair_T = bits(s1_update.bits.br_mask, 0, 0) node _columns_0_io_update_repair_T_1 = and(s1_update.valid, _columns_0_io_update_repair_T) node _columns_0_io_update_repair_T_2 = and(_columns_0_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_0.io.update_repair, _columns_0_io_update_repair_T_2 connect columns_0.io.update_idx, s1_update_idx connect columns_0.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_0.io.update_meta.s_cnt, update_meta[0].s_cnt connect f3_meta[0], columns_0.io.f3_meta connect columns_1.io.f2_req_valid, s2_valid connect columns_1.io.f2_req_idx, s2_idx node _columns_1_io_f3_req_fire_T = bits(s3_mask, 1, 1) node _columns_1_io_f3_req_fire_T_1 = and(s3_valid, _columns_1_io_f3_req_fire_T) node _columns_1_io_f3_req_fire_T_2 = and(_columns_1_io_f3_req_fire_T_1, io.f3_fire) node _columns_1_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].is_br) reg columns_1_io_f3_req_fire_REG : UInt<1>, clock connect columns_1_io_f3_req_fire_REG, _columns_1_io_f3_req_fire_T_3 node _columns_1_io_f3_req_fire_T_4 = and(_columns_1_io_f3_req_fire_T_2, columns_1_io_f3_req_fire_REG) connect columns_1.io.f3_req_fire, _columns_1_io_f3_req_fire_T_4 connect columns_1.io.f3_pred_in, io.resp_in[0].f3[1].taken connect io.resp.f3[1].taken, columns_1.io.f3_pred node _columns_1_io_update_mispredict_T = bits(s1_update.bits.br_mask, 1, 1) node _columns_1_io_update_mispredict_T_1 = and(s1_update.valid, _columns_1_io_update_mispredict_T) node _columns_1_io_update_mispredict_T_2 = and(_columns_1_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_1_io_update_mispredict_T_3 = and(_columns_1_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_1.io.update_mispredict, _columns_1_io_update_mispredict_T_3 node _columns_1_io_update_repair_T = bits(s1_update.bits.br_mask, 1, 1) node _columns_1_io_update_repair_T_1 = and(s1_update.valid, _columns_1_io_update_repair_T) node _columns_1_io_update_repair_T_2 = and(_columns_1_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_1.io.update_repair, _columns_1_io_update_repair_T_2 connect columns_1.io.update_idx, s1_update_idx connect columns_1.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_1.io.update_meta.s_cnt, update_meta[1].s_cnt connect f3_meta[1], columns_1.io.f3_meta connect columns_2.io.f2_req_valid, s2_valid connect columns_2.io.f2_req_idx, s2_idx node _columns_2_io_f3_req_fire_T = bits(s3_mask, 2, 2) node _columns_2_io_f3_req_fire_T_1 = and(s3_valid, _columns_2_io_f3_req_fire_T) node _columns_2_io_f3_req_fire_T_2 = and(_columns_2_io_f3_req_fire_T_1, io.f3_fire) node _columns_2_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].is_br) reg columns_2_io_f3_req_fire_REG : UInt<1>, clock connect columns_2_io_f3_req_fire_REG, _columns_2_io_f3_req_fire_T_3 node _columns_2_io_f3_req_fire_T_4 = and(_columns_2_io_f3_req_fire_T_2, columns_2_io_f3_req_fire_REG) connect columns_2.io.f3_req_fire, _columns_2_io_f3_req_fire_T_4 connect columns_2.io.f3_pred_in, io.resp_in[0].f3[2].taken connect io.resp.f3[2].taken, columns_2.io.f3_pred node _columns_2_io_update_mispredict_T = bits(s1_update.bits.br_mask, 2, 2) node _columns_2_io_update_mispredict_T_1 = and(s1_update.valid, _columns_2_io_update_mispredict_T) node _columns_2_io_update_mispredict_T_2 = and(_columns_2_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_2_io_update_mispredict_T_3 = and(_columns_2_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_2.io.update_mispredict, _columns_2_io_update_mispredict_T_3 node _columns_2_io_update_repair_T = bits(s1_update.bits.br_mask, 2, 2) node _columns_2_io_update_repair_T_1 = and(s1_update.valid, _columns_2_io_update_repair_T) node _columns_2_io_update_repair_T_2 = and(_columns_2_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_2.io.update_repair, _columns_2_io_update_repair_T_2 connect columns_2.io.update_idx, s1_update_idx connect columns_2.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_2.io.update_meta.s_cnt, update_meta[2].s_cnt connect f3_meta[2], columns_2.io.f3_meta connect columns_3.io.f2_req_valid, s2_valid connect columns_3.io.f2_req_idx, s2_idx node _columns_3_io_f3_req_fire_T = bits(s3_mask, 3, 3) node _columns_3_io_f3_req_fire_T_1 = and(s3_valid, _columns_3_io_f3_req_fire_T) node _columns_3_io_f3_req_fire_T_2 = and(_columns_3_io_f3_req_fire_T_1, io.f3_fire) node _columns_3_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].is_br) reg columns_3_io_f3_req_fire_REG : UInt<1>, clock connect columns_3_io_f3_req_fire_REG, _columns_3_io_f3_req_fire_T_3 node _columns_3_io_f3_req_fire_T_4 = and(_columns_3_io_f3_req_fire_T_2, columns_3_io_f3_req_fire_REG) connect columns_3.io.f3_req_fire, _columns_3_io_f3_req_fire_T_4 connect columns_3.io.f3_pred_in, io.resp_in[0].f3[3].taken connect io.resp.f3[3].taken, columns_3.io.f3_pred node _columns_3_io_update_mispredict_T = bits(s1_update.bits.br_mask, 3, 3) node _columns_3_io_update_mispredict_T_1 = and(s1_update.valid, _columns_3_io_update_mispredict_T) node _columns_3_io_update_mispredict_T_2 = and(_columns_3_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_3_io_update_mispredict_T_3 = and(_columns_3_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_3.io.update_mispredict, _columns_3_io_update_mispredict_T_3 node _columns_3_io_update_repair_T = bits(s1_update.bits.br_mask, 3, 3) node _columns_3_io_update_repair_T_1 = and(s1_update.valid, _columns_3_io_update_repair_T) node _columns_3_io_update_repair_T_2 = and(_columns_3_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_3.io.update_repair, _columns_3_io_update_repair_T_2 connect columns_3.io.update_idx, s1_update_idx connect columns_3.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_3.io.update_meta.s_cnt, update_meta[3].s_cnt connect f3_meta[3], columns_3.io.f3_meta node io_f3_meta_lo = cat(f3_meta[1].s_cnt, f3_meta[0].s_cnt) node io_f3_meta_hi = cat(f3_meta[3].s_cnt, f3_meta[2].s_cnt) node _io_f3_meta_T = cat(io_f3_meta_hi, io_f3_meta_lo) connect io.f3_meta, _io_f3_meta_T	module LoopBranchPredictorBank_1( // @[loop.scala:20:7] input clock, // @[loop.scala:20:7] input reset, // @[loop.scala:20:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire io_f0_valid_0 = io_f0_valid; // @[loop.scala:20:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[loop.scala:20:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[loop.scala:20:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_f3_fire_0 = io_f3_fire; // @[loop.scala:20:7] wire io_update_valid_0 = io_update_valid; // @[loop.scala:20:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[loop.scala:20:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[loop.scala:20:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[loop.scala:20:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[loop.scala:20:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[loop.scala:20:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[loop.scala:20:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[loop.scala:20:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[loop.scala:20:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[loop.scala:20:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[loop.scala:20:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[loop.scala:20:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[loop.scala:20:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[loop.scala:20:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[loop.scala:20:7] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_taken_0; // @[loop.scala:20:7] wire io_resp_f3_1_taken_0; // @[loop.scala:20:7] wire io_resp_f3_2_taken_0; // @[loop.scala:20:7] wire io_resp_f3_3_taken_0; // @[loop.scala:20:7] wire [119:0] io_f3_meta_0; // @[loop.scala:20:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [36:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire [9:0] f3_meta_0_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_1_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_2_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_3_s_cnt; // @[loop.scala:184:21] wire [19:0] _GEN = {f3_meta_1_s_cnt, f3_meta_0_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] lo; // @[loop.scala:185:33] assign lo = _GEN; // @[loop.scala:185:33] wire [19:0] io_f3_meta_lo; // @[loop.scala:212:25] assign io_f3_meta_lo = _GEN; // @[loop.scala:185:33, :212:25] wire [19:0] _GEN_0 = {f3_meta_3_s_cnt, f3_meta_2_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] hi; // @[loop.scala:185:33] assign hi = _GEN_0; // @[loop.scala:185:33] wire [19:0] io_f3_meta_hi; // @[loop.scala:212:25] assign io_f3_meta_hi = _GEN_0; // @[loop.scala:185:33, :212:25] wire [9:0] _update_meta_T; // @[loop.scala:187:49] wire [9:0] _update_meta_T_1; // @[loop.scala:187:49] wire [9:0] _update_meta_T_2; // @[loop.scala:187:49] wire [9:0] _update_meta_T_3; // @[loop.scala:187:49] wire [9:0] update_meta_0_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_1_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_2_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_3_s_cnt; // @[loop.scala:187:49] wire [39:0] _update_meta_WIRE = s1_update_bits_meta[39:0]; // @[predictor.scala:184:30] assign _update_meta_T = _update_meta_WIRE[9:0]; // @[loop.scala:187:49] assign update_meta_0_s_cnt = _update_meta_T; // @[loop.scala:187:49] assign _update_meta_T_1 = _update_meta_WIRE[19:10]; // @[loop.scala:187:49] assign update_meta_1_s_cnt = _update_meta_T_1; // @[loop.scala:187:49] assign _update_meta_T_2 = _update_meta_WIRE[29:20]; // @[loop.scala:187:49] assign update_meta_2_s_cnt = _update_meta_T_2; // @[loop.scala:187:49] assign _update_meta_T_3 = _update_meta_WIRE[39:30]; // @[loop.scala:187:49] assign update_meta_3_s_cnt = _update_meta_T_3; // @[loop.scala:187:49] wire _columns_0_io_f3_req_fire_T = s3_mask[0]; // @[predictor.scala:175:24] wire _columns_0_io_f3_req_fire_T_1 = s3_valid & _columns_0_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_0_io_f3_req_fire_T_2 = _columns_0_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_0_io_f3_req_fire_T_3 = io_resp_in_0_f2_0_predicted_pc_valid_0 & io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_0_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_0_io_f3_req_fire_T_4 = _columns_0_io_f3_req_fire_T_2 & columns_0_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_0_io_update_mispredict_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_1 = s1_update_valid & _columns_0_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_2 = _columns_0_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_3 = _columns_0_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_1 = s1_update_valid & _columns_0_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_2 = _columns_0_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_1_io_f3_req_fire_T = s3_mask[1]; // @[predictor.scala:175:24] wire _columns_1_io_f3_req_fire_T_1 = s3_valid & _columns_1_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_1_io_f3_req_fire_T_2 = _columns_1_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_1_io_f3_req_fire_T_3 = io_resp_in_0_f2_1_predicted_pc_valid_0 & io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_1_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_1_io_f3_req_fire_T_4 = _columns_1_io_f3_req_fire_T_2 & columns_1_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_1_io_update_mispredict_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_1 = s1_update_valid & _columns_1_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_2 = _columns_1_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_3 = _columns_1_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_1 = s1_update_valid & _columns_1_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_2 = _columns_1_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_2_io_f3_req_fire_T = s3_mask[2]; // @[predictor.scala:175:24] wire _columns_2_io_f3_req_fire_T_1 = s3_valid & _columns_2_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_2_io_f3_req_fire_T_2 = _columns_2_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_2_io_f3_req_fire_T_3 = io_resp_in_0_f2_2_predicted_pc_valid_0 & io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_2_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_2_io_f3_req_fire_T_4 = _columns_2_io_f3_req_fire_T_2 & columns_2_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_2_io_update_mispredict_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_1 = s1_update_valid & _columns_2_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_2 = _columns_2_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_3 = _columns_2_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_1 = s1_update_valid & _columns_2_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_2 = _columns_2_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_3_io_f3_req_fire_T = s3_mask[3]; // @[predictor.scala:175:24] wire _columns_3_io_f3_req_fire_T_1 = s3_valid & _columns_3_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_3_io_f3_req_fire_T_2 = _columns_3_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_3_io_f3_req_fire_T_3 = io_resp_in_0_f2_3_predicted_pc_valid_0 & io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_3_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_3_io_f3_req_fire_T_4 = _columns_3_io_f3_req_fire_T_2 & columns_3_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_3_io_update_mispredict_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_1 = s1_update_valid & _columns_3_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_2 = _columns_3_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_3 = _columns_3_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_1 = s1_update_valid & _columns_3_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_2 = _columns_3_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire [39:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[loop.scala:212:25] assign io_f3_meta_0 = {80'h0, _io_f3_meta_T}; // @[loop.scala:20:7, :212:{14,25}] always @(posedge clock) begin // @[loop.scala:20:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] columns_0_io_f3_req_fire_REG <= _columns_0_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_1_io_f3_req_fire_REG <= _columns_1_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_2_io_f3_req_fire_REG <= _columns_2_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_3_io_f3_req_fire_REG <= _columns_3_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] always @(posedge) LoopBranchPredictorColumn_4 columns_0 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_0_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_0_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_0_taken_0), .io_f3_meta_s_cnt (f3_meta_0_s_cnt), .io_update_mispredict (_columns_0_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_0_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_0_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_5 columns_1 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_1_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_1_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_1_taken_0), .io_f3_meta_s_cnt (f3_meta_1_s_cnt), .io_update_mispredict (_columns_1_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_1_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_1_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_6 columns_2 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_2_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_2_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_2_taken_0), .io_f3_meta_s_cnt (f3_meta_2_s_cnt), .io_update_mispredict (_columns_2_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_2_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_2_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_7 columns_3 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_3_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_3_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_3_taken_0), .io_f3_meta_s_cnt (f3_meta_3_s_cnt), .io_update_mispredict (_columns_3_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_3_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_3_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_f3_meta = io_f3_meta_0; // @[loop.scala:20:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_22 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_22 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i1_e8_s24_22(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_22 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FPUUnit_1 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip fcsr_rm : UInt<3>} connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.sfence.bits.hg invalidate io.resp.bits.sfence.bits.hv invalidate io.resp.bits.sfence.bits.asid invalidate io.resp.bits.sfence.bits.addr invalidate io.resp.bits.sfence.bits.rs2 invalidate io.resp.bits.sfence.bits.rs1 invalidate io.resp.bits.sfence.valid invalidate io.resp.bits.mxcpt.bits invalidate io.resp.bits.mxcpt.valid invalidate io.resp.bits.addr invalidate io.resp.bits.fflags.bits.flags invalidate io.resp.bits.fflags.bits.uop.debug_tsrc invalidate io.resp.bits.fflags.bits.uop.debug_fsrc invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.resp.bits.fflags.bits.uop.bp_debug_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.resp.bits.fflags.bits.uop.fp_single invalidate io.resp.bits.fflags.bits.uop.fp_val invalidate io.resp.bits.fflags.bits.uop.frs3_en invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate io.resp.bits.fflags.bits.uop.dst_rtype invalidate io.resp.bits.fflags.bits.uop.ldst_val invalidate io.resp.bits.fflags.bits.uop.lrs3 invalidate io.resp.bits.fflags.bits.uop.lrs2 invalidate io.resp.bits.fflags.bits.uop.lrs1 invalidate io.resp.bits.fflags.bits.uop.ldst invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.resp.bits.fflags.bits.uop.flush_on_commit invalidate io.resp.bits.fflags.bits.uop.is_unique invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.resp.bits.fflags.bits.uop.uses_stq invalidate io.resp.bits.fflags.bits.uop.uses_ldq invalidate io.resp.bits.fflags.bits.uop.is_amo invalidate io.resp.bits.fflags.bits.uop.is_fencei invalidate io.resp.bits.fflags.bits.uop.is_fence invalidate io.resp.bits.fflags.bits.uop.mem_signed invalidate io.resp.bits.fflags.bits.uop.mem_size invalidate io.resp.bits.fflags.bits.uop.mem_cmd invalidate io.resp.bits.fflags.bits.uop.bypassable invalidate io.resp.bits.fflags.bits.uop.exc_cause invalidate io.resp.bits.fflags.bits.uop.exception invalidate io.resp.bits.fflags.bits.uop.stale_pdst invalidate io.resp.bits.fflags.bits.uop.ppred_busy invalidate io.resp.bits.fflags.bits.uop.prs3_busy invalidate io.resp.bits.fflags.bits.uop.prs2_busy invalidate io.resp.bits.fflags.bits.uop.prs1_busy invalidate io.resp.bits.fflags.bits.uop.ppred invalidate io.resp.bits.fflags.bits.uop.prs3 invalidate io.resp.bits.fflags.bits.uop.prs2 invalidate io.resp.bits.fflags.bits.uop.prs1 invalidate io.resp.bits.fflags.bits.uop.pdst invalidate io.resp.bits.fflags.bits.uop.rxq_idx invalidate io.resp.bits.fflags.bits.uop.stq_idx invalidate io.resp.bits.fflags.bits.uop.ldq_idx invalidate io.resp.bits.fflags.bits.uop.rob_idx invalidate io.resp.bits.fflags.bits.uop.csr_addr invalidate io.resp.bits.fflags.bits.uop.imm_packed invalidate io.resp.bits.fflags.bits.uop.taken invalidate io.resp.bits.fflags.bits.uop.pc_lob invalidate io.resp.bits.fflags.bits.uop.edge_inst invalidate io.resp.bits.fflags.bits.uop.ftq_idx invalidate io.resp.bits.fflags.bits.uop.br_tag invalidate io.resp.bits.fflags.bits.uop.br_mask invalidate io.resp.bits.fflags.bits.uop.is_sfb invalidate io.resp.bits.fflags.bits.uop.is_jal invalidate io.resp.bits.fflags.bits.uop.is_jalr invalidate io.resp.bits.fflags.bits.uop.is_br invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_state invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate io.resp.bits.fflags.bits.uop.fu_code invalidate io.resp.bits.fflags.bits.uop.iq_type invalidate io.resp.bits.fflags.bits.uop.debug_pc invalidate io.resp.bits.fflags.bits.uop.is_rvc invalidate io.resp.bits.fflags.bits.uop.debug_inst invalidate io.resp.bits.fflags.bits.uop.inst invalidate io.resp.bits.fflags.bits.uop.uopc invalidate io.resp.bits.fflags.valid invalidate io.resp.bits.data invalidate io.resp.bits.predicated invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.req.ready, UInt<1>(0h1) wire _r_valids_WIRE : UInt<1>[4] connect _r_valids_WIRE[0], UInt<1>(0h0) connect _r_valids_WIRE[1], UInt<1>(0h0) connect _r_valids_WIRE[2], UInt<1>(0h0) connect _r_valids_WIRE[3], UInt<1>(0h0) regreset r_valids : UInt<1>[4], clock, reset, _r_valids_WIRE reg r_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[4], clock node _r_valids_0_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _r_valids_0_T_1 = neq(_r_valids_0_T, UInt<1>(0h0)) node _r_valids_0_T_2 = eq(_r_valids_0_T_1, UInt<1>(0h0)) node _r_valids_0_T_3 = and(io.req.valid, _r_valids_0_T_2) node _r_valids_0_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_0_T_5 = and(_r_valids_0_T_3, _r_valids_0_T_4) connect r_valids[0], _r_valids_0_T_5 connect r_uops[0], io.req.bits.uop node _r_uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_0_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uops_0_br_mask_T) connect r_uops[0].br_mask, _r_uops_0_br_mask_T_1 node _r_valids_1_T = and(io.brupdate.b1.mispredict_mask, r_uops[0].br_mask) node _r_valids_1_T_1 = neq(_r_valids_1_T, UInt<1>(0h0)) node _r_valids_1_T_2 = eq(_r_valids_1_T_1, UInt<1>(0h0)) node _r_valids_1_T_3 = and(r_valids[0], _r_valids_1_T_2) node _r_valids_1_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_1_T_5 = and(_r_valids_1_T_3, _r_valids_1_T_4) connect r_valids[1], _r_valids_1_T_5 connect r_uops[1], r_uops[0] node _r_uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_1_br_mask_T_1 = and(r_uops[0].br_mask, _r_uops_1_br_mask_T) connect r_uops[1].br_mask, _r_uops_1_br_mask_T_1 node _r_valids_2_T = and(io.brupdate.b1.mispredict_mask, r_uops[1].br_mask) node _r_valids_2_T_1 = neq(_r_valids_2_T, UInt<1>(0h0)) node _r_valids_2_T_2 = eq(_r_valids_2_T_1, UInt<1>(0h0)) node _r_valids_2_T_3 = and(r_valids[1], _r_valids_2_T_2) node _r_valids_2_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_2_T_5 = and(_r_valids_2_T_3, _r_valids_2_T_4) connect r_valids[2], _r_valids_2_T_5 connect r_uops[2], r_uops[1] node _r_uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_2_br_mask_T_1 = and(r_uops[1].br_mask, _r_uops_2_br_mask_T) connect r_uops[2].br_mask, _r_uops_2_br_mask_T_1 node _r_valids_3_T = and(io.brupdate.b1.mispredict_mask, r_uops[2].br_mask) node _r_valids_3_T_1 = neq(_r_valids_3_T, UInt<1>(0h0)) node _r_valids_3_T_2 = eq(_r_valids_3_T_1, UInt<1>(0h0)) node _r_valids_3_T_3 = and(r_valids[2], _r_valids_3_T_2) node _r_valids_3_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_3_T_5 = and(_r_valids_3_T_3, _r_valids_3_T_4) connect r_valids[3], _r_valids_3_T_5 connect r_uops[3], r_uops[2] node _r_uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_3_br_mask_T_1 = and(r_uops[2].br_mask, _r_uops_3_br_mask_T) connect r_uops[3].br_mask, _r_uops_3_br_mask_T_1 node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_uops[3].br_mask) node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0)) node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0)) node _io_resp_valid_T_3 = and(r_valids[3], _io_resp_valid_T_2) connect io.resp.valid, _io_resp_valid_T_3 connect io.resp.bits.predicated, UInt<1>(0h0) connect io.resp.bits.uop, r_uops[3] node _io_resp_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_resp_bits_uop_br_mask_T_1 = and(r_uops[3].br_mask, _io_resp_bits_uop_br_mask_T) connect io.resp.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T_1 inst fpu of FPU_3 connect fpu.clock, clock connect fpu.reset, reset connect fpu.io.req.valid, io.req.valid connect fpu.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect fpu.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect fpu.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect fpu.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect fpu.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect fpu.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect fpu.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect fpu.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect fpu.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect fpu.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect fpu.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect fpu.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect fpu.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect fpu.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect fpu.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect fpu.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect fpu.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect fpu.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect fpu.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect fpu.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect fpu.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect fpu.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect fpu.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect fpu.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect fpu.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect fpu.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect fpu.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect fpu.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect fpu.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect fpu.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect fpu.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect fpu.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect fpu.io.req.bits.uop.exception, io.req.bits.uop.exception connect fpu.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect fpu.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect fpu.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect fpu.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect fpu.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect fpu.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect fpu.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect fpu.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect fpu.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect fpu.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect fpu.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect fpu.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect fpu.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect fpu.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect fpu.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect fpu.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect fpu.io.req.bits.uop.taken, io.req.bits.uop.taken connect fpu.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect fpu.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect fpu.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect fpu.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect fpu.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect fpu.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect fpu.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect fpu.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect fpu.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect fpu.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect fpu.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect fpu.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect fpu.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect fpu.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect fpu.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect fpu.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect fpu.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect fpu.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect fpu.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect fpu.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect fpu.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect fpu.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect fpu.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect fpu.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect fpu.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect fpu.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect fpu.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect fpu.io.req.bits.uop.inst, io.req.bits.uop.inst connect fpu.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect fpu.io.req.bits.rs1_data, io.req.bits.rs1_data connect fpu.io.req.bits.rs2_data, io.req.bits.rs2_data connect fpu.io.req.bits.rs3_data, io.req.bits.rs3_data connect fpu.io.req.bits.fcsr_rm, io.fcsr_rm connect io.resp.bits.data, fpu.io.resp.bits.data connect io.resp.bits.fflags.valid, fpu.io.resp.bits.fflags.valid connect io.resp.bits.fflags.bits.uop.debug_tsrc, io.resp.bits.uop.debug_tsrc connect io.resp.bits.fflags.bits.uop.debug_fsrc, io.resp.bits.uop.debug_fsrc connect io.resp.bits.fflags.bits.uop.bp_xcpt_if, io.resp.bits.uop.bp_xcpt_if connect io.resp.bits.fflags.bits.uop.bp_debug_if, io.resp.bits.uop.bp_debug_if connect io.resp.bits.fflags.bits.uop.xcpt_ma_if, io.resp.bits.uop.xcpt_ma_if connect io.resp.bits.fflags.bits.uop.xcpt_ae_if, io.resp.bits.uop.xcpt_ae_if connect io.resp.bits.fflags.bits.uop.xcpt_pf_if, io.resp.bits.uop.xcpt_pf_if connect io.resp.bits.fflags.bits.uop.fp_single, io.resp.bits.uop.fp_single connect io.resp.bits.fflags.bits.uop.fp_val, io.resp.bits.uop.fp_val connect io.resp.bits.fflags.bits.uop.frs3_en, io.resp.bits.uop.frs3_en connect io.resp.bits.fflags.bits.uop.lrs2_rtype, io.resp.bits.uop.lrs2_rtype connect io.resp.bits.fflags.bits.uop.lrs1_rtype, io.resp.bits.uop.lrs1_rtype connect io.resp.bits.fflags.bits.uop.dst_rtype, io.resp.bits.uop.dst_rtype connect io.resp.bits.fflags.bits.uop.ldst_val, io.resp.bits.uop.ldst_val connect io.resp.bits.fflags.bits.uop.lrs3, io.resp.bits.uop.lrs3 connect io.resp.bits.fflags.bits.uop.lrs2, io.resp.bits.uop.lrs2 connect io.resp.bits.fflags.bits.uop.lrs1, io.resp.bits.uop.lrs1 connect io.resp.bits.fflags.bits.uop.ldst, io.resp.bits.uop.ldst connect io.resp.bits.fflags.bits.uop.ldst_is_rs1, io.resp.bits.uop.ldst_is_rs1 connect io.resp.bits.fflags.bits.uop.flush_on_commit, io.resp.bits.uop.flush_on_commit connect io.resp.bits.fflags.bits.uop.is_unique, io.resp.bits.uop.is_unique connect io.resp.bits.fflags.bits.uop.is_sys_pc2epc, io.resp.bits.uop.is_sys_pc2epc connect io.resp.bits.fflags.bits.uop.uses_stq, io.resp.bits.uop.uses_stq connect io.resp.bits.fflags.bits.uop.uses_ldq, io.resp.bits.uop.uses_ldq connect io.resp.bits.fflags.bits.uop.is_amo, io.resp.bits.uop.is_amo connect io.resp.bits.fflags.bits.uop.is_fencei, io.resp.bits.uop.is_fencei connect io.resp.bits.fflags.bits.uop.is_fence, io.resp.bits.uop.is_fence connect io.resp.bits.fflags.bits.uop.mem_signed, io.resp.bits.uop.mem_signed connect io.resp.bits.fflags.bits.uop.mem_size, io.resp.bits.uop.mem_size connect io.resp.bits.fflags.bits.uop.mem_cmd, io.resp.bits.uop.mem_cmd connect io.resp.bits.fflags.bits.uop.bypassable, io.resp.bits.uop.bypassable connect io.resp.bits.fflags.bits.uop.exc_cause, io.resp.bits.uop.exc_cause connect io.resp.bits.fflags.bits.uop.exception, io.resp.bits.uop.exception connect io.resp.bits.fflags.bits.uop.stale_pdst, io.resp.bits.uop.stale_pdst connect io.resp.bits.fflags.bits.uop.ppred_busy, io.resp.bits.uop.ppred_busy connect io.resp.bits.fflags.bits.uop.prs3_busy, io.resp.bits.uop.prs3_busy connect io.resp.bits.fflags.bits.uop.prs2_busy, io.resp.bits.uop.prs2_busy connect io.resp.bits.fflags.bits.uop.prs1_busy, io.resp.bits.uop.prs1_busy connect io.resp.bits.fflags.bits.uop.ppred, io.resp.bits.uop.ppred connect io.resp.bits.fflags.bits.uop.prs3, io.resp.bits.uop.prs3 connect io.resp.bits.fflags.bits.uop.prs2, io.resp.bits.uop.prs2 connect io.resp.bits.fflags.bits.uop.prs1, io.resp.bits.uop.prs1 connect io.resp.bits.fflags.bits.uop.pdst, io.resp.bits.uop.pdst connect io.resp.bits.fflags.bits.uop.rxq_idx, io.resp.bits.uop.rxq_idx connect io.resp.bits.fflags.bits.uop.stq_idx, io.resp.bits.uop.stq_idx connect io.resp.bits.fflags.bits.uop.ldq_idx, io.resp.bits.uop.ldq_idx connect io.resp.bits.fflags.bits.uop.rob_idx, io.resp.bits.uop.rob_idx connect io.resp.bits.fflags.bits.uop.csr_addr, io.resp.bits.uop.csr_addr connect io.resp.bits.fflags.bits.uop.imm_packed, io.resp.bits.uop.imm_packed connect io.resp.bits.fflags.bits.uop.taken, io.resp.bits.uop.taken connect io.resp.bits.fflags.bits.uop.pc_lob, io.resp.bits.uop.pc_lob connect io.resp.bits.fflags.bits.uop.edge_inst, io.resp.bits.uop.edge_inst connect io.resp.bits.fflags.bits.uop.ftq_idx, io.resp.bits.uop.ftq_idx connect io.resp.bits.fflags.bits.uop.br_tag, io.resp.bits.uop.br_tag connect io.resp.bits.fflags.bits.uop.br_mask, io.resp.bits.uop.br_mask connect io.resp.bits.fflags.bits.uop.is_sfb, io.resp.bits.uop.is_sfb connect io.resp.bits.fflags.bits.uop.is_jal, io.resp.bits.uop.is_jal connect io.resp.bits.fflags.bits.uop.is_jalr, io.resp.bits.uop.is_jalr connect io.resp.bits.fflags.bits.uop.is_br, io.resp.bits.uop.is_br connect io.resp.bits.fflags.bits.uop.iw_p2_poisoned, io.resp.bits.uop.iw_p2_poisoned connect io.resp.bits.fflags.bits.uop.iw_p1_poisoned, io.resp.bits.uop.iw_p1_poisoned connect io.resp.bits.fflags.bits.uop.iw_state, io.resp.bits.uop.iw_state connect io.resp.bits.fflags.bits.uop.ctrl.is_std, io.resp.bits.uop.ctrl.is_std connect io.resp.bits.fflags.bits.uop.ctrl.is_sta, io.resp.bits.uop.ctrl.is_sta connect io.resp.bits.fflags.bits.uop.ctrl.is_load, io.resp.bits.uop.ctrl.is_load connect io.resp.bits.fflags.bits.uop.ctrl.csr_cmd, io.resp.bits.uop.ctrl.csr_cmd connect io.resp.bits.fflags.bits.uop.ctrl.fcn_dw, io.resp.bits.uop.ctrl.fcn_dw connect io.resp.bits.fflags.bits.uop.ctrl.op_fcn, io.resp.bits.uop.ctrl.op_fcn connect io.resp.bits.fflags.bits.uop.ctrl.imm_sel, io.resp.bits.uop.ctrl.imm_sel connect io.resp.bits.fflags.bits.uop.ctrl.op2_sel, io.resp.bits.uop.ctrl.op2_sel connect io.resp.bits.fflags.bits.uop.ctrl.op1_sel, io.resp.bits.uop.ctrl.op1_sel connect io.resp.bits.fflags.bits.uop.ctrl.br_type, io.resp.bits.uop.ctrl.br_type connect io.resp.bits.fflags.bits.uop.fu_code, io.resp.bits.uop.fu_code connect io.resp.bits.fflags.bits.uop.iq_type, io.resp.bits.uop.iq_type connect io.resp.bits.fflags.bits.uop.debug_pc, io.resp.bits.uop.debug_pc connect io.resp.bits.fflags.bits.uop.is_rvc, io.resp.bits.uop.is_rvc connect io.resp.bits.fflags.bits.uop.debug_inst, io.resp.bits.uop.debug_inst connect io.resp.bits.fflags.bits.uop.inst, io.resp.bits.uop.inst connect io.resp.bits.fflags.bits.uop.uopc, io.resp.bits.uop.uopc connect io.resp.bits.fflags.bits.flags, fpu.io.resp.bits.fflags.bits.flags	module FPUUnit_1( // @[functional-unit.scala:564:7] input clock, // @[functional-unit.scala:564:7] input reset, // @[functional-unit.scala:564:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs3_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:564:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:564:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:564:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:564:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:564:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:564:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:564:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:564:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:564:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:564:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:564:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:564:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:564:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:564:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:564:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:564:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:564:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:564:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:564:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:564:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:564:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:564:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:564:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:564:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:564:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:564:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:564:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:564:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:564:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:564:7] wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[functional-unit.scala:564:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:564:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:564:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:564:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:564:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:564:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:564:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:564:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:564:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:564:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:564:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:564:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:564:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:564:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:564:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:564:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:564:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:564:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:564:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:564:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:564:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:564:7] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:564:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:564:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_2 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_3 = 1'h0; // @[functional-unit.scala:236:35] wire io_req_ready = 1'h1; // @[functional-unit.scala:564:7] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] wire [15:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:564:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:564:7] wire io_resp_valid_0; // @[functional-unit.scala:564:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg r_valids_2; // @[functional-unit.scala:236:27] reg r_valids_3; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_1_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_1_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_2_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_2_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_2_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_2_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_2_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_iw_state; // @[functional-unit.scala:237:23] reg r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_2_is_br; // @[functional-unit.scala:237:23] reg r_uops_2_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_2_is_jal; // @[functional-unit.scala:237:23] reg r_uops_2_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_2_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_2_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_2_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_2_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_2_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_2_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ppred; // @[functional-unit.scala:237:23] reg r_uops_2_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_2_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_2_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_2_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_2_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_2_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_2_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_mem_size; // @[functional-unit.scala:237:23] reg r_uops_2_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_2_is_fence; // @[functional-unit.scala:237:23] reg r_uops_2_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_2_is_amo; // @[functional-unit.scala:237:23] reg r_uops_2_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_2_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_2_is_unique; // @[functional-unit.scala:237:23] reg r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_lrs3; // @[functional-unit.scala:237:23] reg r_uops_2_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_2_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_2_fp_val; // @[functional-unit.scala:237:23] reg r_uops_2_fp_single; // @[functional-unit.scala:237:23] reg r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_3_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_3_uopc; // @[functional-unit.scala:237:23, :564:7] reg [31:0] r_uops_3_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_3_inst; // @[functional-unit.scala:237:23, :564:7] reg [31:0] r_uops_3_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_3_debug_inst; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_3_is_rvc; // @[functional-unit.scala:237:23, :564:7] reg [39:0] r_uops_3_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_3_debug_pc; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_3_iq_type; // @[functional-unit.scala:237:23, :564:7] reg [9:0] r_uops_3_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_3_fu_code; // @[functional-unit.scala:237:23, :564:7] reg [3:0] r_uops_3_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_3_ctrl_br_type; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_3_ctrl_op1_sel; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_3_ctrl_op2_sel; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_3_ctrl_imm_sel; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_3_ctrl_op_fcn; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_3_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_3_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_3_ctrl_is_load; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_3_ctrl_is_sta; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_3_ctrl_is_std; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_3_iw_state; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_3_iw_p1_poisoned; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_3_iw_p2_poisoned; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_3_is_br; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_3_is_jalr; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_3_is_jal; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_3_is_sfb; // @[functional-unit.scala:237:23, :564:7] reg [15:0] r_uops_3_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_3_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_3_br_tag; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_3_ftq_idx; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_3_edge_inst; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_3_pc_lob; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_3_taken; // @[functional-unit.scala:237:23, :564:7] reg [19:0] r_uops_3_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_3_imm_packed; // @[functional-unit.scala:237:23, :564:7] reg [11:0] r_uops_3_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_3_csr_addr; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_3_rob_idx; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_3_ldq_idx; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_3_stq_idx; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_3_rxq_idx; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_3_pdst; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_3_prs1; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_3_prs2; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_3_prs3; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_3_ppred; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_3_prs1_busy; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_3_prs2_busy; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_3_prs3_busy; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_3_ppred_busy; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_3_stale_pdst; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_3_exception; // @[functional-unit.scala:237:23, :564:7] reg [63:0] r_uops_3_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_3_exc_cause; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_3_bypassable; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_3_mem_cmd; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_3_mem_size; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_3_mem_signed; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_3_is_fence; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_3_is_fencei; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_3_is_amo; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_3_uses_ldq; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_3_uses_stq; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_3_is_sys_pc2epc; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_3_is_unique; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_3_flush_on_commit; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_3_ldst_is_rs1; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_3_ldst; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_3_lrs1; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_3_lrs2; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_3_lrs3; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_3_ldst_val; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_3_dst_rtype; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_3_lrs1_rtype; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_3_lrs2_rtype; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_3_frs3_en; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_3_fp_val; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_3_fp_single; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_3_xcpt_pf_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_3_xcpt_ae_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_3_xcpt_ma_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_3_bp_debug_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_3_bp_xcpt_if; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_3_debug_fsrc; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_3_debug_tsrc; // @[functional-unit.scala:237:23, :564:7] wire [15:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = \|_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :564:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :564:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [15:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = \|_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_2_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _r_valids_2_T_1 = \|_r_valids_2_T; // @[util.scala:118:{51,59}] wire _r_valids_2_T_2 = ~_r_valids_2_T_1; // @[util.scala:118:59] wire _r_valids_2_T_3 = r_valids_1 & _r_valids_2_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_2_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7] wire _r_valids_2_T_5 = _r_valids_2_T_3 & _r_valids_2_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_2_br_mask_T_1 = r_uops_1_br_mask & _r_uops_2_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_3_T = io_brupdate_b1_mispredict_mask_0 & r_uops_2_br_mask; // @[util.scala:118:51] wire _r_valids_3_T_1 = \|_r_valids_3_T; // @[util.scala:118:{51,59}] wire _r_valids_3_T_2 = ~_r_valids_3_T_1; // @[util.scala:118:59] wire _r_valids_3_T_3 = r_valids_2 & _r_valids_3_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_3_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7] wire _r_valids_3_T_5 = _r_valids_3_T_3 & _r_valids_3_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_3_br_mask_T_1 = r_uops_2_br_mask & _r_uops_3_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_3_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = \|_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_3 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :564:7] wire [15:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_3_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] always @(posedge clock) begin // @[functional-unit.scala:564:7] if (reset) begin // @[functional-unit.scala:564:7] r_valids_0 <= 1'h0; // @[functional-unit.scala:236:27] r_valids_1 <= 1'h0; // @[functional-unit.scala:236:27] r_valids_2 <= 1'h0; // @[functional-unit.scala:236:27] r_valids_3 <= 1'h0; // @[functional-unit.scala:236:27] end else begin // @[functional-unit.scala:564:7] r_valids_0 <= _r_valids_0_T_5; // @[functional-unit.scala:236:27, :240:84] r_valids_1 <= _r_valids_1_T_5; // @[functional-unit.scala:236:27, :246:83] r_valids_2 <= _r_valids_2_T_5; // @[functional-unit.scala:236:27, :246:83] r_valids_3 <= _r_valids_3_T_5; // @[functional-unit.scala:236:27, :246:83] end r_uops_0_uopc <= io_req_bits_uop_uopc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_inst <= io_req_bits_uop_inst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_inst <= io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_rvc <= io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_pc <= io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iq_type <= io_req_bits_uop_iq_type_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_fu_code <= io_req_bits_uop_fu_code_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_br_type <= io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_is_load <= io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_is_std <= io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iw_state <= io_req_bits_uop_iw_state_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_br <= io_req_bits_uop_is_br_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_jalr <= io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_jal <= io_req_bits_uop_is_jal_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_sfb <= io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_br_mask <= _r_uops_0_br_mask_T_1; // @[util.scala:85:25] r_uops_0_br_tag <= io_req_bits_uop_br_tag_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ftq_idx <= io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_edge_inst <= io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_pc_lob <= io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_taken <= io_req_bits_uop_taken_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_imm_packed <= io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_csr_addr <= io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_rob_idx <= io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldq_idx <= io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_stq_idx <= io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_rxq_idx <= io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_pdst <= io_req_bits_uop_pdst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs1 <= io_req_bits_uop_prs1_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs2 <= io_req_bits_uop_prs2_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs3 <= io_req_bits_uop_prs3_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ppred <= io_req_bits_uop_ppred_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs1_busy <= io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs2_busy <= io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs3_busy <= io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ppred_busy <= io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_stale_pdst <= io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_exception <= io_req_bits_uop_exception_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_exc_cause <= io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_bypassable <= io_req_bits_uop_bypassable_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_mem_cmd <= io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_mem_size <= io_req_bits_uop_mem_size_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_mem_signed <= io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_fence <= io_req_bits_uop_is_fence_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_fencei <= io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_amo <= io_req_bits_uop_is_amo_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_uses_ldq <= io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_uses_stq <= io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_unique <= io_req_bits_uop_is_unique_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_flush_on_commit <= io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldst <= io_req_bits_uop_ldst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs1 <= io_req_bits_uop_lrs1_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs2 <= io_req_bits_uop_lrs2_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs3 <= io_req_bits_uop_lrs3_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldst_val <= io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_dst_rtype <= io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs1_rtype <= io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs2_rtype <= io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_frs3_en <= io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_fp_val <= io_req_bits_uop_fp_val_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_fp_single <= io_req_bits_uop_fp_single_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_bp_debug_if <= io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_fsrc <= io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_tsrc <= io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_1_uopc <= r_uops_0_uopc; // @[functional-unit.scala:237:23] r_uops_1_inst <= r_uops_0_inst; // @[functional-unit.scala:237:23] r_uops_1_debug_inst <= r_uops_0_debug_inst; // @[functional-unit.scala:237:23] r_uops_1_is_rvc <= r_uops_0_is_rvc; // @[functional-unit.scala:237:23] r_uops_1_debug_pc <= r_uops_0_debug_pc; // @[functional-unit.scala:237:23] r_uops_1_iq_type <= r_uops_0_iq_type; // @[functional-unit.scala:237:23] r_uops_1_fu_code <= r_uops_0_fu_code; // @[functional-unit.scala:237:23] r_uops_1_ctrl_br_type <= r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] r_uops_1_ctrl_op1_sel <= r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] r_uops_1_ctrl_op2_sel <= r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] r_uops_1_ctrl_imm_sel <= r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] r_uops_1_ctrl_op_fcn <= r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] r_uops_1_ctrl_fcn_dw <= r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] r_uops_1_ctrl_csr_cmd <= r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] r_uops_1_ctrl_is_load <= r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] r_uops_1_ctrl_is_sta <= r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] r_uops_1_ctrl_is_std <= r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] r_uops_1_iw_state <= r_uops_0_iw_state; // @[functional-unit.scala:237:23] r_uops_1_iw_p1_poisoned <= r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] r_uops_1_iw_p2_poisoned <= r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] r_uops_1_is_br <= r_uops_0_is_br; // @[functional-unit.scala:237:23] r_uops_1_is_jalr <= r_uops_0_is_jalr; // @[functional-unit.scala:237:23] r_uops_1_is_jal <= r_uops_0_is_jal; // @[functional-unit.scala:237:23] r_uops_1_is_sfb <= r_uops_0_is_sfb; // @[functional-unit.scala:237:23] r_uops_1_br_mask <= _r_uops_1_br_mask_T_1; // @[util.scala:85:25] r_uops_1_br_tag <= r_uops_0_br_tag; // @[functional-unit.scala:237:23] r_uops_1_ftq_idx <= r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] r_uops_1_edge_inst <= r_uops_0_edge_inst; // @[functional-unit.scala:237:23] r_uops_1_pc_lob <= r_uops_0_pc_lob; // @[functional-unit.scala:237:23] r_uops_1_taken <= r_uops_0_taken; // @[functional-unit.scala:237:23] r_uops_1_imm_packed <= r_uops_0_imm_packed; // @[functional-unit.scala:237:23] r_uops_1_csr_addr <= r_uops_0_csr_addr; // @[functional-unit.scala:237:23] r_uops_1_rob_idx <= r_uops_0_rob_idx; // @[functional-unit.scala:237:23] r_uops_1_ldq_idx <= r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] r_uops_1_stq_idx <= r_uops_0_stq_idx; // @[functional-unit.scala:237:23] r_uops_1_rxq_idx <= r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] r_uops_1_pdst <= r_uops_0_pdst; // @[functional-unit.scala:237:23] r_uops_1_prs1 <= r_uops_0_prs1; // @[functional-unit.scala:237:23] r_uops_1_prs2 <= r_uops_0_prs2; // @[functional-unit.scala:237:23] r_uops_1_prs3 <= r_uops_0_prs3; // @[functional-unit.scala:237:23] r_uops_1_ppred <= r_uops_0_ppred; // @[functional-unit.scala:237:23] r_uops_1_prs1_busy <= r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] r_uops_1_prs2_busy <= r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] r_uops_1_prs3_busy <= r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] r_uops_1_ppred_busy <= r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] r_uops_1_stale_pdst <= r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] r_uops_1_exception <= r_uops_0_exception; // @[functional-unit.scala:237:23] r_uops_1_exc_cause <= r_uops_0_exc_cause; // @[functional-unit.scala:237:23] r_uops_1_bypassable <= r_uops_0_bypassable; // @[functional-unit.scala:237:23] r_uops_1_mem_cmd <= r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] r_uops_1_mem_size <= r_uops_0_mem_size; // @[functional-unit.scala:237:23] r_uops_1_mem_signed <= r_uops_0_mem_signed; // @[functional-unit.scala:237:23] r_uops_1_is_fence <= r_uops_0_is_fence; // @[functional-unit.scala:237:23] r_uops_1_is_fencei <= r_uops_0_is_fencei; // @[functional-unit.scala:237:23] r_uops_1_is_amo <= r_uops_0_is_amo; // @[functional-unit.scala:237:23] r_uops_1_uses_ldq <= r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] r_uops_1_uses_stq <= r_uops_0_uses_stq; // @[functional-unit.scala:237:23] r_uops_1_is_sys_pc2epc <= r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] r_uops_1_is_unique <= r_uops_0_is_unique; // @[functional-unit.scala:237:23] r_uops_1_flush_on_commit <= r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] r_uops_1_ldst_is_rs1 <= r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] r_uops_1_ldst <= r_uops_0_ldst; // @[functional-unit.scala:237:23] r_uops_1_lrs1 <= r_uops_0_lrs1; // @[functional-unit.scala:237:23] r_uops_1_lrs2 <= r_uops_0_lrs2; // @[functional-unit.scala:237:23] r_uops_1_lrs3 <= r_uops_0_lrs3; // @[functional-unit.scala:237:23] r_uops_1_ldst_val <= r_uops_0_ldst_val; // @[functional-unit.scala:237:23] r_uops_1_dst_rtype <= r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] r_uops_1_lrs1_rtype <= r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] r_uops_1_lrs2_rtype <= r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] r_uops_1_frs3_en <= r_uops_0_frs3_en; // @[functional-unit.scala:237:23] r_uops_1_fp_val <= r_uops_0_fp_val; // @[functional-unit.scala:237:23] r_uops_1_fp_single <= r_uops_0_fp_single; // @[functional-unit.scala:237:23] r_uops_1_xcpt_pf_if <= r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] r_uops_1_xcpt_ae_if <= r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] r_uops_1_xcpt_ma_if <= r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] r_uops_1_bp_debug_if <= r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] r_uops_1_bp_xcpt_if <= r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] r_uops_1_debug_fsrc <= r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] r_uops_1_debug_tsrc <= r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] r_uops_2_uopc <= r_uops_1_uopc; // @[functional-unit.scala:237:23] r_uops_2_inst <= r_uops_1_inst; // @[functional-unit.scala:237:23] r_uops_2_debug_inst <= r_uops_1_debug_inst; // @[functional-unit.scala:237:23] r_uops_2_is_rvc <= r_uops_1_is_rvc; // @[functional-unit.scala:237:23] r_uops_2_debug_pc <= r_uops_1_debug_pc; // @[functional-unit.scala:237:23] r_uops_2_iq_type <= r_uops_1_iq_type; // @[functional-unit.scala:237:23] r_uops_2_fu_code <= r_uops_1_fu_code; // @[functional-unit.scala:237:23] r_uops_2_ctrl_br_type <= r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] r_uops_2_ctrl_op1_sel <= r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] r_uops_2_ctrl_op2_sel <= r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] r_uops_2_ctrl_imm_sel <= r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] r_uops_2_ctrl_op_fcn <= r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] r_uops_2_ctrl_fcn_dw <= r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] r_uops_2_ctrl_csr_cmd <= r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] r_uops_2_ctrl_is_load <= r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] r_uops_2_ctrl_is_sta <= r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] r_uops_2_ctrl_is_std <= r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] r_uops_2_iw_state <= r_uops_1_iw_state; // @[functional-unit.scala:237:23] r_uops_2_iw_p1_poisoned <= r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] r_uops_2_iw_p2_poisoned <= r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] r_uops_2_is_br <= r_uops_1_is_br; // @[functional-unit.scala:237:23] r_uops_2_is_jalr <= r_uops_1_is_jalr; // @[functional-unit.scala:237:23] r_uops_2_is_jal <= r_uops_1_is_jal; // @[functional-unit.scala:237:23] r_uops_2_is_sfb <= r_uops_1_is_sfb; // @[functional-unit.scala:237:23] r_uops_2_br_mask <= _r_uops_2_br_mask_T_1; // @[util.scala:85:25] r_uops_2_br_tag <= r_uops_1_br_tag; // @[functional-unit.scala:237:23] r_uops_2_ftq_idx <= r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] r_uops_2_edge_inst <= r_uops_1_edge_inst; // @[functional-unit.scala:237:23] r_uops_2_pc_lob <= r_uops_1_pc_lob; // @[functional-unit.scala:237:23] r_uops_2_taken <= r_uops_1_taken; // @[functional-unit.scala:237:23] r_uops_2_imm_packed <= r_uops_1_imm_packed; // @[functional-unit.scala:237:23] r_uops_2_csr_addr <= r_uops_1_csr_addr; // @[functional-unit.scala:237:23] r_uops_2_rob_idx <= r_uops_1_rob_idx; // @[functional-unit.scala:237:23] r_uops_2_ldq_idx <= r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] r_uops_2_stq_idx <= r_uops_1_stq_idx; // @[functional-unit.scala:237:23] r_uops_2_rxq_idx <= r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] r_uops_2_pdst <= r_uops_1_pdst; // @[functional-unit.scala:237:23] r_uops_2_prs1 <= r_uops_1_prs1; // @[functional-unit.scala:237:23] r_uops_2_prs2 <= r_uops_1_prs2; // @[functional-unit.scala:237:23] r_uops_2_prs3 <= r_uops_1_prs3; // @[functional-unit.scala:237:23] r_uops_2_ppred <= r_uops_1_ppred; // @[functional-unit.scala:237:23] r_uops_2_prs1_busy <= r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] r_uops_2_prs2_busy <= r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] r_uops_2_prs3_busy <= r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] r_uops_2_ppred_busy <= r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] r_uops_2_stale_pdst <= r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] r_uops_2_exception <= r_uops_1_exception; // @[functional-unit.scala:237:23] r_uops_2_exc_cause <= r_uops_1_exc_cause; // @[functional-unit.scala:237:23] r_uops_2_bypassable <= r_uops_1_bypassable; // @[functional-unit.scala:237:23] r_uops_2_mem_cmd <= r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] r_uops_2_mem_size <= r_uops_1_mem_size; // @[functional-unit.scala:237:23] r_uops_2_mem_signed <= r_uops_1_mem_signed; // @[functional-unit.scala:237:23] r_uops_2_is_fence <= r_uops_1_is_fence; // @[functional-unit.scala:237:23] r_uops_2_is_fencei <= r_uops_1_is_fencei; // @[functional-unit.scala:237:23] r_uops_2_is_amo <= r_uops_1_is_amo; // @[functional-unit.scala:237:23] r_uops_2_uses_ldq <= r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] r_uops_2_uses_stq <= r_uops_1_uses_stq; // @[functional-unit.scala:237:23] r_uops_2_is_sys_pc2epc <= r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] r_uops_2_is_unique <= r_uops_1_is_unique; // @[functional-unit.scala:237:23] r_uops_2_flush_on_commit <= r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] r_uops_2_ldst_is_rs1 <= r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] r_uops_2_ldst <= r_uops_1_ldst; // @[functional-unit.scala:237:23] r_uops_2_lrs1 <= r_uops_1_lrs1; // @[functional-unit.scala:237:23] r_uops_2_lrs2 <= r_uops_1_lrs2; // @[functional-unit.scala:237:23] r_uops_2_lrs3 <= r_uops_1_lrs3; // @[functional-unit.scala:237:23] r_uops_2_ldst_val <= r_uops_1_ldst_val; // @[functional-unit.scala:237:23] r_uops_2_dst_rtype <= r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] r_uops_2_lrs1_rtype <= r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] r_uops_2_lrs2_rtype <= r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] r_uops_2_frs3_en <= r_uops_1_frs3_en; // @[functional-unit.scala:237:23] r_uops_2_fp_val <= r_uops_1_fp_val; // @[functional-unit.scala:237:23] r_uops_2_fp_single <= r_uops_1_fp_single; // @[functional-unit.scala:237:23] r_uops_2_xcpt_pf_if <= r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] r_uops_2_xcpt_ae_if <= r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] r_uops_2_xcpt_ma_if <= r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] r_uops_2_bp_debug_if <= r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] r_uops_2_bp_xcpt_if <= r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] r_uops_2_debug_fsrc <= r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] r_uops_2_debug_tsrc <= r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] r_uops_3_uopc <= r_uops_2_uopc; // @[functional-unit.scala:237:23] r_uops_3_inst <= r_uops_2_inst; // @[functional-unit.scala:237:23] r_uops_3_debug_inst <= r_uops_2_debug_inst; // @[functional-unit.scala:237:23] r_uops_3_is_rvc <= r_uops_2_is_rvc; // @[functional-unit.scala:237:23] r_uops_3_debug_pc <= r_uops_2_debug_pc; // @[functional-unit.scala:237:23] r_uops_3_iq_type <= r_uops_2_iq_type; // @[functional-unit.scala:237:23] r_uops_3_fu_code <= r_uops_2_fu_code; // @[functional-unit.scala:237:23] r_uops_3_ctrl_br_type <= r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23] r_uops_3_ctrl_op1_sel <= r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23] r_uops_3_ctrl_op2_sel <= r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23] r_uops_3_ctrl_imm_sel <= r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23] r_uops_3_ctrl_op_fcn <= r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23] r_uops_3_ctrl_fcn_dw <= r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23] r_uops_3_ctrl_csr_cmd <= r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23] r_uops_3_ctrl_is_load <= r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23] r_uops_3_ctrl_is_sta <= r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23] r_uops_3_ctrl_is_std <= r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23] r_uops_3_iw_state <= r_uops_2_iw_state; // @[functional-unit.scala:237:23] r_uops_3_iw_p1_poisoned <= r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23] r_uops_3_iw_p2_poisoned <= r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23] r_uops_3_is_br <= r_uops_2_is_br; // @[functional-unit.scala:237:23] r_uops_3_is_jalr <= r_uops_2_is_jalr; // @[functional-unit.scala:237:23] r_uops_3_is_jal <= r_uops_2_is_jal; // @[functional-unit.scala:237:23] r_uops_3_is_sfb <= r_uops_2_is_sfb; // @[functional-unit.scala:237:23] r_uops_3_br_mask <= _r_uops_3_br_mask_T_1; // @[util.scala:85:25] r_uops_3_br_tag <= r_uops_2_br_tag; // @[functional-unit.scala:237:23] r_uops_3_ftq_idx <= r_uops_2_ftq_idx; // @[functional-unit.scala:237:23] r_uops_3_edge_inst <= r_uops_2_edge_inst; // @[functional-unit.scala:237:23] r_uops_3_pc_lob <= r_uops_2_pc_lob; // @[functional-unit.scala:237:23] r_uops_3_taken <= r_uops_2_taken; // @[functional-unit.scala:237:23] r_uops_3_imm_packed <= r_uops_2_imm_packed; // @[functional-unit.scala:237:23] r_uops_3_csr_addr <= r_uops_2_csr_addr; // @[functional-unit.scala:237:23] r_uops_3_rob_idx <= r_uops_2_rob_idx; // @[functional-unit.scala:237:23] r_uops_3_ldq_idx <= r_uops_2_ldq_idx; // @[functional-unit.scala:237:23] r_uops_3_stq_idx <= r_uops_2_stq_idx; // @[functional-unit.scala:237:23] r_uops_3_rxq_idx <= r_uops_2_rxq_idx; // @[functional-unit.scala:237:23] r_uops_3_pdst <= r_uops_2_pdst; // @[functional-unit.scala:237:23] r_uops_3_prs1 <= r_uops_2_prs1; // @[functional-unit.scala:237:23] r_uops_3_prs2 <= r_uops_2_prs2; // @[functional-unit.scala:237:23] r_uops_3_prs3 <= r_uops_2_prs3; // @[functional-unit.scala:237:23] r_uops_3_ppred <= r_uops_2_ppred; // @[functional-unit.scala:237:23] r_uops_3_prs1_busy <= r_uops_2_prs1_busy; // @[functional-unit.scala:237:23] r_uops_3_prs2_busy <= r_uops_2_prs2_busy; // @[functional-unit.scala:237:23] r_uops_3_prs3_busy <= r_uops_2_prs3_busy; // @[functional-unit.scala:237:23] r_uops_3_ppred_busy <= r_uops_2_ppred_busy; // @[functional-unit.scala:237:23] r_uops_3_stale_pdst <= r_uops_2_stale_pdst; // @[functional-unit.scala:237:23] r_uops_3_exception <= r_uops_2_exception; // @[functional-unit.scala:237:23] r_uops_3_exc_cause <= r_uops_2_exc_cause; // @[functional-unit.scala:237:23] r_uops_3_bypassable <= r_uops_2_bypassable; // @[functional-unit.scala:237:23] r_uops_3_mem_cmd <= r_uops_2_mem_cmd; // @[functional-unit.scala:237:23] r_uops_3_mem_size <= r_uops_2_mem_size; // @[functional-unit.scala:237:23] r_uops_3_mem_signed <= r_uops_2_mem_signed; // @[functional-unit.scala:237:23] r_uops_3_is_fence <= r_uops_2_is_fence; // @[functional-unit.scala:237:23] r_uops_3_is_fencei <= r_uops_2_is_fencei; // @[functional-unit.scala:237:23] r_uops_3_is_amo <= r_uops_2_is_amo; // @[functional-unit.scala:237:23] r_uops_3_uses_ldq <= r_uops_2_uses_ldq; // @[functional-unit.scala:237:23] r_uops_3_uses_stq <= r_uops_2_uses_stq; // @[functional-unit.scala:237:23] r_uops_3_is_sys_pc2epc <= r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23] r_uops_3_is_unique <= r_uops_2_is_unique; // @[functional-unit.scala:237:23] r_uops_3_flush_on_commit <= r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23] r_uops_3_ldst_is_rs1 <= r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23] r_uops_3_ldst <= r_uops_2_ldst; // @[functional-unit.scala:237:23] r_uops_3_lrs1 <= r_uops_2_lrs1; // @[functional-unit.scala:237:23] r_uops_3_lrs2 <= r_uops_2_lrs2; // @[functional-unit.scala:237:23] r_uops_3_lrs3 <= r_uops_2_lrs3; // @[functional-unit.scala:237:23] r_uops_3_ldst_val <= r_uops_2_ldst_val; // @[functional-unit.scala:237:23] r_uops_3_dst_rtype <= r_uops_2_dst_rtype; // @[functional-unit.scala:237:23] r_uops_3_lrs1_rtype <= r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23] r_uops_3_lrs2_rtype <= r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23] r_uops_3_frs3_en <= r_uops_2_frs3_en; // @[functional-unit.scala:237:23] r_uops_3_fp_val <= r_uops_2_fp_val; // @[functional-unit.scala:237:23] r_uops_3_fp_single <= r_uops_2_fp_single; // @[functional-unit.scala:237:23] r_uops_3_xcpt_pf_if <= r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23] r_uops_3_xcpt_ae_if <= r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23] r_uops_3_xcpt_ma_if <= r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23] r_uops_3_bp_debug_if <= r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23] r_uops_3_bp_xcpt_if <= r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23] r_uops_3_debug_fsrc <= r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23] r_uops_3_debug_tsrc <= r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23] always @(posedge) FPU_3 fpu ( // @[functional-unit.scala:572:19] .clock (clock), .reset (reset), .io_req_valid (io_req_valid_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_uopc (io_req_bits_uop_uopc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_inst (io_req_bits_uop_inst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iq_type (io_req_bits_uop_iq_type_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_fu_code (io_req_bits_uop_fu_code_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iw_state (io_req_bits_uop_iw_state_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_br (io_req_bits_uop_is_br_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_jal (io_req_bits_uop_is_jal_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_taken (io_req_bits_uop_taken_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_pdst (io_req_bits_uop_pdst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs1 (io_req_bits_uop_prs1_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs2 (io_req_bits_uop_prs2_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs3 (io_req_bits_uop_prs3_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ppred (io_req_bits_uop_ppred_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_exception (io_req_bits_uop_exception_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_mem_size (io_req_bits_uop_mem_size_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_fence (io_req_bits_uop_is_fence_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_unique (io_req_bits_uop_is_unique_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldst (io_req_bits_uop_ldst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_fp_single (io_req_bits_uop_fp_single_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc_0), // @[functional-unit.scala:564:7] .io_req_bits_rs1_data (io_req_bits_rs1_data_0), // @[functional-unit.scala:564:7] .io_req_bits_rs2_data (io_req_bits_rs2_data_0), // @[functional-unit.scala:564:7] .io_req_bits_rs3_data (io_req_bits_rs3_data_0), // @[functional-unit.scala:564:7] .io_req_bits_fcsr_rm (io_fcsr_rm_0), // @[functional-unit.scala:564:7] .io_resp_bits_data (io_resp_bits_data_0), .io_resp_bits_fflags_valid (io_resp_bits_fflags_valid_0), .io_resp_bits_fflags_bits_flags (io_resp_bits_fflags_bits_flags_0) ); // @[functional-unit.scala:572:19] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_uopc = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iq_type = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_fu_code = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_br_type = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_op1_sel = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_op2_sel = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_imm_sel = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_op_fcn = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_fcn_dw = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_csr_cmd = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_is_load = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_is_sta = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_is_std = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iw_state = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iw_p1_poisoned = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iw_p2_poisoned = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_br = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_jalr = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_jal = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_csr_addr = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_bypassable = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldst_val = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_fp_single = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_valid = io_resp_bits_fflags_valid_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_uopc = io_resp_bits_fflags_bits_uop_uopc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_inst = io_resp_bits_fflags_bits_uop_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_inst = io_resp_bits_fflags_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_rvc = io_resp_bits_fflags_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_pc = io_resp_bits_fflags_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iq_type = io_resp_bits_fflags_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_fu_code = io_resp_bits_fflags_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_br_type = io_resp_bits_fflags_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel = io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel = io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel = io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn = io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_is_load = io_resp_bits_fflags_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_is_sta = io_resp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_is_std = io_resp_bits_fflags_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iw_state = io_resp_bits_fflags_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned = io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned = io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_br = io_resp_bits_fflags_bits_uop_is_br_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_jalr = io_resp_bits_fflags_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_jal = io_resp_bits_fflags_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_sfb = io_resp_bits_fflags_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_br_mask = io_resp_bits_fflags_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_br_tag = io_resp_bits_fflags_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ftq_idx = io_resp_bits_fflags_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_edge_inst = io_resp_bits_fflags_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_pc_lob = io_resp_bits_fflags_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_taken = io_resp_bits_fflags_bits_uop_taken_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_imm_packed = io_resp_bits_fflags_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_csr_addr = io_resp_bits_fflags_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_rob_idx = io_resp_bits_fflags_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldq_idx = io_resp_bits_fflags_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_stq_idx = io_resp_bits_fflags_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_rxq_idx = io_resp_bits_fflags_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_pdst = io_resp_bits_fflags_bits_uop_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs1 = io_resp_bits_fflags_bits_uop_prs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs2 = io_resp_bits_fflags_bits_uop_prs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs3 = io_resp_bits_fflags_bits_uop_prs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ppred = io_resp_bits_fflags_bits_uop_ppred_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs1_busy = io_resp_bits_fflags_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs2_busy = io_resp_bits_fflags_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs3_busy = io_resp_bits_fflags_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ppred_busy = io_resp_bits_fflags_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_stale_pdst = io_resp_bits_fflags_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_exception = io_resp_bits_fflags_bits_uop_exception_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_exc_cause = io_resp_bits_fflags_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_bypassable = io_resp_bits_fflags_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_mem_cmd = io_resp_bits_fflags_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_mem_size = io_resp_bits_fflags_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_mem_signed = io_resp_bits_fflags_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_fence = io_resp_bits_fflags_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_fencei = io_resp_bits_fflags_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_amo = io_resp_bits_fflags_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_uses_ldq = io_resp_bits_fflags_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_uses_stq = io_resp_bits_fflags_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc = io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_unique = io_resp_bits_fflags_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_flush_on_commit = io_resp_bits_fflags_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldst_is_rs1 = io_resp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldst = io_resp_bits_fflags_bits_uop_ldst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs1 = io_resp_bits_fflags_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs2 = io_resp_bits_fflags_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs3 = io_resp_bits_fflags_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldst_val = io_resp_bits_fflags_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_dst_rtype = io_resp_bits_fflags_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs1_rtype = io_resp_bits_fflags_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs2_rtype = io_resp_bits_fflags_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_frs3_en = io_resp_bits_fflags_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_fp_val = io_resp_bits_fflags_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_fp_single = io_resp_bits_fflags_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_xcpt_pf_if = io_resp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_xcpt_ae_if = io_resp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_xcpt_ma_if = io_resp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_bp_debug_if = io_resp_bits_fflags_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_bp_xcpt_if = io_resp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_fsrc = io_resp_bits_fflags_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_tsrc = io_resp_bits_fflags_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_flags = io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:564:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_14 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_14( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_104 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_104( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_87 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_87( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_3 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_3( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_4 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleC_a32d128s7k6z4c_4 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40)) node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0)) node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<7>(0h40)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T	module TLCToNoC_4( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 \| tail_beats1 == 8'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_56 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_56 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_56( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_56 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NonSyncResetSynchronizerPrimitiveShiftReg_d3_6 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} reg sync_0 : UInt<1>, clock reg sync_1 : UInt<1>, clock reg sync_2 : UInt<1>, clock node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module NonSyncResetSynchronizerPrimitiveShiftReg_d3_6( // @[SynchronizerReg.scala:37:15] input clock, // @[SynchronizerReg.scala:37:15] input reset, // @[SynchronizerReg.scala:37:15] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:37:15] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:37:15, :54:22] wire io_q_0; // @[SynchronizerReg.scala:37:15] reg sync_0; // @[SynchronizerReg.scala:51:66] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:37:15, :51:66] reg sync_1; // @[SynchronizerReg.scala:51:66] reg sync_2; // @[SynchronizerReg.scala:51:66] always @(posedge clock) begin // @[SynchronizerReg.scala:37:15] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:66] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:66] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:66, :54:22] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:37:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_322 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_66 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_322( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_66 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_119 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_120 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_449 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_193 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_449( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_193 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_60 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_127 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_128 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_129 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_5 of InputUnit_127 connect input_unit_0_from_5.clock, clock connect input_unit_0_from_5.reset, reset inst input_unit_1_from_12 of InputUnit_128 connect input_unit_1_from_12.clock, clock connect input_unit_1_from_12.reset, reset inst input_unit_2_from_14 of InputUnit_129 connect input_unit_2_from_14.clock, clock connect input_unit_2_from_14.reset, reset inst output_unit_0_to_5 of OutputUnit_127 connect output_unit_0_to_5.clock, clock connect output_unit_0_to_5.reset, reset inst output_unit_1_to_12 of OutputUnit_128 connect output_unit_1_to_12.clock, clock connect output_unit_1_to_12.reset, reset inst output_unit_2_to_14 of OutputUnit_129 connect output_unit_2_to_14.clock, clock connect output_unit_2_to_14.reset, reset inst switch of Switch_60 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_60 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_60 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_60 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_6 connect input_unit_0_from_5.io.in, destNodesIn connect input_unit_1_from_12.io.in, destNodesIn_1 connect input_unit_2_from_14.io.in, destNodesIn_2 connect output_unit_0_to_5.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_5.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_5.io.out.flit connect output_unit_1_to_12.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_12.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_12.io.out.flit connect output_unit_2_to_14.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_14.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_14.io.out.flit connect route_computer.io.req.`0`, input_unit_0_from_5.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_12.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_14.io.router_req connect input_unit_0_from_5.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_12.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_14.io.router_resp, route_computer.io.resp.`2` connect vc_allocator.io.req.`0`, input_unit_0_from_5.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_12.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_14.io.vcalloc_req connect input_unit_0_from_5.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_12.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_14.io.vcalloc_resp, vc_allocator.io.resp.`2` connect output_unit_0_to_5.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_12.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_14.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_5.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_5.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_5.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_5.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_5.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_5.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_5.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_5.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_5.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_5.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_5.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_5.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_5.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_5.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_5.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_5.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_5.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_5.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_5.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_5.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_5.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_5.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_5.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_5.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_5.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_5.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_5.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_5.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_5.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_5.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_5.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_5.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_5.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_5.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_5.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_5.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_5.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_5.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_5.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_5.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`0`[8].flow.egress_node_id, output_unit_0_to_5.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[8].flow.egress_node, output_unit_0_to_5.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node, output_unit_0_to_5.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`0`[8].flow.vnet_id, output_unit_0_to_5.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`0`[8].occupied, output_unit_0_to_5.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`0`[9].flow.egress_node_id, output_unit_0_to_5.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[9].flow.egress_node, output_unit_0_to_5.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node, output_unit_0_to_5.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`0`[9].flow.vnet_id, output_unit_0_to_5.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`0`[9].occupied, output_unit_0_to_5.io.channel_status[9].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_12.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_12.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_12.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_12.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_12.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_12.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_12.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_12.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_12.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_12.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_12.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_12.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_12.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_12.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_12.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_12.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_12.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_12.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_12.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_12.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_12.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[5].flow.egress_node_id, output_unit_1_to_12.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.egress_node, output_unit_1_to_12.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node, output_unit_1_to_12.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`1`[5].flow.vnet_id, output_unit_1_to_12.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`1`[5].occupied, output_unit_1_to_12.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`1`[6].flow.egress_node_id, output_unit_1_to_12.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.egress_node, output_unit_1_to_12.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node, output_unit_1_to_12.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`1`[6].flow.vnet_id, output_unit_1_to_12.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`1`[6].occupied, output_unit_1_to_12.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`1`[7].flow.egress_node_id, output_unit_1_to_12.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.egress_node, output_unit_1_to_12.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node, output_unit_1_to_12.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`1`[7].flow.vnet_id, output_unit_1_to_12.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`1`[7].occupied, output_unit_1_to_12.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[8].flow.egress_node_id, output_unit_1_to_12.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[8].flow.egress_node, output_unit_1_to_12.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`1`[8].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[8].flow.ingress_node, output_unit_1_to_12.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`1`[8].flow.vnet_id, output_unit_1_to_12.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`1`[8].occupied, output_unit_1_to_12.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`1`[9].flow.egress_node_id, output_unit_1_to_12.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[9].flow.egress_node, output_unit_1_to_12.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`1`[9].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[9].flow.ingress_node, output_unit_1_to_12.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`1`[9].flow.vnet_id, output_unit_1_to_12.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`1`[9].occupied, output_unit_1_to_12.io.channel_status[9].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_14.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_14.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_14.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_14.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_14.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_14.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_14.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_14.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_14.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_14.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_14.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_14.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_14.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_14.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_14.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_14.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_14.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_14.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_14.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_14.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_14.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_14.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_14.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_14.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_14.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`2`[5].flow.egress_node_id, output_unit_2_to_14.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[5].flow.egress_node, output_unit_2_to_14.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node, output_unit_2_to_14.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`2`[5].flow.vnet_id, output_unit_2_to_14.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`2`[5].occupied, output_unit_2_to_14.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`2`[6].flow.egress_node_id, output_unit_2_to_14.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[6].flow.egress_node, output_unit_2_to_14.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node, output_unit_2_to_14.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`2`[6].flow.vnet_id, output_unit_2_to_14.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`2`[6].occupied, output_unit_2_to_14.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`2`[7].flow.egress_node_id, output_unit_2_to_14.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[7].flow.egress_node, output_unit_2_to_14.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node, output_unit_2_to_14.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`2`[7].flow.vnet_id, output_unit_2_to_14.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`2`[7].occupied, output_unit_2_to_14.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`2`[8].flow.egress_node_id, output_unit_2_to_14.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[8].flow.egress_node, output_unit_2_to_14.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`2`[8].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[8].flow.ingress_node, output_unit_2_to_14.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`2`[8].flow.vnet_id, output_unit_2_to_14.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`2`[8].occupied, output_unit_2_to_14.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`2`[9].flow.egress_node_id, output_unit_2_to_14.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[9].flow.egress_node, output_unit_2_to_14.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`2`[9].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[9].flow.ingress_node, output_unit_2_to_14.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`2`[9].flow.vnet_id, output_unit_2_to_14.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`2`[9].occupied, output_unit_2_to_14.io.channel_status[9].occupied connect input_unit_0_from_5.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`0`[8], output_unit_0_to_5.io.credit_available[8] connect input_unit_0_from_5.io.out_credit_available.`0`[9], output_unit_0_to_5.io.credit_available[9] connect input_unit_0_from_5.io.out_credit_available.`1`[0], output_unit_1_to_12.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`1`[1], output_unit_1_to_12.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`1`[2], output_unit_1_to_12.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`1`[3], output_unit_1_to_12.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`1`[4], output_unit_1_to_12.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`1`[5], output_unit_1_to_12.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`1`[6], output_unit_1_to_12.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`1`[7], output_unit_1_to_12.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`1`[8], output_unit_1_to_12.io.credit_available[8] connect input_unit_0_from_5.io.out_credit_available.`1`[9], output_unit_1_to_12.io.credit_available[9] connect input_unit_0_from_5.io.out_credit_available.`2`[0], output_unit_2_to_14.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`2`[1], output_unit_2_to_14.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`2`[2], output_unit_2_to_14.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`2`[3], output_unit_2_to_14.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`2`[4], output_unit_2_to_14.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`2`[5], output_unit_2_to_14.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`2`[6], output_unit_2_to_14.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`2`[7], output_unit_2_to_14.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`2`[8], output_unit_2_to_14.io.credit_available[8] connect input_unit_0_from_5.io.out_credit_available.`2`[9], output_unit_2_to_14.io.credit_available[9] connect input_unit_1_from_12.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_1_from_12.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_1_from_12.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_1_from_12.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_1_from_12.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_1_from_12.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_1_from_12.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_1_from_12.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_1_from_12.io.out_credit_available.`0`[8], output_unit_0_to_5.io.credit_available[8] connect input_unit_1_from_12.io.out_credit_available.`0`[9], output_unit_0_to_5.io.credit_available[9] connect input_unit_1_from_12.io.out_credit_available.`1`[0], output_unit_1_to_12.io.credit_available[0] connect input_unit_1_from_12.io.out_credit_available.`1`[1], output_unit_1_to_12.io.credit_available[1] connect input_unit_1_from_12.io.out_credit_available.`1`[2], output_unit_1_to_12.io.credit_available[2] connect input_unit_1_from_12.io.out_credit_available.`1`[3], output_unit_1_to_12.io.credit_available[3] connect input_unit_1_from_12.io.out_credit_available.`1`[4], output_unit_1_to_12.io.credit_available[4] connect input_unit_1_from_12.io.out_credit_available.`1`[5], output_unit_1_to_12.io.credit_available[5] connect input_unit_1_from_12.io.out_credit_available.`1`[6], output_unit_1_to_12.io.credit_available[6] connect input_unit_1_from_12.io.out_credit_available.`1`[7], output_unit_1_to_12.io.credit_available[7] connect input_unit_1_from_12.io.out_credit_available.`1`[8], output_unit_1_to_12.io.credit_available[8] connect input_unit_1_from_12.io.out_credit_available.`1`[9], output_unit_1_to_12.io.credit_available[9] connect input_unit_1_from_12.io.out_credit_available.`2`[0], output_unit_2_to_14.io.credit_available[0] connect input_unit_1_from_12.io.out_credit_available.`2`[1], output_unit_2_to_14.io.credit_available[1] connect input_unit_1_from_12.io.out_credit_available.`2`[2], output_unit_2_to_14.io.credit_available[2] connect input_unit_1_from_12.io.out_credit_available.`2`[3], output_unit_2_to_14.io.credit_available[3] connect input_unit_1_from_12.io.out_credit_available.`2`[4], output_unit_2_to_14.io.credit_available[4] connect input_unit_1_from_12.io.out_credit_available.`2`[5], output_unit_2_to_14.io.credit_available[5] connect input_unit_1_from_12.io.out_credit_available.`2`[6], output_unit_2_to_14.io.credit_available[6] connect input_unit_1_from_12.io.out_credit_available.`2`[7], output_unit_2_to_14.io.credit_available[7] connect input_unit_1_from_12.io.out_credit_available.`2`[8], output_unit_2_to_14.io.credit_available[8] connect input_unit_1_from_12.io.out_credit_available.`2`[9], output_unit_2_to_14.io.credit_available[9] connect input_unit_2_from_14.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_2_from_14.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_2_from_14.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_2_from_14.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_2_from_14.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_2_from_14.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_2_from_14.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_2_from_14.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_2_from_14.io.out_credit_available.`0`[8], output_unit_0_to_5.io.credit_available[8] connect input_unit_2_from_14.io.out_credit_available.`0`[9], output_unit_0_to_5.io.credit_available[9] connect input_unit_2_from_14.io.out_credit_available.`1`[0], output_unit_1_to_12.io.credit_available[0] connect input_unit_2_from_14.io.out_credit_available.`1`[1], output_unit_1_to_12.io.credit_available[1] connect input_unit_2_from_14.io.out_credit_available.`1`[2], output_unit_1_to_12.io.credit_available[2] connect input_unit_2_from_14.io.out_credit_available.`1`[3], output_unit_1_to_12.io.credit_available[3] connect input_unit_2_from_14.io.out_credit_available.`1`[4], output_unit_1_to_12.io.credit_available[4] connect input_unit_2_from_14.io.out_credit_available.`1`[5], output_unit_1_to_12.io.credit_available[5] connect input_unit_2_from_14.io.out_credit_available.`1`[6], output_unit_1_to_12.io.credit_available[6] connect input_unit_2_from_14.io.out_credit_available.`1`[7], output_unit_1_to_12.io.credit_available[7] connect input_unit_2_from_14.io.out_credit_available.`1`[8], output_unit_1_to_12.io.credit_available[8] connect input_unit_2_from_14.io.out_credit_available.`1`[9], output_unit_1_to_12.io.credit_available[9] connect input_unit_2_from_14.io.out_credit_available.`2`[0], output_unit_2_to_14.io.credit_available[0] connect input_unit_2_from_14.io.out_credit_available.`2`[1], output_unit_2_to_14.io.credit_available[1] connect input_unit_2_from_14.io.out_credit_available.`2`[2], output_unit_2_to_14.io.credit_available[2] connect input_unit_2_from_14.io.out_credit_available.`2`[3], output_unit_2_to_14.io.credit_available[3] connect input_unit_2_from_14.io.out_credit_available.`2`[4], output_unit_2_to_14.io.credit_available[4] connect input_unit_2_from_14.io.out_credit_available.`2`[5], output_unit_2_to_14.io.credit_available[5] connect input_unit_2_from_14.io.out_credit_available.`2`[6], output_unit_2_to_14.io.credit_available[6] connect input_unit_2_from_14.io.out_credit_available.`2`[7], output_unit_2_to_14.io.credit_available[7] connect input_unit_2_from_14.io.out_credit_available.`2`[8], output_unit_2_to_14.io.credit_available[8] connect input_unit_2_from_14.io.out_credit_available.`2`[9], output_unit_2_to_14.io.credit_available[9] connect switch_allocator.io.req.`0`[0], input_unit_0_from_5.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_12.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_14.io.salloc_req[0] connect output_unit_0_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_5.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_5.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_5.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_5.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_5.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_5.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_5.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_5.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_5.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_5.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_5.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_5.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_5.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_5.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect output_unit_0_to_5.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`0`[8].tail connect output_unit_0_to_5.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`0`[8].alloc connect output_unit_0_to_5.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`0`[9].tail connect output_unit_0_to_5.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`0`[9].alloc connect output_unit_1_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_1_to_12.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail connect output_unit_1_to_12.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc connect output_unit_1_to_12.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail connect output_unit_1_to_12.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc connect output_unit_1_to_12.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`1`[5].tail connect output_unit_1_to_12.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`1`[5].alloc connect output_unit_1_to_12.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`1`[6].tail connect output_unit_1_to_12.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`1`[6].alloc connect output_unit_1_to_12.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`1`[7].tail connect output_unit_1_to_12.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`1`[7].alloc connect output_unit_1_to_12.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`1`[8].tail connect output_unit_1_to_12.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`1`[8].alloc connect output_unit_1_to_12.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`1`[9].tail connect output_unit_1_to_12.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`1`[9].alloc connect output_unit_2_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_14.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_14.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_14.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_14.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect output_unit_2_to_14.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail connect output_unit_2_to_14.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc connect output_unit_2_to_14.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail connect output_unit_2_to_14.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc connect output_unit_2_to_14.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`2`[5].tail connect output_unit_2_to_14.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`2`[5].alloc connect output_unit_2_to_14.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`2`[6].tail connect output_unit_2_to_14.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`2`[6].alloc connect output_unit_2_to_14.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`2`[7].tail connect output_unit_2_to_14.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`2`[7].alloc connect output_unit_2_to_14.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`2`[8].tail connect output_unit_2_to_14.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`2`[8].alloc connect output_unit_2_to_14.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`2`[9].tail connect output_unit_2_to_14.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`2`[9].alloc connect switch.io.in.`0`[0], input_unit_0_from_5.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_12.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_14.io.out[0] connect output_unit_0_to_5.io.in, switch.io.out.`0` connect output_unit_1_to_12.io.in, switch.io.out.`1` connect output_unit_2_to_14.io.in, switch.io.out.`2` reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect input_unit_0_from_5.io.block, UInt<1>(0h0) connect input_unit_1_from_12.io.block, UInt<1>(0h0) connect input_unit_2_from_14.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_5.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_12.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_14.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_5.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_12.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_14.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_138 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 5 13 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 12 13 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 14 13 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid	module Router_60( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [3:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_9; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_9; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_14_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_2_to_14_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_12_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_1_to_12_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_9_occupied; // @[Router.scala:122:13] wire [3:0] _input_unit_2_from_14_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_14_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_14_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_8; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_14_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_15 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = or(_T_518, _T_523) node _T_525 = and(_T_513, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = and(_T_512, _T_526) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_527, UInt<1>(0h1), "") : assert_2 node _T_531 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h0)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_8) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<1>(0h1)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_9) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h2)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_10) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_550 = shr(io.in.a.bits.source, 2) node _T_551 = eq(_T_550, UInt<2>(0h3)) node _T_552 = leq(UInt<1>(0h0), uncommonBits_11) node _T_553 = and(_T_551, _T_552) node _T_554 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_562 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_563 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_564 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_565 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_566 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_567 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_592 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_531 connect _WIRE[1], _T_537 connect _WIRE[2], _T_543 connect _WIRE[3], _T_549 connect _WIRE[4], _T_555 connect _WIRE[5], _T_556 connect _WIRE[6], _T_557 connect _WIRE[7], _T_558 connect _WIRE[8], _T_559 connect _WIRE[9], _T_560 connect _WIRE[10], _T_561 connect _WIRE[11], _T_562 connect _WIRE[12], _T_563 connect _WIRE[13], _T_564 connect _WIRE[14], _T_565 connect _WIRE[15], _T_566 connect _WIRE[16], _T_567 connect _WIRE[17], _T_568 connect _WIRE[18], _T_569 connect _WIRE[19], _T_570 connect _WIRE[20], _T_571 connect _WIRE[21], _T_572 connect _WIRE[22], _T_573 connect _WIRE[23], _T_574 connect _WIRE[24], _T_575 connect _WIRE[25], _T_576 connect _WIRE[26], _T_577 connect _WIRE[27], _T_578 connect _WIRE[28], _T_579 connect _WIRE[29], _T_580 connect _WIRE[30], _T_581 connect _WIRE[31], _T_582 connect _WIRE[32], _T_583 connect _WIRE[33], _T_584 connect _WIRE[34], _T_585 connect _WIRE[35], _T_586 connect _WIRE[36], _T_587 connect _WIRE[37], _T_588 connect _WIRE[38], _T_589 connect _WIRE[39], _T_590 connect _WIRE[40], _T_591 connect _WIRE[41], _T_592 node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_600 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_601 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_602 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_603 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_604 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_605 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_608 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[5], _T_593, UInt<1>(0h0)) node _T_611 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[8], _T_594, UInt<1>(0h0)) node _T_614 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[11], _T_595, UInt<1>(0h0)) node _T_617 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[14], _T_596, UInt<1>(0h0)) node _T_620 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[17], _T_597, UInt<1>(0h0)) node _T_623 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[20], _T_598, UInt<1>(0h0)) node _T_626 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[23], _T_599, UInt<1>(0h0)) node _T_629 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[26], _T_600, UInt<1>(0h0)) node _T_632 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[29], _T_601, UInt<1>(0h0)) node _T_635 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[32], _T_602, UInt<1>(0h0)) node _T_638 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[35], _T_603, UInt<1>(0h0)) node _T_641 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_642 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_643 = mux(_WIRE[38], _T_604, UInt<1>(0h0)) node _T_644 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_645 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_646 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_647 = or(_T_605, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) node _T_682 = or(_T_681, _T_641) node _T_683 = or(_T_682, _T_642) node _T_684 = or(_T_683, _T_643) node _T_685 = or(_T_684, _T_644) node _T_686 = or(_T_685, _T_645) node _T_687 = or(_T_686, _T_646) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_687 node _T_688 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_689 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_690 = and(_T_688, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<13>(0h1000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<13>(0h1000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = or(_T_696, _T_701) node _T_703 = and(_T_691, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = and(_WIRE_1, _T_704) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_705, UInt<1>(0h1), "") : assert_3 node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(source_ok, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_712 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_712, UInt<1>(0h1), "") : assert_5 node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(is_aligned, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_719 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_719, UInt<1>(0h1), "") : assert_7 node _T_723 = not(io.in.a.bits.mask) node _T_724 = eq(_T_723, UInt<1>(0h0)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_724, UInt<1>(0h1), "") : assert_8 node _T_728 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_728, UInt<1>(0h1), "") : assert_9 node _T_732 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_732 : node _T_733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<1>(0h0)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_12) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<1>(0h1)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_13) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_749 = shr(io.in.a.bits.source, 2) node _T_750 = eq(_T_749, UInt<2>(0h2)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_14) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_755 = shr(io.in.a.bits.source, 2) node _T_756 = eq(_T_755, UInt<2>(0h3)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_15) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_760 = and(_T_758, _T_759) node _T_761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_798 = or(_T_736, _T_742) node _T_799 = or(_T_798, _T_748) node _T_800 = or(_T_799, _T_754) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = or(_T_826, _T_786) node _T_828 = or(_T_827, _T_787) node _T_829 = or(_T_828, _T_788) node _T_830 = or(_T_829, _T_789) node _T_831 = or(_T_830, _T_790) node _T_832 = or(_T_831, _T_791) node _T_833 = or(_T_832, _T_792) node _T_834 = or(_T_833, _T_793) node _T_835 = or(_T_834, _T_794) node _T_836 = or(_T_835, _T_795) node _T_837 = or(_T_836, _T_796) node _T_838 = or(_T_837, _T_797) node _T_839 = and(_T_735, _T_838) node _T_840 = or(UInt<1>(0h0), _T_839) node _T_841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_842 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_843 = cvt(_T_842) node _T_844 = and(_T_843, asSInt(UInt<13>(0h1000))) node _T_845 = asSInt(_T_844) node _T_846 = eq(_T_845, asSInt(UInt<1>(0h0))) node _T_847 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = or(_T_846, _T_851) node _T_853 = and(_T_841, _T_852) node _T_854 = or(UInt<1>(0h0), _T_853) node _T_855 = and(_T_840, _T_854) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_855, UInt<1>(0h1), "") : assert_10 node _T_859 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<1>(0h0)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_16) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_866 = shr(io.in.a.bits.source, 2) node _T_867 = eq(_T_866, UInt<1>(0h1)) node _T_868 = leq(UInt<1>(0h0), uncommonBits_17) node _T_869 = and(_T_867, _T_868) node _T_870 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_871 = and(_T_869, _T_870) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_872 = shr(io.in.a.bits.source, 2) node _T_873 = eq(_T_872, UInt<2>(0h2)) node _T_874 = leq(UInt<1>(0h0), uncommonBits_18) node _T_875 = and(_T_873, _T_874) node _T_876 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_877 = and(_T_875, _T_876) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_878 = shr(io.in.a.bits.source, 2) node _T_879 = eq(_T_878, UInt<2>(0h3)) node _T_880 = leq(UInt<1>(0h0), uncommonBits_19) node _T_881 = and(_T_879, _T_880) node _T_882 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_883 = and(_T_881, _T_882) node _T_884 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_885 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_886 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_887 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_888 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_889 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_890 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_891 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_892 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_893 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_894 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_895 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_902 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_903 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_904 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_911 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_912 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_913 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_914 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_915 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_916 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_917 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_918 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_919 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_920 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_859 connect _WIRE_2[1], _T_865 connect _WIRE_2[2], _T_871 connect _WIRE_2[3], _T_877 connect _WIRE_2[4], _T_883 connect _WIRE_2[5], _T_884 connect _WIRE_2[6], _T_885 connect _WIRE_2[7], _T_886 connect _WIRE_2[8], _T_887 connect _WIRE_2[9], _T_888 connect _WIRE_2[10], _T_889 connect _WIRE_2[11], _T_890 connect _WIRE_2[12], _T_891 connect _WIRE_2[13], _T_892 connect _WIRE_2[14], _T_893 connect _WIRE_2[15], _T_894 connect _WIRE_2[16], _T_895 connect _WIRE_2[17], _T_896 connect _WIRE_2[18], _T_897 connect _WIRE_2[19], _T_898 connect _WIRE_2[20], _T_899 connect _WIRE_2[21], _T_900 connect _WIRE_2[22], _T_901 connect _WIRE_2[23], _T_902 connect _WIRE_2[24], _T_903 connect _WIRE_2[25], _T_904 connect _WIRE_2[26], _T_905 connect _WIRE_2[27], _T_906 connect _WIRE_2[28], _T_907 connect _WIRE_2[29], _T_908 connect _WIRE_2[30], _T_909 connect _WIRE_2[31], _T_910 connect _WIRE_2[32], _T_911 connect _WIRE_2[33], _T_912 connect _WIRE_2[34], _T_913 connect _WIRE_2[35], _T_914 connect _WIRE_2[36], _T_915 connect _WIRE_2[37], _T_916 connect _WIRE_2[38], _T_917 connect _WIRE_2[39], _T_918 connect _WIRE_2[40], _T_919 connect _WIRE_2[41], _T_920 node _T_921 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_922 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_923 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_924 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_925 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_926 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_927 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_928 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_929 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_930 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_931 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_932 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_933 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[5], _T_921, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[8], _T_922, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[11], _T_923, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[14], _T_924, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[17], _T_925, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[20], _T_926, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[23], _T_927, UInt<1>(0h0)) node _T_957 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_958 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_959 = mux(_WIRE_2[26], _T_928, UInt<1>(0h0)) node _T_960 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_961 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_962 = mux(_WIRE_2[29], _T_929, UInt<1>(0h0)) node _T_963 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_964 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_965 = mux(_WIRE_2[32], _T_930, UInt<1>(0h0)) node _T_966 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_967 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_968 = mux(_WIRE_2[35], _T_931, UInt<1>(0h0)) node _T_969 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_970 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_971 = mux(_WIRE_2[38], _T_932, UInt<1>(0h0)) node _T_972 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_973 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_974 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_975 = or(_T_933, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) node _T_998 = or(_T_997, _T_957) node _T_999 = or(_T_998, _T_958) node _T_1000 = or(_T_999, _T_959) node _T_1001 = or(_T_1000, _T_960) node _T_1002 = or(_T_1001, _T_961) node _T_1003 = or(_T_1002, _T_962) node _T_1004 = or(_T_1003, _T_963) node _T_1005 = or(_T_1004, _T_964) node _T_1006 = or(_T_1005, _T_965) node _T_1007 = or(_T_1006, _T_966) node _T_1008 = or(_T_1007, _T_967) node _T_1009 = or(_T_1008, _T_968) node _T_1010 = or(_T_1009, _T_969) node _T_1011 = or(_T_1010, _T_970) node _T_1012 = or(_T_1011, _T_971) node _T_1013 = or(_T_1012, _T_972) node _T_1014 = or(_T_1013, _T_973) node _T_1015 = or(_T_1014, _T_974) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1015 node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1017 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<13>(0h1000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<13>(0h1000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = or(_T_1024, _T_1029) node _T_1031 = and(_T_1019, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = and(_WIRE_3, _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_11 node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(source_ok, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1040 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_13 node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(is_aligned, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1047 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_15 node _T_1051 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_16 node _T_1055 = not(io.in.a.bits.mask) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_17 node _T_1060 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_18 node _T_1064 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1064 : node _T_1065 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1066 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1067 = and(_T_1065, _T_1066) node _T_1068 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1069 = shr(io.in.a.bits.source, 2) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) node _T_1071 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1074 = and(_T_1072, _T_1073) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1075 = shr(io.in.a.bits.source, 2) node _T_1076 = eq(_T_1075, UInt<1>(0h1)) node _T_1077 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1080 = and(_T_1078, _T_1079) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1081 = shr(io.in.a.bits.source, 2) node _T_1082 = eq(_T_1081, UInt<2>(0h2)) node _T_1083 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1086 = and(_T_1084, _T_1085) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<2>(0h3)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1094 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1095 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1096 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1097 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1098 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1099 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1100 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1101 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1102 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1103 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1104 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1125 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1126 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1128 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1129 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1130 = or(_T_1068, _T_1074) node _T_1131 = or(_T_1130, _T_1080) node _T_1132 = or(_T_1131, _T_1086) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = or(_T_1146, _T_1106) node _T_1148 = or(_T_1147, _T_1107) node _T_1149 = or(_T_1148, _T_1108) node _T_1150 = or(_T_1149, _T_1109) node _T_1151 = or(_T_1150, _T_1110) node _T_1152 = or(_T_1151, _T_1111) node _T_1153 = or(_T_1152, _T_1112) node _T_1154 = or(_T_1153, _T_1113) node _T_1155 = or(_T_1154, _T_1114) node _T_1156 = or(_T_1155, _T_1115) node _T_1157 = or(_T_1156, _T_1116) node _T_1158 = or(_T_1157, _T_1117) node _T_1159 = or(_T_1158, _T_1118) node _T_1160 = or(_T_1159, _T_1119) node _T_1161 = or(_T_1160, _T_1120) node _T_1162 = or(_T_1161, _T_1121) node _T_1163 = or(_T_1162, _T_1122) node _T_1164 = or(_T_1163, _T_1123) node _T_1165 = or(_T_1164, _T_1124) node _T_1166 = or(_T_1165, _T_1125) node _T_1167 = or(_T_1166, _T_1126) node _T_1168 = or(_T_1167, _T_1127) node _T_1169 = or(_T_1168, _T_1128) node _T_1170 = or(_T_1169, _T_1129) node _T_1171 = and(_T_1067, _T_1170) node _T_1172 = or(UInt<1>(0h0), _T_1171) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_19 node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1177 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1178 = and(_T_1176, _T_1177) node _T_1179 = or(UInt<1>(0h0), _T_1178) node _T_1180 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1181 = cvt(_T_1180) node _T_1182 = and(_T_1181, asSInt(UInt<13>(0h1000))) node _T_1183 = asSInt(_T_1182) node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0))) node _T_1185 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<13>(0h1000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = or(_T_1184, _T_1189) node _T_1191 = and(_T_1179, _T_1190) node _T_1192 = or(UInt<1>(0h0), _T_1191) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_20 node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(source_ok, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(is_aligned, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1202 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_23 node _T_1206 = eq(io.in.a.bits.mask, mask) node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(_T_1206, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1206, UInt<1>(0h1), "") : assert_24 node _T_1210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_25 node _T_1214 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1214 : node _T_1215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1217 = and(_T_1215, _T_1216) node _T_1218 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1219 = shr(io.in.a.bits.source, 2) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) node _T_1221 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1224 = and(_T_1222, _T_1223) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1225 = shr(io.in.a.bits.source, 2) node _T_1226 = eq(_T_1225, UInt<1>(0h1)) node _T_1227 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1230 = and(_T_1228, _T_1229) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1231 = shr(io.in.a.bits.source, 2) node _T_1232 = eq(_T_1231, UInt<2>(0h2)) node _T_1233 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1236 = and(_T_1234, _T_1235) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1237 = shr(io.in.a.bits.source, 2) node _T_1238 = eq(_T_1237, UInt<2>(0h3)) node _T_1239 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1240 = and(_T_1238, _T_1239) node _T_1241 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1242 = and(_T_1240, _T_1241) node _T_1243 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1244 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1245 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1246 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1247 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1248 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1249 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1250 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1251 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1252 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1253 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1254 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1255 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1256 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1257 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1258 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1259 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1260 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1261 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1262 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1263 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1264 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1265 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1266 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1267 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1268 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1269 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1270 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1271 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1272 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1273 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1274 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1275 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1279 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1280 = or(_T_1218, _T_1224) node _T_1281 = or(_T_1280, _T_1230) node _T_1282 = or(_T_1281, _T_1236) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = or(_T_1290, _T_1250) node _T_1292 = or(_T_1291, _T_1251) node _T_1293 = or(_T_1292, _T_1252) node _T_1294 = or(_T_1293, _T_1253) node _T_1295 = or(_T_1294, _T_1254) node _T_1296 = or(_T_1295, _T_1255) node _T_1297 = or(_T_1296, _T_1256) node _T_1298 = or(_T_1297, _T_1257) node _T_1299 = or(_T_1298, _T_1258) node _T_1300 = or(_T_1299, _T_1259) node _T_1301 = or(_T_1300, _T_1260) node _T_1302 = or(_T_1301, _T_1261) node _T_1303 = or(_T_1302, _T_1262) node _T_1304 = or(_T_1303, _T_1263) node _T_1305 = or(_T_1304, _T_1264) node _T_1306 = or(_T_1305, _T_1265) node _T_1307 = or(_T_1306, _T_1266) node _T_1308 = or(_T_1307, _T_1267) node _T_1309 = or(_T_1308, _T_1268) node _T_1310 = or(_T_1309, _T_1269) node _T_1311 = or(_T_1310, _T_1270) node _T_1312 = or(_T_1311, _T_1271) node _T_1313 = or(_T_1312, _T_1272) node _T_1314 = or(_T_1313, _T_1273) node _T_1315 = or(_T_1314, _T_1274) node _T_1316 = or(_T_1315, _T_1275) node _T_1317 = or(_T_1316, _T_1276) node _T_1318 = or(_T_1317, _T_1277) node _T_1319 = or(_T_1318, _T_1278) node _T_1320 = or(_T_1319, _T_1279) node _T_1321 = and(_T_1217, _T_1320) node _T_1322 = or(UInt<1>(0h0), _T_1321) node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = or(UInt<1>(0h0), _T_1325) node _T_1327 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<13>(0h1000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = or(_T_1331, _T_1336) node _T_1338 = and(_T_1326, _T_1337) node _T_1339 = or(UInt<1>(0h0), _T_1338) node _T_1340 = and(_T_1322, _T_1339) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_26 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(source_ok, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1350 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_29 node _T_1354 = eq(io.in.a.bits.mask, mask) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_30 node _T_1358 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1358 : node _T_1359 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1360 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1361 = and(_T_1359, _T_1360) node _T_1362 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1363 = shr(io.in.a.bits.source, 2) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) node _T_1365 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1366 = and(_T_1364, _T_1365) node _T_1367 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1368 = and(_T_1366, _T_1367) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1369 = shr(io.in.a.bits.source, 2) node _T_1370 = eq(_T_1369, UInt<1>(0h1)) node _T_1371 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1372 = and(_T_1370, _T_1371) node _T_1373 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1374 = and(_T_1372, _T_1373) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1375 = shr(io.in.a.bits.source, 2) node _T_1376 = eq(_T_1375, UInt<2>(0h2)) node _T_1377 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1380 = and(_T_1378, _T_1379) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1381 = shr(io.in.a.bits.source, 2) node _T_1382 = eq(_T_1381, UInt<2>(0h3)) node _T_1383 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1388 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1389 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1390 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1391 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1392 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1393 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1394 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1395 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1396 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1397 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1398 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1399 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1400 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1401 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1402 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1403 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1404 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1405 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1406 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1407 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1408 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1409 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1410 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1423 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1424 = or(_T_1362, _T_1368) node _T_1425 = or(_T_1424, _T_1374) node _T_1426 = or(_T_1425, _T_1380) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = or(_T_1428, _T_1388) node _T_1430 = or(_T_1429, _T_1389) node _T_1431 = or(_T_1430, _T_1390) node _T_1432 = or(_T_1431, _T_1391) node _T_1433 = or(_T_1432, _T_1392) node _T_1434 = or(_T_1433, _T_1393) node _T_1435 = or(_T_1434, _T_1394) node _T_1436 = or(_T_1435, _T_1395) node _T_1437 = or(_T_1436, _T_1396) node _T_1438 = or(_T_1437, _T_1397) node _T_1439 = or(_T_1438, _T_1398) node _T_1440 = or(_T_1439, _T_1399) node _T_1441 = or(_T_1440, _T_1400) node _T_1442 = or(_T_1441, _T_1401) node _T_1443 = or(_T_1442, _T_1402) node _T_1444 = or(_T_1443, _T_1403) node _T_1445 = or(_T_1444, _T_1404) node _T_1446 = or(_T_1445, _T_1405) node _T_1447 = or(_T_1446, _T_1406) node _T_1448 = or(_T_1447, _T_1407) node _T_1449 = or(_T_1448, _T_1408) node _T_1450 = or(_T_1449, _T_1409) node _T_1451 = or(_T_1450, _T_1410) node _T_1452 = or(_T_1451, _T_1411) node _T_1453 = or(_T_1452, _T_1412) node _T_1454 = or(_T_1453, _T_1413) node _T_1455 = or(_T_1454, _T_1414) node _T_1456 = or(_T_1455, _T_1415) node _T_1457 = or(_T_1456, _T_1416) node _T_1458 = or(_T_1457, _T_1417) node _T_1459 = or(_T_1458, _T_1418) node _T_1460 = or(_T_1459, _T_1419) node _T_1461 = or(_T_1460, _T_1420) node _T_1462 = or(_T_1461, _T_1421) node _T_1463 = or(_T_1462, _T_1422) node _T_1464 = or(_T_1463, _T_1423) node _T_1465 = and(_T_1361, _T_1464) node _T_1466 = or(UInt<1>(0h0), _T_1465) node _T_1467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = or(UInt<1>(0h0), _T_1469) node _T_1471 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<13>(0h1000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = or(_T_1475, _T_1480) node _T_1482 = and(_T_1470, _T_1481) node _T_1483 = or(UInt<1>(0h0), _T_1482) node _T_1484 = and(_T_1466, _T_1483) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_31 node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(source_ok, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(is_aligned, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1494 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_34 node _T_1498 = not(mask) node _T_1499 = and(io.in.a.bits.mask, _T_1498) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_35 node _T_1504 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1504 : node _T_1505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1507 = and(_T_1505, _T_1506) node _T_1508 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1509 = shr(io.in.a.bits.source, 2) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) node _T_1511 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1512 = and(_T_1510, _T_1511) node _T_1513 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1514 = and(_T_1512, _T_1513) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1515 = shr(io.in.a.bits.source, 2) node _T_1516 = eq(_T_1515, UInt<1>(0h1)) node _T_1517 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1518 = and(_T_1516, _T_1517) node _T_1519 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1520 = and(_T_1518, _T_1519) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1521 = shr(io.in.a.bits.source, 2) node _T_1522 = eq(_T_1521, UInt<2>(0h2)) node _T_1523 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1524 = and(_T_1522, _T_1523) node _T_1525 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1526 = and(_T_1524, _T_1525) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1527 = shr(io.in.a.bits.source, 2) node _T_1528 = eq(_T_1527, UInt<2>(0h3)) node _T_1529 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1532 = and(_T_1530, _T_1531) node _T_1533 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1534 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1535 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1536 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1537 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1538 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1539 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1540 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1541 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1542 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1543 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1544 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1545 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1546 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1547 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1548 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1549 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1550 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1551 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1552 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1553 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1554 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1555 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1556 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1557 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1558 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1559 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1560 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1561 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1562 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1563 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1565 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1566 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1567 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1568 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1569 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1570 = or(_T_1508, _T_1514) node _T_1571 = or(_T_1570, _T_1520) node _T_1572 = or(_T_1571, _T_1526) node _T_1573 = or(_T_1572, _T_1532) node _T_1574 = or(_T_1573, _T_1533) node _T_1575 = or(_T_1574, _T_1534) node _T_1576 = or(_T_1575, _T_1535) node _T_1577 = or(_T_1576, _T_1536) node _T_1578 = or(_T_1577, _T_1537) node _T_1579 = or(_T_1578, _T_1538) node _T_1580 = or(_T_1579, _T_1539) node _T_1581 = or(_T_1580, _T_1540) node _T_1582 = or(_T_1581, _T_1541) node _T_1583 = or(_T_1582, _T_1542) node _T_1584 = or(_T_1583, _T_1543) node _T_1585 = or(_T_1584, _T_1544) node _T_1586 = or(_T_1585, _T_1545) node _T_1587 = or(_T_1586, _T_1546) node _T_1588 = or(_T_1587, _T_1547) node _T_1589 = or(_T_1588, _T_1548) node _T_1590 = or(_T_1589, _T_1549) node _T_1591 = or(_T_1590, _T_1550) node _T_1592 = or(_T_1591, _T_1551) node _T_1593 = or(_T_1592, _T_1552) node _T_1594 = or(_T_1593, _T_1553) node _T_1595 = or(_T_1594, _T_1554) node _T_1596 = or(_T_1595, _T_1555) node _T_1597 = or(_T_1596, _T_1556) node _T_1598 = or(_T_1597, _T_1557) node _T_1599 = or(_T_1598, _T_1558) node _T_1600 = or(_T_1599, _T_1559) node _T_1601 = or(_T_1600, _T_1560) node _T_1602 = or(_T_1601, _T_1561) node _T_1603 = or(_T_1602, _T_1562) node _T_1604 = or(_T_1603, _T_1563) node _T_1605 = or(_T_1604, _T_1564) node _T_1606 = or(_T_1605, _T_1565) node _T_1607 = or(_T_1606, _T_1566) node _T_1608 = or(_T_1607, _T_1567) node _T_1609 = or(_T_1608, _T_1568) node _T_1610 = or(_T_1609, _T_1569) node _T_1611 = and(_T_1507, _T_1610) node _T_1612 = or(UInt<1>(0h0), _T_1611) node _T_1613 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1614 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1615 = cvt(_T_1614) node _T_1616 = and(_T_1615, asSInt(UInt<13>(0h1000))) node _T_1617 = asSInt(_T_1616) node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) node _T_1619 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1620 = cvt(_T_1619) node _T_1621 = and(_T_1620, asSInt(UInt<13>(0h1000))) node _T_1622 = asSInt(_T_1621) node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) node _T_1624 = or(_T_1618, _T_1623) node _T_1625 = and(_T_1613, _T_1624) node _T_1626 = or(UInt<1>(0h0), _T_1625) node _T_1627 = and(_T_1612, _T_1626) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_36 node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(source_ok, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(is_aligned, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1637 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_39 node _T_1641 = eq(io.in.a.bits.mask, mask) node _T_1642 = asUInt(reset) node _T_1643 = eq(_T_1642, UInt<1>(0h0)) when _T_1643 : node _T_1644 = eq(_T_1641, UInt<1>(0h0)) when _T_1644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1641, UInt<1>(0h1), "") : assert_40 node _T_1645 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1645 : node _T_1646 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1647 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1648 = and(_T_1646, _T_1647) node _T_1649 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1650 = shr(io.in.a.bits.source, 2) node _T_1651 = eq(_T_1650, UInt<1>(0h0)) node _T_1652 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1653 = and(_T_1651, _T_1652) node _T_1654 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1655 = and(_T_1653, _T_1654) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1656 = shr(io.in.a.bits.source, 2) node _T_1657 = eq(_T_1656, UInt<1>(0h1)) node _T_1658 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1661 = and(_T_1659, _T_1660) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1662 = shr(io.in.a.bits.source, 2) node _T_1663 = eq(_T_1662, UInt<2>(0h2)) node _T_1664 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1667 = and(_T_1665, _T_1666) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1668 = shr(io.in.a.bits.source, 2) node _T_1669 = eq(_T_1668, UInt<2>(0h3)) node _T_1670 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1673 = and(_T_1671, _T_1672) node _T_1674 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1675 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1676 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1677 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1678 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1679 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1680 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1681 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1682 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1683 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1684 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1685 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1686 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1687 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1688 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1689 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1690 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1691 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1692 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1693 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1694 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1695 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1696 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1697 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1698 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1699 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1700 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1701 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1702 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1703 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1704 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1705 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1706 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1707 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1708 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1709 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1710 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1711 = or(_T_1649, _T_1655) node _T_1712 = or(_T_1711, _T_1661) node _T_1713 = or(_T_1712, _T_1667) node _T_1714 = or(_T_1713, _T_1673) node _T_1715 = or(_T_1714, _T_1674) node _T_1716 = or(_T_1715, _T_1675) node _T_1717 = or(_T_1716, _T_1676) node _T_1718 = or(_T_1717, _T_1677) node _T_1719 = or(_T_1718, _T_1678) node _T_1720 = or(_T_1719, _T_1679) node _T_1721 = or(_T_1720, _T_1680) node _T_1722 = or(_T_1721, _T_1681) node _T_1723 = or(_T_1722, _T_1682) node _T_1724 = or(_T_1723, _T_1683) node _T_1725 = or(_T_1724, _T_1684) node _T_1726 = or(_T_1725, _T_1685) node _T_1727 = or(_T_1726, _T_1686) node _T_1728 = or(_T_1727, _T_1687) node _T_1729 = or(_T_1728, _T_1688) node _T_1730 = or(_T_1729, _T_1689) node _T_1731 = or(_T_1730, _T_1690) node _T_1732 = or(_T_1731, _T_1691) node _T_1733 = or(_T_1732, _T_1692) node _T_1734 = or(_T_1733, _T_1693) node _T_1735 = or(_T_1734, _T_1694) node _T_1736 = or(_T_1735, _T_1695) node _T_1737 = or(_T_1736, _T_1696) node _T_1738 = or(_T_1737, _T_1697) node _T_1739 = or(_T_1738, _T_1698) node _T_1740 = or(_T_1739, _T_1699) node _T_1741 = or(_T_1740, _T_1700) node _T_1742 = or(_T_1741, _T_1701) node _T_1743 = or(_T_1742, _T_1702) node _T_1744 = or(_T_1743, _T_1703) node _T_1745 = or(_T_1744, _T_1704) node _T_1746 = or(_T_1745, _T_1705) node _T_1747 = or(_T_1746, _T_1706) node _T_1748 = or(_T_1747, _T_1707) node _T_1749 = or(_T_1748, _T_1708) node _T_1750 = or(_T_1749, _T_1709) node _T_1751 = or(_T_1750, _T_1710) node _T_1752 = and(_T_1648, _T_1751) node _T_1753 = or(UInt<1>(0h0), _T_1752) node _T_1754 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1755 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1756 = cvt(_T_1755) node _T_1757 = and(_T_1756, asSInt(UInt<13>(0h1000))) node _T_1758 = asSInt(_T_1757) node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0))) node _T_1760 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1761 = cvt(_T_1760) node _T_1762 = and(_T_1761, asSInt(UInt<13>(0h1000))) node _T_1763 = asSInt(_T_1762) node _T_1764 = eq(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = or(_T_1759, _T_1764) node _T_1766 = and(_T_1754, _T_1765) node _T_1767 = or(UInt<1>(0h0), _T_1766) node _T_1768 = and(_T_1753, _T_1767) node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(_T_1768, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1768, UInt<1>(0h1), "") : assert_41 node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(source_ok, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1775 = asUInt(reset) node _T_1776 = eq(_T_1775, UInt<1>(0h0)) when _T_1776 : node _T_1777 = eq(is_aligned, UInt<1>(0h0)) when _T_1777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1778 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_44 node _T_1782 = eq(io.in.a.bits.mask, mask) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_45 node _T_1786 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1786 : node _T_1787 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1788 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1789 = and(_T_1787, _T_1788) node _T_1790 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1791 = shr(io.in.a.bits.source, 2) node _T_1792 = eq(_T_1791, UInt<1>(0h0)) node _T_1793 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1794 = and(_T_1792, _T_1793) node _T_1795 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1796 = and(_T_1794, _T_1795) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1797 = shr(io.in.a.bits.source, 2) node _T_1798 = eq(_T_1797, UInt<1>(0h1)) node _T_1799 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1800 = and(_T_1798, _T_1799) node _T_1801 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1802 = and(_T_1800, _T_1801) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1803 = shr(io.in.a.bits.source, 2) node _T_1804 = eq(_T_1803, UInt<2>(0h2)) node _T_1805 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1806 = and(_T_1804, _T_1805) node _T_1807 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1808 = and(_T_1806, _T_1807) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1809 = shr(io.in.a.bits.source, 2) node _T_1810 = eq(_T_1809, UInt<2>(0h3)) node _T_1811 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1812 = and(_T_1810, _T_1811) node _T_1813 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1814 = and(_T_1812, _T_1813) node _T_1815 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1816 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1817 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1818 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1819 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1820 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1821 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1822 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1823 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1824 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1825 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1826 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1827 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1828 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1829 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1830 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1831 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1832 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1833 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1834 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1835 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1836 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1837 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1838 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1839 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1840 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1841 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1842 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1843 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1844 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1845 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1846 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1847 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1848 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1849 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1850 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1851 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1852 = or(_T_1790, _T_1796) node _T_1853 = or(_T_1852, _T_1802) node _T_1854 = or(_T_1853, _T_1808) node _T_1855 = or(_T_1854, _T_1814) node _T_1856 = or(_T_1855, _T_1815) node _T_1857 = or(_T_1856, _T_1816) node _T_1858 = or(_T_1857, _T_1817) node _T_1859 = or(_T_1858, _T_1818) node _T_1860 = or(_T_1859, _T_1819) node _T_1861 = or(_T_1860, _T_1820) node _T_1862 = or(_T_1861, _T_1821) node _T_1863 = or(_T_1862, _T_1822) node _T_1864 = or(_T_1863, _T_1823) node _T_1865 = or(_T_1864, _T_1824) node _T_1866 = or(_T_1865, _T_1825) node _T_1867 = or(_T_1866, _T_1826) node _T_1868 = or(_T_1867, _T_1827) node _T_1869 = or(_T_1868, _T_1828) node _T_1870 = or(_T_1869, _T_1829) node _T_1871 = or(_T_1870, _T_1830) node _T_1872 = or(_T_1871, _T_1831) node _T_1873 = or(_T_1872, _T_1832) node _T_1874 = or(_T_1873, _T_1833) node _T_1875 = or(_T_1874, _T_1834) node _T_1876 = or(_T_1875, _T_1835) node _T_1877 = or(_T_1876, _T_1836) node _T_1878 = or(_T_1877, _T_1837) node _T_1879 = or(_T_1878, _T_1838) node _T_1880 = or(_T_1879, _T_1839) node _T_1881 = or(_T_1880, _T_1840) node _T_1882 = or(_T_1881, _T_1841) node _T_1883 = or(_T_1882, _T_1842) node _T_1884 = or(_T_1883, _T_1843) node _T_1885 = or(_T_1884, _T_1844) node _T_1886 = or(_T_1885, _T_1845) node _T_1887 = or(_T_1886, _T_1846) node _T_1888 = or(_T_1887, _T_1847) node _T_1889 = or(_T_1888, _T_1848) node _T_1890 = or(_T_1889, _T_1849) node _T_1891 = or(_T_1890, _T_1850) node _T_1892 = or(_T_1891, _T_1851) node _T_1893 = and(_T_1789, _T_1892) node _T_1894 = or(UInt<1>(0h0), _T_1893) node _T_1895 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1896 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1897 = cvt(_T_1896) node _T_1898 = and(_T_1897, asSInt(UInt<13>(0h1000))) node _T_1899 = asSInt(_T_1898) node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = or(_T_1900, _T_1905) node _T_1907 = and(_T_1895, _T_1906) node _T_1908 = or(UInt<1>(0h0), _T_1907) node _T_1909 = and(_T_1894, _T_1908) node _T_1910 = asUInt(reset) node _T_1911 = eq(_T_1910, UInt<1>(0h0)) when _T_1911 : node _T_1912 = eq(_T_1909, UInt<1>(0h0)) when _T_1912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1909, UInt<1>(0h1), "") : assert_46 node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(source_ok, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(is_aligned, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1919 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_49 node _T_1923 = eq(io.in.a.bits.mask, mask) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_50 node _T_1927 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1928 = asUInt(reset) node _T_1929 = eq(_T_1928, UInt<1>(0h0)) when _T_1929 : node _T_1930 = eq(_T_1927, UInt<1>(0h0)) when _T_1930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1927, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1931 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1932 = asUInt(reset) node _T_1933 = eq(_T_1932, UInt<1>(0h0)) when _T_1933 : node _T_1934 = eq(_T_1931, UInt<1>(0h0)) when _T_1934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1931, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1935 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1935 : node _T_1936 = asUInt(reset) node _T_1937 = eq(_T_1936, UInt<1>(0h0)) when _T_1937 : node _T_1938 = eq(source_ok_1, UInt<1>(0h0)) when _T_1938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1939 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_54 node _T_1943 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_55 node _T_1947 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1948 = asUInt(reset) node _T_1949 = eq(_T_1948, UInt<1>(0h0)) when _T_1949 : node _T_1950 = eq(_T_1947, UInt<1>(0h0)) when _T_1950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1947, UInt<1>(0h1), "") : assert_56 node _T_1951 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1952 = asUInt(reset) node _T_1953 = eq(_T_1952, UInt<1>(0h0)) when _T_1953 : node _T_1954 = eq(_T_1951, UInt<1>(0h0)) when _T_1954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1951, UInt<1>(0h1), "") : assert_57 node _T_1955 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1955 : node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(source_ok_1, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(sink_ok, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1962 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_60 node _T_1966 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(_T_1966, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1966, UInt<1>(0h1), "") : assert_61 node _T_1970 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1971 = asUInt(reset) node _T_1972 = eq(_T_1971, UInt<1>(0h0)) when _T_1972 : node _T_1973 = eq(_T_1970, UInt<1>(0h0)) when _T_1973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1970, UInt<1>(0h1), "") : assert_62 node _T_1974 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1975 = asUInt(reset) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : node _T_1977 = eq(_T_1974, UInt<1>(0h0)) when _T_1977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1974, UInt<1>(0h1), "") : assert_63 node _T_1978 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1979 = or(UInt<1>(0h0), _T_1978) node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(_T_1979, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1979, UInt<1>(0h1), "") : assert_64 node _T_1983 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1983 : node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(source_ok_1, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1987 = asUInt(reset) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) when _T_1988 : node _T_1989 = eq(sink_ok, UInt<1>(0h0)) when _T_1989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(_T_1990, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1990, UInt<1>(0h1), "") : assert_67 node _T_1994 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_68 node _T_1998 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_69 node _T_2002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2003 = or(_T_2002, io.in.d.bits.corrupt) node _T_2004 = asUInt(reset) node _T_2005 = eq(_T_2004, UInt<1>(0h0)) when _T_2005 : node _T_2006 = eq(_T_2003, UInt<1>(0h0)) when _T_2006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2003, UInt<1>(0h1), "") : assert_70 node _T_2007 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2008 = or(UInt<1>(0h0), _T_2007) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_71 node _T_2012 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2012 : node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(source_ok_1, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2016 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_73 node _T_2020 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_74 node _T_2024 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = asUInt(reset) node _T_2027 = eq(_T_2026, UInt<1>(0h0)) when _T_2027 : node _T_2028 = eq(_T_2025, UInt<1>(0h0)) when _T_2028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2025, UInt<1>(0h1), "") : assert_75 node _T_2029 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2029 : node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_1, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2033 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_77 node _T_2037 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2038 = or(_T_2037, io.in.d.bits.corrupt) node _T_2039 = asUInt(reset) node _T_2040 = eq(_T_2039, UInt<1>(0h0)) when _T_2040 : node _T_2041 = eq(_T_2038, UInt<1>(0h0)) when _T_2041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2038, UInt<1>(0h1), "") : assert_78 node _T_2042 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2043 = or(UInt<1>(0h0), _T_2042) node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(_T_2043, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2043, UInt<1>(0h1), "") : assert_79 node _T_2047 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2047 : node _T_2048 = asUInt(reset) node _T_2049 = eq(_T_2048, UInt<1>(0h0)) when _T_2049 : node _T_2050 = eq(source_ok_1, UInt<1>(0h0)) when _T_2050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2051 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2052 = asUInt(reset) node _T_2053 = eq(_T_2052, UInt<1>(0h0)) when _T_2053 : node _T_2054 = eq(_T_2051, UInt<1>(0h0)) when _T_2054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2051, UInt<1>(0h1), "") : assert_81 node _T_2055 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2056 = asUInt(reset) node _T_2057 = eq(_T_2056, UInt<1>(0h0)) when _T_2057 : node _T_2058 = eq(_T_2055, UInt<1>(0h0)) when _T_2058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2055, UInt<1>(0h1), "") : assert_82 node _T_2059 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2060 = or(UInt<1>(0h0), _T_2059) node _T_2061 = asUInt(reset) node _T_2062 = eq(_T_2061, UInt<1>(0h0)) when _T_2062 : node _T_2063 = eq(_T_2060, UInt<1>(0h0)) when _T_2063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2060, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2064 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2065 = asUInt(reset) node _T_2066 = eq(_T_2065, UInt<1>(0h0)) when _T_2066 : node _T_2067 = eq(_T_2064, UInt<1>(0h0)) when _T_2067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2064, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2068 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2069 = asUInt(reset) node _T_2070 = eq(_T_2069, UInt<1>(0h0)) when _T_2070 : node _T_2071 = eq(_T_2068, UInt<1>(0h0)) when _T_2071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2068, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2072 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2073 = asUInt(reset) node _T_2074 = eq(_T_2073, UInt<1>(0h0)) when _T_2074 : node _T_2075 = eq(_T_2072, UInt<1>(0h0)) when _T_2075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2072, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2076 = eq(a_first, UInt<1>(0h0)) node _T_2077 = and(io.in.a.valid, _T_2076) when _T_2077 : node _T_2078 = eq(io.in.a.bits.opcode, opcode) node _T_2079 = asUInt(reset) node _T_2080 = eq(_T_2079, UInt<1>(0h0)) when _T_2080 : node _T_2081 = eq(_T_2078, UInt<1>(0h0)) when _T_2081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2078, UInt<1>(0h1), "") : assert_87 node _T_2082 = eq(io.in.a.bits.param, param) node _T_2083 = asUInt(reset) node _T_2084 = eq(_T_2083, UInt<1>(0h0)) when _T_2084 : node _T_2085 = eq(_T_2082, UInt<1>(0h0)) when _T_2085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2082, UInt<1>(0h1), "") : assert_88 node _T_2086 = eq(io.in.a.bits.size, size) node _T_2087 = asUInt(reset) node _T_2088 = eq(_T_2087, UInt<1>(0h0)) when _T_2088 : node _T_2089 = eq(_T_2086, UInt<1>(0h0)) when _T_2089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2086, UInt<1>(0h1), "") : assert_89 node _T_2090 = eq(io.in.a.bits.source, source) node _T_2091 = asUInt(reset) node _T_2092 = eq(_T_2091, UInt<1>(0h0)) when _T_2092 : node _T_2093 = eq(_T_2090, UInt<1>(0h0)) when _T_2093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2090, UInt<1>(0h1), "") : assert_90 node _T_2094 = eq(io.in.a.bits.address, address) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_91 node _T_2098 = and(io.in.a.ready, io.in.a.valid) node _T_2099 = and(_T_2098, a_first) when _T_2099 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2100 = eq(d_first, UInt<1>(0h0)) node _T_2101 = and(io.in.d.valid, _T_2100) when _T_2101 : node _T_2102 = eq(io.in.d.bits.opcode, opcode_1) node _T_2103 = asUInt(reset) node _T_2104 = eq(_T_2103, UInt<1>(0h0)) when _T_2104 : node _T_2105 = eq(_T_2102, UInt<1>(0h0)) when _T_2105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2102, UInt<1>(0h1), "") : assert_92 node _T_2106 = eq(io.in.d.bits.param, param_1) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_93 node _T_2110 = eq(io.in.d.bits.size, size_1) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_94 node _T_2114 = eq(io.in.d.bits.source, source_1) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_95 node _T_2118 = eq(io.in.d.bits.sink, sink) node _T_2119 = asUInt(reset) node _T_2120 = eq(_T_2119, UInt<1>(0h0)) when _T_2120 : node _T_2121 = eq(_T_2118, UInt<1>(0h0)) when _T_2121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2118, UInt<1>(0h1), "") : assert_96 node _T_2122 = eq(io.in.d.bits.denied, denied) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_97 node _T_2126 = and(io.in.d.ready, io.in.d.valid) node _T_2127 = and(_T_2126, d_first) when _T_2127 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2128 = and(io.in.a.valid, a_first_1) node _T_2129 = and(_T_2128, UInt<1>(0h1)) when _T_2129 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2130 = and(io.in.a.ready, io.in.a.valid) node _T_2131 = and(_T_2130, a_first_1) node _T_2132 = and(_T_2131, UInt<1>(0h1)) when _T_2132 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2133 = dshr(inflight, io.in.a.bits.source) node _T_2134 = bits(_T_2133, 0, 0) node _T_2135 = eq(_T_2134, UInt<1>(0h0)) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2139 = and(io.in.d.valid, d_first_1) node _T_2140 = and(_T_2139, UInt<1>(0h1)) node _T_2141 = eq(d_release_ack, UInt<1>(0h0)) node _T_2142 = and(_T_2140, _T_2141) when _T_2142 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2143 = and(io.in.d.ready, io.in.d.valid) node _T_2144 = and(_T_2143, d_first_1) node _T_2145 = and(_T_2144, UInt<1>(0h1)) node _T_2146 = eq(d_release_ack, UInt<1>(0h0)) node _T_2147 = and(_T_2145, _T_2146) when _T_2147 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2148 = and(io.in.d.valid, d_first_1) node _T_2149 = and(_T_2148, UInt<1>(0h1)) node _T_2150 = eq(d_release_ack, UInt<1>(0h0)) node _T_2151 = and(_T_2149, _T_2150) when _T_2151 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2152 = dshr(inflight, io.in.d.bits.source) node _T_2153 = bits(_T_2152, 0, 0) node _T_2154 = or(_T_2153, same_cycle_resp) node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(_T_2154, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2154, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2158 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2159 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2160 = or(_T_2158, _T_2159) node _T_2161 = asUInt(reset) node _T_2162 = eq(_T_2161, UInt<1>(0h0)) when _T_2162 : node _T_2163 = eq(_T_2160, UInt<1>(0h0)) when _T_2163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2160, UInt<1>(0h1), "") : assert_100 node _T_2164 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(_T_2164, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2164, UInt<1>(0h1), "") : assert_101 else : node _T_2168 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2169 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2170 = or(_T_2168, _T_2169) node _T_2171 = asUInt(reset) node _T_2172 = eq(_T_2171, UInt<1>(0h0)) when _T_2172 : node _T_2173 = eq(_T_2170, UInt<1>(0h0)) when _T_2173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2170, UInt<1>(0h1), "") : assert_102 node _T_2174 = eq(io.in.d.bits.size, a_size_lookup) node _T_2175 = asUInt(reset) node _T_2176 = eq(_T_2175, UInt<1>(0h0)) when _T_2176 : node _T_2177 = eq(_T_2174, UInt<1>(0h0)) when _T_2177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2174, UInt<1>(0h1), "") : assert_103 node _T_2178 = and(io.in.d.valid, d_first_1) node _T_2179 = and(_T_2178, a_first_1) node _T_2180 = and(_T_2179, io.in.a.valid) node _T_2181 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2182 = and(_T_2180, _T_2181) node _T_2183 = eq(d_release_ack, UInt<1>(0h0)) node _T_2184 = and(_T_2182, _T_2183) when _T_2184 : node _T_2185 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2186 = or(_T_2185, io.in.a.ready) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_62 node _T_2190 = orr(inflight) node _T_2191 = eq(_T_2190, UInt<1>(0h0)) node _T_2192 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2193 = or(_T_2191, _T_2192) node _T_2194 = lt(watchdog, plusarg_reader.out) node _T_2195 = or(_T_2193, _T_2194) node _T_2196 = asUInt(reset) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) when _T_2197 : node _T_2198 = eq(_T_2195, UInt<1>(0h0)) when _T_2198 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2195, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2199 = and(io.in.a.ready, io.in.a.valid) node _T_2200 = and(io.in.d.ready, io.in.d.valid) node _T_2201 = or(_T_2199, _T_2200) when _T_2201 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2202 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2203 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2204 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2205 = and(_T_2203, _T_2204) node _T_2206 = and(_T_2202, _T_2205) when _T_2206 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2207 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2208 = and(_T_2207, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2209 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2210 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2211 = and(_T_2209, _T_2210) node _T_2212 = and(_T_2208, _T_2211) when _T_2212 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2213 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2214 = bits(_T_2213, 0, 0) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2219 = and(io.in.d.valid, d_first_2) node _T_2220 = and(_T_2219, UInt<1>(0h1)) node _T_2221 = and(_T_2220, d_release_ack_1) when _T_2221 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2222 = and(io.in.d.ready, io.in.d.valid) node _T_2223 = and(_T_2222, d_first_2) node _T_2224 = and(_T_2223, UInt<1>(0h1)) node _T_2225 = and(_T_2224, d_release_ack_1) when _T_2225 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2226 = and(io.in.d.valid, d_first_2) node _T_2227 = and(_T_2226, UInt<1>(0h1)) node _T_2228 = and(_T_2227, d_release_ack_1) when _T_2228 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2229 = dshr(inflight_1, io.in.d.bits.source) node _T_2230 = bits(_T_2229, 0, 0) node _T_2231 = or(_T_2230, same_cycle_resp_1) node _T_2232 = asUInt(reset) node _T_2233 = eq(_T_2232, UInt<1>(0h0)) when _T_2233 : node _T_2234 = eq(_T_2231, UInt<1>(0h0)) when _T_2234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2231, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2235 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2236 = asUInt(reset) node _T_2237 = eq(_T_2236, UInt<1>(0h0)) when _T_2237 : node _T_2238 = eq(_T_2235, UInt<1>(0h0)) when _T_2238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2235, UInt<1>(0h1), "") : assert_108 else : node _T_2239 = eq(io.in.d.bits.size, c_size_lookup) node _T_2240 = asUInt(reset) node _T_2241 = eq(_T_2240, UInt<1>(0h0)) when _T_2241 : node _T_2242 = eq(_T_2239, UInt<1>(0h0)) when _T_2242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2239, UInt<1>(0h1), "") : assert_109 node _T_2243 = and(io.in.d.valid, d_first_2) node _T_2244 = and(_T_2243, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2245 = and(_T_2244, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2246 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2247 = and(_T_2245, _T_2246) node _T_2248 = and(_T_2247, d_release_ack_1) node _T_2249 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2250 = and(_T_2248, _T_2249) when _T_2250 : node _T_2251 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2252 = or(_T_2251, _WIRE_27.ready) node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(_T_2252, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2252, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_63 node _T_2256 = orr(inflight_1) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) node _T_2258 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2259 = or(_T_2257, _T_2258) node _T_2260 = lt(watchdog_1, plusarg_reader_1.out) node _T_2261 = or(_T_2259, _T_2260) node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : node _T_2264 = eq(_T_2261, UInt<1>(0h0)) when _T_2264 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2261, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2265 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2266 = and(io.in.d.ready, io.in.d.valid) node _T_2267 = or(_T_2265, _T_2266) when _T_2267 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module LoopMatmulStC : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { max_k : UInt<16>, max_j : UInt<16>, max_i : UInt<16>, pad_j : UInt<2>, pad_i : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, full_c : UInt<1>, act : UInt<3>, addr_start : UInt<12>, loop_id : UInt<1>, is_resadd : UInt<1>}}, cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, flip ex_k : UInt<16>, flip ex_j : UInt<16>, flip ex_i : UInt<16>, flip ex_completed : UInt<1>, j : UInt<16>, i : UInt<16>, idle : UInt<1>, flip rob_overloaded : UInt<1>, loop_id : UInt<1>} regreset state : UInt<2>, clock, reset, UInt<1>(0h0) reg req : { max_k : UInt<16>, max_j : UInt<16>, max_i : UInt<16>, pad_j : UInt<2>, pad_i : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, full_c : UInt<1>, act : UInt<3>, addr_start : UInt<12>, loop_id : UInt<1>, is_resadd : UInt<1>}, clock node _max_blocks_T = leq(req.max_j, UInt<3>(0h4)) node _max_blocks_T_1 = mux(_max_blocks_T, req.max_j, UInt<3>(0h4)) node max_blocks = mux(req.full_c, UInt<1>(0h1), _max_blocks_T_1) reg j : UInt<16>, clock reg i : UInt<16>, clock node _dram_offset_T = mul(i, req.dram_stride) node _dram_offset_T_1 = add(_dram_offset_T, j) node _dram_offset_T_2 = tail(_dram_offset_T_1, 1) node _dram_offset_T_3 = mul(_dram_offset_T_2, UInt<3>(0h4)) node _dram_offset_T_4 = mul(_dram_offset_T_3, UInt<3>(0h4)) node _dram_offset_T_5 = mul(i, req.dram_stride) node _dram_offset_T_6 = add(_dram_offset_T_5, j) node _dram_offset_T_7 = tail(_dram_offset_T_6, 1) node _dram_offset_T_8 = mul(_dram_offset_T_7, UInt<3>(0h4)) node _dram_offset_T_9 = mul(_dram_offset_T_8, UInt<3>(0h4)) node dram_offset = mux(req.full_c, _dram_offset_T_4, _dram_offset_T_9) node _dram_addr_T = and(dram_offset, UInt<32>(0hffffffff)) node _dram_addr_T_1 = add(req.dram_addr, _dram_addr_T) node dram_addr = tail(_dram_addr_T_1, 1) node _sp_addr_T = mul(i, req.max_j) node _sp_addr_T_1 = add(_sp_addr_T, j) node _sp_addr_T_2 = tail(_sp_addr_T_1, 1) node _sp_addr_T_3 = mul(_sp_addr_T_2, UInt<3>(0h4)) node _sp_addr_T_4 = add(req.addr_start, _sp_addr_T_3) node sp_addr = tail(_sp_addr_T_4, 1) node _blocks_T = add(j, max_blocks) node _blocks_T_1 = tail(_blocks_T, 1) node _blocks_T_2 = leq(_blocks_T_1, req.max_j) node _blocks_T_3 = sub(req.max_j, j) node _blocks_T_4 = tail(_blocks_T_3, 1) node blocks = mux(_blocks_T_2, max_blocks, _blocks_T_4) node _cols_T = mul(blocks, UInt<3>(0h4)) node _cols_T_1 = add(j, blocks) node _cols_T_2 = tail(_cols_T_1, 1) node _cols_T_3 = geq(_cols_T_2, req.max_j) node _cols_T_4 = mux(_cols_T_3, req.pad_j, UInt<1>(0h0)) node _cols_T_5 = sub(_cols_T, _cols_T_4) node cols = tail(_cols_T_5, 1) node _rows_T = sub(req.max_i, UInt<1>(0h1)) node _rows_T_1 = tail(_rows_T, 1) node _rows_T_2 = eq(i, _rows_T_1) node _rows_T_3 = mux(_rows_T_2, req.pad_i, UInt<1>(0h0)) node _rows_T_4 = sub(UInt<3>(0h4), _rows_T_3) node rows = tail(_rows_T_4, 1) wire mvout_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate mvout_cmd.status.uie invalidate mvout_cmd.status.sie invalidate mvout_cmd.status.hie invalidate mvout_cmd.status.mie invalidate mvout_cmd.status.upie invalidate mvout_cmd.status.spie invalidate mvout_cmd.status.ube invalidate mvout_cmd.status.mpie invalidate mvout_cmd.status.spp invalidate mvout_cmd.status.vs invalidate mvout_cmd.status.mpp invalidate mvout_cmd.status.fs invalidate mvout_cmd.status.xs invalidate mvout_cmd.status.mprv invalidate mvout_cmd.status.sum invalidate mvout_cmd.status.mxr invalidate mvout_cmd.status.tvm invalidate mvout_cmd.status.tw invalidate mvout_cmd.status.tsr invalidate mvout_cmd.status.zero1 invalidate mvout_cmd.status.sd_rv32 invalidate mvout_cmd.status.uxl invalidate mvout_cmd.status.sxl invalidate mvout_cmd.status.sbe invalidate mvout_cmd.status.mbe invalidate mvout_cmd.status.gva invalidate mvout_cmd.status.mpv invalidate mvout_cmd.status.zero2 invalidate mvout_cmd.status.sd invalidate mvout_cmd.status.v invalidate mvout_cmd.status.prv invalidate mvout_cmd.status.dv invalidate mvout_cmd.status.dprv invalidate mvout_cmd.status.isa invalidate mvout_cmd.status.wfi invalidate mvout_cmd.status.cease invalidate mvout_cmd.status.debug invalidate mvout_cmd.rs2 invalidate mvout_cmd.rs1 invalidate mvout_cmd.inst.opcode invalidate mvout_cmd.inst.rd invalidate mvout_cmd.inst.xs2 invalidate mvout_cmd.inst.xs1 invalidate mvout_cmd.inst.xd invalidate mvout_cmd.inst.rs1 invalidate mvout_cmd.inst.rs2 invalidate mvout_cmd.inst.funct connect mvout_cmd.inst.funct, UInt<2>(0h3) connect mvout_cmd.rs1, dram_addr wire mvout_cmd_rs2 : { _spacer2 : UInt<13>, num_rows : UInt<3>, _spacer1 : UInt<11>, num_cols : UInt<5>, _spacer0 : UInt<0>, local_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}} invalidate mvout_cmd_rs2.local_addr.data invalidate mvout_cmd_rs2.local_addr.garbage_bit invalidate mvout_cmd_rs2.local_addr.garbage invalidate mvout_cmd_rs2.local_addr.norm_cmd invalidate mvout_cmd_rs2.local_addr.read_full_acc_row invalidate mvout_cmd_rs2.local_addr.accumulate invalidate mvout_cmd_rs2.local_addr.is_acc_addr invalidate mvout_cmd_rs2._spacer0 invalidate mvout_cmd_rs2.num_cols invalidate mvout_cmd_rs2._spacer1 invalidate mvout_cmd_rs2.num_rows invalidate mvout_cmd_rs2._spacer2 connect mvout_cmd_rs2.num_rows, rows connect mvout_cmd_rs2.num_cols, cols wire _mvout_cmd_rs2_local_addr_result_result_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _mvout_cmd_rs2_local_addr_result_result_WIRE_1 : UInt<32> connect _mvout_cmd_rs2_local_addr_result_result_WIRE_1, sp_addr node _mvout_cmd_rs2_local_addr_result_result_T = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 13, 0) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.data, _mvout_cmd_rs2_local_addr_result_result_T node _mvout_cmd_rs2_local_addr_result_result_T_1 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 14, 14) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.garbage_bit, _mvout_cmd_rs2_local_addr_result_result_T_1 node _mvout_cmd_rs2_local_addr_result_result_T_2 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 25, 15) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.garbage, _mvout_cmd_rs2_local_addr_result_result_T_2 node _mvout_cmd_rs2_local_addr_result_result_T_3 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 28, 26) wire _mvout_cmd_rs2_local_addr_result_result_WIRE_2 : UInt<3> connect _mvout_cmd_rs2_local_addr_result_result_WIRE_2, _mvout_cmd_rs2_local_addr_result_result_T_3 wire _mvout_cmd_rs2_local_addr_result_result_WIRE_3 : UInt<3> connect _mvout_cmd_rs2_local_addr_result_result_WIRE_3, _mvout_cmd_rs2_local_addr_result_result_WIRE_2 connect _mvout_cmd_rs2_local_addr_result_result_WIRE.norm_cmd, _mvout_cmd_rs2_local_addr_result_result_WIRE_3 node _mvout_cmd_rs2_local_addr_result_result_T_4 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 29, 29) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.read_full_acc_row, _mvout_cmd_rs2_local_addr_result_result_T_4 node _mvout_cmd_rs2_local_addr_result_result_T_5 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 30, 30) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.accumulate, _mvout_cmd_rs2_local_addr_result_result_T_5 node _mvout_cmd_rs2_local_addr_result_result_T_6 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 31, 31) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.is_acc_addr, _mvout_cmd_rs2_local_addr_result_result_T_6 wire mvout_cmd_rs2_local_addr_result_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvout_cmd_rs2_local_addr_result_result, _mvout_cmd_rs2_local_addr_result_result_WIRE connect mvout_cmd_rs2_local_addr_result_result.garbage, UInt<1>(0h0) wire mvout_cmd_rs2_local_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvout_cmd_rs2_local_addr_result, mvout_cmd_rs2_local_addr_result_result connect mvout_cmd_rs2_local_addr_result.is_acc_addr, UInt<1>(0h1) connect mvout_cmd_rs2_local_addr_result.accumulate, UInt<1>(0h0) connect mvout_cmd_rs2_local_addr_result.read_full_acc_row, req.full_c connect mvout_cmd_rs2.local_addr, mvout_cmd_rs2_local_addr_result node _mvout_cmd_rs2_T = asUInt(mvout_cmd_rs2.local_addr.norm_cmd) node mvout_cmd_rs2_lo_hi = cat(mvout_cmd_rs2.local_addr.garbage, mvout_cmd_rs2.local_addr.garbage_bit) node mvout_cmd_rs2_lo = cat(mvout_cmd_rs2_lo_hi, mvout_cmd_rs2.local_addr.data) node mvout_cmd_rs2_hi_lo = cat(mvout_cmd_rs2.local_addr.read_full_acc_row, _mvout_cmd_rs2_T) node mvout_cmd_rs2_hi_hi = cat(mvout_cmd_rs2.local_addr.is_acc_addr, mvout_cmd_rs2.local_addr.accumulate) node mvout_cmd_rs2_hi = cat(mvout_cmd_rs2_hi_hi, mvout_cmd_rs2_hi_lo) node _mvout_cmd_rs2_T_1 = cat(mvout_cmd_rs2_hi, mvout_cmd_rs2_lo) node mvout_cmd_rs2_lo_hi_1 = cat(mvout_cmd_rs2.num_cols, mvout_cmd_rs2._spacer0) node mvout_cmd_rs2_lo_1 = cat(mvout_cmd_rs2_lo_hi_1, _mvout_cmd_rs2_T_1) node mvout_cmd_rs2_hi_hi_1 = cat(mvout_cmd_rs2._spacer2, mvout_cmd_rs2.num_rows) node mvout_cmd_rs2_hi_1 = cat(mvout_cmd_rs2_hi_hi_1, mvout_cmd_rs2._spacer1) node _mvout_cmd_rs2_T_2 = cat(mvout_cmd_rs2_hi_1, mvout_cmd_rs2_lo_1) connect mvout_cmd.rs2, _mvout_cmd_rs2_T_2 reg ln_row : UInt<16>, clock reg ln_cmd : UInt<16>, clock reg ln_stat_id : UInt<16>, clock wire _ln_norm_cmds_WIRE : UInt<3>[2] connect _ln_norm_cmds_WIRE[0], UInt<1>(0h1) connect _ln_norm_cmds_WIRE[1], UInt<2>(0h2) wire _ln_norm_cmds_WIRE_1 : UInt<3>[2] connect _ln_norm_cmds_WIRE_1[0], UInt<2>(0h3) connect _ln_norm_cmds_WIRE_1[1], UInt<3>(0h4) wire _ln_norm_cmds_WIRE_2 : UInt<3>[2] connect _ln_norm_cmds_WIRE_2[0], UInt<1>(0h0) connect _ln_norm_cmds_WIRE_2[1], UInt<1>(0h0) wire ln_norm_cmds : UInt<3>[2][3] connect ln_norm_cmds[0], _ln_norm_cmds_WIRE connect ln_norm_cmds[1], _ln_norm_cmds_WIRE_1 connect ln_norm_cmds[2], _ln_norm_cmds_WIRE_2 wire _sm_norm_cmds_WIRE : UInt<3>[2] connect _sm_norm_cmds_WIRE[0], UInt<3>(0h5) connect _sm_norm_cmds_WIRE[1], UInt<3>(0h5) wire _sm_norm_cmds_WIRE_1 : UInt<3>[2] connect _sm_norm_cmds_WIRE_1[0], UInt<3>(0h6) connect _sm_norm_cmds_WIRE_1[1], UInt<3>(0h7) wire _sm_norm_cmds_WIRE_2 : UInt<3>[2] connect _sm_norm_cmds_WIRE_2[0], UInt<1>(0h0) connect _sm_norm_cmds_WIRE_2[1], UInt<1>(0h0) wire sm_norm_cmds : UInt<3>[2][3] connect sm_norm_cmds[0], _sm_norm_cmds_WIRE connect sm_norm_cmds[1], _sm_norm_cmds_WIRE_1 connect sm_norm_cmds[2], _sm_norm_cmds_WIRE_2 node _ln_stat_ids_T = sub(rows, ln_row) node _ln_stat_ids_T_1 = asUInt(_ln_stat_ids_T) node _ln_stat_ids_T_2 = gt(_ln_stat_ids_T_1, UInt<2>(0h2)) node _ln_stat_ids_T_3 = sub(rows, ln_row) node _ln_stat_ids_T_4 = asUInt(_ln_stat_ids_T_3) node ln_stat_ids = mux(_ln_stat_ids_T_2, UInt<2>(0h2), _ln_stat_ids_T_4) node ln_r = add(ln_row, ln_stat_id) node _ln_sp_addr_T = mul(i, req.max_j) node _ln_sp_addr_T_1 = add(_ln_sp_addr_T, j) node _ln_sp_addr_T_2 = mul(_ln_sp_addr_T_1, UInt<3>(0h4)) node _ln_sp_addr_T_3 = add(req.addr_start, _ln_sp_addr_T_2) node ln_sp_addr = add(_ln_sp_addr_T_3, ln_r) node _ln_norm_cmd_T = add(j, max_blocks) node _ln_norm_cmd_T_1 = geq(_ln_norm_cmd_T, req.max_j) node _ln_norm_cmd_T_2 = eq(req.act, UInt<2>(0h2)) node _ln_norm_cmd_T_3 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_4 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_5 = mux(_ln_norm_cmd_T_2, ln_norm_cmds[_ln_norm_cmd_T_3][1], sm_norm_cmds[_ln_norm_cmd_T_4][1]) node _ln_norm_cmd_T_6 = eq(req.act, UInt<2>(0h2)) node _ln_norm_cmd_T_7 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_8 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_9 = mux(_ln_norm_cmd_T_6, ln_norm_cmds[_ln_norm_cmd_T_7][0], sm_norm_cmds[_ln_norm_cmd_T_8][0]) node ln_norm_cmd = mux(_ln_norm_cmd_T_1, _ln_norm_cmd_T_5, _ln_norm_cmd_T_9) node _ln_dram_offset_T = mul(i, req.dram_stride) node _ln_dram_offset_T_1 = add(_ln_dram_offset_T, j) node _ln_dram_offset_T_2 = mul(_ln_dram_offset_T_1, UInt<3>(0h4)) node _ln_dram_offset_T_3 = mul(ln_r, req.dram_stride) node _ln_dram_offset_T_4 = add(_ln_dram_offset_T_2, _ln_dram_offset_T_3) node ln_dram_offset = mul(_ln_dram_offset_T_4, UInt<3>(0h4)) node _ln_dram_addr_T = and(ln_dram_offset, UInt<32>(0hffffffff)) node _ln_dram_addr_T_1 = add(req.dram_addr, _ln_dram_addr_T) node ln_dram_addr = tail(_ln_dram_addr_T_1, 1) wire ln_config_norm_rs1 : { q_const : UInt<32>, _spacer1 : UInt<13>, q_const_type : UInt<1>, set_stats_id_only : UInt<1>, act_msb : UInt<1>, norm_stats_id : UInt<8>, _spacer0 : UInt<6>, cmd_type : UInt<2>} invalidate ln_config_norm_rs1.cmd_type invalidate ln_config_norm_rs1._spacer0 invalidate ln_config_norm_rs1.norm_stats_id invalidate ln_config_norm_rs1.act_msb invalidate ln_config_norm_rs1.set_stats_id_only invalidate ln_config_norm_rs1.q_const_type invalidate ln_config_norm_rs1._spacer1 invalidate ln_config_norm_rs1.q_const connect ln_config_norm_rs1.set_stats_id_only, UInt<1>(0h1) connect ln_config_norm_rs1.cmd_type, UInt<2>(0h3) connect ln_config_norm_rs1.norm_stats_id, ln_stat_id wire ln_config_norm : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate ln_config_norm.status.uie invalidate ln_config_norm.status.sie invalidate ln_config_norm.status.hie invalidate ln_config_norm.status.mie invalidate ln_config_norm.status.upie invalidate ln_config_norm.status.spie invalidate ln_config_norm.status.ube invalidate ln_config_norm.status.mpie invalidate ln_config_norm.status.spp invalidate ln_config_norm.status.vs invalidate ln_config_norm.status.mpp invalidate ln_config_norm.status.fs invalidate ln_config_norm.status.xs invalidate ln_config_norm.status.mprv invalidate ln_config_norm.status.sum invalidate ln_config_norm.status.mxr invalidate ln_config_norm.status.tvm invalidate ln_config_norm.status.tw invalidate ln_config_norm.status.tsr invalidate ln_config_norm.status.zero1 invalidate ln_config_norm.status.sd_rv32 invalidate ln_config_norm.status.uxl invalidate ln_config_norm.status.sxl invalidate ln_config_norm.status.sbe invalidate ln_config_norm.status.mbe invalidate ln_config_norm.status.gva invalidate ln_config_norm.status.mpv invalidate ln_config_norm.status.zero2 invalidate ln_config_norm.status.sd invalidate ln_config_norm.status.v invalidate ln_config_norm.status.prv invalidate ln_config_norm.status.dv invalidate ln_config_norm.status.dprv invalidate ln_config_norm.status.isa invalidate ln_config_norm.status.wfi invalidate ln_config_norm.status.cease invalidate ln_config_norm.status.debug invalidate ln_config_norm.rs2 invalidate ln_config_norm.rs1 invalidate ln_config_norm.inst.opcode invalidate ln_config_norm.inst.rd invalidate ln_config_norm.inst.xs2 invalidate ln_config_norm.inst.xs1 invalidate ln_config_norm.inst.xd invalidate ln_config_norm.inst.rs1 invalidate ln_config_norm.inst.rs2 invalidate ln_config_norm.inst.funct connect ln_config_norm.inst.funct, UInt<1>(0h0) node ln_config_norm_rs1_lo_lo = cat(ln_config_norm_rs1._spacer0, ln_config_norm_rs1.cmd_type) node ln_config_norm_rs1_lo_hi = cat(ln_config_norm_rs1.act_msb, ln_config_norm_rs1.norm_stats_id) node ln_config_norm_rs1_lo = cat(ln_config_norm_rs1_lo_hi, ln_config_norm_rs1_lo_lo) node ln_config_norm_rs1_hi_lo = cat(ln_config_norm_rs1.q_const_type, ln_config_norm_rs1.set_stats_id_only) node ln_config_norm_rs1_hi_hi = cat(ln_config_norm_rs1.q_const, ln_config_norm_rs1._spacer1) node ln_config_norm_rs1_hi = cat(ln_config_norm_rs1_hi_hi, ln_config_norm_rs1_hi_lo) node _ln_config_norm_rs1_T = cat(ln_config_norm_rs1_hi, ln_config_norm_rs1_lo) connect ln_config_norm.rs1, _ln_config_norm_rs1_T invalidate ln_config_norm.rs2 wire ln_mvout_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate ln_mvout_cmd.status.uie invalidate ln_mvout_cmd.status.sie invalidate ln_mvout_cmd.status.hie invalidate ln_mvout_cmd.status.mie invalidate ln_mvout_cmd.status.upie invalidate ln_mvout_cmd.status.spie invalidate ln_mvout_cmd.status.ube invalidate ln_mvout_cmd.status.mpie invalidate ln_mvout_cmd.status.spp invalidate ln_mvout_cmd.status.vs invalidate ln_mvout_cmd.status.mpp invalidate ln_mvout_cmd.status.fs invalidate ln_mvout_cmd.status.xs invalidate ln_mvout_cmd.status.mprv invalidate ln_mvout_cmd.status.sum invalidate ln_mvout_cmd.status.mxr invalidate ln_mvout_cmd.status.tvm invalidate ln_mvout_cmd.status.tw invalidate ln_mvout_cmd.status.tsr invalidate ln_mvout_cmd.status.zero1 invalidate ln_mvout_cmd.status.sd_rv32 invalidate ln_mvout_cmd.status.uxl invalidate ln_mvout_cmd.status.sxl invalidate ln_mvout_cmd.status.sbe invalidate ln_mvout_cmd.status.mbe invalidate ln_mvout_cmd.status.gva invalidate ln_mvout_cmd.status.mpv invalidate ln_mvout_cmd.status.zero2 invalidate ln_mvout_cmd.status.sd invalidate ln_mvout_cmd.status.v invalidate ln_mvout_cmd.status.prv invalidate ln_mvout_cmd.status.dv invalidate ln_mvout_cmd.status.dprv invalidate ln_mvout_cmd.status.isa invalidate ln_mvout_cmd.status.wfi invalidate ln_mvout_cmd.status.cease invalidate ln_mvout_cmd.status.debug invalidate ln_mvout_cmd.rs2 invalidate ln_mvout_cmd.rs1 invalidate ln_mvout_cmd.inst.opcode invalidate ln_mvout_cmd.inst.rd invalidate ln_mvout_cmd.inst.xs2 invalidate ln_mvout_cmd.inst.xs1 invalidate ln_mvout_cmd.inst.xd invalidate ln_mvout_cmd.inst.rs1 invalidate ln_mvout_cmd.inst.rs2 invalidate ln_mvout_cmd.inst.funct connect ln_mvout_cmd.inst.funct, UInt<2>(0h3) connect ln_mvout_cmd.rs1, ln_dram_addr wire ln_mvout_cmd_rs2 : { _spacer2 : UInt<13>, num_rows : UInt<3>, _spacer1 : UInt<11>, num_cols : UInt<5>, _spacer0 : UInt<0>, local_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}} invalidate ln_mvout_cmd_rs2.local_addr.data invalidate ln_mvout_cmd_rs2.local_addr.garbage_bit invalidate ln_mvout_cmd_rs2.local_addr.garbage invalidate ln_mvout_cmd_rs2.local_addr.norm_cmd invalidate ln_mvout_cmd_rs2.local_addr.read_full_acc_row invalidate ln_mvout_cmd_rs2.local_addr.accumulate invalidate ln_mvout_cmd_rs2.local_addr.is_acc_addr invalidate ln_mvout_cmd_rs2._spacer0 invalidate ln_mvout_cmd_rs2.num_cols invalidate ln_mvout_cmd_rs2._spacer1 invalidate ln_mvout_cmd_rs2.num_rows invalidate ln_mvout_cmd_rs2._spacer2 connect ln_mvout_cmd_rs2.num_rows, UInt<1>(0h1) connect ln_mvout_cmd_rs2.num_cols, cols wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1 : UInt<32> connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, ln_sp_addr node _ln_mvout_cmd_rs2_local_addr_result_result_T = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 13, 0) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.data, _ln_mvout_cmd_rs2_local_addr_result_result_T node _ln_mvout_cmd_rs2_local_addr_result_result_T_1 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 14, 14) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.garbage_bit, _ln_mvout_cmd_rs2_local_addr_result_result_T_1 node _ln_mvout_cmd_rs2_local_addr_result_result_T_2 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 25, 15) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.garbage, _ln_mvout_cmd_rs2_local_addr_result_result_T_2 node _ln_mvout_cmd_rs2_local_addr_result_result_T_3 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 28, 26) wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2 : UInt<3> connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2, _ln_mvout_cmd_rs2_local_addr_result_result_T_3 wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3 : UInt<3> connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3, _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2 connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.norm_cmd, _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3 node _ln_mvout_cmd_rs2_local_addr_result_result_T_4 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 29, 29) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.read_full_acc_row, _ln_mvout_cmd_rs2_local_addr_result_result_T_4 node _ln_mvout_cmd_rs2_local_addr_result_result_T_5 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 30, 30) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.accumulate, _ln_mvout_cmd_rs2_local_addr_result_result_T_5 node _ln_mvout_cmd_rs2_local_addr_result_result_T_6 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 31, 31) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.is_acc_addr, _ln_mvout_cmd_rs2_local_addr_result_result_T_6 wire ln_mvout_cmd_rs2_local_addr_result_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect ln_mvout_cmd_rs2_local_addr_result_result, _ln_mvout_cmd_rs2_local_addr_result_result_WIRE connect ln_mvout_cmd_rs2_local_addr_result_result.garbage, UInt<1>(0h0) wire ln_mvout_cmd_rs2_local_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect ln_mvout_cmd_rs2_local_addr_result, ln_mvout_cmd_rs2_local_addr_result_result connect ln_mvout_cmd_rs2_local_addr_result.is_acc_addr, UInt<1>(0h1) connect ln_mvout_cmd_rs2_local_addr_result.accumulate, UInt<1>(0h0) connect ln_mvout_cmd_rs2_local_addr_result.read_full_acc_row, req.full_c connect ln_mvout_cmd_rs2.local_addr, ln_mvout_cmd_rs2_local_addr_result connect ln_mvout_cmd_rs2.local_addr.norm_cmd, ln_norm_cmd node _ln_mvout_cmd_rs2_T = asUInt(ln_mvout_cmd_rs2.local_addr.norm_cmd) node ln_mvout_cmd_rs2_lo_hi = cat(ln_mvout_cmd_rs2.local_addr.garbage, ln_mvout_cmd_rs2.local_addr.garbage_bit) node ln_mvout_cmd_rs2_lo = cat(ln_mvout_cmd_rs2_lo_hi, ln_mvout_cmd_rs2.local_addr.data) node ln_mvout_cmd_rs2_hi_lo = cat(ln_mvout_cmd_rs2.local_addr.read_full_acc_row, _ln_mvout_cmd_rs2_T) node ln_mvout_cmd_rs2_hi_hi = cat(ln_mvout_cmd_rs2.local_addr.is_acc_addr, ln_mvout_cmd_rs2.local_addr.accumulate) node ln_mvout_cmd_rs2_hi = cat(ln_mvout_cmd_rs2_hi_hi, ln_mvout_cmd_rs2_hi_lo) node _ln_mvout_cmd_rs2_T_1 = cat(ln_mvout_cmd_rs2_hi, ln_mvout_cmd_rs2_lo) node ln_mvout_cmd_rs2_lo_hi_1 = cat(ln_mvout_cmd_rs2.num_cols, ln_mvout_cmd_rs2._spacer0) node ln_mvout_cmd_rs2_lo_1 = cat(ln_mvout_cmd_rs2_lo_hi_1, _ln_mvout_cmd_rs2_T_1) node ln_mvout_cmd_rs2_hi_hi_1 = cat(ln_mvout_cmd_rs2._spacer2, ln_mvout_cmd_rs2.num_rows) node ln_mvout_cmd_rs2_hi_1 = cat(ln_mvout_cmd_rs2_hi_hi_1, ln_mvout_cmd_rs2._spacer1) node _ln_mvout_cmd_rs2_T_2 = cat(ln_mvout_cmd_rs2_hi_1, ln_mvout_cmd_rs2_lo_1) connect ln_mvout_cmd.rs2, _ln_mvout_cmd_rs2_T_2 node _io_req_ready_T = eq(state, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T connect io.j, j connect io.i, i node _io_idle_T = eq(state, UInt<1>(0h0)) connect io.idle, _io_idle_T node _ex_ahead_T = neq(req.act, UInt<2>(0h2)) node _ex_ahead_T_1 = neq(req.act, UInt<3>(0h4)) node _ex_ahead_T_2 = and(_ex_ahead_T, _ex_ahead_T_1) node _ex_ahead_T_3 = sub(req.max_k, UInt<1>(0h1)) node _ex_ahead_T_4 = tail(_ex_ahead_T_3, 1) node _ex_ahead_T_5 = eq(io.ex_k, _ex_ahead_T_4) node _ex_ahead_T_6 = add(j, blocks) node _ex_ahead_T_7 = tail(_ex_ahead_T_6, 1) node _ex_ahead_T_8 = geq(io.ex_j, _ex_ahead_T_7) node _ex_ahead_T_9 = add(j, blocks) node _ex_ahead_T_10 = tail(_ex_ahead_T_9, 1) node _ex_ahead_T_11 = sub(_ex_ahead_T_10, UInt<1>(0h1)) node _ex_ahead_T_12 = tail(_ex_ahead_T_11, 1) node _ex_ahead_T_13 = eq(io.ex_j, _ex_ahead_T_12) node _ex_ahead_T_14 = gt(io.ex_i, i) node _ex_ahead_T_15 = and(_ex_ahead_T_13, _ex_ahead_T_14) node _ex_ahead_T_16 = or(_ex_ahead_T_8, _ex_ahead_T_15) node _ex_ahead_T_17 = and(_ex_ahead_T_5, _ex_ahead_T_16) node _ex_ahead_T_18 = and(_ex_ahead_T_2, _ex_ahead_T_17) node _ex_ahead_T_19 = or(io.ex_completed, _ex_ahead_T_18) wire ex_ahead : UInt<1> connect ex_ahead, _ex_ahead_T_19 when req.is_resadd : node _ex_ahead_T_20 = gt(io.ex_i, i) node _ex_ahead_T_21 = eq(io.ex_i, i) node _ex_ahead_T_22 = add(j, blocks) node _ex_ahead_T_23 = tail(_ex_ahead_T_22, 1) node _ex_ahead_T_24 = geq(io.ex_j, _ex_ahead_T_23) node _ex_ahead_T_25 = and(_ex_ahead_T_21, _ex_ahead_T_24) node _ex_ahead_T_26 = or(_ex_ahead_T_20, _ex_ahead_T_25) node _ex_ahead_T_27 = or(io.ex_completed, _ex_ahead_T_26) connect ex_ahead, _ex_ahead_T_27 node _io_cmd_valid_T = neq(state, UInt<1>(0h0)) node _io_cmd_valid_T_1 = eq(io.rob_overloaded, UInt<1>(0h0)) node _io_cmd_valid_T_2 = and(_io_cmd_valid_T, _io_cmd_valid_T_1) node _io_cmd_valid_T_3 = and(_io_cmd_valid_T_2, ex_ahead) node _io_cmd_valid_T_4 = neq(req.dram_addr, UInt<1>(0h0)) node _io_cmd_valid_T_5 = and(_io_cmd_valid_T_3, _io_cmd_valid_T_4) connect io.cmd.valid, _io_cmd_valid_T_5 node _io_cmd_bits_T = eq(state, UInt<2>(0h2)) node _io_cmd_bits_T_1 = eq(state, UInt<2>(0h3)) node _io_cmd_bits_T_2 = mux(_io_cmd_bits_T_1, ln_mvout_cmd, mvout_cmd) node _io_cmd_bits_T_3 = mux(_io_cmd_bits_T, ln_config_norm, _io_cmd_bits_T_2) connect io.cmd.bits, _io_cmd_bits_T_3 connect io.loop_id, req.loop_id node _T = eq(req.dram_addr, UInt<1>(0h0)) when _T : connect state, UInt<1>(0h0) else : node _T_1 = and(io.cmd.ready, io.cmd.valid) node _T_2 = eq(state, UInt<1>(0h1)) node _T_3 = and(_T_1, _T_2) when _T_3 : node _next_i_max_T = sub(req.max_i, UInt<1>(0h1)) node next_i_max = tail(_next_i_max_T, 1) node _next_i_T = add(i, UInt<1>(0h1)) node _next_i_T_1 = tail(_next_i_T, 1) node _next_i_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _next_i_T_3 = add(i, UInt<1>(0h1)) node _next_i_T_4 = gt(_next_i_T_3, next_i_max) node _next_i_T_5 = mux(_next_i_T_4, UInt<1>(0h0), _next_i_T_1) node next_i = mux(_next_i_T_2, i, _next_i_T_5) node _next_j_T = eq(next_i, UInt<1>(0h0)) node _next_j_max_T = sub(req.max_j, UInt<1>(0h1)) node next_j_max = tail(_next_j_max_T, 1) node _next_j_T_1 = add(j, max_blocks) node _next_j_T_2 = tail(_next_j_T_1, 1) node _next_j_T_3 = eq(_next_j_T, UInt<1>(0h0)) node _next_j_T_4 = add(j, max_blocks) node _next_j_T_5 = gt(_next_j_T_4, next_j_max) node _next_j_T_6 = mux(_next_j_T_5, UInt<1>(0h0), _next_j_T_2) node next_j = mux(_next_j_T_3, j, _next_j_T_6) connect i, next_i connect j, next_j node _T_4 = eq(next_i, UInt<1>(0h0)) node _T_5 = eq(next_j, UInt<1>(0h0)) node _T_6 = and(_T_4, _T_5) when _T_6 : connect state, UInt<1>(0h0) else : node _T_7 = and(io.cmd.ready, io.cmd.valid) node _T_8 = eq(state, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) when _T_9 : connect state, UInt<2>(0h3) else : node _T_10 = and(io.cmd.ready, io.cmd.valid) node _T_11 = eq(state, UInt<2>(0h3)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _next_j_max_T_1 = sub(req.max_j, UInt<1>(0h1)) node next_j_max_1 = tail(_next_j_max_T_1, 1) node _next_j_T_7 = add(j, max_blocks) node _next_j_T_8 = tail(_next_j_T_7, 1) node _next_j_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _next_j_T_10 = add(j, max_blocks) node _next_j_T_11 = gt(_next_j_T_10, next_j_max_1) node _next_j_T_12 = mux(_next_j_T_11, UInt<1>(0h0), _next_j_T_8) node next_j_1 = mux(_next_j_T_9, j, _next_j_T_12) node _next_stat_id_T = eq(next_j_1, UInt<1>(0h0)) node _next_stat_id_max_T = sub(ln_stat_ids, UInt<1>(0h1)) node next_stat_id_max = tail(_next_stat_id_max_T, 1) node _next_stat_id_T_1 = add(ln_stat_id, UInt<1>(0h1)) node _next_stat_id_T_2 = tail(_next_stat_id_T_1, 1) node _next_stat_id_T_3 = eq(_next_stat_id_T, UInt<1>(0h0)) node _next_stat_id_T_4 = add(ln_stat_id, UInt<1>(0h1)) node _next_stat_id_T_5 = gt(_next_stat_id_T_4, next_stat_id_max) node _next_stat_id_T_6 = mux(_next_stat_id_T_5, UInt<1>(0h0), _next_stat_id_T_2) node next_stat_id = mux(_next_stat_id_T_3, ln_stat_id, _next_stat_id_T_6) node _next_cmd_T = eq(next_j_1, UInt<1>(0h0)) node _next_cmd_T_1 = eq(next_stat_id, UInt<1>(0h0)) node _next_cmd_T_2 = and(_next_cmd_T, _next_cmd_T_1) node _next_cmd_max_T = sub(UInt<2>(0h3), UInt<1>(0h1)) node next_cmd_max = tail(_next_cmd_max_T, 1) node _next_cmd_T_3 = add(ln_cmd, UInt<1>(0h1)) node _next_cmd_T_4 = tail(_next_cmd_T_3, 1) node _next_cmd_T_5 = eq(_next_cmd_T_2, UInt<1>(0h0)) node _next_cmd_T_6 = add(ln_cmd, UInt<1>(0h1)) node _next_cmd_T_7 = gt(_next_cmd_T_6, next_cmd_max) node _next_cmd_T_8 = mux(_next_cmd_T_7, UInt<1>(0h0), _next_cmd_T_4) node next_cmd = mux(_next_cmd_T_5, ln_cmd, _next_cmd_T_8) node _next_row_T = eq(next_j_1, UInt<1>(0h0)) node _next_row_T_1 = eq(next_stat_id, UInt<1>(0h0)) node _next_row_T_2 = and(_next_row_T, _next_row_T_1) node _next_row_T_3 = eq(next_cmd, UInt<1>(0h0)) node _next_row_T_4 = and(_next_row_T_2, _next_row_T_3) node _next_row_max_T = sub(rows, UInt<1>(0h1)) node next_row_max = tail(_next_row_max_T, 1) node _next_row_T_5 = add(ln_row, UInt<2>(0h2)) node _next_row_T_6 = tail(_next_row_T_5, 1) node _next_row_T_7 = eq(_next_row_T_4, UInt<1>(0h0)) node _next_row_T_8 = add(ln_row, UInt<2>(0h2)) node _next_row_T_9 = gt(_next_row_T_8, next_row_max) node _next_row_T_10 = mux(_next_row_T_9, UInt<1>(0h0), _next_row_T_6) node next_row = mux(_next_row_T_7, ln_row, _next_row_T_10) node _next_i_T_6 = eq(next_j_1, UInt<1>(0h0)) node _next_i_T_7 = eq(next_stat_id, UInt<1>(0h0)) node _next_i_T_8 = and(_next_i_T_6, _next_i_T_7) node _next_i_T_9 = eq(next_cmd, UInt<1>(0h0)) node _next_i_T_10 = and(_next_i_T_8, _next_i_T_9) node _next_i_T_11 = eq(next_row, UInt<1>(0h0)) node _next_i_T_12 = and(_next_i_T_10, _next_i_T_11) node _next_i_max_T_1 = sub(req.max_i, UInt<1>(0h1)) node next_i_max_1 = tail(_next_i_max_T_1, 1) node _next_i_T_13 = add(i, UInt<1>(0h1)) node _next_i_T_14 = tail(_next_i_T_13, 1) node _next_i_T_15 = eq(_next_i_T_12, UInt<1>(0h0)) node _next_i_T_16 = add(i, UInt<1>(0h1)) node _next_i_T_17 = gt(_next_i_T_16, next_i_max_1) node _next_i_T_18 = mux(_next_i_T_17, UInt<1>(0h0), _next_i_T_14) node next_i_1 = mux(_next_i_T_15, i, _next_i_T_18) connect j, next_j_1 connect ln_stat_id, next_stat_id connect ln_cmd, next_cmd connect ln_row, next_row connect i, next_i_1 node _T_13 = eq(next_i_1, UInt<1>(0h0)) node _T_14 = eq(next_row, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(next_cmd, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(next_stat_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(next_j_1, UInt<1>(0h0)) node _T_21 = and(_T_19, _T_20) when _T_21 : connect state, UInt<1>(0h0) else : node _T_22 = eq(next_j_1, UInt<1>(0h0)) when _T_22 : connect state, UInt<2>(0h2) node _T_23 = and(io.req.ready, io.req.valid) when _T_23 : connect req, io.req.bits node _state_T = eq(io.req.bits.act, UInt<2>(0h2)) node _state_T_1 = eq(io.req.bits.act, UInt<3>(0h4)) node _state_T_2 = or(_state_T, _state_T_1) node _state_T_3 = mux(_state_T_2, UInt<2>(0h2), UInt<1>(0h1)) connect state, _state_T_3 connect j, UInt<1>(0h0) connect i, UInt<1>(0h0) connect ln_row, UInt<1>(0h0) connect ln_cmd, UInt<1>(0h0) connect ln_stat_id, UInt<1>(0h0)	module LoopMatmulStC( // @[LoopMatmul.scala:514:7] input clock, // @[LoopMatmul.scala:514:7] input reset, // @[LoopMatmul.scala:514:7] output io_req_ready, // @[LoopMatmul.scala:516:14] input io_req_valid, // @[LoopMatmul.scala:516:14] input [15:0] io_req_bits_max_k, // @[LoopMatmul.scala:516:14] input [15:0] io_req_bits_max_j, // @[LoopMatmul.scala:516:14] input [15:0] io_req_bits_max_i, // @[LoopMatmul.scala:516:14] input [1:0] io_req_bits_pad_j, // @[LoopMatmul.scala:516:14] input [1:0] io_req_bits_pad_i, // @[LoopMatmul.scala:516:14] input [39:0] io_req_bits_dram_addr, // @[LoopMatmul.scala:516:14] input [39:0] io_req_bits_dram_stride, // @[LoopMatmul.scala:516:14] input io_req_bits_full_c, // @[LoopMatmul.scala:516:14] input [2:0] io_req_bits_act, // @[LoopMatmul.scala:516:14] input [11:0] io_req_bits_addr_start, // @[LoopMatmul.scala:516:14] input io_req_bits_loop_id, // @[LoopMatmul.scala:516:14] input io_req_bits_is_resadd, // @[LoopMatmul.scala:516:14] input io_cmd_ready, // @[LoopMatmul.scala:516:14] output io_cmd_valid, // @[LoopMatmul.scala:516:14] output [6:0] io_cmd_bits_inst_funct, // @[LoopMatmul.scala:516:14] output [63:0] io_cmd_bits_rs1, // @[LoopMatmul.scala:516:14] output [63:0] io_cmd_bits_rs2, // @[LoopMatmul.scala:516:14] input [15:0] io_ex_k, // @[LoopMatmul.scala:516:14] input [15:0] io_ex_j, // @[LoopMatmul.scala:516:14] input [15:0] io_ex_i, // @[LoopMatmul.scala:516:14] input io_ex_completed, // @[LoopMatmul.scala:516:14] output io_idle, // @[LoopMatmul.scala:516:14] input io_rob_overloaded, // @[LoopMatmul.scala:516:14] output io_loop_id // @[LoopMatmul.scala:516:14] ); wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [4:0] mvout_cmd_rs2_num_cols; // @[LoopMatmul.scala:563:27] wire [2:0] mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:563:27] wire io_req_valid_0 = io_req_valid; // @[LoopMatmul.scala:514:7] wire [15:0] io_req_bits_max_k_0 = io_req_bits_max_k; // @[LoopMatmul.scala:514:7] wire [15:0] io_req_bits_max_j_0 = io_req_bits_max_j; // @[LoopMatmul.scala:514:7] wire [15:0] io_req_bits_max_i_0 = io_req_bits_max_i; // @[LoopMatmul.scala:514:7] wire [1:0] io_req_bits_pad_j_0 = io_req_bits_pad_j; // @[LoopMatmul.scala:514:7] wire [1:0] io_req_bits_pad_i_0 = io_req_bits_pad_i; // @[LoopMatmul.scala:514:7] wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopMatmul.scala:514:7] wire [39:0] io_req_bits_dram_stride_0 = io_req_bits_dram_stride; // @[LoopMatmul.scala:514:7] wire io_req_bits_full_c_0 = io_req_bits_full_c; // @[LoopMatmul.scala:514:7] wire [2:0] io_req_bits_act_0 = io_req_bits_act; // @[LoopMatmul.scala:514:7] wire [11:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopMatmul.scala:514:7] wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopMatmul.scala:514:7] wire io_req_bits_is_resadd_0 = io_req_bits_is_resadd; // @[LoopMatmul.scala:514:7] wire io_cmd_ready_0 = io_cmd_ready; // @[LoopMatmul.scala:514:7] wire [15:0] io_ex_k_0 = io_ex_k; // @[LoopMatmul.scala:514:7] wire [15:0] io_ex_j_0 = io_ex_j; // @[LoopMatmul.scala:514:7] wire [15:0] io_ex_i_0 = io_ex_i; // @[LoopMatmul.scala:514:7] wire io_ex_completed_0 = io_ex_completed; // @[LoopMatmul.scala:514:7] wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopMatmul.scala:514:7] wire [3:0][2:0] _GEN = '{3'h5, 3'h0, 3'h6, 3'h5}; wire [3:0][2:0] _GEN_0 = '{3'h1, 3'h0, 3'h3, 3'h1}; wire [3:0][2:0] _GEN_1 = '{3'h5, 3'h0, 3'h7, 3'h5}; wire [3:0][2:0] _GEN_2 = '{3'h2, 3'h0, 3'h4, 3'h2}; wire [2:0] _ln_norm_cmds_WIRE_1_0 = 3'h3; // @[LoopMatmul.scala:577:73] wire [2:0] ln_norm_cmds_1_0 = 3'h3; // @[LoopMatmul.scala:577:29] wire [2:0] _ln_norm_cmds_WIRE_1_1 = 3'h4; // @[LoopMatmul.scala:577:73] wire [2:0] ln_norm_cmds_1_1 = 3'h4; // @[LoopMatmul.scala:577:29] wire [2:0] _sm_norm_cmds_WIRE_0 = 3'h5; // @[LoopMatmul.scala:580:37] wire [2:0] _sm_norm_cmds_WIRE_1 = 3'h5; // @[LoopMatmul.scala:580:37] wire [2:0] sm_norm_cmds_0_0 = 3'h5; // @[LoopMatmul.scala:580:29] wire [2:0] sm_norm_cmds_0_1 = 3'h5; // @[LoopMatmul.scala:580:29] wire [2:0] _sm_norm_cmds_WIRE_1_0 = 3'h6; // @[LoopMatmul.scala:580:72] wire [2:0] sm_norm_cmds_1_0 = 3'h6; // @[LoopMatmul.scala:580:29] wire [2:0] _sm_norm_cmds_WIRE_1_1 = 3'h7; // @[LoopMatmul.scala:580:72] wire [2:0] sm_norm_cmds_1_1 = 3'h7; // @[LoopMatmul.scala:580:29] wire [2:0] _ln_norm_cmds_WIRE_2_0 = 3'h0; // @[LoopMatmul.scala:578:12] wire [2:0] _ln_norm_cmds_WIRE_2_1 = 3'h0; // @[LoopMatmul.scala:578:12] wire [2:0] ln_norm_cmds_2_0 = 3'h0; // @[LoopMatmul.scala:577:29] wire [2:0] ln_norm_cmds_2_1 = 3'h0; // @[LoopMatmul.scala:577:29] wire [2:0] _sm_norm_cmds_WIRE_2_0 = 3'h0; // @[LoopMatmul.scala:581:12] wire [2:0] _sm_norm_cmds_WIRE_2_1 = 3'h0; // @[LoopMatmul.scala:581:12] wire [2:0] sm_norm_cmds_2_0 = 3'h0; // @[LoopMatmul.scala:580:29] wire [2:0] sm_norm_cmds_2_1 = 3'h0; // @[LoopMatmul.scala:580:29] wire [5:0] ln_config_norm_rs1__spacer0 = 6'h0; // @[LoopMatmul.scala:596:32] wire [1:0] ln_config_norm_rs1_cmd_type = 2'h3; // @[LoopMatmul.scala:596:32] wire [63:0] ln_config_norm_rs2 = 64'h0; // @[LoopMatmul.scala:602:28] wire [7:0] ln_config_norm_rs1_lo_lo = 8'h3; // @[LoopMatmul.scala:605:44] wire [1:0] ln_config_norm_rs1_hi_lo = 2'h1; // @[LoopMatmul.scala:605:44, :646:36] wire [44:0] ln_config_norm_rs1_hi_hi = 45'h0; // @[LoopMatmul.scala:605:44] wire [46:0] ln_config_norm_rs1_hi = 47'h1; // @[LoopMatmul.scala:605:44] wire [12:0] mvout_cmd_rs2__spacer2 = 13'h0; // @[LoopMatmul.scala:563:27] wire [12:0] ln_config_norm_rs1__spacer1 = 13'h0; // @[LoopMatmul.scala:596:32] wire [12:0] ln_mvout_cmd_rs2__spacer2 = 13'h0; // @[LoopMatmul.scala:613:30] wire [2:0] _ln_norm_cmds_WIRE_0 = 3'h1; // @[LoopMatmul.scala:577:37] wire [2:0] ln_norm_cmds_0_0 = 3'h1; // @[LoopMatmul.scala:577:29] wire [2:0] ln_mvout_cmd_rs2_num_rows = 3'h1; // @[LoopMatmul.scala:613:30] wire mvout_cmd_rs2_local_addr_is_acc_addr = 1'h1; // @[LoopMatmul.scala:563:27] wire mvout_cmd_rs2_local_addr_result_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire ln_config_norm_rs1_set_stats_id_only = 1'h1; // @[LoopMatmul.scala:596:32] wire ln_mvout_cmd_rs2_local_addr_is_acc_addr = 1'h1; // @[LoopMatmul.scala:613:30] wire ln_mvout_cmd_rs2_local_addr_result_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire [10:0] mvout_cmd_rs2__spacer1 = 11'h0; // @[LoopMatmul.scala:563:27] wire [10:0] mvout_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopMatmul.scala:563:27] wire [10:0] mvout_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvout_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [10:0] ln_mvout_cmd_rs2__spacer1 = 11'h0; // @[LoopMatmul.scala:613:30] wire [10:0] ln_mvout_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopMatmul.scala:613:30] wire [10:0] ln_mvout_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] ln_mvout_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [15:0] ln_mvout_cmd_rs2_hi_hi_1 = 16'h1; // @[LoopMatmul.scala:619:40] wire [26:0] ln_mvout_cmd_rs2_hi_1 = 27'h800; // @[LoopMatmul.scala:619:40] wire [6:0] mvout_cmd_inst_funct = 7'h3; // @[LoopMatmul.scala:558:23] wire [6:0] ln_mvout_cmd_inst_funct = 7'h3; // @[LoopMatmul.scala:608:26] wire [6:0] _io_cmd_bits_T_2_inst_funct = 7'h3; // @[Mux.scala:126:16] wire [2:0] _ln_norm_cmds_WIRE_1 = 3'h2; // @[LoopMatmul.scala:577:37, :589:17] wire [2:0] ln_norm_cmds_0_1 = 3'h2; // @[LoopMatmul.scala:577:29, :589:17] wire [2:0] _next_cmd_max_T = 3'h2; // @[Util.scala:39:28] wire [1:0] mvout_cmd_rs2_hi_hi = 2'h2; // @[LoopMatmul.scala:568:34] wire [1:0] ln_mvout_cmd_rs2_hi_hi = 2'h2; // @[LoopMatmul.scala:619:40] wire [1:0] next_cmd_max = 2'h2; // @[Util.scala:39:28] wire [7:0] io_cmd_bits_status_zero1 = 8'h0; // @[LoopMatmul.scala:514:7] wire [7:0] mvout_cmd_status_zero1 = 8'h0; // @[LoopMatmul.scala:558:23] wire [7:0] ln_config_norm_status_zero1 = 8'h0; // @[LoopMatmul.scala:602:28] wire [7:0] ln_mvout_cmd_status_zero1 = 8'h0; // @[LoopMatmul.scala:608:26] wire [7:0] _io_cmd_bits_T_2_status_zero1 = 8'h0; // @[Mux.scala:126:16] wire [7:0] _io_cmd_bits_T_3_status_zero1 = 8'h0; // @[Mux.scala:126:16] wire [22:0] io_cmd_bits_status_zero2 = 23'h0; // @[LoopMatmul.scala:514:7] wire [22:0] mvout_cmd_status_zero2 = 23'h0; // @[LoopMatmul.scala:558:23] wire [22:0] ln_config_norm_status_zero2 = 23'h0; // @[LoopMatmul.scala:602:28] wire [22:0] ln_mvout_cmd_status_zero2 = 23'h0; // @[LoopMatmul.scala:608:26] wire [22:0] _io_cmd_bits_T_2_status_zero2 = 23'h0; // @[Mux.scala:126:16] wire [22:0] _io_cmd_bits_T_3_status_zero2 = 23'h0; // @[Mux.scala:126:16] wire [1:0] io_cmd_bits_status_dprv = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_prv = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_sxl = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_uxl = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_xs = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_fs = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_mpp = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_vs = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] mvout_cmd_status_dprv = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_prv = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_sxl = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_uxl = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_xs = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_fs = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_mpp = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_vs = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] ln_config_norm_status_dprv = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_prv = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_sxl = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_uxl = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_xs = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_fs = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_mpp = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_vs = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_mvout_cmd_status_dprv = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_prv = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_sxl = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_uxl = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_xs = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_fs = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_mpp = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_vs = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] _io_cmd_bits_T_2_status_dprv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_prv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_sxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_uxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_xs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_fs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_mpp = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_vs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_dprv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_prv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_sxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_uxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_xs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_fs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_mpp = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_vs = 2'h0; // @[Mux.scala:126:16] wire [31:0] io_cmd_bits_status_isa = 32'h0; // @[LoopMatmul.scala:514:7] wire [31:0] mvout_cmd_status_isa = 32'h0; // @[LoopMatmul.scala:558:23] wire [31:0] ln_config_norm_rs1_q_const = 32'h0; // @[LoopMatmul.scala:596:32] wire [31:0] ln_config_norm_status_isa = 32'h0; // @[LoopMatmul.scala:602:28] wire [31:0] ln_mvout_cmd_status_isa = 32'h0; // @[LoopMatmul.scala:608:26] wire [31:0] _io_cmd_bits_T_2_status_isa = 32'h0; // @[Mux.scala:126:16] wire [31:0] _io_cmd_bits_T_3_status_isa = 32'h0; // @[Mux.scala:126:16] wire [6:0] io_cmd_bits_inst_opcode = 7'h0; // @[LoopMatmul.scala:514:7] wire [6:0] mvout_cmd_inst_opcode = 7'h0; // @[LoopMatmul.scala:558:23] wire [6:0] ln_config_norm_inst_funct = 7'h0; // @[LoopMatmul.scala:602:28] wire [6:0] ln_config_norm_inst_opcode = 7'h0; // @[LoopMatmul.scala:602:28] wire [6:0] ln_mvout_cmd_inst_opcode = 7'h0; // @[LoopMatmul.scala:608:26] wire [6:0] _io_cmd_bits_T_2_inst_opcode = 7'h0; // @[Mux.scala:126:16] wire [6:0] _io_cmd_bits_T_3_inst_opcode = 7'h0; // @[Mux.scala:126:16] wire io_cmd_bits_inst_xd = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_inst_xs1 = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_inst_xs2 = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_debug = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_cease = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_wfi = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_dv = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_v = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sd = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mpv = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_gva = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mbe = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sbe = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_tsr = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_tw = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_tvm = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mxr = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sum = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mprv = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_spp = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mpie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_ube = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_spie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_upie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_hie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_uie = 1'h0; // @[LoopMatmul.scala:514:7] wire mvout_cmd_inst_xd = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_inst_xs1 = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_inst_xs2 = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_debug = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_cease = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_wfi = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_dv = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_v = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sd = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mpv = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_gva = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mbe = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sbe = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_tsr = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_tw = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_tvm = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mxr = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sum = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mprv = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_spp = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mpie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_ube = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_spie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_upie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_hie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_uie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopMatmul.scala:563:27] wire mvout_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire ln_config_norm_rs1_q_const_type = 1'h0; // @[LoopMatmul.scala:596:32] wire ln_config_norm_rs1_act_msb = 1'h0; // @[LoopMatmul.scala:596:32] wire ln_config_norm_inst_xd = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_inst_xs1 = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_inst_xs2 = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_debug = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_cease = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_wfi = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_dv = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_v = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sd = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mpv = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_gva = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mbe = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sbe = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_tsr = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_tw = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_tvm = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mxr = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sum = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mprv = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_spp = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mpie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_ube = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_spie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_upie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_hie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_uie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_mvout_cmd_inst_xd = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_inst_xs1 = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_inst_xs2 = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_debug = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_cease = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_wfi = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_dv = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_v = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sd = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mpv = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_gva = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mbe = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sbe = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_tsr = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_tw = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_tvm = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mxr = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sum = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mprv = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_spp = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mpie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_ube = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_spie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_upie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_hie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_uie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopMatmul.scala:613:30] wire ln_mvout_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire _io_cmd_bits_T_2_inst_xd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_inst_xs1 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_inst_xs2 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_debug = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_cease = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_wfi = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_dv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_v = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mpv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_gva = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sd_rv32 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_tsr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_tw = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_tvm = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mxr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sum = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mprv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_spp = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mpie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_ube = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_spie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_upie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_hie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_uie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_inst_xd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_inst_xs1 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_inst_xs2 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_debug = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_cease = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_wfi = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_dv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_v = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mpv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_gva = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sd_rv32 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_tsr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_tw = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_tvm = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mxr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sum = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mprv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_spp = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mpie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_ube = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_spie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_upie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_hie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_uie = 1'h0; // @[Mux.scala:126:16] wire _next_i_T_2 = 1'h0; // @[Util.scala:42:8] wire _next_j_T_9 = 1'h0; // @[Util.scala:42:8] wire [4:0] io_cmd_bits_inst_rs2 = 5'h0; // @[LoopMatmul.scala:514:7] wire [4:0] io_cmd_bits_inst_rs1 = 5'h0; // @[LoopMatmul.scala:514:7] wire [4:0] io_cmd_bits_inst_rd = 5'h0; // @[LoopMatmul.scala:514:7] wire [4:0] mvout_cmd_inst_rs2 = 5'h0; // @[LoopMatmul.scala:558:23] wire [4:0] mvout_cmd_inst_rs1 = 5'h0; // @[LoopMatmul.scala:558:23] wire [4:0] mvout_cmd_inst_rd = 5'h0; // @[LoopMatmul.scala:558:23] wire [4:0] ln_config_norm_inst_rs2 = 5'h0; // @[LoopMatmul.scala:602:28] wire [4:0] ln_config_norm_inst_rs1 = 5'h0; // @[LoopMatmul.scala:602:28] wire [4:0] ln_config_norm_inst_rd = 5'h0; // @[LoopMatmul.scala:602:28] wire [4:0] ln_mvout_cmd_inst_rs2 = 5'h0; // @[LoopMatmul.scala:608:26] wire [4:0] ln_mvout_cmd_inst_rs1 = 5'h0; // @[LoopMatmul.scala:608:26] wire [4:0] ln_mvout_cmd_inst_rd = 5'h0; // @[LoopMatmul.scala:608:26] wire _io_req_ready_T; // @[LoopMatmul.scala:621:25] wire [4:0] _io_cmd_bits_T_2_inst_rs2 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_2_inst_rs1 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_2_inst_rd = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_3_inst_rs2 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_3_inst_rs1 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_3_inst_rd = 5'h0; // @[Mux.scala:126:16] wire _io_cmd_valid_T_5; // @[LoopMatmul.scala:636:68] wire [6:0] _io_cmd_bits_T_3_inst_funct; // @[Mux.scala:126:16] wire [63:0] _io_cmd_bits_T_3_rs1; // @[Mux.scala:126:16] wire [63:0] _io_cmd_bits_T_3_rs2; // @[Mux.scala:126:16] wire _io_idle_T; // @[LoopMatmul.scala:624:20] wire io_req_ready_0; // @[LoopMatmul.scala:514:7] wire [6:0] io_cmd_bits_inst_funct_0; // @[LoopMatmul.scala:514:7] wire [63:0] io_cmd_bits_rs1_0; // @[LoopMatmul.scala:514:7] wire [63:0] io_cmd_bits_rs2_0; // @[LoopMatmul.scala:514:7] wire io_cmd_valid_0; // @[LoopMatmul.scala:514:7] wire [15:0] io_j; // @[LoopMatmul.scala:514:7] wire [15:0] io_i; // @[LoopMatmul.scala:514:7] wire io_idle_0; // @[LoopMatmul.scala:514:7] wire io_loop_id_0; // @[LoopMatmul.scala:514:7] reg [1:0] state; // @[LoopMatmul.scala:538:22] reg [15:0] req_max_k; // @[LoopMatmul.scala:540:16] reg [15:0] req_max_j; // @[LoopMatmul.scala:540:16] reg [15:0] req_max_i; // @[LoopMatmul.scala:540:16] reg [1:0] req_pad_j; // @[LoopMatmul.scala:540:16] reg [1:0] req_pad_i; // @[LoopMatmul.scala:540:16] reg [39:0] req_dram_addr; // @[LoopMatmul.scala:540:16] reg [39:0] req_dram_stride; // @[LoopMatmul.scala:540:16] reg req_full_c; // @[LoopMatmul.scala:540:16] wire mvout_cmd_rs2_local_addr_result_read_full_acc_row = req_full_c; // @[LoopMatmul.scala:540:16] wire ln_mvout_cmd_rs2_local_addr_result_read_full_acc_row = req_full_c; // @[LoopMatmul.scala:540:16] reg [2:0] req_act; // @[LoopMatmul.scala:540:16] reg [11:0] req_addr_start; // @[LoopMatmul.scala:540:16] reg req_loop_id; // @[LoopMatmul.scala:540:16] assign io_loop_id_0 = req_loop_id; // @[LoopMatmul.scala:514:7, :540:16] reg req_is_resadd; // @[LoopMatmul.scala:540:16] wire _max_blocks_T = req_max_j < 16'h5; // @[LoopMatmul.scala:540:16, :542:55] wire [15:0] _max_blocks_T_1 = _max_blocks_T ? req_max_j : 16'h4; // @[LoopMatmul.scala:540:16, :542:{44,55}] wire [15:0] max_blocks = req_full_c ? 16'h1 : _max_blocks_T_1; // @[LoopMatmul.scala:540:16, :542:{23,44}] reg [15:0] j; // @[LoopMatmul.scala:545:14] assign io_j = j; // @[LoopMatmul.scala:514:7, :545:14] reg [15:0] i; // @[LoopMatmul.scala:546:14] assign io_i = i; // @[LoopMatmul.scala:514:7, :546:14] wire [55:0] _GEN_3 = {40'h0, i} * {16'h0, req_dram_stride}; // @[LoopMatmul.scala:540:16, :546:14, :550:40] wire [55:0] _dram_offset_T; // @[LoopMatmul.scala:550:40] assign _dram_offset_T = _GEN_3; // @[LoopMatmul.scala:550:40] wire [55:0] _dram_offset_T_5; // @[LoopMatmul.scala:551:8] assign _dram_offset_T_5 = _GEN_3; // @[LoopMatmul.scala:550:40, :551:8] wire [55:0] _ln_dram_offset_T; // @[LoopMatmul.scala:593:28] assign _ln_dram_offset_T = _GEN_3; // @[LoopMatmul.scala:550:40, :593:28] wire [56:0] _GEN_4 = {41'h0, j}; // @[LoopMatmul.scala:545:14, :550:58] wire [56:0] _dram_offset_T_1 = {1'h0, _dram_offset_T} + _GEN_4; // @[LoopMatmul.scala:550:{40,58}] wire [55:0] _dram_offset_T_2 = _dram_offset_T_1[55:0]; // @[LoopMatmul.scala:550:58] wire [58:0] _dram_offset_T_3 = {1'h0, _dram_offset_T_2, 2'h0}; // @[LoopMatmul.scala:550:{58,63}] wire [61:0] _dram_offset_T_4 = {1'h0, _dram_offset_T_3, 2'h0}; // @[LoopMatmul.scala:550:{63,78}] wire [56:0] _dram_offset_T_6 = {1'h0, _dram_offset_T_5} + _GEN_4; // @[LoopMatmul.scala:550:58, :551:{8,26}] wire [55:0] _dram_offset_T_7 = _dram_offset_T_6[55:0]; // @[LoopMatmul.scala:551:26] wire [58:0] _dram_offset_T_8 = {1'h0, _dram_offset_T_7, 2'h0}; // @[LoopMatmul.scala:551:{26,31}] wire [61:0] _dram_offset_T_9 = {1'h0, _dram_offset_T_8, 2'h0}; // @[LoopMatmul.scala:551:{31,46}] wire [61:0] dram_offset = req_full_c ? _dram_offset_T_4 : _dram_offset_T_9; // @[LoopMatmul.scala:540:16, :550:{24,78}, :551:46] wire [61:0] _dram_addr_T = {30'h0, dram_offset[31:0]}; // @[LoopMatmul.scala:550:24, :1139:17] wire [62:0] _dram_addr_T_1 = {23'h0, req_dram_addr} + {1'h0, _dram_addr_T}; // @[LoopMatmul.scala:540:16, :552:33, :1139:17] wire [61:0] dram_addr = _dram_addr_T_1[61:0]; // @[LoopMatmul.scala:552:33] wire [31:0] _GEN_5 = {16'h0, i} * {16'h0, req_max_j}; // @[LoopMatmul.scala:540:16, :546:14, :553:37] wire [31:0] _sp_addr_T; // @[LoopMatmul.scala:553:37] assign _sp_addr_T = _GEN_5; // @[LoopMatmul.scala:553:37] wire [31:0] _ln_sp_addr_T; // @[LoopMatmul.scala:587:41] assign _ln_sp_addr_T = _GEN_5; // @[LoopMatmul.scala:553:37, :587:41] wire [32:0] _GEN_6 = {17'h0, j}; // @[LoopMatmul.scala:545:14, :553:49] wire [32:0] _sp_addr_T_1 = {1'h0, _sp_addr_T} + _GEN_6; // @[LoopMatmul.scala:553:{37,49}] wire [31:0] _sp_addr_T_2 = _sp_addr_T_1[31:0]; // @[LoopMatmul.scala:553:49] wire [34:0] _sp_addr_T_3 = {1'h0, _sp_addr_T_2, 2'h0}; // @[LoopMatmul.scala:553:{49,54}] wire [35:0] _sp_addr_T_4 = {24'h0, req_addr_start} + {1'h0, _sp_addr_T_3}; // @[LoopMatmul.scala:540:16, :553:{32,54}] wire [34:0] sp_addr = _sp_addr_T_4[34:0]; // @[LoopMatmul.scala:553:32] wire [16:0] _GEN_7 = {1'h0, j}; // @[LoopMatmul.scala:545:14, :554:22] wire [16:0] _GEN_8 = _GEN_7 + {1'h0, max_blocks}; // @[LoopMatmul.scala:542:23, :554:22] wire [16:0] _blocks_T; // @[LoopMatmul.scala:554:22] assign _blocks_T = _GEN_8; // @[LoopMatmul.scala:554:22] wire [16:0] _ln_norm_cmd_T; // @[LoopMatmul.scala:588:27] assign _ln_norm_cmd_T = _GEN_8; // @[LoopMatmul.scala:554:22, :588:27] wire [16:0] _next_j_T_1; // @[Util.scala:41:15] assign _next_j_T_1 = _GEN_8; // @[Util.scala:41:15] wire [16:0] _next_j_T_4; // @[Util.scala:43:11] assign _next_j_T_4 = _GEN_8; // @[Util.scala:43:11] wire [16:0] _next_j_T_7; // @[Util.scala:41:15] assign _next_j_T_7 = _GEN_8; // @[Util.scala:41:15] wire [16:0] _next_j_T_10; // @[Util.scala:43:11] assign _next_j_T_10 = _GEN_8; // @[Util.scala:43:11] wire [15:0] _blocks_T_1 = _blocks_T[15:0]; // @[LoopMatmul.scala:554:22] wire _blocks_T_2 = _blocks_T_1 <= req_max_j; // @[LoopMatmul.scala:540:16, :554:{22,35}] wire [16:0] _GEN_9 = {1'h0, req_max_j}; // @[LoopMatmul.scala:540:16, :554:70] wire [16:0] _blocks_T_3 = _GEN_9 - _GEN_7; // @[LoopMatmul.scala:554:{22,70}] wire [15:0] _blocks_T_4 = _blocks_T_3[15:0]; // @[LoopMatmul.scala:554:70] wire [15:0] blocks = _blocks_T_2 ? max_blocks : _blocks_T_4; // @[LoopMatmul.scala:542:23, :554:{19,35,70}] wire [18:0] _cols_T = {1'h0, blocks, 2'h0}; // @[LoopMatmul.scala:554:19, :555:22] wire [16:0] _GEN_10 = _GEN_7 + {1'h0, blocks}; // @[LoopMatmul.scala:554:{19,22}, :555:46] wire [16:0] _cols_T_1; // @[LoopMatmul.scala:555:46] assign _cols_T_1 = _GEN_10; // @[LoopMatmul.scala:555:46] wire [16:0] _ex_ahead_T_6; // @[LoopMatmul.scala:630:23] assign _ex_ahead_T_6 = _GEN_10; // @[LoopMatmul.scala:555:46, :630:23] wire [16:0] _ex_ahead_T_9; // @[LoopMatmul.scala:631:27] assign _ex_ahead_T_9 = _GEN_10; // @[LoopMatmul.scala:555:46, :631:27] wire [16:0] _ex_ahead_T_22; // @[LoopMatmul.scala:633:83] assign _ex_ahead_T_22 = _GEN_10; // @[LoopMatmul.scala:555:46, :633:83] wire [15:0] _cols_T_2 = _cols_T_1[15:0]; // @[LoopMatmul.scala:555:46] wire _cols_T_3 = _cols_T_2 >= req_max_j; // @[LoopMatmul.scala:540:16, :555:{46,55}] wire [1:0] _cols_T_4 = _cols_T_3 ? req_pad_j : 2'h0; // @[LoopMatmul.scala:540:16, :555:{43,55}] wire [19:0] _cols_T_5 = {1'h0, _cols_T} - {18'h0, _cols_T_4}; // @[LoopMatmul.scala:555:{22,38,43}] wire [18:0] cols = _cols_T_5[18:0]; // @[LoopMatmul.scala:555:38] wire [16:0] _GEN_11 = {1'h0, req_max_i} - 17'h1; // @[LoopMatmul.scala:540:16, :556:48] wire [16:0] _rows_T; // @[LoopMatmul.scala:556:48] assign _rows_T = _GEN_11; // @[LoopMatmul.scala:556:48] wire [16:0] _next_i_max_T; // @[Util.scala:39:28] assign _next_i_max_T = _GEN_11; // @[Util.scala:39:28] wire [16:0] _next_i_max_T_1; // @[Util.scala:39:28] assign _next_i_max_T_1 = _GEN_11; // @[Util.scala:39:28] wire [15:0] _rows_T_1 = _rows_T[15:0]; // @[LoopMatmul.scala:556:48] wire _rows_T_2 = i == _rows_T_1; // @[LoopMatmul.scala:546:14, :556:{35,48}] wire [1:0] _rows_T_3 = _rows_T_2 ? req_pad_i : 2'h0; // @[LoopMatmul.scala:540:16, :556:{32,35}] wire [3:0] _rows_T_4 = 4'h4 - {2'h0, _rows_T_3}; // @[LoopMatmul.scala:556:{27,32}] wire [2:0] rows = _rows_T_4[2:0]; // @[LoopMatmul.scala:556:27] wire [2:0] mvout_cmd_rs2_num_rows = rows; // @[LoopMatmul.scala:556:27, :563:27] wire [63:0] _mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:568:34] wire [63:0] mvout_cmd_rs1; // @[LoopMatmul.scala:558:23] wire [63:0] mvout_cmd_rs2; // @[LoopMatmul.scala:558:23] assign mvout_cmd_rs1 = {2'h0, dram_addr}; // @[LoopMatmul.scala:552:33, :558:23, :561:17] wire [4:0] mvout_cmd_rs2_lo_hi_1 = mvout_cmd_rs2_num_cols; // @[LoopMatmul.scala:563:27, :568:34] wire [2:0] mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LocalAddr.scala:129:26] wire [2:0] _mvout_cmd_rs2_T = mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:563:27, :568:34] wire mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:129:26] wire [13:0] mvout_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:129:26] wire mvout_cmd_rs2_local_addr_read_full_acc_row; // @[LoopMatmul.scala:563:27] wire mvout_cmd_rs2_local_addr_garbage_bit; // @[LoopMatmul.scala:563:27] wire [13:0] mvout_cmd_rs2_local_addr_data; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_num_cols = cols[4:0]; // @[LoopMatmul.scala:555:38, :563:27, :566:26] wire _mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire [4:0] ln_mvout_cmd_rs2_num_cols = cols[4:0]; // @[LoopMatmul.scala:555:38, :566:26, :613:30] wire _mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_is_acc_addr = _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_accumulate = _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] mvout_cmd_rs2_local_addr_result_result_norm_cmd = _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_garbage_bit = _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvout_cmd_rs2_local_addr_result_result_data = _mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_1 = sp_addr[31:0]; // @[LoopMatmul.scala:553:32] assign _mvout_cmd_rs2_local_addr_result_result_T = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_data = _mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_1 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_2 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_T_3 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_2 = _mvout_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_3 = _mvout_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_4 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_5 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_6 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] assign mvout_cmd_rs2_local_addr_result_norm_cmd = mvout_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_result_garbage_bit = mvout_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_result_data = mvout_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_read_full_acc_row = mvout_cmd_rs2_local_addr_result_read_full_acc_row; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_local_addr_norm_cmd = mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_local_addr_garbage_bit = mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_local_addr_data = mvout_cmd_rs2_local_addr_result_data; // @[LoopMatmul.scala:563:27] wire [11:0] mvout_cmd_rs2_lo_hi = {11'h0, mvout_cmd_rs2_local_addr_garbage_bit}; // @[LoopMatmul.scala:563:27, :568:34] wire [25:0] mvout_cmd_rs2_lo = {mvout_cmd_rs2_lo_hi, mvout_cmd_rs2_local_addr_data}; // @[LoopMatmul.scala:563:27, :568:34] wire [3:0] mvout_cmd_rs2_hi_lo = {mvout_cmd_rs2_local_addr_read_full_acc_row, _mvout_cmd_rs2_T}; // @[LoopMatmul.scala:563:27, :568:34] wire [5:0] mvout_cmd_rs2_hi = {2'h2, mvout_cmd_rs2_hi_lo}; // @[LoopMatmul.scala:568:34] wire [31:0] _mvout_cmd_rs2_T_1 = {mvout_cmd_rs2_hi, mvout_cmd_rs2_lo}; // @[LoopMatmul.scala:568:34] wire [36:0] mvout_cmd_rs2_lo_1 = {mvout_cmd_rs2_lo_hi_1, _mvout_cmd_rs2_T_1}; // @[LoopMatmul.scala:568:34] wire [15:0] mvout_cmd_rs2_hi_hi_1 = {13'h0, mvout_cmd_rs2_num_rows}; // @[LoopMatmul.scala:563:27, :568:34] wire [26:0] mvout_cmd_rs2_hi_1 = {mvout_cmd_rs2_hi_hi_1, 11'h0}; // @[LoopMatmul.scala:568:34] assign _mvout_cmd_rs2_T_2 = {mvout_cmd_rs2_hi_1, mvout_cmd_rs2_lo_1}; // @[LoopMatmul.scala:568:34] assign mvout_cmd_rs2 = _mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:558:23, :568:34] reg [15:0] ln_row; // @[LoopMatmul.scala:571:19] reg [15:0] ln_cmd; // @[LoopMatmul.scala:572:19] reg [15:0] ln_stat_id; // @[LoopMatmul.scala:573:23] wire [16:0] _GEN_12 = {1'h0, ln_row}; // @[LoopMatmul.scala:571:19, :583:30] wire [16:0] _GEN_13 = {14'h0, rows} - _GEN_12; // @[LoopMatmul.scala:556:27, :583:30] wire [16:0] _ln_stat_ids_T; // @[LoopMatmul.scala:583:30] assign _ln_stat_ids_T = _GEN_13; // @[LoopMatmul.scala:583:30] wire [16:0] _ln_stat_ids_T_3; // @[LoopMatmul.scala:583:81] assign _ln_stat_ids_T_3 = _GEN_13; // @[LoopMatmul.scala:583:{30,81}] wire [16:0] _ln_stat_ids_T_1 = _ln_stat_ids_T; // @[LoopMatmul.scala:583:30] wire _ln_stat_ids_T_2 = _ln_stat_ids_T_1 > 17'h2; // @[LoopMatmul.scala:583:{30,40}] wire [16:0] _ln_stat_ids_T_4 = _ln_stat_ids_T_3; // @[LoopMatmul.scala:583:81] wire [16:0] ln_stat_ids = _ln_stat_ids_T_2 ? 17'h2 : _ln_stat_ids_T_4; // @[LoopMatmul.scala:583:{24,40,81}] wire [16:0] _GEN_14 = {1'h0, ln_stat_id}; // @[LoopMatmul.scala:573:23, :585:21] wire [16:0] ln_r = _GEN_12 + _GEN_14; // @[LoopMatmul.scala:583:30, :585:21] wire [32:0] _ln_sp_addr_T_1 = {1'h0, _ln_sp_addr_T} + _GEN_6; // @[LoopMatmul.scala:553:49, :587:{41,53}] wire [35:0] _ln_sp_addr_T_2 = {1'h0, _ln_sp_addr_T_1, 2'h0}; // @[LoopMatmul.scala:587:{53,59}] wire [36:0] _ln_sp_addr_T_3 = {25'h0, req_addr_start} + {1'h0, _ln_sp_addr_T_2}; // @[LoopMatmul.scala:540:16, :587:{35,59}] wire [37:0] ln_sp_addr = {1'h0, _ln_sp_addr_T_3} + {21'h0, ln_r}; // @[LoopMatmul.scala:585:21, :587:{35,74}] wire _ln_norm_cmd_T_1 = _ln_norm_cmd_T >= _GEN_9; // @[LoopMatmul.scala:554:70, :588:{27,41}] wire _GEN_15 = req_act == 3'h2; // @[LoopMatmul.scala:540:16, :589:17] wire _ln_norm_cmd_T_2; // @[LoopMatmul.scala:589:17] assign _ln_norm_cmd_T_2 = _GEN_15; // @[LoopMatmul.scala:589:17] wire _ln_norm_cmd_T_6; // @[LoopMatmul.scala:590:17] assign _ln_norm_cmd_T_6 = _GEN_15; // @[LoopMatmul.scala:589:17, :590:17] wire [1:0] _ln_norm_cmd_T_3 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [1:0] _ln_norm_cmd_T_4 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [1:0] _ln_norm_cmd_T_7 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [1:0] _ln_norm_cmd_T_8 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [2:0] _ln_norm_cmd_T_5 = _ln_norm_cmd_T_2 ? _GEN_2[_ln_norm_cmd_T_3] : _GEN_1[_ln_norm_cmd_T_4]; // @[LoopMatmul.scala:589:{8,17}] wire [2:0] _ln_norm_cmd_T_9 = _ln_norm_cmd_T_6 ? _GEN_0[_ln_norm_cmd_T_7] : _GEN[_ln_norm_cmd_T_8]; // @[LoopMatmul.scala:590:{8,17}] wire [2:0] ln_norm_cmd = _ln_norm_cmd_T_1 ? _ln_norm_cmd_T_5 : _ln_norm_cmd_T_9; // @[LoopMatmul.scala:588:{24,41}, :589:8, :590:8] wire [2:0] ln_mvout_cmd_rs2_local_addr_norm_cmd = ln_norm_cmd; // @[LoopMatmul.scala:588:24, :613:30] wire [56:0] _ln_dram_offset_T_1 = {1'h0, _ln_dram_offset_T} + _GEN_4; // @[LoopMatmul.scala:550:58, :593:{28,46}] wire [59:0] _ln_dram_offset_T_2 = {1'h0, _ln_dram_offset_T_1, 2'h0}; // @[LoopMatmul.scala:593:{46,52}] wire [56:0] _ln_dram_offset_T_3 = {40'h0, ln_r} * {17'h0, req_dram_stride}; // @[LoopMatmul.scala:540:16, :550:40, :553:49, :585:21, :593:75] wire [60:0] _ln_dram_offset_T_4 = {1'h0, _ln_dram_offset_T_2} + {4'h0, _ln_dram_offset_T_3}; // @[LoopMatmul.scala:593:{52,67,75}] wire [63:0] ln_dram_offset = {1'h0, _ln_dram_offset_T_4, 2'h0}; // @[LoopMatmul.scala:593:{67,94}] wire [63:0] _ln_dram_addr_T = {32'h0, ln_dram_offset[31:0]}; // @[LoopMatmul.scala:593:94, :1139:17] wire [64:0] _ln_dram_addr_T_1 = {25'h0, req_dram_addr} + {1'h0, _ln_dram_addr_T}; // @[LoopMatmul.scala:540:16, :587:35, :594:36, :1139:17] wire [63:0] ln_dram_addr = _ln_dram_addr_T_1[63:0]; // @[LoopMatmul.scala:594:36] wire [63:0] ln_mvout_cmd_rs1 = ln_dram_addr; // @[LoopMatmul.scala:594:36, :608:26] wire [7:0] ln_config_norm_rs1_norm_stats_id; // @[LoopMatmul.scala:596:32] assign ln_config_norm_rs1_norm_stats_id = ln_stat_id[7:0]; // @[LoopMatmul.scala:573:23, :596:32, :600:36] wire [63:0] _ln_config_norm_rs1_T; // @[LoopMatmul.scala:605:44] wire [63:0] ln_config_norm_rs1; // @[LoopMatmul.scala:602:28] wire [8:0] ln_config_norm_rs1_lo_hi = {1'h0, ln_config_norm_rs1_norm_stats_id}; // @[LoopMatmul.scala:596:32, :605:44] wire [16:0] ln_config_norm_rs1_lo = {ln_config_norm_rs1_lo_hi, 8'h3}; // @[LoopMatmul.scala:605:44] assign _ln_config_norm_rs1_T = {47'h1, ln_config_norm_rs1_lo}; // @[LoopMatmul.scala:605:44] assign ln_config_norm_rs1 = _ln_config_norm_rs1_T; // @[LoopMatmul.scala:602:28, :605:44] wire [63:0] _ln_mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:619:40] wire [63:0] ln_mvout_cmd_rs2; // @[LoopMatmul.scala:608:26] wire [4:0] ln_mvout_cmd_rs2_lo_hi_1 = ln_mvout_cmd_rs2_num_cols; // @[LoopMatmul.scala:613:30, :619:40] wire [2:0] _ln_mvout_cmd_rs2_T = ln_mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:613:30, :619:40] wire ln_mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:129:26] wire [13:0] ln_mvout_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:129:26] wire ln_mvout_cmd_rs2_local_addr_read_full_acc_row; // @[LoopMatmul.scala:613:30] wire ln_mvout_cmd_rs2_local_addr_garbage_bit; // @[LoopMatmul.scala:613:30] wire [13:0] ln_mvout_cmd_rs2_local_addr_data; // @[LoopMatmul.scala:613:30] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_is_acc_addr = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_accumulate = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_read_full_acc_row = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _ln_mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] ln_mvout_cmd_rs2_local_addr_result_result_norm_cmd = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _ln_mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_garbage_bit = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] ln_mvout_cmd_rs2_local_addr_result_result_data = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1 = ln_sp_addr[31:0]; // @[LoopMatmul.scala:587:74] assign _ln_mvout_cmd_rs2_local_addr_result_result_T = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_data = _ln_mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_1 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _ln_mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_2 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage = _ln_mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_T_3 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2 = _ln_mvout_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_4 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _ln_mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_5 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate = _ln_mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_6 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _ln_mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire [2:0] ln_mvout_cmd_rs2_local_addr_result_norm_cmd = ln_mvout_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] assign ln_mvout_cmd_rs2_local_addr_result_garbage_bit = ln_mvout_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] assign ln_mvout_cmd_rs2_local_addr_result_data = ln_mvout_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :129:26] assign ln_mvout_cmd_rs2_local_addr_read_full_acc_row = ln_mvout_cmd_rs2_local_addr_result_read_full_acc_row; // @[LoopMatmul.scala:613:30] assign ln_mvout_cmd_rs2_local_addr_garbage_bit = ln_mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LoopMatmul.scala:613:30] assign ln_mvout_cmd_rs2_local_addr_data = ln_mvout_cmd_rs2_local_addr_result_data; // @[LoopMatmul.scala:613:30] wire [11:0] ln_mvout_cmd_rs2_lo_hi = {11'h0, ln_mvout_cmd_rs2_local_addr_garbage_bit}; // @[LoopMatmul.scala:613:30, :619:40] wire [25:0] ln_mvout_cmd_rs2_lo = {ln_mvout_cmd_rs2_lo_hi, ln_mvout_cmd_rs2_local_addr_data}; // @[LoopMatmul.scala:613:30, :619:40] wire [3:0] ln_mvout_cmd_rs2_hi_lo = {ln_mvout_cmd_rs2_local_addr_read_full_acc_row, _ln_mvout_cmd_rs2_T}; // @[LoopMatmul.scala:613:30, :619:40] wire [5:0] ln_mvout_cmd_rs2_hi = {2'h2, ln_mvout_cmd_rs2_hi_lo}; // @[LoopMatmul.scala:619:40] wire [31:0] _ln_mvout_cmd_rs2_T_1 = {ln_mvout_cmd_rs2_hi, ln_mvout_cmd_rs2_lo}; // @[LoopMatmul.scala:619:40] wire [36:0] ln_mvout_cmd_rs2_lo_1 = {ln_mvout_cmd_rs2_lo_hi_1, _ln_mvout_cmd_rs2_T_1}; // @[LoopMatmul.scala:619:40] assign _ln_mvout_cmd_rs2_T_2 = {27'h800, ln_mvout_cmd_rs2_lo_1}; // @[LoopMatmul.scala:619:40] assign ln_mvout_cmd_rs2 = _ln_mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:608:26, :619:40] assign _io_req_ready_T = ~(\|state); // @[LoopMatmul.scala:538:22, :621:25] assign io_req_ready_0 = _io_req_ready_T; // @[LoopMatmul.scala:514:7, :621:25] assign _io_idle_T = ~(\|state); // @[LoopMatmul.scala:538:22, :621:25, :624:20] assign io_idle_0 = _io_idle_T; // @[LoopMatmul.scala:514:7, :624:20] wire _ex_ahead_T = req_act != 3'h2; // @[LoopMatmul.scala:540:16, :589:17, :628:15] wire _ex_ahead_T_1 = req_act != 3'h4; // @[LoopMatmul.scala:540:16, :628:53] wire _ex_ahead_T_2 = _ex_ahead_T & _ex_ahead_T_1; // @[LoopMatmul.scala:628:{15,41,53}] wire [16:0] _ex_ahead_T_3 = {1'h0, req_max_k} - 17'h1; // @[LoopMatmul.scala:540:16, :629:30] wire [15:0] _ex_ahead_T_4 = _ex_ahead_T_3[15:0]; // @[LoopMatmul.scala:629:30] wire _ex_ahead_T_5 = io_ex_k_0 == _ex_ahead_T_4; // @[LoopMatmul.scala:514:7, :629:{16,30}] wire [15:0] _ex_ahead_T_7 = _ex_ahead_T_6[15:0]; // @[LoopMatmul.scala:630:23] wire _ex_ahead_T_8 = io_ex_j_0 >= _ex_ahead_T_7; // @[LoopMatmul.scala:514:7, :630:{18,23}] wire [15:0] _ex_ahead_T_10 = _ex_ahead_T_9[15:0]; // @[LoopMatmul.scala:631:27] wire [16:0] _ex_ahead_T_11 = {1'h0, _ex_ahead_T_10} - 17'h1; // @[LoopMatmul.scala:631:{27,36}] wire [15:0] _ex_ahead_T_12 = _ex_ahead_T_11[15:0]; // @[LoopMatmul.scala:631:36] wire _ex_ahead_T_13 = io_ex_j_0 == _ex_ahead_T_12; // @[LoopMatmul.scala:514:7, :631:{21,36}] wire _GEN_16 = io_ex_i_0 > i; // @[LoopMatmul.scala:514:7, :546:14, :631:54] wire _ex_ahead_T_14; // @[LoopMatmul.scala:631:54] assign _ex_ahead_T_14 = _GEN_16; // @[LoopMatmul.scala:631:54] wire _ex_ahead_T_20; // @[LoopMatmul.scala:633:45] assign _ex_ahead_T_20 = _GEN_16; // @[LoopMatmul.scala:631:54, :633:45] wire _ex_ahead_T_15 = _ex_ahead_T_13 & _ex_ahead_T_14; // @[LoopMatmul.scala:631:{21,43,54}] wire _ex_ahead_T_16 = _ex_ahead_T_8 \| _ex_ahead_T_15; // @[LoopMatmul.scala:630:{18,32}, :631:43] wire _ex_ahead_T_17 = _ex_ahead_T_5 & _ex_ahead_T_16; // @[LoopMatmul.scala:629:{16,36}, :630:32] wire _ex_ahead_T_18 = _ex_ahead_T_2 & _ex_ahead_T_17; // @[LoopMatmul.scala:628:{41,77}, :629:36] wire _ex_ahead_T_19 = io_ex_completed_0 \| _ex_ahead_T_18; // @[LoopMatmul.scala:514:7, :627:43, :628:77] wire ex_ahead; // @[LoopMatmul.scala:627:26] wire _ex_ahead_T_21 = io_ex_i_0 == i; // @[LoopMatmul.scala:514:7, :546:14, :633:61] wire [15:0] _ex_ahead_T_23 = _ex_ahead_T_22[15:0]; // @[LoopMatmul.scala:633:83] wire _ex_ahead_T_24 = io_ex_j_0 >= _ex_ahead_T_23; // @[LoopMatmul.scala:514:7, :633:{78,83}] wire _ex_ahead_T_25 = _ex_ahead_T_21 & _ex_ahead_T_24; // @[LoopMatmul.scala:633:{61,67,78}] wire _ex_ahead_T_26 = _ex_ahead_T_20 \| _ex_ahead_T_25; // @[LoopMatmul.scala:633:{45,49,67}] wire _ex_ahead_T_27 = io_ex_completed_0 \| _ex_ahead_T_26; // @[LoopMatmul.scala:514:7, :633:{33,49}] assign ex_ahead = req_is_resadd ? _ex_ahead_T_27 : _ex_ahead_T_19; // @[LoopMatmul.scala:540:16, :627:{26,43}, :632:22, :633:{14,33}] wire _io_cmd_valid_T = \|state; // @[LoopMatmul.scala:538:22, :621:25, :636:25] wire _io_cmd_valid_T_1 = ~io_rob_overloaded_0; // @[LoopMatmul.scala:514:7, :636:37] wire _io_cmd_valid_T_2 = _io_cmd_valid_T & _io_cmd_valid_T_1; // @[LoopMatmul.scala:636:{25,34,37}] wire _io_cmd_valid_T_3 = _io_cmd_valid_T_2 & ex_ahead; // @[LoopMatmul.scala:627:26, :636:{34,56}] wire _io_cmd_valid_T_4 = \|req_dram_addr; // @[LoopMatmul.scala:540:16, :636:85] assign _io_cmd_valid_T_5 = _io_cmd_valid_T_3 & _io_cmd_valid_T_4; // @[LoopMatmul.scala:636:{56,68,85}] assign io_cmd_valid_0 = _io_cmd_valid_T_5; // @[LoopMatmul.scala:514:7, :636:68] wire _io_cmd_bits_T = state == 2'h2; // @[LoopMatmul.scala:538:22, :638:12] wire _io_cmd_bits_T_1 = &state; // @[LoopMatmul.scala:538:22, :639:12] wire [63:0] _io_cmd_bits_T_2_rs1 = _io_cmd_bits_T_1 ? ln_mvout_cmd_rs1 : mvout_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_cmd_bits_T_2_rs2 = _io_cmd_bits_T_1 ? ln_mvout_cmd_rs2 : mvout_cmd_rs2; // @[Mux.scala:126:16] assign _io_cmd_bits_T_3_inst_funct = _io_cmd_bits_T ? 7'h0 : 7'h3; // @[Mux.scala:126:16] assign _io_cmd_bits_T_3_rs1 = _io_cmd_bits_T ? ln_config_norm_rs1 : _io_cmd_bits_T_2_rs1; // @[Mux.scala:126:16] assign _io_cmd_bits_T_3_rs2 = _io_cmd_bits_T ? 64'h0 : _io_cmd_bits_T_2_rs2; // @[Mux.scala:126:16] assign io_cmd_bits_inst_funct_0 = _io_cmd_bits_T_3_inst_funct; // @[Mux.scala:126:16] assign io_cmd_bits_rs1_0 = _io_cmd_bits_T_3_rs1; // @[Mux.scala:126:16] assign io_cmd_bits_rs2_0 = _io_cmd_bits_T_3_rs2; // @[Mux.scala:126:16] wire [15:0] next_i_max = _next_i_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_17 = {1'h0, i} + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_i_T; // @[Util.scala:41:15] assign _next_i_T = _GEN_17; // @[Util.scala:41:15] wire [16:0] _next_i_T_3; // @[Util.scala:43:11] assign _next_i_T_3 = _GEN_17; // @[Util.scala:41:15, :43:11] wire [16:0] _next_i_T_13; // @[Util.scala:41:15] assign _next_i_T_13 = _GEN_17; // @[Util.scala:41:15] wire [16:0] _next_i_T_16; // @[Util.scala:43:11] assign _next_i_T_16 = _GEN_17; // @[Util.scala:41:15, :43:11] wire [15:0] _next_i_T_1 = _next_i_T[15:0]; // @[Util.scala:41:15] wire _next_i_T_4 = _next_i_T_3 > {1'h0, next_i_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_i_T_5 = _next_i_T_4 ? 16'h0 : _next_i_T_1; // @[Mux.scala:126:16] wire [15:0] next_i = _next_i_T_5; // @[Mux.scala:126:16] wire _next_j_T = next_i == 16'h0; // @[Mux.scala:126:16] wire [16:0] _GEN_18 = _GEN_9 - 17'h1; // @[Util.scala:39:28] wire [16:0] _next_j_max_T; // @[Util.scala:39:28] assign _next_j_max_T = _GEN_18; // @[Util.scala:39:28] wire [16:0] _next_j_max_T_1; // @[Util.scala:39:28] assign _next_j_max_T_1 = _GEN_18; // @[Util.scala:39:28] wire [15:0] next_j_max = _next_j_max_T[15:0]; // @[Util.scala:39:28] wire [15:0] _next_j_T_2 = _next_j_T_1[15:0]; // @[Util.scala:41:15] wire _next_j_T_3 = ~_next_j_T; // @[Util.scala:42:8] wire _next_j_T_5 = _next_j_T_4 > {1'h0, next_j_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_j_T_6 = _next_j_T_5 ? 16'h0 : _next_j_T_2; // @[Mux.scala:126:16] wire [15:0] next_j = _next_j_T_3 ? j : _next_j_T_6; // @[Mux.scala:126:16] wire [15:0] next_j_max_1 = _next_j_max_T_1[15:0]; // @[Util.scala:39:28] wire [15:0] _next_j_T_8 = _next_j_T_7[15:0]; // @[Util.scala:41:15] wire _next_j_T_11 = _next_j_T_10 > {1'h0, next_j_max_1}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_j_T_12 = _next_j_T_11 ? 16'h0 : _next_j_T_8; // @[Mux.scala:126:16] wire [15:0] next_j_1 = _next_j_T_12; // @[Mux.scala:126:16] wire _T_22 = next_j_1 == 16'h0; // @[Mux.scala:126:16] wire _next_stat_id_T; // @[LoopMatmul.scala:661:70] assign _next_stat_id_T = _T_22; // @[LoopMatmul.scala:661:70] wire _next_cmd_T; // @[LoopMatmul.scala:662:70] assign _next_cmd_T = _T_22; // @[LoopMatmul.scala:661:70, :662:70] wire _next_row_T; // @[LoopMatmul.scala:663:67] assign _next_row_T = _T_22; // @[LoopMatmul.scala:661:70, :663:67] wire _next_i_T_6; // @[LoopMatmul.scala:665:14] assign _next_i_T_6 = _T_22; // @[LoopMatmul.scala:661:70, :665:14] wire [17:0] _next_stat_id_max_T = {1'h0, ln_stat_ids} - 18'h1; // @[Util.scala:39:28] wire [16:0] next_stat_id_max = _next_stat_id_max_T[16:0]; // @[Util.scala:39:28] wire [16:0] _GEN_19 = _GEN_14 + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_stat_id_T_1; // @[Util.scala:41:15] assign _next_stat_id_T_1 = _GEN_19; // @[Util.scala:41:15] wire [16:0] _next_stat_id_T_4; // @[Util.scala:43:11] assign _next_stat_id_T_4 = _GEN_19; // @[Util.scala:41:15, :43:11] wire [15:0] _next_stat_id_T_2 = _next_stat_id_T_1[15:0]; // @[Util.scala:41:15] wire _next_stat_id_T_3 = ~_next_stat_id_T; // @[Util.scala:42:8] wire _next_stat_id_T_5 = _next_stat_id_T_4 > next_stat_id_max; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_stat_id_T_6 = _next_stat_id_T_5 ? 16'h0 : _next_stat_id_T_2; // @[Mux.scala:126:16] wire [15:0] next_stat_id = _next_stat_id_T_3 ? ln_stat_id : _next_stat_id_T_6; // @[Mux.scala:126:16] wire _T_18 = next_stat_id == 16'h0; // @[Mux.scala:126:16] wire _next_cmd_T_1; // @[LoopMatmul.scala:662:94] assign _next_cmd_T_1 = _T_18; // @[LoopMatmul.scala:662:94] wire _next_row_T_1; // @[LoopMatmul.scala:663:91] assign _next_row_T_1 = _T_18; // @[LoopMatmul.scala:662:94, :663:91] wire _next_i_T_7; // @[LoopMatmul.scala:665:38] assign _next_i_T_7 = _T_18; // @[LoopMatmul.scala:662:94, :665:38] wire _next_cmd_T_2 = _next_cmd_T & _next_cmd_T_1; // @[LoopMatmul.scala:662:{70,78,94}] wire [16:0] _GEN_20 = {1'h0, ln_cmd} + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_cmd_T_3; // @[Util.scala:41:15] assign _next_cmd_T_3 = _GEN_20; // @[Util.scala:41:15] wire [16:0] _next_cmd_T_6; // @[Util.scala:43:11] assign _next_cmd_T_6 = _GEN_20; // @[Util.scala:41:15, :43:11] wire [15:0] _next_cmd_T_4 = _next_cmd_T_3[15:0]; // @[Util.scala:41:15] wire _next_cmd_T_5 = ~_next_cmd_T_2; // @[Util.scala:42:8] wire _next_cmd_T_7 = _next_cmd_T_6 > 17'h2; // @[Util.scala:43:{11,17}] wire [15:0] _next_cmd_T_8 = _next_cmd_T_7 ? 16'h0 : _next_cmd_T_4; // @[Mux.scala:126:16] wire [15:0] next_cmd = _next_cmd_T_5 ? ln_cmd : _next_cmd_T_8; // @[Mux.scala:126:16] wire _next_row_T_2 = _next_row_T & _next_row_T_1; // @[LoopMatmul.scala:663:{67,75,91}] wire _T_16 = next_cmd == 16'h0; // @[Mux.scala:126:16] wire _next_row_T_3; // @[LoopMatmul.scala:663:111] assign _next_row_T_3 = _T_16; // @[LoopMatmul.scala:663:111] wire _next_i_T_9; // @[LoopMatmul.scala:665:58] assign _next_i_T_9 = _T_16; // @[LoopMatmul.scala:663:111, :665:58] wire _next_row_T_4 = _next_row_T_2 & _next_row_T_3; // @[LoopMatmul.scala:663:{75,99,111}] wire [3:0] _next_row_max_T = {1'h0, rows} - 4'h1; // @[Util.scala:39:28] wire [2:0] next_row_max = _next_row_max_T[2:0]; // @[Util.scala:39:28] wire [16:0] _GEN_21 = _GEN_12 + 17'h2; // @[Util.scala:41:15] wire [16:0] _next_row_T_5; // @[Util.scala:41:15] assign _next_row_T_5 = _GEN_21; // @[Util.scala:41:15] wire [16:0] _next_row_T_8; // @[Util.scala:43:11] assign _next_row_T_8 = _GEN_21; // @[Util.scala:41:15, :43:11] wire [15:0] _next_row_T_6 = _next_row_T_5[15:0]; // @[Util.scala:41:15] wire _next_row_T_7 = ~_next_row_T_4; // @[Util.scala:42:8] wire _next_row_T_9 = _next_row_T_8 > {14'h0, next_row_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_row_T_10 = _next_row_T_9 ? 16'h0 : _next_row_T_6; // @[Mux.scala:126:16] wire [15:0] next_row = _next_row_T_7 ? ln_row : _next_row_T_10; // @[Mux.scala:126:16] wire _next_i_T_8 = _next_i_T_6 & _next_i_T_7; // @[LoopMatmul.scala:665:{14,22,38}] wire _next_i_T_10 = _next_i_T_8 & _next_i_T_9; // @[LoopMatmul.scala:665:{22,46,58}] wire _next_i_T_11 = next_row == 16'h0; // @[Mux.scala:126:16] wire _next_i_T_12 = _next_i_T_10 & _next_i_T_11; // @[LoopMatmul.scala:665:{46,66,78}] wire [15:0] next_i_max_1 = _next_i_max_T_1[15:0]; // @[Util.scala:39:28] wire [15:0] _next_i_T_14 = _next_i_T_13[15:0]; // @[Util.scala:41:15] wire _next_i_T_15 = ~_next_i_T_12; // @[Util.scala:42:8] wire _next_i_T_17 = _next_i_T_16 > {1'h0, next_i_max_1}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_i_T_18 = _next_i_T_17 ? 16'h0 : _next_i_T_14; // @[Mux.scala:126:16] wire [15:0] next_i_1 = _next_i_T_15 ? i : _next_i_T_18; // @[Mux.scala:126:16] wire _state_T = io_req_bits_act_0 == 3'h2; // @[LoopMatmul.scala:514:7, :589:17, :682:35] wire _state_T_1 = io_req_bits_act_0 == 3'h4; // @[LoopMatmul.scala:514:7, :682:81] wire _state_T_2 = _state_T \| _state_T_1; // @[LoopMatmul.scala:682:{35,61,81}] wire [1:0] _state_T_3 = _state_T_2 ? 2'h2 : 2'h1; // @[LoopMatmul.scala:646:36, :682:{17,61}] wire _T_10 = io_cmd_ready_0 & io_cmd_valid_0; // @[Decoupled.scala:51:35] wire _T_3 = _T_10 & state == 2'h1; // @[Decoupled.scala:51:35] wire _T_9 = _T_10 & _io_cmd_bits_T; // @[Decoupled.scala:51:35] wire _T_12 = _T_10 & (&state); // @[Decoupled.scala:51:35] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoopMatmul.scala:514:7] if (reset) // @[LoopMatmul.scala:514:7] state <= 2'h0; // @[LoopMatmul.scala:538:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[LoopMatmul.scala:538:22, :682:17] else if (\|req_dram_addr) begin // @[LoopMatmul.scala:540:16, :636:85] if (_T_3) begin // @[LoopMatmul.scala:646:27] if (_next_j_T & next_j == 16'h0) // @[Mux.scala:126:16] state <= 2'h0; // @[LoopMatmul.scala:538:22] end else if (_T_9) // @[LoopMatmul.scala:657:27] state <= 2'h3; // @[LoopMatmul.scala:538:22] else if (_T_12) begin // @[LoopMatmul.scala:659:27] if (next_i_1 == 16'h0 & _next_i_T_11 & _T_16 & _T_18 & _T_22) // @[Mux.scala:126:16] state <= 2'h0; // @[LoopMatmul.scala:538:22] else if (_T_22) // @[LoopMatmul.scala:661:70] state <= 2'h2; // @[LoopMatmul.scala:538:22] end end else // @[LoopMatmul.scala:636:85] state <= 2'h0; // @[LoopMatmul.scala:538:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_max_k <= io_req_bits_max_k_0; // @[LoopMatmul.scala:514:7, :540:16] req_max_j <= io_req_bits_max_j_0; // @[LoopMatmul.scala:514:7, :540:16] req_max_i <= io_req_bits_max_i_0; // @[LoopMatmul.scala:514:7, :540:16] req_pad_j <= io_req_bits_pad_j_0; // @[LoopMatmul.scala:514:7, :540:16] req_pad_i <= io_req_bits_pad_i_0; // @[LoopMatmul.scala:514:7, :540:16] req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopMatmul.scala:514:7, :540:16] req_dram_stride <= io_req_bits_dram_stride_0; // @[LoopMatmul.scala:514:7, :540:16] req_full_c <= io_req_bits_full_c_0; // @[LoopMatmul.scala:514:7, :540:16] req_act <= io_req_bits_act_0; // @[LoopMatmul.scala:514:7, :540:16] req_addr_start <= io_req_bits_addr_start_0; // @[LoopMatmul.scala:514:7, :540:16] req_loop_id <= io_req_bits_loop_id_0; // @[LoopMatmul.scala:514:7, :540:16] req_is_resadd <= io_req_bits_is_resadd_0; // @[LoopMatmul.scala:514:7, :540:16] j <= 16'h0; // @[LoopMatmul.scala:545:14] i <= 16'h0; // @[LoopMatmul.scala:546:14] ln_row <= 16'h0; // @[LoopMatmul.scala:571:19] ln_cmd <= 16'h0; // @[LoopMatmul.scala:572:19] ln_stat_id <= 16'h0; // @[LoopMatmul.scala:573:23] end else begin // @[Decoupled.scala:51:35] if (\|req_dram_addr) begin // @[LoopMatmul.scala:540:16, :636:85] if (_T_3) begin // @[LoopMatmul.scala:646:27] j <= next_j; // @[Mux.scala:126:16] i <= next_i; // @[Mux.scala:126:16] end else if (_T_9 \| ~_T_12) begin // @[LoopMatmul.scala:545:14, :546:14, :657:{27,51}, :659:{27,47}] end else begin // @[LoopMatmul.scala:546:14, :657:51, :659:47] j <= next_j_1; // @[Mux.scala:126:16] i <= next_i_1; // @[Mux.scala:126:16] end end if (~(\|req_dram_addr) \| _T_3 \| _T_9 \| ~_T_12) begin // @[LoopMatmul.scala:540:16, :545:14, :573:23, :636:85, :644:{23,32}, :646:{27,44}, :657:{27,51}, :659:{27,47}] end else begin // @[LoopMatmul.scala:573:23, :644:32, :646:44, :657:51, :659:47] ln_row <= next_row; // @[Mux.scala:126:16] ln_cmd <= next_cmd; // @[Mux.scala:126:16] ln_stat_id <= next_stat_id; // @[Mux.scala:126:16] end end always @(posedge) assign io_req_ready = io_req_ready_0; // @[LoopMatmul.scala:514:7] assign io_cmd_valid = io_cmd_valid_0; // @[LoopMatmul.scala:514:7] assign io_cmd_bits_inst_funct = io_cmd_bits_inst_funct_0; // @[LoopMatmul.scala:514:7] assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopMatmul.scala:514:7] assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopMatmul.scala:514:7] assign io_idle = io_idle_0; // @[LoopMatmul.scala:514:7] assign io_loop_id = io_loop_id_0; // @[LoopMatmul.scala:514:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FPToInt_3 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : connect in, io.in.bits reg valid : UInt<1>, clock connect valid, io.in.valid inst dcmp of CompareRecFN_3 connect dcmp.io.a, in.in1 connect dcmp.io.b, in.in2 node _dcmp_io_signaling_T = bits(in.rm, 1, 1) node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0)) connect dcmp.io.signaling, _dcmp_io_signaling_T_1 node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9) node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp) connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T) node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3 node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T) node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1) node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist) node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0) node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1) node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2) node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf) node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5) node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T) node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1) node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut) node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut) node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1) node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_unrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T) node toint_ieee_prevUnrecoded_unrecoded_fractOut = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, toint_ieee_prevUnrecoded_unrecoded_denormFract, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_unrecoded_hi = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, toint_ieee_prevUnrecoded_unrecoded_expOut) node toint_ieee_prevUnrecoded_unrecoded = cat(toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut) node _toint_ieee_prevUnrecoded_prevRecoded_T = bits(toint_ieee_prevRecoded, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_1 = bits(toint_ieee_prevRecoded, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_2 = bits(toint_ieee_prevRecoded, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi = cat(_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1) node toint_ieee_prevUnrecoded_prevRecoded = cat(toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevUnrecoded_prevRecoded, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevUnrecoded_prevRecoded, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut) node toint_ieee_prevUnrecoded_prevUnrecoded = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut) node _toint_ieee_prevUnrecoded_T = shr(toint_ieee_prevUnrecoded_unrecoded, 16) node _toint_ieee_prevUnrecoded_T_1 = bits(toint_ieee_prevRecoded, 31, 29) node _toint_ieee_prevUnrecoded_T_2 = andr(_toint_ieee_prevUnrecoded_T_1) node _toint_ieee_prevUnrecoded_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded, 15, 0) node _toint_ieee_prevUnrecoded_T_4 = mux(_toint_ieee_prevUnrecoded_T_2, toint_ieee_prevUnrecoded_prevUnrecoded, _toint_ieee_prevUnrecoded_T_3) node toint_ieee_prevUnrecoded = cat(_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4) node _toint_ieee_T = shr(toint_ieee_unrecoded, 32) node _toint_ieee_T_1 = bits(in.in1, 63, 61) node _toint_ieee_T_2 = andr(_toint_ieee_T_1) node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0) node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3) node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4) node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 15, 0) node _toint_ieee_T_7 = bits(_toint_ieee_T_6, 15, 15) node _toint_ieee_T_8 = mux(_toint_ieee_T_7, UInt<16>(0hffff), UInt<16>(0h0)) node _toint_ieee_T_9 = cat(_toint_ieee_T_8, _toint_ieee_T_6) node _toint_ieee_T_10 = cat(_toint_ieee_T_9, _toint_ieee_T_9) node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1 node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1) connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7 node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2) node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1) node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1) node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0) node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1) node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8) node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf) node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11) node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2) node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3) node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1) node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1) node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4) node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_unrecoded_denormFract_1, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_unrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1) node toint_ieee_prevUnrecoded_unrecoded_1 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_prevRecoded_T_3 = bits(toint_ieee_prevRecoded_1, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_4 = bits(toint_ieee_prevRecoded_1, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_5 = bits(toint_ieee_prevRecoded_1, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_1 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4) node toint_ieee_prevUnrecoded_prevRecoded_1 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1) node toint_ieee_prevUnrecoded_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_T_5 = shr(toint_ieee_prevUnrecoded_unrecoded_1, 16) node _toint_ieee_prevUnrecoded_T_6 = bits(toint_ieee_prevRecoded_1, 31, 29) node _toint_ieee_prevUnrecoded_T_7 = andr(_toint_ieee_prevUnrecoded_T_6) node _toint_ieee_prevUnrecoded_T_8 = bits(toint_ieee_prevUnrecoded_unrecoded_1, 15, 0) node _toint_ieee_prevUnrecoded_T_9 = mux(_toint_ieee_prevUnrecoded_T_7, toint_ieee_prevUnrecoded_prevUnrecoded_1, _toint_ieee_prevUnrecoded_T_8) node toint_ieee_prevUnrecoded_1 = cat(_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9) node _toint_ieee_T_11 = shr(toint_ieee_unrecoded_1, 32) node _toint_ieee_T_12 = bits(in.in1, 63, 61) node _toint_ieee_T_13 = andr(_toint_ieee_T_12) node _toint_ieee_T_14 = bits(toint_ieee_unrecoded_1, 31, 0) node _toint_ieee_T_15 = mux(_toint_ieee_T_13, toint_ieee_prevUnrecoded_1, _toint_ieee_T_14) node _toint_ieee_T_16 = cat(_toint_ieee_T_11, _toint_ieee_T_15) node _toint_ieee_T_17 = bits(_toint_ieee_T_16, 31, 0) node _toint_ieee_T_18 = cat(_toint_ieee_T_17, _toint_ieee_T_17) node toint_ieee_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_unrecoded_rawIn_2.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_unrecoded_rawIn_2.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_unrecoded_rawIn_2.isZero, toint_ieee_unrecoded_rawIn_isZero_2 node _toint_ieee_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_2.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_unrecoded_rawIn_exp_2) connect toint_ieee_unrecoded_rawIn_2.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_unrecoded_rawIn_2.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_11 node toint_ieee_unrecoded_isSubnormal_2 = lt(toint_ieee_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_4) node toint_ieee_unrecoded_denormShiftDist_2 = tail(_toint_ieee_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_unrecoded_denormFract_T_4 = shr(toint_ieee_unrecoded_rawIn_2.sig, 1) node _toint_ieee_unrecoded_denormFract_T_5 = dshr(_toint_ieee_unrecoded_denormFract_T_4, toint_ieee_unrecoded_denormShiftDist_2) node toint_ieee_unrecoded_denormFract_2 = bits(_toint_ieee_unrecoded_denormFract_T_5, 51, 0) node _toint_ieee_unrecoded_expOut_T_12 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_13 = sub(_toint_ieee_unrecoded_expOut_T_12, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_14 = tail(_toint_ieee_unrecoded_expOut_T_13, 1) node _toint_ieee_unrecoded_expOut_T_15 = mux(toint_ieee_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_14) node _toint_ieee_unrecoded_expOut_T_16 = or(toint_ieee_unrecoded_rawIn_2.isNaN, toint_ieee_unrecoded_rawIn_2.isInf) node _toint_ieee_unrecoded_expOut_T_17 = mux(_toint_ieee_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_2 = or(_toint_ieee_unrecoded_expOut_T_15, _toint_ieee_unrecoded_expOut_T_17) node _toint_ieee_unrecoded_fractOut_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_5 = mux(toint_ieee_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_4) node toint_ieee_unrecoded_fractOut_2 = mux(toint_ieee_unrecoded_isSubnormal_2, toint_ieee_unrecoded_denormFract_2, _toint_ieee_unrecoded_fractOut_T_5) node toint_ieee_unrecoded_hi_2 = cat(toint_ieee_unrecoded_rawIn_2.sign, toint_ieee_unrecoded_expOut_2) node toint_ieee_unrecoded_2 = cat(toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2) node _toint_ieee_prevRecoded_T_6 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_7 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_8 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_2 = cat(_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7) node toint_ieee_prevRecoded_2 = cat(toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(toint_ieee_prevRecoded_2, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevRecoded_2, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevRecoded_2, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_unrecoded_denormFract_2, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_unrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2) node toint_ieee_prevUnrecoded_unrecoded_2 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_prevRecoded_T_6 = bits(toint_ieee_prevRecoded_2, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_7 = bits(toint_ieee_prevRecoded_2, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_8 = bits(toint_ieee_prevRecoded_2, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_2 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7) node toint_ieee_prevUnrecoded_prevRecoded_2 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2) node toint_ieee_prevUnrecoded_prevUnrecoded_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_T_10 = shr(toint_ieee_prevUnrecoded_unrecoded_2, 16) node _toint_ieee_prevUnrecoded_T_11 = bits(toint_ieee_prevRecoded_2, 31, 29) node _toint_ieee_prevUnrecoded_T_12 = andr(_toint_ieee_prevUnrecoded_T_11) node _toint_ieee_prevUnrecoded_T_13 = bits(toint_ieee_prevUnrecoded_unrecoded_2, 15, 0) node _toint_ieee_prevUnrecoded_T_14 = mux(_toint_ieee_prevUnrecoded_T_12, toint_ieee_prevUnrecoded_prevUnrecoded_2, _toint_ieee_prevUnrecoded_T_13) node toint_ieee_prevUnrecoded_2 = cat(_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14) node _toint_ieee_T_19 = shr(toint_ieee_unrecoded_2, 32) node _toint_ieee_T_20 = bits(in.in1, 63, 61) node _toint_ieee_T_21 = andr(_toint_ieee_T_20) node _toint_ieee_T_22 = bits(toint_ieee_unrecoded_2, 31, 0) node _toint_ieee_T_23 = mux(_toint_ieee_T_21, toint_ieee_prevUnrecoded_2, _toint_ieee_T_22) node _toint_ieee_T_24 = cat(_toint_ieee_T_19, _toint_ieee_T_23) node _toint_ieee_T_25 = bits(_toint_ieee_T_24, 63, 0) node _toint_ieee_T_26 = eq(in.typeTagOut, UInt<1>(0h1)) node _toint_ieee_T_27 = mux(_toint_ieee_T_26, _toint_ieee_T_18, _toint_ieee_T_10) node _toint_ieee_T_28 = eq(in.typeTagOut, UInt<2>(0h2)) node _toint_ieee_T_29 = mux(_toint_ieee_T_28, _toint_ieee_T_25, _toint_ieee_T_27) node _toint_ieee_T_30 = eq(in.typeTagOut, UInt<2>(0h3)) node toint_ieee = mux(_toint_ieee_T_30, _toint_ieee_T_25, _toint_ieee_T_29) wire toint : UInt connect toint, toint_ieee node _intType_T = bits(in.fmt, 0, 0) wire intType : UInt<1> connect intType, _intType_T node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp) connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T) node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist) node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0) node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1) node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2) node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf) node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5) node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T) node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1) node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut) node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut) node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1) node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_unrecoded_denormFract, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_unrecoded_hi = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut) node io_out_bits_store_prevUnrecoded_unrecoded = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_prevRecoded_T = bits(io_out_bits_store_prevRecoded, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = bits(io_out_bits_store_prevRecoded, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = bits(io_out_bits_store_prevRecoded, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1) node io_out_bits_store_prevUnrecoded_prevRecoded = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut) node io_out_bits_store_prevUnrecoded_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_T = shr(io_out_bits_store_prevUnrecoded_unrecoded, 16) node _io_out_bits_store_prevUnrecoded_T_1 = bits(io_out_bits_store_prevRecoded, 31, 29) node _io_out_bits_store_prevUnrecoded_T_2 = andr(_io_out_bits_store_prevUnrecoded_T_1) node _io_out_bits_store_prevUnrecoded_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded, 15, 0) node _io_out_bits_store_prevUnrecoded_T_4 = mux(_io_out_bits_store_prevUnrecoded_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded, _io_out_bits_store_prevUnrecoded_T_3) node io_out_bits_store_prevUnrecoded = cat(_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4) node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32) node _io_out_bits_store_T_1 = bits(in.in1, 63, 61) node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1) node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0) node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3) node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4) node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 15, 0) node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6) node _io_out_bits_store_T_8 = cat(_io_out_bits_store_T_7, _io_out_bits_store_T_7) node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1) connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2) node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1) node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1) node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8) node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf) node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11) node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2) node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3) node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1) node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1) node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4) node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_unrecoded_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = bits(io_out_bits_store_prevRecoded_1, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = bits(io_out_bits_store_prevRecoded_1, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = bits(io_out_bits_store_prevRecoded_1, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4) node io_out_bits_store_prevUnrecoded_prevRecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_T_5 = shr(io_out_bits_store_prevUnrecoded_unrecoded_1, 16) node _io_out_bits_store_prevUnrecoded_T_6 = bits(io_out_bits_store_prevRecoded_1, 31, 29) node _io_out_bits_store_prevUnrecoded_T_7 = andr(_io_out_bits_store_prevUnrecoded_T_6) node _io_out_bits_store_prevUnrecoded_T_8 = bits(io_out_bits_store_prevUnrecoded_unrecoded_1, 15, 0) node _io_out_bits_store_prevUnrecoded_T_9 = mux(_io_out_bits_store_prevUnrecoded_T_7, io_out_bits_store_prevUnrecoded_prevUnrecoded_1, _io_out_bits_store_prevUnrecoded_T_8) node io_out_bits_store_prevUnrecoded_1 = cat(_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9) node _io_out_bits_store_T_9 = shr(io_out_bits_store_unrecoded_1, 32) node _io_out_bits_store_T_10 = bits(in.in1, 63, 61) node _io_out_bits_store_T_11 = andr(_io_out_bits_store_T_10) node _io_out_bits_store_T_12 = bits(io_out_bits_store_unrecoded_1, 31, 0) node _io_out_bits_store_T_13 = mux(_io_out_bits_store_T_11, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_12) node _io_out_bits_store_T_14 = cat(_io_out_bits_store_T_9, _io_out_bits_store_T_13) node _io_out_bits_store_T_15 = bits(_io_out_bits_store_T_14, 31, 0) node _io_out_bits_store_T_16 = cat(_io_out_bits_store_T_15, _io_out_bits_store_T_15) node io_out_bits_store_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_unrecoded_rawIn_2.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_unrecoded_rawIn_2.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_unrecoded_rawIn_2.isZero, io_out_bits_store_unrecoded_rawIn_isZero_2 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_2.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_unrecoded_rawIn_exp_2) connect io_out_bits_store_unrecoded_rawIn_2.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_unrecoded_rawIn_2.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_unrecoded_isSubnormal_2 = lt(io_out_bits_store_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_4) node io_out_bits_store_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_unrecoded_denormFract_T_4 = shr(io_out_bits_store_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_unrecoded_denormFract_T_4, io_out_bits_store_unrecoded_denormShiftDist_2) node io_out_bits_store_unrecoded_denormFract_2 = bits(_io_out_bits_store_unrecoded_denormFract_T_5, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_12 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_13 = sub(_io_out_bits_store_unrecoded_expOut_T_12, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_14 = tail(_io_out_bits_store_unrecoded_expOut_T_13, 1) node _io_out_bits_store_unrecoded_expOut_T_15 = mux(io_out_bits_store_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_14) node _io_out_bits_store_unrecoded_expOut_T_16 = or(io_out_bits_store_unrecoded_rawIn_2.isNaN, io_out_bits_store_unrecoded_rawIn_2.isInf) node _io_out_bits_store_unrecoded_expOut_T_17 = mux(_io_out_bits_store_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_2 = or(_io_out_bits_store_unrecoded_expOut_T_15, _io_out_bits_store_unrecoded_expOut_T_17) node _io_out_bits_store_unrecoded_fractOut_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_5 = mux(io_out_bits_store_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_4) node io_out_bits_store_unrecoded_fractOut_2 = mux(io_out_bits_store_unrecoded_isSubnormal_2, io_out_bits_store_unrecoded_denormFract_2, _io_out_bits_store_unrecoded_fractOut_T_5) node io_out_bits_store_unrecoded_hi_2 = cat(io_out_bits_store_unrecoded_rawIn_2.sign, io_out_bits_store_unrecoded_expOut_2) node io_out_bits_store_unrecoded_2 = cat(io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2) node _io_out_bits_store_prevRecoded_T_6 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_7 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_8 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_2 = cat(_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7) node io_out_bits_store_prevRecoded_2 = cat(io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevRecoded_2, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevRecoded_2, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevRecoded_2, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_unrecoded_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = bits(io_out_bits_store_prevRecoded_2, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = bits(io_out_bits_store_prevRecoded_2, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = bits(io_out_bits_store_prevRecoded_2, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7) node io_out_bits_store_prevUnrecoded_prevRecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_T_10 = shr(io_out_bits_store_prevUnrecoded_unrecoded_2, 16) node _io_out_bits_store_prevUnrecoded_T_11 = bits(io_out_bits_store_prevRecoded_2, 31, 29) node _io_out_bits_store_prevUnrecoded_T_12 = andr(_io_out_bits_store_prevUnrecoded_T_11) node _io_out_bits_store_prevUnrecoded_T_13 = bits(io_out_bits_store_prevUnrecoded_unrecoded_2, 15, 0) node _io_out_bits_store_prevUnrecoded_T_14 = mux(_io_out_bits_store_prevUnrecoded_T_12, io_out_bits_store_prevUnrecoded_prevUnrecoded_2, _io_out_bits_store_prevUnrecoded_T_13) node io_out_bits_store_prevUnrecoded_2 = cat(_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14) node _io_out_bits_store_T_17 = shr(io_out_bits_store_unrecoded_2, 32) node _io_out_bits_store_T_18 = bits(in.in1, 63, 61) node _io_out_bits_store_T_19 = andr(_io_out_bits_store_T_18) node _io_out_bits_store_T_20 = bits(io_out_bits_store_unrecoded_2, 31, 0) node _io_out_bits_store_T_21 = mux(_io_out_bits_store_T_19, io_out_bits_store_prevUnrecoded_2, _io_out_bits_store_T_20) node _io_out_bits_store_T_22 = cat(_io_out_bits_store_T_17, _io_out_bits_store_T_21) node _io_out_bits_store_T_23 = bits(_io_out_bits_store_T_22, 63, 0) node _io_out_bits_store_T_24 = eq(in.typeTagOut, UInt<1>(0h1)) node _io_out_bits_store_T_25 = mux(_io_out_bits_store_T_24, _io_out_bits_store_T_16, _io_out_bits_store_T_8) node _io_out_bits_store_T_26 = eq(in.typeTagOut, UInt<2>(0h2)) node _io_out_bits_store_T_27 = mux(_io_out_bits_store_T_26, _io_out_bits_store_T_23, _io_out_bits_store_T_25) node _io_out_bits_store_T_28 = eq(in.typeTagOut, UInt<2>(0h3)) node _io_out_bits_store_T_29 = mux(_io_out_bits_store_T_28, _io_out_bits_store_T_23, _io_out_bits_store_T_27) connect io.out.bits.store, _io_out_bits_store_T_29 node _io_out_bits_toint_T = bits(toint, 31, 0) node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31) node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T) node _io_out_bits_toint_T_4 = bits(toint, 63, 0) node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1)) node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3) connect io.out.bits.toint, _io_out_bits_toint_T_6 connect io.out.bits.exc, UInt<1>(0h0) node _T = bits(in.rm, 0, 0) when _T : node classify_out_sign = bits(in.in1, 64, 64) node classify_out_fractIn = bits(in.in1, 51, 0) node classify_out_expIn = bits(in.in1, 63, 52) node _classify_out_fractOut_T = shl(classify_out_fractIn, 11) node classify_out_fractOut = shr(_classify_out_fractOut_T, 53) node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9) node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<6>(0h20)) node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1) node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800)) node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1) node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0)) node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6)) node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1) node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 2, 0) node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3) node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 5, 0) node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5) node classify_out_hi = cat(classify_out_sign, classify_out_expOut) node _classify_out_T = cat(classify_out_hi, classify_out_fractOut) node classify_out_sign_1 = bits(_classify_out_T, 16, 16) node classify_out_code = bits(_classify_out_T, 15, 13) node classify_out_codeHi = bits(classify_out_code, 2, 1) node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 13, 10) node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2)) node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1)) node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn) node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2) node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0)) node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1) node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2)) node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3) node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0)) node _classify_out_isInf_T = bits(classify_out_code, 0, 0) node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0)) node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1) node classify_out_isNaN = andr(classify_out_code) node _classify_out_isSNaN_T = bits(_classify_out_T, 9, 9) node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0)) node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1) node _classify_out_isQNaN_T = bits(_classify_out_T, 9, 9) node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T) node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1) node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3) node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5) node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7) node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1) node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1) node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1) node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1) node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12) node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9) node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10) node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo) node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6) node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN) node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2) node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo) node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo) node classify_out_sign_2 = bits(in.in1, 64, 64) node classify_out_fractIn_1 = bits(in.in1, 51, 0) node classify_out_expIn_1 = bits(in.in1, 63, 52) node _classify_out_fractOut_T_1 = shl(classify_out_fractIn_1, 24) node classify_out_fractOut_1 = shr(_classify_out_fractOut_T_1, 53) node classify_out_expOut_expCode_1 = bits(classify_out_expIn_1, 11, 9) node _classify_out_expOut_commonCase_T_3 = add(classify_out_expIn_1, UInt<9>(0h100)) node _classify_out_expOut_commonCase_T_4 = tail(_classify_out_expOut_commonCase_T_3, 1) node _classify_out_expOut_commonCase_T_5 = sub(_classify_out_expOut_commonCase_T_4, UInt<12>(0h800)) node classify_out_expOut_commonCase_1 = tail(_classify_out_expOut_commonCase_T_5, 1) node _classify_out_expOut_T_6 = eq(classify_out_expOut_expCode_1, UInt<1>(0h0)) node _classify_out_expOut_T_7 = geq(classify_out_expOut_expCode_1, UInt<3>(0h6)) node _classify_out_expOut_T_8 = or(_classify_out_expOut_T_6, _classify_out_expOut_T_7) node _classify_out_expOut_T_9 = bits(classify_out_expOut_commonCase_1, 5, 0) node _classify_out_expOut_T_10 = cat(classify_out_expOut_expCode_1, _classify_out_expOut_T_9) node _classify_out_expOut_T_11 = bits(classify_out_expOut_commonCase_1, 8, 0) node classify_out_expOut_1 = mux(_classify_out_expOut_T_8, _classify_out_expOut_T_10, _classify_out_expOut_T_11) node classify_out_hi_2 = cat(classify_out_sign_2, classify_out_expOut_1) node _classify_out_T_14 = cat(classify_out_hi_2, classify_out_fractOut_1) node classify_out_sign_3 = bits(_classify_out_T_14, 32, 32) node classify_out_code_1 = bits(_classify_out_T_14, 31, 29) node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1) node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_1 = bits(_classify_out_T_14, 29, 23) node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2)) node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1) node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5) node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0)) node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5) node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2)) node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7) node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0)) node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0) node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0)) node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3) node classify_out_isNaN_1 = andr(classify_out_code_1) node _classify_out_isSNaN_T_2 = bits(_classify_out_T_14, 22, 22) node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0)) node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3) node _classify_out_isQNaN_T_1 = bits(_classify_out_T_14, 22, 22) node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1) node _classify_out_T_15 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_16 = and(classify_out_isInf_1, _classify_out_T_15) node _classify_out_T_17 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_18 = and(classify_out_isNormal_1, _classify_out_T_17) node _classify_out_T_19 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_20 = and(classify_out_isSubnormal_1, _classify_out_T_19) node _classify_out_T_21 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_22 = and(classify_out_isZero_1, _classify_out_T_21) node _classify_out_T_23 = and(classify_out_isZero_1, classify_out_sign_3) node _classify_out_T_24 = and(classify_out_isSubnormal_1, classify_out_sign_3) node _classify_out_T_25 = and(classify_out_isNormal_1, classify_out_sign_3) node _classify_out_T_26 = and(classify_out_isInf_1, classify_out_sign_3) node classify_out_lo_lo_1 = cat(_classify_out_T_25, _classify_out_T_26) node classify_out_lo_hi_hi_1 = cat(_classify_out_T_22, _classify_out_T_23) node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_24) node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1) node classify_out_hi_lo_1 = cat(_classify_out_T_18, _classify_out_T_20) node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1) node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_16) node classify_out_hi_3 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1) node _classify_out_T_27 = cat(classify_out_hi_3, classify_out_lo_1) node classify_out_sign_4 = bits(in.in1, 64, 64) node classify_out_code_2 = bits(in.in1, 63, 61) node classify_out_codeHi_2 = bits(classify_out_code_2, 2, 1) node classify_out_isSpecial_2 = eq(classify_out_codeHi_2, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_2 = bits(in.in1, 61, 52) node classify_out_isHighSubnormalIn_2 = lt(_classify_out_isHighSubnormalIn_T_2, UInt<2>(0h2)) node _classify_out_isSubnormal_T_6 = eq(classify_out_code_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_7 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_8 = and(_classify_out_isSubnormal_T_7, classify_out_isHighSubnormalIn_2) node classify_out_isSubnormal_2 = or(_classify_out_isSubnormal_T_6, _classify_out_isSubnormal_T_8) node _classify_out_isNormal_T_8 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isNormal_T_9 = eq(classify_out_isHighSubnormalIn_2, UInt<1>(0h0)) node _classify_out_isNormal_T_10 = and(_classify_out_isNormal_T_8, _classify_out_isNormal_T_9) node _classify_out_isNormal_T_11 = eq(classify_out_codeHi_2, UInt<2>(0h2)) node classify_out_isNormal_2 = or(_classify_out_isNormal_T_10, _classify_out_isNormal_T_11) node classify_out_isZero_2 = eq(classify_out_code_2, UInt<1>(0h0)) node _classify_out_isInf_T_4 = bits(classify_out_code_2, 0, 0) node _classify_out_isInf_T_5 = eq(_classify_out_isInf_T_4, UInt<1>(0h0)) node classify_out_isInf_2 = and(classify_out_isSpecial_2, _classify_out_isInf_T_5) node classify_out_isNaN_2 = andr(classify_out_code_2) node _classify_out_isSNaN_T_4 = bits(in.in1, 51, 51) node _classify_out_isSNaN_T_5 = eq(_classify_out_isSNaN_T_4, UInt<1>(0h0)) node classify_out_isSNaN_2 = and(classify_out_isNaN_2, _classify_out_isSNaN_T_5) node _classify_out_isQNaN_T_2 = bits(in.in1, 51, 51) node classify_out_isQNaN_2 = and(classify_out_isNaN_2, _classify_out_isQNaN_T_2) node _classify_out_T_28 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_29 = and(classify_out_isInf_2, _classify_out_T_28) node _classify_out_T_30 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_31 = and(classify_out_isNormal_2, _classify_out_T_30) node _classify_out_T_32 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_33 = and(classify_out_isSubnormal_2, _classify_out_T_32) node _classify_out_T_34 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_35 = and(classify_out_isZero_2, _classify_out_T_34) node _classify_out_T_36 = and(classify_out_isZero_2, classify_out_sign_4) node _classify_out_T_37 = and(classify_out_isSubnormal_2, classify_out_sign_4) node _classify_out_T_38 = and(classify_out_isNormal_2, classify_out_sign_4) node _classify_out_T_39 = and(classify_out_isInf_2, classify_out_sign_4) node classify_out_lo_lo_2 = cat(_classify_out_T_38, _classify_out_T_39) node classify_out_lo_hi_hi_2 = cat(_classify_out_T_35, _classify_out_T_36) node classify_out_lo_hi_2 = cat(classify_out_lo_hi_hi_2, _classify_out_T_37) node classify_out_lo_2 = cat(classify_out_lo_hi_2, classify_out_lo_lo_2) node classify_out_hi_lo_2 = cat(_classify_out_T_31, _classify_out_T_33) node classify_out_hi_hi_hi_2 = cat(classify_out_isQNaN_2, classify_out_isSNaN_2) node classify_out_hi_hi_2 = cat(classify_out_hi_hi_hi_2, _classify_out_T_29) node classify_out_hi_4 = cat(classify_out_hi_hi_2, classify_out_hi_lo_2) node _classify_out_T_40 = cat(classify_out_hi_4, classify_out_lo_2) node _classify_out_T_41 = eq(in.typeTagOut, UInt<1>(0h1)) node _classify_out_T_42 = mux(_classify_out_T_41, _classify_out_T_27, _classify_out_T_13) node _classify_out_T_43 = eq(in.typeTagOut, UInt<2>(0h2)) node _classify_out_T_44 = mux(_classify_out_T_43, _classify_out_T_40, _classify_out_T_42) node _classify_out_T_45 = eq(in.typeTagOut, UInt<2>(0h3)) node classify_out = mux(_classify_out_T_45, _classify_out_T_40, _classify_out_T_44) node _toint_T = shr(toint_ieee, 32) node _toint_T_1 = shl(_toint_T, 32) node _toint_T_2 = or(classify_out, _toint_T_1) connect toint, _toint_T_2 connect intType, UInt<1>(0h0) when in.wflags : node _toint_T_3 = not(in.rm) node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq) node _toint_T_5 = and(_toint_T_3, _toint_T_4) node _toint_T_6 = orr(_toint_T_5) node _toint_T_7 = shr(toint_ieee, 32) node _toint_T_8 = shl(_toint_T_7, 32) node _toint_T_9 = or(_toint_T_6, _toint_T_8) connect toint, _toint_T_9 connect io.out.bits.exc, dcmp.io.exceptionFlags connect intType, UInt<1>(0h0) node _T_1 = eq(in.ren2, UInt<1>(0h0)) when _T_1 : node cvtType = bits(in.typ, 1, 1) connect intType, cvtType inst conv of RecFNToIN_e11_s53_i64_3 connect conv.clock, clock connect conv.reset, reset connect conv.io.in, in.in1 connect conv.io.roundingMode, in.rm node _conv_io_signedOut_T = bits(in.typ, 0, 0) node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T) connect conv.io.signedOut, _conv_io_signedOut_T_1 connect toint, conv.io.out node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1) node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T) node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0) node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0)) node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2) connect io.out.bits.exc, _io_out_bits_exc_T_3 node _T_2 = eq(cvtType, UInt<1>(0h0)) when _T_2 : inst narrow of RecFNToIN_e11_s53_i32_3 connect narrow.clock, clock connect narrow.reset, reset connect narrow.io.in, in.in1 connect narrow.io.roundingMode, in.rm node _narrow_io_signedOut_T = bits(in.typ, 0, 0) node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T) connect narrow.io.signedOut, _narrow_io_signedOut_T_1 node _excSign_T = bits(in.in1, 64, 64) node _excSign_T_1 = bits(in.in1, 63, 61) node _excSign_T_2 = andr(_excSign_T_1) node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0)) node excSign = and(_excSign_T, _excSign_T_3) node _excOut_T = eq(conv.io.signedOut, excSign) node _excOut_T_1 = eq(excSign, UInt<1>(0h0)) node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0)) node excOut = cat(_excOut_T, _excOut_T_2) node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2) node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1) node invalid = or(_invalid_T, _invalid_T_1) when invalid : node _toint_T_10 = shr(conv.io.out, 32) node _toint_T_11 = cat(_toint_T_10, excOut) connect toint, _toint_T_11 node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0)) node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0) node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5) node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0)) node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6) connect io.out.bits.exc, _io_out_bits_exc_T_7 connect io.out.valid, valid node _io_out_bits_lt_T = asSInt(dcmp.io.a) node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b) node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3) node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4) connect io.out.bits.lt, _io_out_bits_lt_T_5 connect io.out.bits.in, in	module FPToInt_3( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input reset, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ldst, // @[FPU.scala:461:14] input io_in_bits_wen, // @[FPU.scala:461:14] input io_in_bits_ren1, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input io_in_bits_ren3, // @[FPU.scala:461:14] input io_in_bits_swap12, // @[FPU.scala:461:14] input io_in_bits_swap23, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_fromint, // @[FPU.scala:461:14] input io_in_bits_toint, // @[FPU.scala:461:14] input io_in_bits_fastpipe, // @[FPU.scala:461:14] input io_in_bits_fma, // @[FPU.scala:461:14] input io_in_bits_div, // @[FPU.scala:461:14] input io_in_bits_sqrt, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input io_in_bits_vec, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] input [64:0] io_in_bits_in3, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2, // @[FPU.scala:461:14] output io_out_bits_lt, // @[FPU.scala:461:14] output [63:0] io_out_bits_store, // @[FPU.scala:461:14] output [63:0] io_out_bits_toint, // @[FPU.scala:461:14] output [4:0] io_out_bits_exc // @[FPU.scala:461:14] ); wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:453:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:453:7] wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32] wire [63:0] _io_out_bits_store_T_29; // @[package.scala:39:76] wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76] wire io_out_bits_in_ldst; // @[FPU.scala:453:7] wire io_out_bits_in_wen; // @[FPU.scala:453:7] wire io_out_bits_in_ren1; // @[FPU.scala:453:7] wire io_out_bits_in_ren2; // @[FPU.scala:453:7] wire io_out_bits_in_ren3; // @[FPU.scala:453:7] wire io_out_bits_in_swap12; // @[FPU.scala:453:7] wire io_out_bits_in_swap23; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagOut; // @[FPU.scala:453:7] wire io_out_bits_in_fromint; // @[FPU.scala:453:7] wire io_out_bits_in_toint; // @[FPU.scala:453:7] wire io_out_bits_in_fastpipe; // @[FPU.scala:453:7] wire io_out_bits_in_fma; // @[FPU.scala:453:7] wire io_out_bits_in_div; // @[FPU.scala:453:7] wire io_out_bits_in_sqrt; // @[FPU.scala:453:7] wire io_out_bits_in_wflags; // @[FPU.scala:453:7] wire io_out_bits_in_vec; // @[FPU.scala:453:7] wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typ; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmt; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in3; // @[FPU.scala:453:7] wire io_out_bits_lt_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_store_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_toint_0; // @[FPU.scala:453:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:453:7] wire io_out_valid; // @[FPU.scala:453:7] reg in_ldst; // @[FPU.scala:466:21] assign io_out_bits_in_ldst = in_ldst; // @[FPU.scala:453:7, :466:21] reg in_wen; // @[FPU.scala:466:21] assign io_out_bits_in_wen = in_wen; // @[FPU.scala:453:7, :466:21] reg in_ren1; // @[FPU.scala:466:21] assign io_out_bits_in_ren1 = in_ren1; // @[FPU.scala:453:7, :466:21] reg in_ren2; // @[FPU.scala:466:21] assign io_out_bits_in_ren2 = in_ren2; // @[FPU.scala:453:7, :466:21] reg in_ren3; // @[FPU.scala:466:21] assign io_out_bits_in_ren3 = in_ren3; // @[FPU.scala:453:7, :466:21] reg in_swap12; // @[FPU.scala:466:21] assign io_out_bits_in_swap12 = in_swap12; // @[FPU.scala:453:7, :466:21] reg in_swap23; // @[FPU.scala:466:21] assign io_out_bits_in_swap23 = in_swap23; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagIn; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagIn = in_typeTagIn; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagOut = in_typeTagOut; // @[FPU.scala:453:7, :466:21] reg in_fromint; // @[FPU.scala:466:21] assign io_out_bits_in_fromint = in_fromint; // @[FPU.scala:453:7, :466:21] reg in_toint; // @[FPU.scala:466:21] assign io_out_bits_in_toint = in_toint; // @[FPU.scala:453:7, :466:21] reg in_fastpipe; // @[FPU.scala:466:21] assign io_out_bits_in_fastpipe = in_fastpipe; // @[FPU.scala:453:7, :466:21] reg in_fma; // @[FPU.scala:466:21] assign io_out_bits_in_fma = in_fma; // @[FPU.scala:453:7, :466:21] reg in_div; // @[FPU.scala:466:21] assign io_out_bits_in_div = in_div; // @[FPU.scala:453:7, :466:21] reg in_sqrt; // @[FPU.scala:466:21] assign io_out_bits_in_sqrt = in_sqrt; // @[FPU.scala:453:7, :466:21] reg in_wflags; // @[FPU.scala:466:21] assign io_out_bits_in_wflags = in_wflags; // @[FPU.scala:453:7, :466:21] reg in_vec; // @[FPU.scala:466:21] assign io_out_bits_in_vec = in_vec; // @[FPU.scala:453:7, :466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmaCmd; // @[FPU.scala:466:21] assign io_out_bits_in_fmaCmd = in_fmaCmd; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] assign io_out_bits_in_typ = in_typ; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmt; // @[FPU.scala:466:21] assign io_out_bits_in_fmt = in_fmt; // @[FPU.scala:453:7, :466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46] reg [64:0] in_in2; // @[FPU.scala:466:21] assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72] reg [64:0] in_in3; // @[FPU.scala:466:21] assign io_out_bits_in_in3 = in_in3; // @[FPU.scala:453:7, :466:21] reg valid; // @[FPU.scala:467:22] assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22] wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30] wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}] wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [11:0] classify_out_expIn_1 = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_4 = in_in1[64]; // @[FPU.scala:253:17, :466:21] wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31] assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] wire [51:0] classify_out_fractIn_1 = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN \| toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 \| _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN \| toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 \| _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? toint_ieee_prevUnrecoded_unrecoded_denormFract : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi = {toint_ieee_prevUnrecoded_unrecoded_rawIn_sign, toint_ieee_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded = {toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T = toint_ieee_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_1 = toint_ieee_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_2 = toint_ieee_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi = {_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded = {toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = toint_ieee_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN \| toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 \| _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded = {toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T = toint_ieee_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_1 = toint_ieee_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_2 = &_toint_ieee_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_3 = toint_ieee_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_4 = _toint_ieee_prevUnrecoded_T_2 ? toint_ieee_prevUnrecoded_prevUnrecoded : _toint_ieee_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded = {_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_12 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_20 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_10 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_18 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] classify_out_code_2 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21] wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _toint_ieee_T_6 = _toint_ieee_T_5[15:0]; // @[FPU.scala:446:10, :475:107] wire _toint_ieee_T_7 = _toint_ieee_T_6[15]; // @[package.scala:132:38] wire [15:0] _toint_ieee_T_8 = {16{_toint_ieee_T_7}}; // @[package.scala:132:{20,38}] wire [31:0] _toint_ieee_T_9 = {_toint_ieee_T_8, _toint_ieee_T_6}; // @[package.scala:132:{15,20}] wire [63:0] _toint_ieee_T_10 = {2{_toint_ieee_T_9}}; // @[package.scala:132:15] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN \| toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 \| _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN \| toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_1 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 \| _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_1 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_1 = {toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_3 = toint_ieee_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_4 = toint_ieee_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_5 = toint_ieee_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_1 = {_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_1 = {toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN \| toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 \| _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_5 = toint_ieee_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_6 = toint_ieee_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_7 = &_toint_ieee_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_8 = toint_ieee_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_9 = _toint_ieee_prevUnrecoded_T_7 ? toint_ieee_prevUnrecoded_prevUnrecoded_1 : _toint_ieee_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_1 = {_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_13 = &_toint_ieee_T_12; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_14 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_15 = _toint_ieee_T_13 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_14; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_16 = {_toint_ieee_T_11, _toint_ieee_T_15}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_17 = _toint_ieee_T_16[31:0]; // @[FPU.scala:446:10, :476:109] wire [63:0] _toint_ieee_T_18 = {2{_toint_ieee_T_17}}; // @[FPU.scala:476:{63,109}] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_2 = _toint_ieee_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_2_isZero = toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_2_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_2_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_2_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_2_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_2_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_4 = toint_ieee_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_2 = _toint_ieee_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_4 = toint_ieee_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_5 = _toint_ieee_unrecoded_denormFract_T_4 >> toint_ieee_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_2 = _toint_ieee_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_12 = toint_ieee_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_14 = _toint_ieee_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_15 = toint_ieee_unrecoded_isSubnormal_2 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_16 = toint_ieee_unrecoded_rawIn_2_isNaN \| toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_17 = {11{_toint_ieee_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_2 = _toint_ieee_unrecoded_expOut_T_15 \| _toint_ieee_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_4 = toint_ieee_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_5 = toint_ieee_unrecoded_rawIn_2_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_2 = toint_ieee_unrecoded_isSubnormal_2 ? toint_ieee_unrecoded_denormFract_2 : _toint_ieee_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_2 = {toint_ieee_unrecoded_rawIn_2_sign, toint_ieee_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_2 = {toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_2 = {_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_2 = {toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = toint_ieee_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = toint_ieee_prevRecoded_2[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = toint_ieee_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN \| toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 \| _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_2 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_2 = {toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_6 = toint_ieee_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_7 = toint_ieee_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_8 = toint_ieee_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_2 = {_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_2 = {toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = toint_ieee_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = toint_ieee_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = toint_ieee_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN \| toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 \| _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_10 = toint_ieee_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_11 = toint_ieee_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_12 = &_toint_ieee_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_13 = toint_ieee_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_14 = _toint_ieee_prevUnrecoded_T_12 ? toint_ieee_prevUnrecoded_prevUnrecoded_2 : _toint_ieee_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_2 = {_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_19 = toint_ieee_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_21 = &_toint_ieee_T_20; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_22 = toint_ieee_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_23 = _toint_ieee_T_21 ? toint_ieee_prevUnrecoded_2 : _toint_ieee_T_22; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_24 = {_toint_ieee_T_19, _toint_ieee_T_23}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _toint_ieee_T_25 = _toint_ieee_T_24; // @[FPU.scala:446:10, :476:109] wire _GEN = in_typeTagOut == 2'h1; // @[package.scala:39:86] wire _toint_ieee_T_26; // @[package.scala:39:86] assign _toint_ieee_T_26 = _GEN; // @[package.scala:39:86] wire _io_out_bits_store_T_24; // @[package.scala:39:86] assign _io_out_bits_store_T_24 = _GEN; // @[package.scala:39:86] wire _classify_out_T_41; // @[package.scala:39:86] assign _classify_out_T_41 = _GEN; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_27 = _toint_ieee_T_26 ? _toint_ieee_T_18 : _toint_ieee_T_10; // @[package.scala:39:{76,86}] wire _GEN_0 = in_typeTagOut == 2'h2; // @[package.scala:39:86] wire _toint_ieee_T_28; // @[package.scala:39:86] assign _toint_ieee_T_28 = _GEN_0; // @[package.scala:39:86] wire _io_out_bits_store_T_26; // @[package.scala:39:86] assign _io_out_bits_store_T_26 = _GEN_0; // @[package.scala:39:86] wire _classify_out_T_43; // @[package.scala:39:86] assign _classify_out_T_43 = _GEN_0; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_29 = _toint_ieee_T_28 ? _toint_ieee_T_25 : _toint_ieee_T_27; // @[package.scala:39:{76,86}] wire _toint_ieee_T_30 = &in_typeTagOut; // @[package.scala:39:86] wire [63:0] toint_ieee = _toint_ieee_T_30 ? _toint_ieee_T_25 : _toint_ieee_T_29; // @[package.scala:39:{76,86}] wire [63:0] toint; // @[FPU.scala:478:26] wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59] wire _intType_T = in_fmt[0]; // @[FPU.scala:466:21, :479:35] wire intType; // @[FPU.scala:479:28] wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN \| io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 \| _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN \| io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 \| _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded = {io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T = io_out_bits_store_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = io_out_bits_store_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = io_out_bits_store_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi = {_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded = {io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = io_out_bits_store_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN \| io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 \| _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T = io_out_bits_store_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_1 = io_out_bits_store_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_2 = &_io_out_bits_store_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_3 = io_out_bits_store_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_4 = _io_out_bits_store_prevUnrecoded_T_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded : _io_out_bits_store_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded = {_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[15:0]; // @[FPU.scala:446:10, :480:82] wire [31:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}] wire [63:0] _io_out_bits_store_T_8 = {2{_io_out_bits_store_T_7}}; // @[FPU.scala:480:49] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN \| io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 \| _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN \| io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 \| _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_1 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = io_out_bits_store_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = io_out_bits_store_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = io_out_bits_store_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_1 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN \| io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 \| _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_6 = io_out_bits_store_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_7 = &_io_out_bits_store_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_9 = _io_out_bits_store_prevUnrecoded_T_7 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_1 : _io_out_bits_store_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_1 = {_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_9 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_11 = &_io_out_bits_store_T_10; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_12 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_13 = _io_out_bits_store_T_11 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_12; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_14 = {_io_out_bits_store_T_9, _io_out_bits_store_T_13}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_15 = _io_out_bits_store_T_14[31:0]; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_16 = {2{_io_out_bits_store_T_15}}; // @[FPU.scala:480:{49,82}] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_2 = _io_out_bits_store_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_2_isZero = io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_2_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_2_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_2_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_2_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_2_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_4 = io_out_bits_store_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_2 = _io_out_bits_store_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_5 = _io_out_bits_store_unrecoded_denormFract_T_4 >> io_out_bits_store_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_2 = _io_out_bits_store_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_12 = io_out_bits_store_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_14 = _io_out_bits_store_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_15 = io_out_bits_store_unrecoded_isSubnormal_2 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_16 = io_out_bits_store_unrecoded_rawIn_2_isNaN \| io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_17 = {11{_io_out_bits_store_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_2 = _io_out_bits_store_unrecoded_expOut_T_15 \| _io_out_bits_store_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_5 = io_out_bits_store_unrecoded_rawIn_2_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_2 = io_out_bits_store_unrecoded_isSubnormal_2 ? io_out_bits_store_unrecoded_denormFract_2 : _io_out_bits_store_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_2 = {io_out_bits_store_unrecoded_rawIn_2_sign, io_out_bits_store_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_2 = {io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_2 = {_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_2 = {io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = io_out_bits_store_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevRecoded_2[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN \| io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 \| _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_2 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = io_out_bits_store_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = io_out_bits_store_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = io_out_bits_store_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_2 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN \| io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 \| _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_11 = io_out_bits_store_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_12 = &_io_out_bits_store_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_13 = io_out_bits_store_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_14 = _io_out_bits_store_prevUnrecoded_T_12 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_2 : _io_out_bits_store_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_2 = {_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_17 = io_out_bits_store_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_19 = &_io_out_bits_store_T_18; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_20 = io_out_bits_store_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_21 = _io_out_bits_store_T_19 ? io_out_bits_store_prevUnrecoded_2 : _io_out_bits_store_T_20; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_22 = {_io_out_bits_store_T_17, _io_out_bits_store_T_21}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _io_out_bits_store_T_23 = _io_out_bits_store_T_22; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_25 = _io_out_bits_store_T_24 ? _io_out_bits_store_T_16 : _io_out_bits_store_T_8; // @[package.scala:39:{76,86}] wire [63:0] _io_out_bits_store_T_27 = _io_out_bits_store_T_26 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_25; // @[package.scala:39:{76,86}] wire _io_out_bits_store_T_28 = &in_typeTagOut; // @[package.scala:39:86] assign _io_out_bits_store_T_29 = _io_out_bits_store_T_28 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_27; // @[package.scala:39:{76,86}] assign io_out_bits_store_0 = _io_out_bits_store_T_29; // @[package.scala:39:76] wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59] wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38] wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}] wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}] assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15] assign io_out_bits_toint_0 = _io_out_bits_toint_T_6; // @[package.scala:39:76] wire [62:0] _classify_out_fractOut_T = {classify_out_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] classify_out_fractOut = _classify_out_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_2 = _classify_out_expOut_T \| _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_1 = _classify_out_T[16]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code = _classify_out_T[15:13]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28] wire [3:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[13:10]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 4'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_1 = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_1 = _GEN_1; // @[FPU.scala:259:46] wire _classify_out_isNormal_T; // @[FPU.scala:260:27] assign _classify_out_isNormal_T = _GEN_1; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal = _classify_out_isSubnormal_T \| _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal = _classify_out_isNormal_T_2 \| _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}] wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8] wire [75:0] _classify_out_fractOut_T_1 = {classify_out_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] classify_out_fractOut_1 = _classify_out_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode_1 = classify_out_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T_3 = {1'h0, classify_out_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_4 = _classify_out_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_5 = {1'h0, _classify_out_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase_1 = _classify_out_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T_6 = classify_out_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_7 = classify_out_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_8 = _classify_out_expOut_T_6 \| _classify_out_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _classify_out_expOut_T_9 = classify_out_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _classify_out_expOut_T_10 = {classify_out_expOut_expCode_1, _classify_out_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _classify_out_expOut_T_11 = classify_out_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] classify_out_expOut_1 = _classify_out_expOut_T_8 ? _classify_out_expOut_T_10 : _classify_out_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] classify_out_hi_2 = {classify_out_sign_2, classify_out_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _classify_out_T_14 = {classify_out_hi_2, classify_out_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_3 = _classify_out_T_14[32]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code_1 = _classify_out_T_14[31:29]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28] wire [6:0] _classify_out_isHighSubnormalIn_T_1 = _classify_out_T_14[29:23]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 7'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_2 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_4 = _GEN_2; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_4 = _GEN_2; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 \| _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 \| _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_2 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T_1 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_15 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_16 = classify_out_isInf_1 & _classify_out_T_15; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_17 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_18 = classify_out_isNormal_1 & _classify_out_T_17; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_19 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_20 = classify_out_isSubnormal_1 & _classify_out_T_19; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_21 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_22 = classify_out_isZero_1 & _classify_out_T_21; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_23 = classify_out_isZero_1 & classify_out_sign_3; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_24 = classify_out_isSubnormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_25 = classify_out_isNormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_26 = classify_out_isInf_1 & classify_out_sign_3; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_25, _classify_out_T_26}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_22, _classify_out_T_23}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_24}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_18, _classify_out_T_20}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_16}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_3 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_27 = {classify_out_hi_3, classify_out_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_codeHi_2 = classify_out_code_2[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_2 = &classify_out_codeHi_2; // @[FPU.scala:255:22, :256:28] wire [9:0] _classify_out_isHighSubnormalIn_T_2 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21] wire classify_out_isHighSubnormalIn_2 = _classify_out_isHighSubnormalIn_T_2 < 10'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_6 = classify_out_code_2 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_3 = classify_out_codeHi_2 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_7; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_7 = _GEN_3; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_8; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_8 = _GEN_3; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_8 = _classify_out_isSubnormal_T_7 & classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_2 = _classify_out_isSubnormal_T_6 \| _classify_out_isSubnormal_T_8; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_9 = ~classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_10 = _classify_out_isNormal_T_8 & _classify_out_isNormal_T_9; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_11 = classify_out_codeHi_2 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_2 = _classify_out_isNormal_T_10 \| _classify_out_isNormal_T_11; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_2 = classify_out_code_2 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_4 = classify_out_code_2[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_5 = ~_classify_out_isInf_T_4; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_2 = classify_out_isSpecial_2 & _classify_out_isInf_T_5; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_2 = &classify_out_code_2; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_4 = in_in1[51]; // @[FPU.scala:264:29, :466:21] wire _classify_out_isQNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21] wire _classify_out_isSNaN_T_5 = ~_classify_out_isSNaN_T_4; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_2 = classify_out_isNaN_2 & _classify_out_isSNaN_T_5; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_2 = classify_out_isNaN_2 & _classify_out_isQNaN_T_2; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_28 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_29 = classify_out_isInf_2 & _classify_out_T_28; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_30 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_31 = classify_out_isNormal_2 & _classify_out_T_30; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_32 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_33 = classify_out_isSubnormal_2 & _classify_out_T_32; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_34 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_35 = classify_out_isZero_2 & _classify_out_T_34; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_36 = classify_out_isZero_2 & classify_out_sign_4; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_37 = classify_out_isSubnormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_38 = classify_out_isNormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_39 = classify_out_isInf_2 & classify_out_sign_4; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_2 = {_classify_out_T_38, _classify_out_T_39}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_2 = {_classify_out_T_35, _classify_out_T_36}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_2 = {classify_out_lo_hi_hi_2, _classify_out_T_37}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_2 = {classify_out_lo_hi_2, classify_out_lo_lo_2}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_2 = {_classify_out_T_31, _classify_out_T_33}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_2 = {classify_out_isQNaN_2, classify_out_isSNaN_2}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_2 = {classify_out_hi_hi_hi_2, _classify_out_T_29}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_4 = {classify_out_hi_hi_2, classify_out_hi_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_40 = {classify_out_hi_4, classify_out_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_42 = _classify_out_T_41 ? _classify_out_T_27 : _classify_out_T_13; // @[package.scala:39:{76,86}] wire [9:0] _classify_out_T_44 = _classify_out_T_43 ? _classify_out_T_40 : _classify_out_T_42; // @[package.scala:39:{76,86}] wire _classify_out_T_45 = &in_typeTagOut; // @[package.scala:39:86] wire [9:0] classify_out = _classify_out_T_45 ? _classify_out_T_40 : _classify_out_T_44; // @[package.scala:39:{76,86}] wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76] wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76] wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}] wire [63:0] _toint_T_2 = {54'h0, classify_out} \| _toint_T_1; // @[package.scala:39:76] wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15] wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27] wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}] wire _toint_T_6 = \|_toint_T_5; // @[FPU.scala:491:{22,53}] wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}] wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} \| _toint_T_8; // @[FPU.scala:491:{53,57,82}] wire cvtType = in_typ[1]; // @[package.scala:163:13] assign intType = in_wflags ? ~in_ren2 & cvtType : ~(in_rm[0]) & _intType_T; // @[package.scala:163:13] wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41] wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}] wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55] wire _io_out_bits_exc_T_1 = \|_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}] wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102] wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90] wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}] wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}] wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}] wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}] wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62] wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}] wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46] wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69] wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}] wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}] wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50] wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84] wire invalid = _invalid_T \| _invalid_T_1; // @[FPU.scala:515:{50,54,84}] wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53] wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}] assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13] wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53] wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}] wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33] wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}] assign io_out_bits_exc_0 = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13] wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}] wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}] wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}] assign _io_out_bits_lt_T_5 = _dcmp_io_lt \| _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}] assign io_out_bits_lt_0 = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid_0) begin // @[FPU.scala:453:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21] in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21] in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21] in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21] in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21] in_vec <= io_in_bits_vec_0; // @[FPU.scala:453:7, :466:21] in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:453:7, :466:21] in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:453:7, :466:21] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21] in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21] in_in3 <= io_in_bits_in3_0; // @[FPU.scala:453:7, :466:21] end valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22] always @(posedge) CompareRecFN_3 dcmp ( // @[FPU.scala:469:20] .io_a (in_in1), // @[FPU.scala:466:21] .io_b (in_in2), // @[FPU.scala:466:21] .io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24] .io_lt (_dcmp_io_lt), .io_eq (_dcmp_io_eq), .io_exceptionFlags (_dcmp_io_exceptionFlags) ); // @[FPU.scala:469:20] RecFNToIN_e11_s53_i64_3 conv ( // @[FPU.scala:498:24] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28] .io_out (_conv_io_out), .io_intExceptionFlags (_conv_io_intExceptionFlags) ); // @[FPU.scala:498:24] RecFNToIN_e11_s53_i32_3 narrow ( // @[FPU.scala:508:30] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34] .io_intExceptionFlags (_narrow_io_intExceptionFlags) ); // @[FPU.scala:508:30] assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7] assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7] assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7] assign io_out_bits_lt = io_out_bits_lt_0; // @[FPU.scala:453:7] assign io_out_bits_store = io_out_bits_store_0; // @[FPU.scala:453:7] assign io_out_bits_toint = io_out_bits_toint_0; // @[FPU.scala:453:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:453:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget16 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_3 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a29d128s6k1z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 127, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<4>(0hf), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 3, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 3, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) wire repeat_anonOut_a_bits_data_mux : UInt<64>[2] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[2] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<4>(0hf), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 3, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<1>, clock, reset, UInt<1>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[1], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLWidthWidget16( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [15:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71] wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T \| _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24] wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24] wire repeat_sel = cated_bits_address[3]; // @[WidthWidget.scala:116:39, :161:25] wire repeat_index = repeat_sel \| repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [18:0] _limit_T = 19'hF << anonOut_d_bits_size; // @[package.scala:243:71] wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire limit = _limit_T_2[3]; // @[package.scala:243:46] reg count; // @[WidthWidget.scala:40:27] wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = ~count; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T \| _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56] wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt \| corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24] wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready \| _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 \| _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 \| _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 \| anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] always @(posedge) TLMonitor_3 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a29d128s6k1z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_104 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_4.bits.sink, UInt<5>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_248 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_249 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_104( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SBToTL : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} input rf_reset : Reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset sbState : UInt, clock, reset, UInt<1>(0h0) inst d_q of Queue2_TLBundleD_a32d8s1k3z4u connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect d_q.io.enq.bits.data, nodeOut.d.bits.data connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect d_q.io.enq.bits.source, nodeOut.d.bits.source connect d_q.io.enq.bits.size, nodeOut.d.bits.size connect d_q.io.enq.bits.param, nodeOut.d.bits.param connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, d_q.io.enq.ready node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 wire muxedData : UInt<8> connect muxedData, UInt<8>(0h0) regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) wire vecData : UInt<8>[8] node _vecData_0_T = bits(io.dataIn, 7, 0) connect vecData[0], _vecData_0_T node _vecData_1_T = bits(io.dataIn, 15, 8) connect vecData[1], _vecData_1_T node _vecData_2_T = bits(io.dataIn, 23, 16) connect vecData[2], _vecData_2_T node _vecData_3_T = bits(io.dataIn, 31, 24) connect vecData[3], _vecData_3_T node _vecData_4_T = bits(io.dataIn, 39, 32) connect vecData[4], _vecData_4_T node _vecData_5_T = bits(io.dataIn, 47, 40) connect vecData[5], _vecData_5_T node _vecData_6_T = bits(io.dataIn, 55, 48) connect vecData[6], _vecData_6_T node _vecData_7_T = bits(io.dataIn, 63, 56) connect vecData[7], _vecData_7_T node _muxedData_T = bits(counter, 2, 0) connect muxedData, vecData[_muxedData_T] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2400)) node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<9>(0h100))) node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<18>(0h2f000))) node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<28>(0hc000000)) node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44) node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<27>(0h4000000))) node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46) node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<29>(0h10020000)) node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49) node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51) node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _rdLegal_addr_T_55 = cvt(_rdLegal_addr_T_54) node _rdLegal_addr_T_56 = and(_rdLegal_addr_T_55, asSInt(UInt<29>(0h10000000))) node _rdLegal_addr_T_57 = asSInt(_rdLegal_addr_T_56) node _rdLegal_addr_T_58 = eq(_rdLegal_addr_T_57, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_59 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) node _rdLegal_addr_T_60 = or(_rdLegal_addr_T_59, _rdLegal_addr_T_18) node _rdLegal_addr_T_61 = or(_rdLegal_addr_T_60, _rdLegal_addr_T_23) node _rdLegal_addr_T_62 = or(_rdLegal_addr_T_61, _rdLegal_addr_T_28) node _rdLegal_addr_T_63 = or(_rdLegal_addr_T_62, _rdLegal_addr_T_33) node _rdLegal_addr_T_64 = or(_rdLegal_addr_T_63, _rdLegal_addr_T_38) node _rdLegal_addr_T_65 = or(_rdLegal_addr_T_64, _rdLegal_addr_T_43) node _rdLegal_addr_T_66 = or(_rdLegal_addr_T_65, _rdLegal_addr_T_48) node _rdLegal_addr_T_67 = or(_rdLegal_addr_T_66, _rdLegal_addr_T_53) node _rdLegal_addr_T_68 = or(_rdLegal_addr_T_67, _rdLegal_addr_T_58) node _rdLegal_addr_T_69 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_68) node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_69) node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2400)) node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<9>(0h100))) node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<18>(0h2f000))) node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2010000)) node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0hc000000)) node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39) node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<27>(0h4000000))) node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41) node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h10020000)) node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44) node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46) node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) node _wrLegal_addr_T_50 = cvt(_wrLegal_addr_T_49) node _wrLegal_addr_T_51 = and(_wrLegal_addr_T_50, asSInt(UInt<29>(0h10000000))) node _wrLegal_addr_T_52 = asSInt(_wrLegal_addr_T_51) node _wrLegal_addr_T_53 = eq(_wrLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_54 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) node _wrLegal_addr_T_55 = or(_wrLegal_addr_T_54, _wrLegal_addr_T_18) node _wrLegal_addr_T_56 = or(_wrLegal_addr_T_55, _wrLegal_addr_T_23) node _wrLegal_addr_T_57 = or(_wrLegal_addr_T_56, _wrLegal_addr_T_28) node _wrLegal_addr_T_58 = or(_wrLegal_addr_T_57, _wrLegal_addr_T_33) node _wrLegal_addr_T_59 = or(_wrLegal_addr_T_58, _wrLegal_addr_T_38) node _wrLegal_addr_T_60 = or(_wrLegal_addr_T_59, _wrLegal_addr_T_43) node _wrLegal_addr_T_61 = or(_wrLegal_addr_T_60, _wrLegal_addr_T_48) node _wrLegal_addr_T_62 = or(_wrLegal_addr_T_61, _wrLegal_addr_T_53) node _wrLegal_addr_T_63 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_62) node _wrLegal_addr_T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) node _wrLegal_addr_T_65 = xor(io.addrIn, UInt<17>(0h10000)) node _wrLegal_addr_T_66 = cvt(_wrLegal_addr_T_65) node _wrLegal_addr_T_67 = and(_wrLegal_addr_T_66, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_68 = asSInt(_wrLegal_addr_T_67) node _wrLegal_addr_T_69 = eq(_wrLegal_addr_T_68, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_70 = and(_wrLegal_addr_T_64, _wrLegal_addr_T_69) node _wrLegal_addr_T_71 = or(UInt<1>(0h0), _wrLegal_addr_T_63) node wrLegal_addr = or(_wrLegal_addr_T_71, _wrLegal_addr_T_70) node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) node _gbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) node _gbits_legal_T_24 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h98013000))) node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) node _gbits_legal_T_29 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) node _gbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2000000)) node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) node _gbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) node _gbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_45 = cvt(_gbits_legal_T_44) node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46) node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0))) node _gbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _gbits_legal_T_50 = cvt(_gbits_legal_T_49) node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51) node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0))) node _gbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _gbits_legal_T_55 = cvt(_gbits_legal_T_54) node _gbits_legal_T_56 = and(_gbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _gbits_legal_T_57 = asSInt(_gbits_legal_T_56) node _gbits_legal_T_58 = eq(_gbits_legal_T_57, asSInt(UInt<1>(0h0))) node _gbits_legal_T_59 = or(_gbits_legal_T_18, _gbits_legal_T_23) node _gbits_legal_T_60 = or(_gbits_legal_T_59, _gbits_legal_T_28) node _gbits_legal_T_61 = or(_gbits_legal_T_60, _gbits_legal_T_33) node _gbits_legal_T_62 = or(_gbits_legal_T_61, _gbits_legal_T_38) node _gbits_legal_T_63 = or(_gbits_legal_T_62, _gbits_legal_T_43) node _gbits_legal_T_64 = or(_gbits_legal_T_63, _gbits_legal_T_48) node _gbits_legal_T_65 = or(_gbits_legal_T_64, _gbits_legal_T_53) node _gbits_legal_T_66 = or(_gbits_legal_T_65, _gbits_legal_T_58) node _gbits_legal_T_67 = and(_gbits_legal_T_13, _gbits_legal_T_66) node _gbits_legal_T_68 = or(UInt<1>(0h0), _gbits_legal_T_9) node gbits_legal = or(_gbits_legal_T_68, _gbits_legal_T_67) wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect gbits.opcode, UInt<3>(0h4) connect gbits.param, UInt<1>(0h0) connect gbits.size, io.sizeIn connect gbits.source, UInt<1>(0h0) connect gbits.address, io.addrIn node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect gbits.mask, UInt<1>(0h1) invalidate gbits.data connect gbits.corrupt, UInt<1>(0h0) node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h9a103000))) node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39) node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41) node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44) node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46) node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _pfbits_legal_T_50 = cvt(_pfbits_legal_T_49) node _pfbits_legal_T_51 = and(_pfbits_legal_T_50, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_52 = asSInt(_pfbits_legal_T_51) node _pfbits_legal_T_53 = eq(_pfbits_legal_T_52, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _pfbits_legal_T_55 = cvt(_pfbits_legal_T_54) node _pfbits_legal_T_56 = and(_pfbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _pfbits_legal_T_57 = asSInt(_pfbits_legal_T_56) node _pfbits_legal_T_58 = eq(_pfbits_legal_T_57, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_59 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) node _pfbits_legal_T_60 = or(_pfbits_legal_T_59, _pfbits_legal_T_28) node _pfbits_legal_T_61 = or(_pfbits_legal_T_60, _pfbits_legal_T_33) node _pfbits_legal_T_62 = or(_pfbits_legal_T_61, _pfbits_legal_T_38) node _pfbits_legal_T_63 = or(_pfbits_legal_T_62, _pfbits_legal_T_43) node _pfbits_legal_T_64 = or(_pfbits_legal_T_63, _pfbits_legal_T_48) node _pfbits_legal_T_65 = or(_pfbits_legal_T_64, _pfbits_legal_T_53) node _pfbits_legal_T_66 = or(_pfbits_legal_T_65, _pfbits_legal_T_58) node _pfbits_legal_T_67 = and(_pfbits_legal_T_13, _pfbits_legal_T_66) node _pfbits_legal_T_68 = or(UInt<1>(0h0), UInt<1>(0h0)) node _pfbits_legal_T_69 = xor(io.addrIn, UInt<17>(0h10000)) node _pfbits_legal_T_70 = cvt(_pfbits_legal_T_69) node _pfbits_legal_T_71 = and(_pfbits_legal_T_70, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_72 = asSInt(_pfbits_legal_T_71) node _pfbits_legal_T_73 = eq(_pfbits_legal_T_72, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_74 = and(_pfbits_legal_T_68, _pfbits_legal_T_73) node _pfbits_legal_T_75 = or(UInt<1>(0h0), _pfbits_legal_T_9) node _pfbits_legal_T_76 = or(_pfbits_legal_T_75, _pfbits_legal_T_67) node pfbits_legal = or(_pfbits_legal_T_76, _pfbits_legal_T_74) wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect pfbits.opcode, UInt<1>(0h0) connect pfbits.param, UInt<1>(0h0) connect pfbits.size, io.sizeIn connect pfbits.source, UInt<1>(0h0) connect pfbits.address, io.addrIn node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect pfbits.mask, UInt<1>(0h1) connect pfbits.data, muxedData connect pfbits.corrupt, UInt<1>(0h0) connect io.rdLegal, rdLegal_addr connect io.wrLegal, wrLegal_addr connect io.sbStateOut, sbState node _T = eq(sbState, UInt<1>(0h1)) when _T : connect nodeOut.a.bits, gbits else : connect nodeOut.a.bits, pfbits node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) connect io.respError, respError node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) node _txLast_T_2 = tail(_txLast_T_1, 1) node txLast = eq(counter, _txLast_T_2) node _counter_T = or(wrTxValid, rdTxValid) node _counter_T_1 = and(_counter_T, txLast) node _counter_T_2 = or(wrTxValid, rdTxValid) node _counter_T_3 = add(counter, UInt<1>(0h1)) node _counter_T_4 = tail(_counter_T_3, 1) node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) connect counter, _counter_T_6 node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) connect io.rdLoad[0], _io_rdLoad_0_T_1 node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) connect io.rdLoad[1], _io_rdLoad_1_T_1 node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) connect io.rdLoad[2], _io_rdLoad_2_T_1 node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) connect io.rdLoad[3], _io_rdLoad_3_T_1 node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) connect io.rdLoad[4], _io_rdLoad_4_T_1 node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) connect io.rdLoad[5], _io_rdLoad_5_T_1 node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) connect io.rdLoad[6], _io_rdLoad_6_T_1 node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) connect io.rdLoad[7], _io_rdLoad_7_T_1 node _T_1 = eq(sbState, UInt<1>(0h0)) when _T_1 : node _sbState_T = and(io.rdEn, io.rdLegal) node _sbState_T_1 = and(io.wrEn, io.wrLegal) node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) connect sbState, _sbState_T_3 else : node _T_2 = eq(sbState, UInt<1>(0h1)) when _T_2 : node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) connect sbState, _sbState_T_5 else : node _T_3 = eq(sbState, UInt<2>(0h2)) when _T_3 : node _sbState_T_6 = and(wrTxValid, txLast) node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) connect sbState, _sbState_T_7 else : node _T_4 = eq(sbState, UInt<2>(0h3)) when _T_4 : node _sbState_T_8 = and(rdTxValid, txLast) node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) connect sbState, _sbState_T_9 else : node _T_5 = eq(sbState, UInt<3>(0h4)) when _T_5 : node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) connect sbState, _sbState_T_11 node _io_rdDone_T = and(rdTxValid, txLast) connect io.rdDone, _io_rdDone_T node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) connect io.wrDone, _io_wrDone_T_2 connect io.dataOut, d_q.io.deq.bits.data node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T_6 = eq(sbState, UInt<1>(0h0)) node _T_7 = eq(sbState, UInt<1>(0h1)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(sbState, UInt<2>(0h2)) node _T_10 = or(_T_8, _T_9) node _T_11 = eq(sbState, UInt<2>(0h3)) node _T_12 = or(_T_10, _T_11) node _T_13 = eq(sbState, UInt<3>(0h4)) node _T_14 = or(_T_12, _T_13) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U \|\|\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert node _T_18 = eq(sbState, UInt<1>(0h0)) node _T_19 = eq(sbState, UInt<1>(0h1)) node _T_20 = eq(sbState, UInt<2>(0h2)) node _T_21 = eq(sbState, UInt<2>(0h3)) node _T_22 = eq(sbState, UInt<3>(0h4)) node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) node _T_24 = and(io.rdEn, _T_23) node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) node _T_26 = and(io.wrEn, _T_25) extmodule plusarg_reader_97 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module SBToTL( // @[SBA.scala:273:9] input clock, // @[SBA.scala:273:9] input reset, // @[SBA.scala:273:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_rdEn, // @[SBA.scala:274:16] input io_wrEn, // @[SBA.scala:274:16] input [127:0] io_addrIn, // @[SBA.scala:274:16] input [127:0] io_dataIn, // @[SBA.scala:274:16] input [2:0] io_sizeIn, // @[SBA.scala:274:16] output io_rdLegal, // @[SBA.scala:274:16] output io_wrLegal, // @[SBA.scala:274:16] output io_rdDone, // @[SBA.scala:274:16] output io_wrDone, // @[SBA.scala:274:16] output io_respError, // @[SBA.scala:274:16] output [7:0] io_dataOut, // @[SBA.scala:274:16] output io_rdLoad_0, // @[SBA.scala:274:16] output io_rdLoad_1, // @[SBA.scala:274:16] output io_rdLoad_2, // @[SBA.scala:274:16] output io_rdLoad_3, // @[SBA.scala:274:16] output io_rdLoad_4, // @[SBA.scala:274:16] output io_rdLoad_5, // @[SBA.scala:274:16] output io_rdLoad_6, // @[SBA.scala:274:16] output io_rdLoad_7, // @[SBA.scala:274:16] output [2:0] io_sbStateOut // @[SBA.scala:274:16] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] reg [2:0] sbState; // @[SBA.scala:295:26] wire _rdTxValid_T = sbState == 3'h3; // @[SBA.scala:295:26, :299:25] wire _io_wrDone_T = sbState == 3'h4; // @[SBA.scala:295:26, :299:62] wire d_q_io_deq_ready = _rdTxValid_T \| _io_wrDone_T; // @[SBA.scala:299:{25,50,62}] reg [3:0] counter; // @[SBA.scala:307:26] wire [7:0][7:0] _GEN = {{io_dataIn[63:56]}, {io_dataIn[55:48]}, {io_dataIn[47:40]}, {io_dataIn[39:32]}, {io_dataIn[31:24]}, {io_dataIn[23:16]}, {io_dataIn[15:8]}, {io_dataIn[7:0]}}; // @[SBA.scala:309:63, :310:15] wire [119:0] _GEN_0 = {io_addrIn[127:14], io_addrIn[13:8] ^ 6'h24}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_1 = {io_addrIn[127:14], ~(io_addrIn[13:12])}; // @[Parameters.scala:137:{31,41,46}] wire [114:0] _GEN_2 = {io_addrIn[127:21], io_addrIn[20:17] ^ 4'h8, io_addrIn[15:12]}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_3 = {io_addrIn[127:26], io_addrIn[25:16] ^ 10'h200}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_4 = {io_addrIn[127:26], io_addrIn[25:12] ^ 14'h2010}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_5 = {io_addrIn[127:28], io_addrIn[27:16] ^ 12'h800}; // @[Parameters.scala:137:{31,41,46}] wire [101:0] _GEN_6 = {io_addrIn[127:28], ~(io_addrIn[27:26])}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_7 = {io_addrIn[127:29], io_addrIn[28:12] ^ 17'h10020}; // @[Parameters.scala:137:{31,41,46}] wire [99:0] _GEN_8 = {io_addrIn[127:32], io_addrIn[31:28] ^ 4'h8}; // @[Parameters.scala:137:{31,41,46}] wire io_rdLegal_0 = ~(\|(io_addrIn[127:13])) \| ~(\|_GEN_0) \| ~(\|_GEN_1) \| {io_addrIn[127:17], ~(io_addrIn[16])} == 112'h0 \| ~(\|_GEN_2) \| ~(\|_GEN_3) \| ~(\|_GEN_4) \| ~(\|_GEN_5) \| ~(\|_GEN_6) \| ~(\|_GEN_7) \| ~(\|_GEN_8); // @[Parameters.scala:685:42] wire io_wrLegal_0 = ~(\|(io_addrIn[127:13])) \| ~(\|_GEN_0) \| ~(\|_GEN_1) \| ~(\|_GEN_2) \| ~(\|_GEN_3) \| ~(\|_GEN_4) \| ~(\|_GEN_5) \| ~(\|_GEN_6) \| ~(\|_GEN_7) \| ~(\|_GEN_8); // @[Parameters.scala:685:42] wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18] wire _nodeOut_a_valid_T_1 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29] wire rdTxValid = _rdTxValid_T & _d_q_io_deq_valid & d_q_io_deq_ready; // @[Decoupled.scala:362:21] wire txLast = {4'h0, counter} == (8'h1 << io_sizeIn) - 8'h1; // @[SBA.scala:307:26, :340:{29,39,53}] wire _GEN_9 = sbState == 3'h0; // @[SBA.scala:295:26, :349:19] wire nodeOut_a_valid = _nodeOut_a_valid_T \| _nodeOut_a_valid_T_1; // @[SBA.scala:322:18, :338:29, :366:52]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_211 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_211( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_174 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_189 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_174( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_189 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_24 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_25 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_65 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_65( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_6 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 1, 0) node _req_clientBit_T = shr(request.source, 2) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0ha)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<2>(0h2)) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 1, 0) node _req_clientBit_T_6 = shr(request.source, 2) node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<4>(0h8)) node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8) node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<2>(0h2)) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 1, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 2) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0ha)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<2>(0h2)) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 1, 0) node _probe_bit_T_6 = shr(io.sinkc.bits.source, 2) node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<4>(0h8)) node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8) node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<2>(0h2)) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 1, 0) node _new_clientBit_T = shr(new_request.source, 2) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0ha)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<2>(0h2)) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 1, 0) node _new_clientBit_T_6 = shr(new_request.source, 2) node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<4>(0h8)) node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8) node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<2>(0h2)) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_6( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53] wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [5:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [5:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_6 = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = _req_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_6 = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = _probe_bit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [5:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_6 = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = _new_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_55 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_55( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_4 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_4 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_4 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id) when _T_11 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) node _T_12 = eq(UInt<2>(0h3), io.in.flit[0].bits.flow.egress_node_id) when _T_12 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) node _T_13 = eq(UInt<3>(0h4), io.in.flit[0].bits.flow.egress_node_id) when _T_13 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_14 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_14 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_15 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_15 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_16 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_16 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_17 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_17 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_18 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_18 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_19 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_19 : connect states[5].g, UInt<3>(0h2) connect route_arbiter.io.in[6].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[6].bits.flow.egress_node_id invalidate route_arbiter.io.in[6].bits.flow.egress_node invalidate route_arbiter.io.in[6].bits.flow.ingress_node_id invalidate route_arbiter.io.in[6].bits.flow.ingress_node invalidate route_arbiter.io.in[6].bits.flow.vnet_id invalidate route_arbiter.io.in[6].bits.src_virt_id connect route_arbiter.io.in[7].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[7].bits.flow.egress_node_id invalidate route_arbiter.io.in[7].bits.flow.egress_node invalidate route_arbiter.io.in[7].bits.flow.ingress_node_id invalidate route_arbiter.io.in[7].bits.flow.ingress_node invalidate route_arbiter.io.in[7].bits.flow.vnet_id invalidate route_arbiter.io.in[7].bits.src_virt_id node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_20 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_20 : connect states[8].g, UInt<3>(0h2) node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1)) connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9) node _T_21 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid) when _T_21 : connect states[9].g, UInt<3>(0h2) node _T_22 = and(io.router_req.ready, io.router_req.valid) when _T_22 : node _T_23 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_23, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_27 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_27 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_28 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_28 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_29 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_29 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_30 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_30 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[3].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_31 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_31 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[4].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_32 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_32 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[5].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_33 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_33 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[6].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_34 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_34 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[7].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_35 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_35 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[8].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[8].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[8].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_36 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_36 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[9].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[9].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[9].vc_sel.`5`, io.router_resp.vc_sel.`5` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_37 = and(io.router_req.ready, io.router_req.valid) when _T_37 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_38 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_39 = or(_T_38, vcalloc_vals[2]) node _T_40 = or(_T_39, vcalloc_vals[3]) node _T_41 = or(_T_40, vcalloc_vals[4]) node _T_42 = or(_T_41, vcalloc_vals[5]) node _T_43 = or(_T_42, vcalloc_vals[6]) node _T_44 = or(_T_43, vcalloc_vals[7]) node _T_45 = or(_T_44, vcalloc_vals[8]) node _T_46 = or(_T_45, vcalloc_vals[9]) when _T_46 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>[1] node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_15[0], _io_vcalloc_req_bits_WIRE_16 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_15 wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>[1] node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_17[0], _io_vcalloc_req_bits_WIRE_18 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_17 wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>[1] node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_20 : UInt<1> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_19[0], _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_19 wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>[1] node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_21[0], _io_vcalloc_req_bits_WIRE_22 connect _io_vcalloc_req_bits_WIRE_1.`5`, _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_23 : UInt<4> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_23 wire _io_vcalloc_req_bits_WIRE_24 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_25 : UInt<3> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_24.egress_node_id, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_26 : UInt<4> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_24.egress_node, _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_27 : UInt<3> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_24.ingress_node_id, _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375) node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376) node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377) node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378) node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379) node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380) wire _io_vcalloc_req_bits_WIRE_28 : UInt<4> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_389 connect _io_vcalloc_req_bits_WIRE_24.ingress_node, _io_vcalloc_req_bits_WIRE_28 node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391) node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392) node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393) node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394) node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395) node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399) wire _io_vcalloc_req_bits_WIRE_29 : UInt<3> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_408 connect _io_vcalloc_req_bits_WIRE_24.vnet_id, _io_vcalloc_req_bits_WIRE_29 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_24 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].vc_sel.`5`, states[0].vc_sel.`5` connect vcalloc_reqs[0].flow, states[0].flow node _T_47 = bits(vcalloc_sel, 0, 0) node _T_48 = and(vcalloc_vals[0], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, states[1].vc_sel.`5` connect vcalloc_reqs[1].flow, states[1].flow node _T_50 = bits(vcalloc_sel, 1, 1) node _T_51 = and(vcalloc_vals[1], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, states[2].vc_sel.`5` connect vcalloc_reqs[2].flow, states[2].flow node _T_53 = bits(vcalloc_sel, 2, 2) node _T_54 = and(vcalloc_vals[2], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].vc_sel.`4`, states[3].vc_sel.`4` connect vcalloc_reqs[3].vc_sel.`5`, states[3].vc_sel.`5` connect vcalloc_reqs[3].flow, states[3].flow node _T_56 = bits(vcalloc_sel, 3, 3) node _T_57 = and(vcalloc_vals[3], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].vc_sel.`4`, states[4].vc_sel.`4` connect vcalloc_reqs[4].vc_sel.`5`, states[4].vc_sel.`5` connect vcalloc_reqs[4].flow, states[4].flow node _T_59 = bits(vcalloc_sel, 4, 4) node _T_60 = and(vcalloc_vals[4], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].vc_sel.`4`, states[5].vc_sel.`4` connect vcalloc_reqs[5].vc_sel.`5`, states[5].vc_sel.`5` connect vcalloc_reqs[5].flow, states[5].flow node _T_62 = bits(vcalloc_sel, 5, 5) node _T_63 = and(vcalloc_vals[5], _T_62) node _T_64 = and(_T_63, io.vcalloc_req.ready) when _T_64 : connect states[5].g, UInt<3>(0h3) connect vcalloc_vals[6], UInt<1>(0h0) invalidate vcalloc_reqs[6].vc_sel.`0`[0] invalidate vcalloc_reqs[6].vc_sel.`0`[1] invalidate vcalloc_reqs[6].vc_sel.`0`[2] invalidate vcalloc_reqs[6].vc_sel.`0`[3] invalidate vcalloc_reqs[6].vc_sel.`0`[4] invalidate vcalloc_reqs[6].vc_sel.`0`[5] invalidate vcalloc_reqs[6].vc_sel.`0`[6] invalidate vcalloc_reqs[6].vc_sel.`0`[7] invalidate vcalloc_reqs[6].vc_sel.`0`[8] invalidate vcalloc_reqs[6].vc_sel.`0`[9] invalidate vcalloc_reqs[6].vc_sel.`1`[0] invalidate vcalloc_reqs[6].vc_sel.`2`[0] invalidate vcalloc_reqs[6].vc_sel.`3`[0] invalidate vcalloc_reqs[6].vc_sel.`4`[0] invalidate vcalloc_reqs[6].vc_sel.`5`[0] invalidate vcalloc_reqs[6].in_vc invalidate vcalloc_reqs[6].flow.egress_node_id invalidate vcalloc_reqs[6].flow.egress_node invalidate vcalloc_reqs[6].flow.ingress_node_id invalidate vcalloc_reqs[6].flow.ingress_node invalidate vcalloc_reqs[6].flow.vnet_id connect vcalloc_vals[7], UInt<1>(0h0) invalidate vcalloc_reqs[7].vc_sel.`0`[0] invalidate vcalloc_reqs[7].vc_sel.`0`[1] invalidate vcalloc_reqs[7].vc_sel.`0`[2] invalidate vcalloc_reqs[7].vc_sel.`0`[3] invalidate vcalloc_reqs[7].vc_sel.`0`[4] invalidate vcalloc_reqs[7].vc_sel.`0`[5] invalidate vcalloc_reqs[7].vc_sel.`0`[6] invalidate vcalloc_reqs[7].vc_sel.`0`[7] invalidate vcalloc_reqs[7].vc_sel.`0`[8] invalidate vcalloc_reqs[7].vc_sel.`0`[9] invalidate vcalloc_reqs[7].vc_sel.`1`[0] invalidate vcalloc_reqs[7].vc_sel.`2`[0] invalidate vcalloc_reqs[7].vc_sel.`3`[0] invalidate vcalloc_reqs[7].vc_sel.`4`[0] invalidate vcalloc_reqs[7].vc_sel.`5`[0] invalidate vcalloc_reqs[7].in_vc invalidate vcalloc_reqs[7].flow.egress_node_id invalidate vcalloc_reqs[7].flow.egress_node invalidate vcalloc_reqs[7].flow.ingress_node_id invalidate vcalloc_reqs[7].flow.ingress_node invalidate vcalloc_reqs[7].flow.vnet_id node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].vc_sel.`3`, states[8].vc_sel.`3` connect vcalloc_reqs[8].vc_sel.`4`, states[8].vc_sel.`4` connect vcalloc_reqs[8].vc_sel.`5`, states[8].vc_sel.`5` connect vcalloc_reqs[8].flow, states[8].flow node _T_65 = bits(vcalloc_sel, 8, 8) node _T_66 = and(vcalloc_vals[8], _T_65) node _T_67 = and(_T_66, io.vcalloc_req.ready) when _T_67 : connect states[8].g, UInt<3>(0h3) node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2)) node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1) connect vcalloc_vals[9], _vcalloc_vals_9_T_2 connect vcalloc_reqs[9].in_vc, UInt<4>(0h9) connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0` connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1` connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2` connect vcalloc_reqs[9].vc_sel.`3`, states[9].vc_sel.`3` connect vcalloc_reqs[9].vc_sel.`4`, states[9].vc_sel.`4` connect vcalloc_reqs[9].vc_sel.`5`, states[9].vc_sel.`5` connect vcalloc_reqs[9].flow, states[9].flow node _T_68 = bits(vcalloc_sel, 9, 9) node _T_69 = and(vcalloc_vals[9], _T_68) node _T_70 = and(_T_69, io.vcalloc_req.ready) when _T_70 : connect states[9].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_71 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_71 : node _T_72 = bits(vcalloc_sel, 0, 0) when _T_72 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[0].g, UInt<3>(0h3) node _T_73 = eq(states[0].g, UInt<3>(0h2)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_73, UInt<1>(0h1), "") : assert_3 node _T_77 = bits(vcalloc_sel, 1, 1) when _T_77 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[1].g, UInt<3>(0h3) node _T_78 = eq(states[1].g, UInt<3>(0h2)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_78, UInt<1>(0h1), "") : assert_4 node _T_82 = bits(vcalloc_sel, 2, 2) when _T_82 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[2].g, UInt<3>(0h3) node _T_83 = eq(states[2].g, UInt<3>(0h2)) node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : node _T_86 = eq(_T_83, UInt<1>(0h0)) when _T_86 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_83, UInt<1>(0h1), "") : assert_5 node _T_87 = bits(vcalloc_sel, 3, 3) when _T_87 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[3].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[3].g, UInt<3>(0h3) node _T_88 = eq(states[3].g, UInt<3>(0h2)) node _T_89 = asUInt(reset) node _T_90 = eq(_T_89, UInt<1>(0h0)) when _T_90 : node _T_91 = eq(_T_88, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_88, UInt<1>(0h1), "") : assert_6 node _T_92 = bits(vcalloc_sel, 4, 4) when _T_92 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[4].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[4].g, UInt<3>(0h3) node _T_93 = eq(states[4].g, UInt<3>(0h2)) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_93, UInt<1>(0h1), "") : assert_7 node _T_97 = bits(vcalloc_sel, 5, 5) when _T_97 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[5].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[5].g, UInt<3>(0h3) node _T_98 = eq(states[5].g, UInt<3>(0h2)) node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(_T_98, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_98, UInt<1>(0h1), "") : assert_8 node _T_102 = bits(vcalloc_sel, 6, 6) when _T_102 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[6].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[6].g, UInt<3>(0h3) node _T_103 = eq(states[6].g, UInt<3>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_103, UInt<1>(0h1), "") : assert_9 node _T_107 = bits(vcalloc_sel, 7, 7) when _T_107 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[7].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[7].g, UInt<3>(0h3) node _T_108 = eq(states[7].g, UInt<3>(0h2)) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_108, UInt<1>(0h1), "") : assert_10 node _T_112 = bits(vcalloc_sel, 8, 8) when _T_112 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[8].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[8].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[8].g, UInt<3>(0h3) node _T_113 = eq(states[8].g, UInt<3>(0h2)) node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : node _T_116 = eq(_T_113, UInt<1>(0h0)) when _T_116 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_113, UInt<1>(0h1), "") : assert_11 node _T_117 = bits(vcalloc_sel, 9, 9) when _T_117 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[9].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[9].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[9].g, UInt<3>(0h3) node _T_118 = eq(states[9].g, UInt<3>(0h2)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_118, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_16 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[0].vc_sel.`0`[4], states[0].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[0].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[0].vc_sel.`0`[6], states[0].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[0].vc_sel.`0`[9], states[0].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[0].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_hi_1 = cat(states[0].vc_sel.`2`[0], states[0].vc_sel.`1`[0]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, _credit_available_T) node credit_available_hi_hi_1 = cat(states[0].vc_sel.`5`[0], states[0].vc_sel.`4`[0]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[0].vc_sel.`3`[0]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_1, io.out_credit_available.`0`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_1, io.out_credit_available.`0`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_1) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, _credit_available_T_2) node credit_available_hi_hi_3 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`3`[0]) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] connect salloc_arb.io.in[0].bits.vc_sel.`0`[8], states[0].vc_sel.`0`[8] connect salloc_arb.io.in[0].bits.vc_sel.`0`[9], states[0].vc_sel.`0`[9] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`5`[0], states[0].vc_sel.`5`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_122 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_123 = and(_T_122, input_buffer.io.deq[0].bits.tail) when _T_123 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_lo_2 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi_hi_2 = cat(states[1].vc_sel.`0`[4], states[1].vc_sel.`0`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_2, states[1].vc_sel.`0`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`0`[6], states[1].vc_sel.`0`[5]) node credit_available_hi_hi_hi_2 = cat(states[1].vc_sel.`0`[9], states[1].vc_sel.`0`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_2, states[1].vc_sel.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, credit_available_hi_lo_2) node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_hi_5 = cat(states[1].vc_sel.`2`[0], states[1].vc_sel.`1`[0]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, _credit_available_T_5) node credit_available_hi_hi_5 = cat(states[1].vc_sel.`5`[0], states[1].vc_sel.`4`[0]) node credit_available_hi_5 = cat(credit_available_hi_hi_5, states[1].vc_sel.`3`[0]) node _credit_available_T_6 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, credit_available_hi_lo_3) node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_hi_7 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, _credit_available_T_7) node credit_available_hi_hi_7 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, io.out_credit_available.`3`[0]) node _credit_available_T_8 = cat(credit_available_hi_7, credit_available_lo_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`0`[8], states[1].vc_sel.`0`[8] connect salloc_arb.io.in[1].bits.vc_sel.`0`[9], states[1].vc_sel.`0`[9] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`5`[0], states[1].vc_sel.`5`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_124 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_125 = and(_T_124, input_buffer.io.deq[1].bits.tail) when _T_125 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_4 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_hi_4 = cat(states[2].vc_sel.`0`[4], states[2].vc_sel.`0`[3]) node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_4, states[2].vc_sel.`0`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[2].vc_sel.`0`[6], states[2].vc_sel.`0`[5]) node credit_available_hi_hi_hi_4 = cat(states[2].vc_sel.`0`[9], states[2].vc_sel.`0`[8]) node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_4, states[2].vc_sel.`0`[7]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, credit_available_hi_lo_4) node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_hi_9 = cat(states[2].vc_sel.`2`[0], states[2].vc_sel.`1`[0]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, _credit_available_T_10) node credit_available_hi_hi_9 = cat(states[2].vc_sel.`5`[0], states[2].vc_sel.`4`[0]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, states[2].vc_sel.`3`[0]) node _credit_available_T_11 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`0`[7]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, credit_available_hi_lo_5) node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_hi_11 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, _credit_available_T_12) node credit_available_hi_hi_11 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_11 = cat(credit_available_hi_hi_11, io.out_credit_available.`3`[0]) node _credit_available_T_13 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`0`[8], states[2].vc_sel.`0`[8] connect salloc_arb.io.in[2].bits.vc_sel.`0`[9], states[2].vc_sel.`0`[9] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`5`[0], states[2].vc_sel.`5`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_126 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_127 = and(_T_126, input_buffer.io.deq[2].bits.tail) when _T_127 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_6 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_hi_6 = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3]) node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_6, states[3].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5]) node credit_available_hi_hi_hi_6 = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8]) node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_6, states[3].vc_sel.`0`[7]) node credit_available_hi_12 = cat(credit_available_hi_hi_12, credit_available_hi_lo_6) node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_hi_13 = cat(states[3].vc_sel.`2`[0], states[3].vc_sel.`1`[0]) node credit_available_lo_13 = cat(credit_available_lo_hi_13, _credit_available_T_15) node credit_available_hi_hi_13 = cat(states[3].vc_sel.`5`[0], states[3].vc_sel.`4`[0]) node credit_available_hi_13 = cat(credit_available_hi_hi_13, states[3].vc_sel.`3`[0]) node _credit_available_T_16 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_lo_7 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_7 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_7, io.out_credit_available.`0`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_7 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_7, io.out_credit_available.`0`[7]) node credit_available_hi_14 = cat(credit_available_hi_hi_14, credit_available_hi_lo_7) node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_hi_15 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_15 = cat(credit_available_lo_hi_15, _credit_available_T_17) node credit_available_hi_hi_15 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_15 = cat(credit_available_hi_hi_15, io.out_credit_available.`3`[0]) node _credit_available_T_18 = cat(credit_available_hi_15, credit_available_lo_15) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8] connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`4`[0], states[3].vc_sel.`4`[0] connect salloc_arb.io.in[3].bits.vc_sel.`5`[0], states[3].vc_sel.`5`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_128 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_129 = and(_T_128, input_buffer.io.deq[3].bits.tail) when _T_129 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_8 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_hi_8 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_lo_hi_16 = cat(credit_available_lo_hi_hi_8, states[4].vc_sel.`0`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5]) node credit_available_hi_hi_hi_8 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8]) node credit_available_hi_hi_16 = cat(credit_available_hi_hi_hi_8, states[4].vc_sel.`0`[7]) node credit_available_hi_16 = cat(credit_available_hi_hi_16, credit_available_hi_lo_8) node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_hi_17 = cat(states[4].vc_sel.`2`[0], states[4].vc_sel.`1`[0]) node credit_available_lo_17 = cat(credit_available_lo_hi_17, _credit_available_T_20) node credit_available_hi_hi_17 = cat(states[4].vc_sel.`5`[0], states[4].vc_sel.`4`[0]) node credit_available_hi_17 = cat(credit_available_hi_hi_17, states[4].vc_sel.`3`[0]) node _credit_available_T_21 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_18 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_18 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7]) node credit_available_hi_18 = cat(credit_available_hi_hi_18, credit_available_hi_lo_9) node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_hi_19 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_19 = cat(credit_available_lo_hi_19, _credit_available_T_22) node credit_available_hi_hi_19 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_19 = cat(credit_available_hi_hi_19, io.out_credit_available.`3`[0]) node _credit_available_T_23 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8] connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`4`[0], states[4].vc_sel.`4`[0] connect salloc_arb.io.in[4].bits.vc_sel.`5`[0], states[4].vc_sel.`5`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_130 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_131 = and(_T_130, input_buffer.io.deq[4].bits.tail) when _T_131 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_10 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_hi_10 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3]) node credit_available_lo_hi_20 = cat(credit_available_lo_hi_hi_10, states[5].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5]) node credit_available_hi_hi_hi_10 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8]) node credit_available_hi_hi_20 = cat(credit_available_hi_hi_hi_10, states[5].vc_sel.`0`[7]) node credit_available_hi_20 = cat(credit_available_hi_hi_20, credit_available_hi_lo_10) node _credit_available_T_25 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_hi_21 = cat(states[5].vc_sel.`2`[0], states[5].vc_sel.`1`[0]) node credit_available_lo_21 = cat(credit_available_lo_hi_21, _credit_available_T_25) node credit_available_hi_hi_21 = cat(states[5].vc_sel.`5`[0], states[5].vc_sel.`4`[0]) node credit_available_hi_21 = cat(credit_available_hi_hi_21, states[5].vc_sel.`3`[0]) node _credit_available_T_26 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_11 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_22 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`0`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_22 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`0`[7]) node credit_available_hi_22 = cat(credit_available_hi_hi_22, credit_available_hi_lo_11) node _credit_available_T_27 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_hi_23 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_23 = cat(credit_available_lo_hi_23, _credit_available_T_27) node credit_available_hi_hi_23 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_23 = cat(credit_available_hi_hi_23, io.out_credit_available.`3`[0]) node _credit_available_T_28 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8] connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`4`[0], states[5].vc_sel.`4`[0] connect salloc_arb.io.in[5].bits.vc_sel.`5`[0], states[5].vc_sel.`5`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_132 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_133 = and(_T_132, input_buffer.io.deq[5].bits.tail) when _T_133 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready connect salloc_arb.io.in[6].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[6].bits.tail invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`5`[0] connect salloc_arb.io.in[7].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[7].bits.tail invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`5`[0] node credit_available_lo_lo_12 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi_12 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi_24 = cat(credit_available_lo_hi_hi_12, states[8].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi_12 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi_24 = cat(credit_available_hi_hi_hi_12, states[8].vc_sel.`0`[7]) node credit_available_hi_24 = cat(credit_available_hi_hi_24, credit_available_hi_lo_12) node _credit_available_T_30 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_hi_25 = cat(states[8].vc_sel.`2`[0], states[8].vc_sel.`1`[0]) node credit_available_lo_25 = cat(credit_available_lo_hi_25, _credit_available_T_30) node credit_available_hi_hi_25 = cat(states[8].vc_sel.`5`[0], states[8].vc_sel.`4`[0]) node credit_available_hi_25 = cat(credit_available_hi_hi_25, states[8].vc_sel.`3`[0]) node _credit_available_T_31 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_13 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_13 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_26 = cat(credit_available_lo_hi_hi_13, io.out_credit_available.`0`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_13 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_26 = cat(credit_available_hi_hi_hi_13, io.out_credit_available.`0`[7]) node credit_available_hi_26 = cat(credit_available_hi_hi_26, credit_available_hi_lo_13) node _credit_available_T_32 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_hi_27 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_27 = cat(credit_available_lo_hi_27, _credit_available_T_32) node credit_available_hi_hi_27 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_27 = cat(credit_available_hi_hi_27, io.out_credit_available.`3`[0]) node _credit_available_T_33 = cat(credit_available_hi_27, credit_available_lo_27) node _credit_available_T_34 = and(_credit_available_T_31, _credit_available_T_33) node credit_available_6 = neq(_credit_available_T_34, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_6) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`3`[0], states[8].vc_sel.`3`[0] connect salloc_arb.io.in[8].bits.vc_sel.`4`[0], states[8].vc_sel.`4`[0] connect salloc_arb.io.in[8].bits.vc_sel.`5`[0], states[8].vc_sel.`5`[0] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_134 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_135 = and(_T_134, input_buffer.io.deq[8].bits.tail) when _T_135 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready node credit_available_lo_lo_14 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0]) node credit_available_lo_hi_hi_14 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3]) node credit_available_lo_hi_28 = cat(credit_available_lo_hi_hi_14, states[9].vc_sel.`0`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5]) node credit_available_hi_hi_hi_14 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8]) node credit_available_hi_hi_28 = cat(credit_available_hi_hi_hi_14, states[9].vc_sel.`0`[7]) node credit_available_hi_28 = cat(credit_available_hi_hi_28, credit_available_hi_lo_14) node _credit_available_T_35 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_hi_29 = cat(states[9].vc_sel.`2`[0], states[9].vc_sel.`1`[0]) node credit_available_lo_29 = cat(credit_available_lo_hi_29, _credit_available_T_35) node credit_available_hi_hi_29 = cat(states[9].vc_sel.`5`[0], states[9].vc_sel.`4`[0]) node credit_available_hi_29 = cat(credit_available_hi_hi_29, states[9].vc_sel.`3`[0]) node _credit_available_T_36 = cat(credit_available_hi_29, credit_available_lo_29) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_30 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_30 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7]) node credit_available_hi_30 = cat(credit_available_hi_hi_30, credit_available_hi_lo_15) node _credit_available_T_37 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_hi_31 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_31 = cat(credit_available_lo_hi_31, _credit_available_T_37) node credit_available_hi_hi_31 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_31 = cat(credit_available_hi_hi_31, io.out_credit_available.`3`[0]) node _credit_available_T_38 = cat(credit_available_hi_31, credit_available_lo_31) node _credit_available_T_39 = and(_credit_available_T_36, _credit_available_T_38) node credit_available_7 = neq(_credit_available_T_39, UInt<1>(0h0)) node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3)) node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_7) node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid) connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2 connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0] connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1] connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2] connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3] connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4] connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5] connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6] connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7] connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8] connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9] connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0] connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0] connect salloc_arb.io.in[9].bits.vc_sel.`3`[0], states[9].vc_sel.`3`[0] connect salloc_arb.io.in[9].bits.vc_sel.`4`[0], states[9].vc_sel.`4`[0] connect salloc_arb.io.in[9].bits.vc_sel.`5`[0], states[9].vc_sel.`5`[0] connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail node _T_136 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid) node _T_137 = and(_T_136, input_buffer.io.deq[9].bits.tail) when _T_137 : connect states[9].g, UInt<3>(0h0) connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[1] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_13 : UInt<1>[1] node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_237 connect _vc_sel_WIRE_13[0], _vc_sel_WIRE_14 connect vc_sel.`2`, _vc_sel_WIRE_13 wire _vc_sel_WIRE_15 : UInt<1>[1] node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_256 connect _vc_sel_WIRE_15[0], _vc_sel_WIRE_16 connect vc_sel.`3`, _vc_sel_WIRE_15 wire _vc_sel_WIRE_17 : UInt<1>[1] node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258) node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259) node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260) node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261) node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266) wire _vc_sel_WIRE_18 : UInt<1> connect _vc_sel_WIRE_18, _vc_sel_T_275 connect _vc_sel_WIRE_17[0], _vc_sel_WIRE_18 connect vc_sel.`4`, _vc_sel_WIRE_17 wire _vc_sel_WIRE_19 : UInt<1>[1] node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283) node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284) node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_294 connect _vc_sel_WIRE_19[0], _vc_sel_WIRE_20 connect vc_sel.`5`, _vc_sel_WIRE_19 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node _virt_channel_T_11 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_12 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_13 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_14 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_15 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_16 = mux(vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_17 = or(_virt_channel_T_11, _virt_channel_T_12) node _virt_channel_T_18 = or(_virt_channel_T_17, _virt_channel_T_13) node _virt_channel_T_19 = or(_virt_channel_T_18, _virt_channel_T_14) node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_15) node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_16) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_21 node _T_138 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_138 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`0`[3], UInt<1>(0h0) connect states[0].vc_sel.`0`[4], UInt<1>(0h0) connect states[0].vc_sel.`0`[5], UInt<1>(0h0) connect states[0].vc_sel.`0`[6], UInt<1>(0h0) connect states[0].vc_sel.`0`[7], UInt<1>(0h0) connect states[0].vc_sel.`0`[8], UInt<1>(0h0) connect states[0].vc_sel.`0`[9], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[1].vc_sel.`0`[6], UInt<1>(0h0) connect states[1].vc_sel.`0`[7], UInt<1>(0h0) connect states[1].vc_sel.`0`[8], UInt<1>(0h0) connect states[1].vc_sel.`0`[9], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[6], UInt<1>(0h0) connect states[2].vc_sel.`0`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[8], UInt<1>(0h0) connect states[2].vc_sel.`0`[9], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[2], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[6], UInt<1>(0h0) connect states[3].vc_sel.`0`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[8], UInt<1>(0h0) connect states[3].vc_sel.`0`[9], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[6], UInt<1>(0h0) connect states[4].vc_sel.`0`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[8], UInt<1>(0h0) connect states[4].vc_sel.`0`[9], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) connect states[5].vc_sel.`0`[6], UInt<1>(0h0) connect states[5].vc_sel.`0`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[8], UInt<1>(0h0) connect states[5].vc_sel.`0`[9], UInt<1>(0h0) invalidate states[6].fifo_deps invalidate states[6].flow.egress_node_id invalidate states[6].flow.egress_node invalidate states[6].flow.ingress_node_id invalidate states[6].flow.ingress_node invalidate states[6].flow.vnet_id invalidate states[6].vc_sel.`0`[0] invalidate states[6].vc_sel.`0`[1] invalidate states[6].vc_sel.`0`[2] invalidate states[6].vc_sel.`0`[3] invalidate states[6].vc_sel.`0`[4] invalidate states[6].vc_sel.`0`[5] invalidate states[6].vc_sel.`0`[6] invalidate states[6].vc_sel.`0`[7] invalidate states[6].vc_sel.`0`[8] invalidate states[6].vc_sel.`0`[9] invalidate states[6].vc_sel.`1`[0] invalidate states[6].vc_sel.`2`[0] invalidate states[6].vc_sel.`3`[0] invalidate states[6].vc_sel.`4`[0] invalidate states[6].vc_sel.`5`[0] invalidate states[6].g invalidate states[7].fifo_deps invalidate states[7].flow.egress_node_id invalidate states[7].flow.egress_node invalidate states[7].flow.ingress_node_id invalidate states[7].flow.ingress_node invalidate states[7].flow.vnet_id invalidate states[7].vc_sel.`0`[0] invalidate states[7].vc_sel.`0`[1] invalidate states[7].vc_sel.`0`[2] invalidate states[7].vc_sel.`0`[3] invalidate states[7].vc_sel.`0`[4] invalidate states[7].vc_sel.`0`[5] invalidate states[7].vc_sel.`0`[6] invalidate states[7].vc_sel.`0`[7] invalidate states[7].vc_sel.`0`[8] invalidate states[7].vc_sel.`0`[9] invalidate states[7].vc_sel.`1`[0] invalidate states[7].vc_sel.`2`[0] invalidate states[7].vc_sel.`3`[0] invalidate states[7].vc_sel.`4`[0] invalidate states[7].vc_sel.`5`[0] invalidate states[7].g connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`0`[9], UInt<1>(0h0) connect states[9].vc_sel.`0`[0], UInt<1>(0h0) connect states[9].vc_sel.`0`[1], UInt<1>(0h0) connect states[9].vc_sel.`0`[2], UInt<1>(0h0) connect states[9].vc_sel.`0`[3], UInt<1>(0h0) connect states[9].vc_sel.`0`[4], UInt<1>(0h0) connect states[9].vc_sel.`0`[5], UInt<1>(0h0) connect states[9].vc_sel.`0`[6], UInt<1>(0h0) connect states[9].vc_sel.`0`[7], UInt<1>(0h0) node _T_139 = asUInt(reset) when _T_139 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)	module InputUnit_4( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, 2'h0, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_0 ? 20'h400 : vcalloc_vals_1 ? 20'h800 : vcalloc_vals_2 ? 20'h1000 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] \| vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 \| vcalloc_vals_1 \| vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_8 \| vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_3 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_3( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module PE_235 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_235( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_111 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_111( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_184 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_184( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_169 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_425 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_169( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_425 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_11 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_11( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Switch_4 : input clock : Clock input reset : Reset output io : { in : { flip `5` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `4` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `3` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `2` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `1` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `0` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1]}, out : { `5` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `4` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `3` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `2` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `1` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `0` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1]}, sel : { `5` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `4` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `3` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `2` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `1` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `0` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1]}} wire in_flat : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[6] connect in_flat[0], io.in.`0`[0] connect in_flat[1], io.in.`1`[0] connect in_flat[2], io.in.`2`[0] connect in_flat[3], io.in.`3`[0] connect in_flat[4], io.in.`4`[0] connect in_flat[5], io.in.`5`[0] node sel_flat_lo_hi = cat(io.sel.`0`[0].`2`[0], io.sel.`0`[0].`1`[0]) node sel_flat_lo = cat(sel_flat_lo_hi, io.sel.`0`[0].`0`[0]) node sel_flat_hi_hi = cat(io.sel.`0`[0].`5`[0], io.sel.`0`[0].`4`[0]) node sel_flat_hi = cat(sel_flat_hi_hi, io.sel.`0`[0].`3`[0]) node sel_flat = cat(sel_flat_hi, sel_flat_lo) node _T = bits(sel_flat, 0, 0) node _T_1 = bits(sel_flat, 1, 1) node _T_2 = bits(sel_flat, 2, 2) node _T_3 = bits(sel_flat, 3, 3) node _T_4 = bits(sel_flat, 4, 4) node _T_5 = bits(sel_flat, 5, 5) node _T_6 = add(_T_1, _T_2) node _T_7 = bits(_T_6, 1, 0) node _T_8 = add(_T, _T_7) node _T_9 = bits(_T_8, 1, 0) node _T_10 = add(_T_4, _T_5) node _T_11 = bits(_T_10, 1, 0) node _T_12 = add(_T_3, _T_11) node _T_13 = bits(_T_12, 1, 0) node _T_14 = add(_T_9, _T_13) node _T_15 = bits(_T_14, 2, 0) node _T_16 = leq(_T_15, UInt<1>(0h1)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf assert(clock, _T_16, UInt<1>(0h1), "") : assert node _io_out_0_0_valid_T = bits(sel_flat, 0, 0) node _io_out_0_0_valid_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_valid_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_valid_T_3 = bits(sel_flat, 3, 3) node _io_out_0_0_valid_T_4 = bits(sel_flat, 4, 4) node _io_out_0_0_valid_T_5 = bits(sel_flat, 5, 5) node _io_out_0_0_valid_T_6 = mux(_io_out_0_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_7 = mux(_io_out_0_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_8 = mux(_io_out_0_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_9 = mux(_io_out_0_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_10 = mux(_io_out_0_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_11 = mux(_io_out_0_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_12 = or(_io_out_0_0_valid_T_6, _io_out_0_0_valid_T_7) node _io_out_0_0_valid_T_13 = or(_io_out_0_0_valid_T_12, _io_out_0_0_valid_T_8) node _io_out_0_0_valid_T_14 = or(_io_out_0_0_valid_T_13, _io_out_0_0_valid_T_9) node _io_out_0_0_valid_T_15 = or(_io_out_0_0_valid_T_14, _io_out_0_0_valid_T_10) node _io_out_0_0_valid_T_16 = or(_io_out_0_0_valid_T_15, _io_out_0_0_valid_T_11) wire _io_out_0_0_valid_WIRE : UInt<1> connect _io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_16 node _io_out_0_0_valid_T_17 = neq(sel_flat, UInt<1>(0h0)) node _io_out_0_0_valid_T_18 = and(_io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_17) connect io.out.`0`[0].valid, _io_out_0_0_valid_T_18 node _io_out_0_0_bits_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_bits_T_3 = bits(sel_flat, 3, 3) node _io_out_0_0_bits_T_4 = bits(sel_flat, 4, 4) node _io_out_0_0_bits_T_5 = bits(sel_flat, 5, 5) wire _io_out_0_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_0_0_bits_T_6 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_7 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_8 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_9 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_10 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_11 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_12 = or(_io_out_0_0_bits_T_6, _io_out_0_0_bits_T_7) node _io_out_0_0_bits_T_13 = or(_io_out_0_0_bits_T_12, _io_out_0_0_bits_T_8) node _io_out_0_0_bits_T_14 = or(_io_out_0_0_bits_T_13, _io_out_0_0_bits_T_9) node _io_out_0_0_bits_T_15 = or(_io_out_0_0_bits_T_14, _io_out_0_0_bits_T_10) node _io_out_0_0_bits_T_16 = or(_io_out_0_0_bits_T_15, _io_out_0_0_bits_T_11) wire _io_out_0_0_bits_WIRE_1 : UInt<4> connect _io_out_0_0_bits_WIRE_1, _io_out_0_0_bits_T_16 connect _io_out_0_0_bits_WIRE.virt_channel_id, _io_out_0_0_bits_WIRE_1 wire _io_out_0_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_0_0_bits_T_17 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_18 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_19 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_20 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_21 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_22 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_23 = or(_io_out_0_0_bits_T_17, _io_out_0_0_bits_T_18) node _io_out_0_0_bits_T_24 = or(_io_out_0_0_bits_T_23, _io_out_0_0_bits_T_19) node _io_out_0_0_bits_T_25 = or(_io_out_0_0_bits_T_24, _io_out_0_0_bits_T_20) node _io_out_0_0_bits_T_26 = or(_io_out_0_0_bits_T_25, _io_out_0_0_bits_T_21) node _io_out_0_0_bits_T_27 = or(_io_out_0_0_bits_T_26, _io_out_0_0_bits_T_22) wire _io_out_0_0_bits_WIRE_3 : UInt<3> connect _io_out_0_0_bits_WIRE_3, _io_out_0_0_bits_T_27 connect _io_out_0_0_bits_WIRE_2.egress_node_id, _io_out_0_0_bits_WIRE_3 node _io_out_0_0_bits_T_28 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_29 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_30 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_31 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_32 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_33 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_34 = or(_io_out_0_0_bits_T_28, _io_out_0_0_bits_T_29) node _io_out_0_0_bits_T_35 = or(_io_out_0_0_bits_T_34, _io_out_0_0_bits_T_30) node _io_out_0_0_bits_T_36 = or(_io_out_0_0_bits_T_35, _io_out_0_0_bits_T_31) node _io_out_0_0_bits_T_37 = or(_io_out_0_0_bits_T_36, _io_out_0_0_bits_T_32) node _io_out_0_0_bits_T_38 = or(_io_out_0_0_bits_T_37, _io_out_0_0_bits_T_33) wire _io_out_0_0_bits_WIRE_4 : UInt<4> connect _io_out_0_0_bits_WIRE_4, _io_out_0_0_bits_T_38 connect _io_out_0_0_bits_WIRE_2.egress_node, _io_out_0_0_bits_WIRE_4 node _io_out_0_0_bits_T_39 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_40 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_41 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_42 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_43 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_44 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_45 = or(_io_out_0_0_bits_T_39, _io_out_0_0_bits_T_40) node _io_out_0_0_bits_T_46 = or(_io_out_0_0_bits_T_45, _io_out_0_0_bits_T_41) node _io_out_0_0_bits_T_47 = or(_io_out_0_0_bits_T_46, _io_out_0_0_bits_T_42) node _io_out_0_0_bits_T_48 = or(_io_out_0_0_bits_T_47, _io_out_0_0_bits_T_43) node _io_out_0_0_bits_T_49 = or(_io_out_0_0_bits_T_48, _io_out_0_0_bits_T_44) wire _io_out_0_0_bits_WIRE_5 : UInt<3> connect _io_out_0_0_bits_WIRE_5, _io_out_0_0_bits_T_49 connect _io_out_0_0_bits_WIRE_2.ingress_node_id, _io_out_0_0_bits_WIRE_5 node _io_out_0_0_bits_T_50 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_51 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_52 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_53 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_54 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_55 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_56 = or(_io_out_0_0_bits_T_50, _io_out_0_0_bits_T_51) node _io_out_0_0_bits_T_57 = or(_io_out_0_0_bits_T_56, _io_out_0_0_bits_T_52) node _io_out_0_0_bits_T_58 = or(_io_out_0_0_bits_T_57, _io_out_0_0_bits_T_53) node _io_out_0_0_bits_T_59 = or(_io_out_0_0_bits_T_58, _io_out_0_0_bits_T_54) node _io_out_0_0_bits_T_60 = or(_io_out_0_0_bits_T_59, _io_out_0_0_bits_T_55) wire _io_out_0_0_bits_WIRE_6 : UInt<4> connect _io_out_0_0_bits_WIRE_6, _io_out_0_0_bits_T_60 connect _io_out_0_0_bits_WIRE_2.ingress_node, _io_out_0_0_bits_WIRE_6 node _io_out_0_0_bits_T_61 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_62 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_63 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_64 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_65 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_66 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_67 = or(_io_out_0_0_bits_T_61, _io_out_0_0_bits_T_62) node _io_out_0_0_bits_T_68 = or(_io_out_0_0_bits_T_67, _io_out_0_0_bits_T_63) node _io_out_0_0_bits_T_69 = or(_io_out_0_0_bits_T_68, _io_out_0_0_bits_T_64) node _io_out_0_0_bits_T_70 = or(_io_out_0_0_bits_T_69, _io_out_0_0_bits_T_65) node _io_out_0_0_bits_T_71 = or(_io_out_0_0_bits_T_70, _io_out_0_0_bits_T_66) wire _io_out_0_0_bits_WIRE_7 : UInt<3> connect _io_out_0_0_bits_WIRE_7, _io_out_0_0_bits_T_71 connect _io_out_0_0_bits_WIRE_2.vnet_id, _io_out_0_0_bits_WIRE_7 connect _io_out_0_0_bits_WIRE.flow, _io_out_0_0_bits_WIRE_2 node _io_out_0_0_bits_T_72 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_73 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_74 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_75 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_76 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_77 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_78 = or(_io_out_0_0_bits_T_72, _io_out_0_0_bits_T_73) node _io_out_0_0_bits_T_79 = or(_io_out_0_0_bits_T_78, _io_out_0_0_bits_T_74) node _io_out_0_0_bits_T_80 = or(_io_out_0_0_bits_T_79, _io_out_0_0_bits_T_75) node _io_out_0_0_bits_T_81 = or(_io_out_0_0_bits_T_80, _io_out_0_0_bits_T_76) node _io_out_0_0_bits_T_82 = or(_io_out_0_0_bits_T_81, _io_out_0_0_bits_T_77) wire _io_out_0_0_bits_WIRE_8 : UInt<73> connect _io_out_0_0_bits_WIRE_8, _io_out_0_0_bits_T_82 connect _io_out_0_0_bits_WIRE.payload, _io_out_0_0_bits_WIRE_8 node _io_out_0_0_bits_T_83 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_84 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_85 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_86 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_87 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_88 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_89 = or(_io_out_0_0_bits_T_83, _io_out_0_0_bits_T_84) node _io_out_0_0_bits_T_90 = or(_io_out_0_0_bits_T_89, _io_out_0_0_bits_T_85) node _io_out_0_0_bits_T_91 = or(_io_out_0_0_bits_T_90, _io_out_0_0_bits_T_86) node _io_out_0_0_bits_T_92 = or(_io_out_0_0_bits_T_91, _io_out_0_0_bits_T_87) node _io_out_0_0_bits_T_93 = or(_io_out_0_0_bits_T_92, _io_out_0_0_bits_T_88) wire _io_out_0_0_bits_WIRE_9 : UInt<1> connect _io_out_0_0_bits_WIRE_9, _io_out_0_0_bits_T_93 connect _io_out_0_0_bits_WIRE.tail, _io_out_0_0_bits_WIRE_9 node _io_out_0_0_bits_T_94 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_95 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_96 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_97 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_98 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_99 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_100 = or(_io_out_0_0_bits_T_94, _io_out_0_0_bits_T_95) node _io_out_0_0_bits_T_101 = or(_io_out_0_0_bits_T_100, _io_out_0_0_bits_T_96) node _io_out_0_0_bits_T_102 = or(_io_out_0_0_bits_T_101, _io_out_0_0_bits_T_97) node _io_out_0_0_bits_T_103 = or(_io_out_0_0_bits_T_102, _io_out_0_0_bits_T_98) node _io_out_0_0_bits_T_104 = or(_io_out_0_0_bits_T_103, _io_out_0_0_bits_T_99) wire _io_out_0_0_bits_WIRE_10 : UInt<1> connect _io_out_0_0_bits_WIRE_10, _io_out_0_0_bits_T_104 connect _io_out_0_0_bits_WIRE.head, _io_out_0_0_bits_WIRE_10 connect io.out.`0`[0].bits, _io_out_0_0_bits_WIRE node _io_out_0_0_bits_virt_channel_id_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_virt_channel_id_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_virt_channel_id_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_bits_virt_channel_id_T_3 = bits(sel_flat, 3, 3) node _io_out_0_0_bits_virt_channel_id_T_4 = bits(sel_flat, 4, 4) node _io_out_0_0_bits_virt_channel_id_T_5 = bits(sel_flat, 5, 5) node _io_out_0_0_bits_virt_channel_id_T_6 = mux(_io_out_0_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_7 = mux(_io_out_0_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_8 = mux(_io_out_0_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_9 = mux(_io_out_0_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_10 = mux(_io_out_0_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_11 = mux(_io_out_0_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_12 = or(_io_out_0_0_bits_virt_channel_id_T_6, _io_out_0_0_bits_virt_channel_id_T_7) node _io_out_0_0_bits_virt_channel_id_T_13 = or(_io_out_0_0_bits_virt_channel_id_T_12, _io_out_0_0_bits_virt_channel_id_T_8) node _io_out_0_0_bits_virt_channel_id_T_14 = or(_io_out_0_0_bits_virt_channel_id_T_13, _io_out_0_0_bits_virt_channel_id_T_9) node _io_out_0_0_bits_virt_channel_id_T_15 = or(_io_out_0_0_bits_virt_channel_id_T_14, _io_out_0_0_bits_virt_channel_id_T_10) node _io_out_0_0_bits_virt_channel_id_T_16 = or(_io_out_0_0_bits_virt_channel_id_T_15, _io_out_0_0_bits_virt_channel_id_T_11) wire _io_out_0_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_0_0_bits_virt_channel_id_WIRE, _io_out_0_0_bits_virt_channel_id_T_16 connect io.out.`0`[0].bits.virt_channel_id, _io_out_0_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_1 = cat(io.sel.`1`[0].`2`[0], io.sel.`1`[0].`1`[0]) node sel_flat_lo_1 = cat(sel_flat_lo_hi_1, io.sel.`1`[0].`0`[0]) node sel_flat_hi_hi_1 = cat(io.sel.`1`[0].`5`[0], io.sel.`1`[0].`4`[0]) node sel_flat_hi_1 = cat(sel_flat_hi_hi_1, io.sel.`1`[0].`3`[0]) node sel_flat_1 = cat(sel_flat_hi_1, sel_flat_lo_1) node _T_20 = bits(sel_flat_1, 0, 0) node _T_21 = bits(sel_flat_1, 1, 1) node _T_22 = bits(sel_flat_1, 2, 2) node _T_23 = bits(sel_flat_1, 3, 3) node _T_24 = bits(sel_flat_1, 4, 4) node _T_25 = bits(sel_flat_1, 5, 5) node _T_26 = add(_T_21, _T_22) node _T_27 = bits(_T_26, 1, 0) node _T_28 = add(_T_20, _T_27) node _T_29 = bits(_T_28, 1, 0) node _T_30 = add(_T_24, _T_25) node _T_31 = bits(_T_30, 1, 0) node _T_32 = add(_T_23, _T_31) node _T_33 = bits(_T_32, 1, 0) node _T_34 = add(_T_29, _T_33) node _T_35 = bits(_T_34, 2, 0) node _T_36 = leq(_T_35, UInt<1>(0h1)) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_1 assert(clock, _T_36, UInt<1>(0h1), "") : assert_1 node _io_out_1_0_valid_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_valid_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_valid_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_valid_T_3 = bits(sel_flat_1, 3, 3) node _io_out_1_0_valid_T_4 = bits(sel_flat_1, 4, 4) node _io_out_1_0_valid_T_5 = bits(sel_flat_1, 5, 5) node _io_out_1_0_valid_T_6 = mux(_io_out_1_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_7 = mux(_io_out_1_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_8 = mux(_io_out_1_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_9 = mux(_io_out_1_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_10 = mux(_io_out_1_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_11 = mux(_io_out_1_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_12 = or(_io_out_1_0_valid_T_6, _io_out_1_0_valid_T_7) node _io_out_1_0_valid_T_13 = or(_io_out_1_0_valid_T_12, _io_out_1_0_valid_T_8) node _io_out_1_0_valid_T_14 = or(_io_out_1_0_valid_T_13, _io_out_1_0_valid_T_9) node _io_out_1_0_valid_T_15 = or(_io_out_1_0_valid_T_14, _io_out_1_0_valid_T_10) node _io_out_1_0_valid_T_16 = or(_io_out_1_0_valid_T_15, _io_out_1_0_valid_T_11) wire _io_out_1_0_valid_WIRE : UInt<1> connect _io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_16 node _io_out_1_0_valid_T_17 = neq(sel_flat_1, UInt<1>(0h0)) node _io_out_1_0_valid_T_18 = and(_io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_17) connect io.out.`1`[0].valid, _io_out_1_0_valid_T_18 node _io_out_1_0_bits_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_bits_T_3 = bits(sel_flat_1, 3, 3) node _io_out_1_0_bits_T_4 = bits(sel_flat_1, 4, 4) node _io_out_1_0_bits_T_5 = bits(sel_flat_1, 5, 5) wire _io_out_1_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_1_0_bits_T_6 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_7 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_8 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_9 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_10 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_11 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_12 = or(_io_out_1_0_bits_T_6, _io_out_1_0_bits_T_7) node _io_out_1_0_bits_T_13 = or(_io_out_1_0_bits_T_12, _io_out_1_0_bits_T_8) node _io_out_1_0_bits_T_14 = or(_io_out_1_0_bits_T_13, _io_out_1_0_bits_T_9) node _io_out_1_0_bits_T_15 = or(_io_out_1_0_bits_T_14, _io_out_1_0_bits_T_10) node _io_out_1_0_bits_T_16 = or(_io_out_1_0_bits_T_15, _io_out_1_0_bits_T_11) wire _io_out_1_0_bits_WIRE_1 : UInt<4> connect _io_out_1_0_bits_WIRE_1, _io_out_1_0_bits_T_16 connect _io_out_1_0_bits_WIRE.virt_channel_id, _io_out_1_0_bits_WIRE_1 wire _io_out_1_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_1_0_bits_T_17 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_18 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_19 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_20 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_21 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_22 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_23 = or(_io_out_1_0_bits_T_17, _io_out_1_0_bits_T_18) node _io_out_1_0_bits_T_24 = or(_io_out_1_0_bits_T_23, _io_out_1_0_bits_T_19) node _io_out_1_0_bits_T_25 = or(_io_out_1_0_bits_T_24, _io_out_1_0_bits_T_20) node _io_out_1_0_bits_T_26 = or(_io_out_1_0_bits_T_25, _io_out_1_0_bits_T_21) node _io_out_1_0_bits_T_27 = or(_io_out_1_0_bits_T_26, _io_out_1_0_bits_T_22) wire _io_out_1_0_bits_WIRE_3 : UInt<3> connect _io_out_1_0_bits_WIRE_3, _io_out_1_0_bits_T_27 connect _io_out_1_0_bits_WIRE_2.egress_node_id, _io_out_1_0_bits_WIRE_3 node _io_out_1_0_bits_T_28 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_29 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_30 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_31 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_32 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_33 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_34 = or(_io_out_1_0_bits_T_28, _io_out_1_0_bits_T_29) node _io_out_1_0_bits_T_35 = or(_io_out_1_0_bits_T_34, _io_out_1_0_bits_T_30) node _io_out_1_0_bits_T_36 = or(_io_out_1_0_bits_T_35, _io_out_1_0_bits_T_31) node _io_out_1_0_bits_T_37 = or(_io_out_1_0_bits_T_36, _io_out_1_0_bits_T_32) node _io_out_1_0_bits_T_38 = or(_io_out_1_0_bits_T_37, _io_out_1_0_bits_T_33) wire _io_out_1_0_bits_WIRE_4 : UInt<4> connect _io_out_1_0_bits_WIRE_4, _io_out_1_0_bits_T_38 connect _io_out_1_0_bits_WIRE_2.egress_node, _io_out_1_0_bits_WIRE_4 node _io_out_1_0_bits_T_39 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_40 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_41 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_42 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_43 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_44 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_45 = or(_io_out_1_0_bits_T_39, _io_out_1_0_bits_T_40) node _io_out_1_0_bits_T_46 = or(_io_out_1_0_bits_T_45, _io_out_1_0_bits_T_41) node _io_out_1_0_bits_T_47 = or(_io_out_1_0_bits_T_46, _io_out_1_0_bits_T_42) node _io_out_1_0_bits_T_48 = or(_io_out_1_0_bits_T_47, _io_out_1_0_bits_T_43) node _io_out_1_0_bits_T_49 = or(_io_out_1_0_bits_T_48, _io_out_1_0_bits_T_44) wire _io_out_1_0_bits_WIRE_5 : UInt<3> connect _io_out_1_0_bits_WIRE_5, _io_out_1_0_bits_T_49 connect _io_out_1_0_bits_WIRE_2.ingress_node_id, _io_out_1_0_bits_WIRE_5 node _io_out_1_0_bits_T_50 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_51 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_52 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_53 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_54 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_55 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_56 = or(_io_out_1_0_bits_T_50, _io_out_1_0_bits_T_51) node _io_out_1_0_bits_T_57 = or(_io_out_1_0_bits_T_56, _io_out_1_0_bits_T_52) node _io_out_1_0_bits_T_58 = or(_io_out_1_0_bits_T_57, _io_out_1_0_bits_T_53) node _io_out_1_0_bits_T_59 = or(_io_out_1_0_bits_T_58, _io_out_1_0_bits_T_54) node _io_out_1_0_bits_T_60 = or(_io_out_1_0_bits_T_59, _io_out_1_0_bits_T_55) wire _io_out_1_0_bits_WIRE_6 : UInt<4> connect _io_out_1_0_bits_WIRE_6, _io_out_1_0_bits_T_60 connect _io_out_1_0_bits_WIRE_2.ingress_node, _io_out_1_0_bits_WIRE_6 node _io_out_1_0_bits_T_61 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_62 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_63 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_64 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_65 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_66 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_67 = or(_io_out_1_0_bits_T_61, _io_out_1_0_bits_T_62) node _io_out_1_0_bits_T_68 = or(_io_out_1_0_bits_T_67, _io_out_1_0_bits_T_63) node _io_out_1_0_bits_T_69 = or(_io_out_1_0_bits_T_68, _io_out_1_0_bits_T_64) node _io_out_1_0_bits_T_70 = or(_io_out_1_0_bits_T_69, _io_out_1_0_bits_T_65) node _io_out_1_0_bits_T_71 = or(_io_out_1_0_bits_T_70, _io_out_1_0_bits_T_66) wire _io_out_1_0_bits_WIRE_7 : UInt<3> connect _io_out_1_0_bits_WIRE_7, _io_out_1_0_bits_T_71 connect _io_out_1_0_bits_WIRE_2.vnet_id, _io_out_1_0_bits_WIRE_7 connect _io_out_1_0_bits_WIRE.flow, _io_out_1_0_bits_WIRE_2 node _io_out_1_0_bits_T_72 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_73 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_74 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_75 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_76 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_77 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_78 = or(_io_out_1_0_bits_T_72, _io_out_1_0_bits_T_73) node _io_out_1_0_bits_T_79 = or(_io_out_1_0_bits_T_78, _io_out_1_0_bits_T_74) node _io_out_1_0_bits_T_80 = or(_io_out_1_0_bits_T_79, _io_out_1_0_bits_T_75) node _io_out_1_0_bits_T_81 = or(_io_out_1_0_bits_T_80, _io_out_1_0_bits_T_76) node _io_out_1_0_bits_T_82 = or(_io_out_1_0_bits_T_81, _io_out_1_0_bits_T_77) wire _io_out_1_0_bits_WIRE_8 : UInt<73> connect _io_out_1_0_bits_WIRE_8, _io_out_1_0_bits_T_82 connect _io_out_1_0_bits_WIRE.payload, _io_out_1_0_bits_WIRE_8 node _io_out_1_0_bits_T_83 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_84 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_85 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_86 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_87 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_88 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_89 = or(_io_out_1_0_bits_T_83, _io_out_1_0_bits_T_84) node _io_out_1_0_bits_T_90 = or(_io_out_1_0_bits_T_89, _io_out_1_0_bits_T_85) node _io_out_1_0_bits_T_91 = or(_io_out_1_0_bits_T_90, _io_out_1_0_bits_T_86) node _io_out_1_0_bits_T_92 = or(_io_out_1_0_bits_T_91, _io_out_1_0_bits_T_87) node _io_out_1_0_bits_T_93 = or(_io_out_1_0_bits_T_92, _io_out_1_0_bits_T_88) wire _io_out_1_0_bits_WIRE_9 : UInt<1> connect _io_out_1_0_bits_WIRE_9, _io_out_1_0_bits_T_93 connect _io_out_1_0_bits_WIRE.tail, _io_out_1_0_bits_WIRE_9 node _io_out_1_0_bits_T_94 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_95 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_96 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_97 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_98 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_99 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_100 = or(_io_out_1_0_bits_T_94, _io_out_1_0_bits_T_95) node _io_out_1_0_bits_T_101 = or(_io_out_1_0_bits_T_100, _io_out_1_0_bits_T_96) node _io_out_1_0_bits_T_102 = or(_io_out_1_0_bits_T_101, _io_out_1_0_bits_T_97) node _io_out_1_0_bits_T_103 = or(_io_out_1_0_bits_T_102, _io_out_1_0_bits_T_98) node _io_out_1_0_bits_T_104 = or(_io_out_1_0_bits_T_103, _io_out_1_0_bits_T_99) wire _io_out_1_0_bits_WIRE_10 : UInt<1> connect _io_out_1_0_bits_WIRE_10, _io_out_1_0_bits_T_104 connect _io_out_1_0_bits_WIRE.head, _io_out_1_0_bits_WIRE_10 connect io.out.`1`[0].bits, _io_out_1_0_bits_WIRE node _io_out_1_0_bits_virt_channel_id_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_virt_channel_id_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_virt_channel_id_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_bits_virt_channel_id_T_3 = bits(sel_flat_1, 3, 3) node _io_out_1_0_bits_virt_channel_id_T_4 = bits(sel_flat_1, 4, 4) node _io_out_1_0_bits_virt_channel_id_T_5 = bits(sel_flat_1, 5, 5) node _io_out_1_0_bits_virt_channel_id_T_6 = mux(_io_out_1_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_7 = mux(_io_out_1_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_8 = mux(_io_out_1_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_9 = mux(_io_out_1_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_10 = mux(_io_out_1_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_11 = mux(_io_out_1_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_12 = or(_io_out_1_0_bits_virt_channel_id_T_6, _io_out_1_0_bits_virt_channel_id_T_7) node _io_out_1_0_bits_virt_channel_id_T_13 = or(_io_out_1_0_bits_virt_channel_id_T_12, _io_out_1_0_bits_virt_channel_id_T_8) node _io_out_1_0_bits_virt_channel_id_T_14 = or(_io_out_1_0_bits_virt_channel_id_T_13, _io_out_1_0_bits_virt_channel_id_T_9) node _io_out_1_0_bits_virt_channel_id_T_15 = or(_io_out_1_0_bits_virt_channel_id_T_14, _io_out_1_0_bits_virt_channel_id_T_10) node _io_out_1_0_bits_virt_channel_id_T_16 = or(_io_out_1_0_bits_virt_channel_id_T_15, _io_out_1_0_bits_virt_channel_id_T_11) wire _io_out_1_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_1_0_bits_virt_channel_id_WIRE, _io_out_1_0_bits_virt_channel_id_T_16 connect io.out.`1`[0].bits.virt_channel_id, _io_out_1_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_2 = cat(io.sel.`2`[0].`2`[0], io.sel.`2`[0].`1`[0]) node sel_flat_lo_2 = cat(sel_flat_lo_hi_2, io.sel.`2`[0].`0`[0]) node sel_flat_hi_hi_2 = cat(io.sel.`2`[0].`5`[0], io.sel.`2`[0].`4`[0]) node sel_flat_hi_2 = cat(sel_flat_hi_hi_2, io.sel.`2`[0].`3`[0]) node sel_flat_2 = cat(sel_flat_hi_2, sel_flat_lo_2) node _T_40 = bits(sel_flat_2, 0, 0) node _T_41 = bits(sel_flat_2, 1, 1) node _T_42 = bits(sel_flat_2, 2, 2) node _T_43 = bits(sel_flat_2, 3, 3) node _T_44 = bits(sel_flat_2, 4, 4) node _T_45 = bits(sel_flat_2, 5, 5) node _T_46 = add(_T_41, _T_42) node _T_47 = bits(_T_46, 1, 0) node _T_48 = add(_T_40, _T_47) node _T_49 = bits(_T_48, 1, 0) node _T_50 = add(_T_44, _T_45) node _T_51 = bits(_T_50, 1, 0) node _T_52 = add(_T_43, _T_51) node _T_53 = bits(_T_52, 1, 0) node _T_54 = add(_T_49, _T_53) node _T_55 = bits(_T_54, 2, 0) node _T_56 = leq(_T_55, UInt<1>(0h1)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_2 assert(clock, _T_56, UInt<1>(0h1), "") : assert_2 node _io_out_2_0_valid_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_valid_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_valid_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_valid_T_3 = bits(sel_flat_2, 3, 3) node _io_out_2_0_valid_T_4 = bits(sel_flat_2, 4, 4) node _io_out_2_0_valid_T_5 = bits(sel_flat_2, 5, 5) node _io_out_2_0_valid_T_6 = mux(_io_out_2_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_7 = mux(_io_out_2_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_8 = mux(_io_out_2_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_9 = mux(_io_out_2_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_10 = mux(_io_out_2_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_11 = mux(_io_out_2_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_12 = or(_io_out_2_0_valid_T_6, _io_out_2_0_valid_T_7) node _io_out_2_0_valid_T_13 = or(_io_out_2_0_valid_T_12, _io_out_2_0_valid_T_8) node _io_out_2_0_valid_T_14 = or(_io_out_2_0_valid_T_13, _io_out_2_0_valid_T_9) node _io_out_2_0_valid_T_15 = or(_io_out_2_0_valid_T_14, _io_out_2_0_valid_T_10) node _io_out_2_0_valid_T_16 = or(_io_out_2_0_valid_T_15, _io_out_2_0_valid_T_11) wire _io_out_2_0_valid_WIRE : UInt<1> connect _io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_16 node _io_out_2_0_valid_T_17 = neq(sel_flat_2, UInt<1>(0h0)) node _io_out_2_0_valid_T_18 = and(_io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_17) connect io.out.`2`[0].valid, _io_out_2_0_valid_T_18 node _io_out_2_0_bits_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_bits_T_3 = bits(sel_flat_2, 3, 3) node _io_out_2_0_bits_T_4 = bits(sel_flat_2, 4, 4) node _io_out_2_0_bits_T_5 = bits(sel_flat_2, 5, 5) wire _io_out_2_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_2_0_bits_T_6 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_7 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_8 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_9 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_10 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_11 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_12 = or(_io_out_2_0_bits_T_6, _io_out_2_0_bits_T_7) node _io_out_2_0_bits_T_13 = or(_io_out_2_0_bits_T_12, _io_out_2_0_bits_T_8) node _io_out_2_0_bits_T_14 = or(_io_out_2_0_bits_T_13, _io_out_2_0_bits_T_9) node _io_out_2_0_bits_T_15 = or(_io_out_2_0_bits_T_14, _io_out_2_0_bits_T_10) node _io_out_2_0_bits_T_16 = or(_io_out_2_0_bits_T_15, _io_out_2_0_bits_T_11) wire _io_out_2_0_bits_WIRE_1 : UInt<4> connect _io_out_2_0_bits_WIRE_1, _io_out_2_0_bits_T_16 connect _io_out_2_0_bits_WIRE.virt_channel_id, _io_out_2_0_bits_WIRE_1 wire _io_out_2_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_2_0_bits_T_17 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_18 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_19 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_20 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_21 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_22 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_23 = or(_io_out_2_0_bits_T_17, _io_out_2_0_bits_T_18) node _io_out_2_0_bits_T_24 = or(_io_out_2_0_bits_T_23, _io_out_2_0_bits_T_19) node _io_out_2_0_bits_T_25 = or(_io_out_2_0_bits_T_24, _io_out_2_0_bits_T_20) node _io_out_2_0_bits_T_26 = or(_io_out_2_0_bits_T_25, _io_out_2_0_bits_T_21) node _io_out_2_0_bits_T_27 = or(_io_out_2_0_bits_T_26, _io_out_2_0_bits_T_22) wire _io_out_2_0_bits_WIRE_3 : UInt<3> connect _io_out_2_0_bits_WIRE_3, _io_out_2_0_bits_T_27 connect _io_out_2_0_bits_WIRE_2.egress_node_id, _io_out_2_0_bits_WIRE_3 node _io_out_2_0_bits_T_28 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_29 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_30 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_31 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_32 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_33 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_34 = or(_io_out_2_0_bits_T_28, _io_out_2_0_bits_T_29) node _io_out_2_0_bits_T_35 = or(_io_out_2_0_bits_T_34, _io_out_2_0_bits_T_30) node _io_out_2_0_bits_T_36 = or(_io_out_2_0_bits_T_35, _io_out_2_0_bits_T_31) node _io_out_2_0_bits_T_37 = or(_io_out_2_0_bits_T_36, _io_out_2_0_bits_T_32) node _io_out_2_0_bits_T_38 = or(_io_out_2_0_bits_T_37, _io_out_2_0_bits_T_33) wire _io_out_2_0_bits_WIRE_4 : UInt<4> connect _io_out_2_0_bits_WIRE_4, _io_out_2_0_bits_T_38 connect _io_out_2_0_bits_WIRE_2.egress_node, _io_out_2_0_bits_WIRE_4 node _io_out_2_0_bits_T_39 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_40 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_41 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_42 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_43 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_44 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_45 = or(_io_out_2_0_bits_T_39, _io_out_2_0_bits_T_40) node _io_out_2_0_bits_T_46 = or(_io_out_2_0_bits_T_45, _io_out_2_0_bits_T_41) node _io_out_2_0_bits_T_47 = or(_io_out_2_0_bits_T_46, _io_out_2_0_bits_T_42) node _io_out_2_0_bits_T_48 = or(_io_out_2_0_bits_T_47, _io_out_2_0_bits_T_43) node _io_out_2_0_bits_T_49 = or(_io_out_2_0_bits_T_48, _io_out_2_0_bits_T_44) wire _io_out_2_0_bits_WIRE_5 : UInt<3> connect _io_out_2_0_bits_WIRE_5, _io_out_2_0_bits_T_49 connect _io_out_2_0_bits_WIRE_2.ingress_node_id, _io_out_2_0_bits_WIRE_5 node _io_out_2_0_bits_T_50 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_51 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_52 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_53 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_54 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_55 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_56 = or(_io_out_2_0_bits_T_50, _io_out_2_0_bits_T_51) node _io_out_2_0_bits_T_57 = or(_io_out_2_0_bits_T_56, _io_out_2_0_bits_T_52) node _io_out_2_0_bits_T_58 = or(_io_out_2_0_bits_T_57, _io_out_2_0_bits_T_53) node _io_out_2_0_bits_T_59 = or(_io_out_2_0_bits_T_58, _io_out_2_0_bits_T_54) node _io_out_2_0_bits_T_60 = or(_io_out_2_0_bits_T_59, _io_out_2_0_bits_T_55) wire _io_out_2_0_bits_WIRE_6 : UInt<4> connect _io_out_2_0_bits_WIRE_6, _io_out_2_0_bits_T_60 connect _io_out_2_0_bits_WIRE_2.ingress_node, _io_out_2_0_bits_WIRE_6 node _io_out_2_0_bits_T_61 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_62 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_63 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_64 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_65 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_66 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_67 = or(_io_out_2_0_bits_T_61, _io_out_2_0_bits_T_62) node _io_out_2_0_bits_T_68 = or(_io_out_2_0_bits_T_67, _io_out_2_0_bits_T_63) node _io_out_2_0_bits_T_69 = or(_io_out_2_0_bits_T_68, _io_out_2_0_bits_T_64) node _io_out_2_0_bits_T_70 = or(_io_out_2_0_bits_T_69, _io_out_2_0_bits_T_65) node _io_out_2_0_bits_T_71 = or(_io_out_2_0_bits_T_70, _io_out_2_0_bits_T_66) wire _io_out_2_0_bits_WIRE_7 : UInt<3> connect _io_out_2_0_bits_WIRE_7, _io_out_2_0_bits_T_71 connect _io_out_2_0_bits_WIRE_2.vnet_id, _io_out_2_0_bits_WIRE_7 connect _io_out_2_0_bits_WIRE.flow, _io_out_2_0_bits_WIRE_2 node _io_out_2_0_bits_T_72 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_73 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_74 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_75 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_76 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_77 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_78 = or(_io_out_2_0_bits_T_72, _io_out_2_0_bits_T_73) node _io_out_2_0_bits_T_79 = or(_io_out_2_0_bits_T_78, _io_out_2_0_bits_T_74) node _io_out_2_0_bits_T_80 = or(_io_out_2_0_bits_T_79, _io_out_2_0_bits_T_75) node _io_out_2_0_bits_T_81 = or(_io_out_2_0_bits_T_80, _io_out_2_0_bits_T_76) node _io_out_2_0_bits_T_82 = or(_io_out_2_0_bits_T_81, _io_out_2_0_bits_T_77) wire _io_out_2_0_bits_WIRE_8 : UInt<73> connect _io_out_2_0_bits_WIRE_8, _io_out_2_0_bits_T_82 connect _io_out_2_0_bits_WIRE.payload, _io_out_2_0_bits_WIRE_8 node _io_out_2_0_bits_T_83 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_84 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_85 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_86 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_87 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_88 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_89 = or(_io_out_2_0_bits_T_83, _io_out_2_0_bits_T_84) node _io_out_2_0_bits_T_90 = or(_io_out_2_0_bits_T_89, _io_out_2_0_bits_T_85) node _io_out_2_0_bits_T_91 = or(_io_out_2_0_bits_T_90, _io_out_2_0_bits_T_86) node _io_out_2_0_bits_T_92 = or(_io_out_2_0_bits_T_91, _io_out_2_0_bits_T_87) node _io_out_2_0_bits_T_93 = or(_io_out_2_0_bits_T_92, _io_out_2_0_bits_T_88) wire _io_out_2_0_bits_WIRE_9 : UInt<1> connect _io_out_2_0_bits_WIRE_9, _io_out_2_0_bits_T_93 connect _io_out_2_0_bits_WIRE.tail, _io_out_2_0_bits_WIRE_9 node _io_out_2_0_bits_T_94 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_95 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_96 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_97 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_98 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_99 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_100 = or(_io_out_2_0_bits_T_94, _io_out_2_0_bits_T_95) node _io_out_2_0_bits_T_101 = or(_io_out_2_0_bits_T_100, _io_out_2_0_bits_T_96) node _io_out_2_0_bits_T_102 = or(_io_out_2_0_bits_T_101, _io_out_2_0_bits_T_97) node _io_out_2_0_bits_T_103 = or(_io_out_2_0_bits_T_102, _io_out_2_0_bits_T_98) node _io_out_2_0_bits_T_104 = or(_io_out_2_0_bits_T_103, _io_out_2_0_bits_T_99) wire _io_out_2_0_bits_WIRE_10 : UInt<1> connect _io_out_2_0_bits_WIRE_10, _io_out_2_0_bits_T_104 connect _io_out_2_0_bits_WIRE.head, _io_out_2_0_bits_WIRE_10 connect io.out.`2`[0].bits, _io_out_2_0_bits_WIRE node _io_out_2_0_bits_virt_channel_id_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_virt_channel_id_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_virt_channel_id_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_bits_virt_channel_id_T_3 = bits(sel_flat_2, 3, 3) node _io_out_2_0_bits_virt_channel_id_T_4 = bits(sel_flat_2, 4, 4) node _io_out_2_0_bits_virt_channel_id_T_5 = bits(sel_flat_2, 5, 5) node _io_out_2_0_bits_virt_channel_id_T_6 = mux(_io_out_2_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_7 = mux(_io_out_2_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_8 = mux(_io_out_2_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_9 = mux(_io_out_2_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_10 = mux(_io_out_2_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_11 = mux(_io_out_2_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_12 = or(_io_out_2_0_bits_virt_channel_id_T_6, _io_out_2_0_bits_virt_channel_id_T_7) node _io_out_2_0_bits_virt_channel_id_T_13 = or(_io_out_2_0_bits_virt_channel_id_T_12, _io_out_2_0_bits_virt_channel_id_T_8) node _io_out_2_0_bits_virt_channel_id_T_14 = or(_io_out_2_0_bits_virt_channel_id_T_13, _io_out_2_0_bits_virt_channel_id_T_9) node _io_out_2_0_bits_virt_channel_id_T_15 = or(_io_out_2_0_bits_virt_channel_id_T_14, _io_out_2_0_bits_virt_channel_id_T_10) node _io_out_2_0_bits_virt_channel_id_T_16 = or(_io_out_2_0_bits_virt_channel_id_T_15, _io_out_2_0_bits_virt_channel_id_T_11) wire _io_out_2_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_2_0_bits_virt_channel_id_WIRE, _io_out_2_0_bits_virt_channel_id_T_16 connect io.out.`2`[0].bits.virt_channel_id, _io_out_2_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_3 = cat(io.sel.`3`[0].`2`[0], io.sel.`3`[0].`1`[0]) node sel_flat_lo_3 = cat(sel_flat_lo_hi_3, io.sel.`3`[0].`0`[0]) node sel_flat_hi_hi_3 = cat(io.sel.`3`[0].`5`[0], io.sel.`3`[0].`4`[0]) node sel_flat_hi_3 = cat(sel_flat_hi_hi_3, io.sel.`3`[0].`3`[0]) node sel_flat_3 = cat(sel_flat_hi_3, sel_flat_lo_3) node _T_60 = bits(sel_flat_3, 0, 0) node _T_61 = bits(sel_flat_3, 1, 1) node _T_62 = bits(sel_flat_3, 2, 2) node _T_63 = bits(sel_flat_3, 3, 3) node _T_64 = bits(sel_flat_3, 4, 4) node _T_65 = bits(sel_flat_3, 5, 5) node _T_66 = add(_T_61, _T_62) node _T_67 = bits(_T_66, 1, 0) node _T_68 = add(_T_60, _T_67) node _T_69 = bits(_T_68, 1, 0) node _T_70 = add(_T_64, _T_65) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(_T_63, _T_71) node _T_73 = bits(_T_72, 1, 0) node _T_74 = add(_T_69, _T_73) node _T_75 = bits(_T_74, 2, 0) node _T_76 = leq(_T_75, UInt<1>(0h1)) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_3 assert(clock, _T_76, UInt<1>(0h1), "") : assert_3 node _io_out_3_0_valid_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_valid_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_valid_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_valid_T_3 = bits(sel_flat_3, 3, 3) node _io_out_3_0_valid_T_4 = bits(sel_flat_3, 4, 4) node _io_out_3_0_valid_T_5 = bits(sel_flat_3, 5, 5) node _io_out_3_0_valid_T_6 = mux(_io_out_3_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_7 = mux(_io_out_3_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_8 = mux(_io_out_3_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_9 = mux(_io_out_3_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_10 = mux(_io_out_3_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_11 = mux(_io_out_3_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_12 = or(_io_out_3_0_valid_T_6, _io_out_3_0_valid_T_7) node _io_out_3_0_valid_T_13 = or(_io_out_3_0_valid_T_12, _io_out_3_0_valid_T_8) node _io_out_3_0_valid_T_14 = or(_io_out_3_0_valid_T_13, _io_out_3_0_valid_T_9) node _io_out_3_0_valid_T_15 = or(_io_out_3_0_valid_T_14, _io_out_3_0_valid_T_10) node _io_out_3_0_valid_T_16 = or(_io_out_3_0_valid_T_15, _io_out_3_0_valid_T_11) wire _io_out_3_0_valid_WIRE : UInt<1> connect _io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_16 node _io_out_3_0_valid_T_17 = neq(sel_flat_3, UInt<1>(0h0)) node _io_out_3_0_valid_T_18 = and(_io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_17) connect io.out.`3`[0].valid, _io_out_3_0_valid_T_18 node _io_out_3_0_bits_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_bits_T_3 = bits(sel_flat_3, 3, 3) node _io_out_3_0_bits_T_4 = bits(sel_flat_3, 4, 4) node _io_out_3_0_bits_T_5 = bits(sel_flat_3, 5, 5) wire _io_out_3_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_3_0_bits_T_6 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_7 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_8 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_9 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_10 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_11 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_12 = or(_io_out_3_0_bits_T_6, _io_out_3_0_bits_T_7) node _io_out_3_0_bits_T_13 = or(_io_out_3_0_bits_T_12, _io_out_3_0_bits_T_8) node _io_out_3_0_bits_T_14 = or(_io_out_3_0_bits_T_13, _io_out_3_0_bits_T_9) node _io_out_3_0_bits_T_15 = or(_io_out_3_0_bits_T_14, _io_out_3_0_bits_T_10) node _io_out_3_0_bits_T_16 = or(_io_out_3_0_bits_T_15, _io_out_3_0_bits_T_11) wire _io_out_3_0_bits_WIRE_1 : UInt<4> connect _io_out_3_0_bits_WIRE_1, _io_out_3_0_bits_T_16 connect _io_out_3_0_bits_WIRE.virt_channel_id, _io_out_3_0_bits_WIRE_1 wire _io_out_3_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_3_0_bits_T_17 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_18 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_19 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_20 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_21 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_22 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_23 = or(_io_out_3_0_bits_T_17, _io_out_3_0_bits_T_18) node _io_out_3_0_bits_T_24 = or(_io_out_3_0_bits_T_23, _io_out_3_0_bits_T_19) node _io_out_3_0_bits_T_25 = or(_io_out_3_0_bits_T_24, _io_out_3_0_bits_T_20) node _io_out_3_0_bits_T_26 = or(_io_out_3_0_bits_T_25, _io_out_3_0_bits_T_21) node _io_out_3_0_bits_T_27 = or(_io_out_3_0_bits_T_26, _io_out_3_0_bits_T_22) wire _io_out_3_0_bits_WIRE_3 : UInt<3> connect _io_out_3_0_bits_WIRE_3, _io_out_3_0_bits_T_27 connect _io_out_3_0_bits_WIRE_2.egress_node_id, _io_out_3_0_bits_WIRE_3 node _io_out_3_0_bits_T_28 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_29 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_30 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_31 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_32 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_33 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_34 = or(_io_out_3_0_bits_T_28, _io_out_3_0_bits_T_29) node _io_out_3_0_bits_T_35 = or(_io_out_3_0_bits_T_34, _io_out_3_0_bits_T_30) node _io_out_3_0_bits_T_36 = or(_io_out_3_0_bits_T_35, _io_out_3_0_bits_T_31) node _io_out_3_0_bits_T_37 = or(_io_out_3_0_bits_T_36, _io_out_3_0_bits_T_32) node _io_out_3_0_bits_T_38 = or(_io_out_3_0_bits_T_37, _io_out_3_0_bits_T_33) wire _io_out_3_0_bits_WIRE_4 : UInt<4> connect _io_out_3_0_bits_WIRE_4, _io_out_3_0_bits_T_38 connect _io_out_3_0_bits_WIRE_2.egress_node, _io_out_3_0_bits_WIRE_4 node _io_out_3_0_bits_T_39 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_40 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_41 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_42 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_43 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_44 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_45 = or(_io_out_3_0_bits_T_39, _io_out_3_0_bits_T_40) node _io_out_3_0_bits_T_46 = or(_io_out_3_0_bits_T_45, _io_out_3_0_bits_T_41) node _io_out_3_0_bits_T_47 = or(_io_out_3_0_bits_T_46, _io_out_3_0_bits_T_42) node _io_out_3_0_bits_T_48 = or(_io_out_3_0_bits_T_47, _io_out_3_0_bits_T_43) node _io_out_3_0_bits_T_49 = or(_io_out_3_0_bits_T_48, _io_out_3_0_bits_T_44) wire _io_out_3_0_bits_WIRE_5 : UInt<3> connect _io_out_3_0_bits_WIRE_5, _io_out_3_0_bits_T_49 connect _io_out_3_0_bits_WIRE_2.ingress_node_id, _io_out_3_0_bits_WIRE_5 node _io_out_3_0_bits_T_50 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_51 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_52 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_53 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_54 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_55 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_56 = or(_io_out_3_0_bits_T_50, _io_out_3_0_bits_T_51) node _io_out_3_0_bits_T_57 = or(_io_out_3_0_bits_T_56, _io_out_3_0_bits_T_52) node _io_out_3_0_bits_T_58 = or(_io_out_3_0_bits_T_57, _io_out_3_0_bits_T_53) node _io_out_3_0_bits_T_59 = or(_io_out_3_0_bits_T_58, _io_out_3_0_bits_T_54) node _io_out_3_0_bits_T_60 = or(_io_out_3_0_bits_T_59, _io_out_3_0_bits_T_55) wire _io_out_3_0_bits_WIRE_6 : UInt<4> connect _io_out_3_0_bits_WIRE_6, _io_out_3_0_bits_T_60 connect _io_out_3_0_bits_WIRE_2.ingress_node, _io_out_3_0_bits_WIRE_6 node _io_out_3_0_bits_T_61 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_62 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_63 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_64 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_65 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_66 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_67 = or(_io_out_3_0_bits_T_61, _io_out_3_0_bits_T_62) node _io_out_3_0_bits_T_68 = or(_io_out_3_0_bits_T_67, _io_out_3_0_bits_T_63) node _io_out_3_0_bits_T_69 = or(_io_out_3_0_bits_T_68, _io_out_3_0_bits_T_64) node _io_out_3_0_bits_T_70 = or(_io_out_3_0_bits_T_69, _io_out_3_0_bits_T_65) node _io_out_3_0_bits_T_71 = or(_io_out_3_0_bits_T_70, _io_out_3_0_bits_T_66) wire _io_out_3_0_bits_WIRE_7 : UInt<3> connect _io_out_3_0_bits_WIRE_7, _io_out_3_0_bits_T_71 connect _io_out_3_0_bits_WIRE_2.vnet_id, _io_out_3_0_bits_WIRE_7 connect _io_out_3_0_bits_WIRE.flow, _io_out_3_0_bits_WIRE_2 node _io_out_3_0_bits_T_72 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_73 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_74 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_75 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_76 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_77 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_78 = or(_io_out_3_0_bits_T_72, _io_out_3_0_bits_T_73) node _io_out_3_0_bits_T_79 = or(_io_out_3_0_bits_T_78, _io_out_3_0_bits_T_74) node _io_out_3_0_bits_T_80 = or(_io_out_3_0_bits_T_79, _io_out_3_0_bits_T_75) node _io_out_3_0_bits_T_81 = or(_io_out_3_0_bits_T_80, _io_out_3_0_bits_T_76) node _io_out_3_0_bits_T_82 = or(_io_out_3_0_bits_T_81, _io_out_3_0_bits_T_77) wire _io_out_3_0_bits_WIRE_8 : UInt<73> connect _io_out_3_0_bits_WIRE_8, _io_out_3_0_bits_T_82 connect _io_out_3_0_bits_WIRE.payload, _io_out_3_0_bits_WIRE_8 node _io_out_3_0_bits_T_83 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_84 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_85 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_86 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_87 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_88 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_89 = or(_io_out_3_0_bits_T_83, _io_out_3_0_bits_T_84) node _io_out_3_0_bits_T_90 = or(_io_out_3_0_bits_T_89, _io_out_3_0_bits_T_85) node _io_out_3_0_bits_T_91 = or(_io_out_3_0_bits_T_90, _io_out_3_0_bits_T_86) node _io_out_3_0_bits_T_92 = or(_io_out_3_0_bits_T_91, _io_out_3_0_bits_T_87) node _io_out_3_0_bits_T_93 = or(_io_out_3_0_bits_T_92, _io_out_3_0_bits_T_88) wire _io_out_3_0_bits_WIRE_9 : UInt<1> connect _io_out_3_0_bits_WIRE_9, _io_out_3_0_bits_T_93 connect _io_out_3_0_bits_WIRE.tail, _io_out_3_0_bits_WIRE_9 node _io_out_3_0_bits_T_94 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_95 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_96 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_97 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_98 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_99 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_100 = or(_io_out_3_0_bits_T_94, _io_out_3_0_bits_T_95) node _io_out_3_0_bits_T_101 = or(_io_out_3_0_bits_T_100, _io_out_3_0_bits_T_96) node _io_out_3_0_bits_T_102 = or(_io_out_3_0_bits_T_101, _io_out_3_0_bits_T_97) node _io_out_3_0_bits_T_103 = or(_io_out_3_0_bits_T_102, _io_out_3_0_bits_T_98) node _io_out_3_0_bits_T_104 = or(_io_out_3_0_bits_T_103, _io_out_3_0_bits_T_99) wire _io_out_3_0_bits_WIRE_10 : UInt<1> connect _io_out_3_0_bits_WIRE_10, _io_out_3_0_bits_T_104 connect _io_out_3_0_bits_WIRE.head, _io_out_3_0_bits_WIRE_10 connect io.out.`3`[0].bits, _io_out_3_0_bits_WIRE node _io_out_3_0_bits_virt_channel_id_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_virt_channel_id_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_virt_channel_id_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_bits_virt_channel_id_T_3 = bits(sel_flat_3, 3, 3) node _io_out_3_0_bits_virt_channel_id_T_4 = bits(sel_flat_3, 4, 4) node _io_out_3_0_bits_virt_channel_id_T_5 = bits(sel_flat_3, 5, 5) node _io_out_3_0_bits_virt_channel_id_T_6 = mux(_io_out_3_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_7 = mux(_io_out_3_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_8 = mux(_io_out_3_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_9 = mux(_io_out_3_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_10 = mux(_io_out_3_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_11 = mux(_io_out_3_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_12 = or(_io_out_3_0_bits_virt_channel_id_T_6, _io_out_3_0_bits_virt_channel_id_T_7) node _io_out_3_0_bits_virt_channel_id_T_13 = or(_io_out_3_0_bits_virt_channel_id_T_12, _io_out_3_0_bits_virt_channel_id_T_8) node _io_out_3_0_bits_virt_channel_id_T_14 = or(_io_out_3_0_bits_virt_channel_id_T_13, _io_out_3_0_bits_virt_channel_id_T_9) node _io_out_3_0_bits_virt_channel_id_T_15 = or(_io_out_3_0_bits_virt_channel_id_T_14, _io_out_3_0_bits_virt_channel_id_T_10) node _io_out_3_0_bits_virt_channel_id_T_16 = or(_io_out_3_0_bits_virt_channel_id_T_15, _io_out_3_0_bits_virt_channel_id_T_11) wire _io_out_3_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_3_0_bits_virt_channel_id_WIRE, _io_out_3_0_bits_virt_channel_id_T_16 connect io.out.`3`[0].bits.virt_channel_id, _io_out_3_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_4 = cat(io.sel.`4`[0].`2`[0], io.sel.`4`[0].`1`[0]) node sel_flat_lo_4 = cat(sel_flat_lo_hi_4, io.sel.`4`[0].`0`[0]) node sel_flat_hi_hi_4 = cat(io.sel.`4`[0].`5`[0], io.sel.`4`[0].`4`[0]) node sel_flat_hi_4 = cat(sel_flat_hi_hi_4, io.sel.`4`[0].`3`[0]) node sel_flat_4 = cat(sel_flat_hi_4, sel_flat_lo_4) node _T_80 = bits(sel_flat_4, 0, 0) node _T_81 = bits(sel_flat_4, 1, 1) node _T_82 = bits(sel_flat_4, 2, 2) node _T_83 = bits(sel_flat_4, 3, 3) node _T_84 = bits(sel_flat_4, 4, 4) node _T_85 = bits(sel_flat_4, 5, 5) node _T_86 = add(_T_81, _T_82) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(_T_80, _T_87) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_84, _T_85) node _T_91 = bits(_T_90, 1, 0) node _T_92 = add(_T_83, _T_91) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_89, _T_93) node _T_95 = bits(_T_94, 2, 0) node _T_96 = leq(_T_95, UInt<1>(0h1)) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_4 assert(clock, _T_96, UInt<1>(0h1), "") : assert_4 node _io_out_4_0_valid_T = bits(sel_flat_4, 0, 0) node _io_out_4_0_valid_T_1 = bits(sel_flat_4, 1, 1) node _io_out_4_0_valid_T_2 = bits(sel_flat_4, 2, 2) node _io_out_4_0_valid_T_3 = bits(sel_flat_4, 3, 3) node _io_out_4_0_valid_T_4 = bits(sel_flat_4, 4, 4) node _io_out_4_0_valid_T_5 = bits(sel_flat_4, 5, 5) node _io_out_4_0_valid_T_6 = mux(_io_out_4_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_7 = mux(_io_out_4_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_8 = mux(_io_out_4_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_9 = mux(_io_out_4_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_10 = mux(_io_out_4_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_11 = mux(_io_out_4_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_12 = or(_io_out_4_0_valid_T_6, _io_out_4_0_valid_T_7) node _io_out_4_0_valid_T_13 = or(_io_out_4_0_valid_T_12, _io_out_4_0_valid_T_8) node _io_out_4_0_valid_T_14 = or(_io_out_4_0_valid_T_13, _io_out_4_0_valid_T_9) node _io_out_4_0_valid_T_15 = or(_io_out_4_0_valid_T_14, _io_out_4_0_valid_T_10) node _io_out_4_0_valid_T_16 = or(_io_out_4_0_valid_T_15, _io_out_4_0_valid_T_11) wire _io_out_4_0_valid_WIRE : UInt<1> connect _io_out_4_0_valid_WIRE, _io_out_4_0_valid_T_16 node _io_out_4_0_valid_T_17 = neq(sel_flat_4, UInt<1>(0h0)) node _io_out_4_0_valid_T_18 = and(_io_out_4_0_valid_WIRE, _io_out_4_0_valid_T_17) connect io.out.`4`[0].valid, _io_out_4_0_valid_T_18 node _io_out_4_0_bits_T = bits(sel_flat_4, 0, 0) node _io_out_4_0_bits_T_1 = bits(sel_flat_4, 1, 1) node _io_out_4_0_bits_T_2 = bits(sel_flat_4, 2, 2) node _io_out_4_0_bits_T_3 = bits(sel_flat_4, 3, 3) node _io_out_4_0_bits_T_4 = bits(sel_flat_4, 4, 4) node _io_out_4_0_bits_T_5 = bits(sel_flat_4, 5, 5) wire _io_out_4_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_4_0_bits_T_6 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_7 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_8 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_9 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_10 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_11 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_12 = or(_io_out_4_0_bits_T_6, _io_out_4_0_bits_T_7) node _io_out_4_0_bits_T_13 = or(_io_out_4_0_bits_T_12, _io_out_4_0_bits_T_8) node _io_out_4_0_bits_T_14 = or(_io_out_4_0_bits_T_13, _io_out_4_0_bits_T_9) node _io_out_4_0_bits_T_15 = or(_io_out_4_0_bits_T_14, _io_out_4_0_bits_T_10) node _io_out_4_0_bits_T_16 = or(_io_out_4_0_bits_T_15, _io_out_4_0_bits_T_11) wire _io_out_4_0_bits_WIRE_1 : UInt<4> connect _io_out_4_0_bits_WIRE_1, _io_out_4_0_bits_T_16 connect _io_out_4_0_bits_WIRE.virt_channel_id, _io_out_4_0_bits_WIRE_1 wire _io_out_4_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_4_0_bits_T_17 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_18 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_19 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_20 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_21 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_22 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_23 = or(_io_out_4_0_bits_T_17, _io_out_4_0_bits_T_18) node _io_out_4_0_bits_T_24 = or(_io_out_4_0_bits_T_23, _io_out_4_0_bits_T_19) node _io_out_4_0_bits_T_25 = or(_io_out_4_0_bits_T_24, _io_out_4_0_bits_T_20) node _io_out_4_0_bits_T_26 = or(_io_out_4_0_bits_T_25, _io_out_4_0_bits_T_21) node _io_out_4_0_bits_T_27 = or(_io_out_4_0_bits_T_26, _io_out_4_0_bits_T_22) wire _io_out_4_0_bits_WIRE_3 : UInt<3> connect _io_out_4_0_bits_WIRE_3, _io_out_4_0_bits_T_27 connect _io_out_4_0_bits_WIRE_2.egress_node_id, _io_out_4_0_bits_WIRE_3 node _io_out_4_0_bits_T_28 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_29 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_30 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_31 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_32 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_33 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_34 = or(_io_out_4_0_bits_T_28, _io_out_4_0_bits_T_29) node _io_out_4_0_bits_T_35 = or(_io_out_4_0_bits_T_34, _io_out_4_0_bits_T_30) node _io_out_4_0_bits_T_36 = or(_io_out_4_0_bits_T_35, _io_out_4_0_bits_T_31) node _io_out_4_0_bits_T_37 = or(_io_out_4_0_bits_T_36, _io_out_4_0_bits_T_32) node _io_out_4_0_bits_T_38 = or(_io_out_4_0_bits_T_37, _io_out_4_0_bits_T_33) wire _io_out_4_0_bits_WIRE_4 : UInt<4> connect _io_out_4_0_bits_WIRE_4, _io_out_4_0_bits_T_38 connect _io_out_4_0_bits_WIRE_2.egress_node, _io_out_4_0_bits_WIRE_4 node _io_out_4_0_bits_T_39 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_40 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_41 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_42 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_43 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_44 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_45 = or(_io_out_4_0_bits_T_39, _io_out_4_0_bits_T_40) node _io_out_4_0_bits_T_46 = or(_io_out_4_0_bits_T_45, _io_out_4_0_bits_T_41) node _io_out_4_0_bits_T_47 = or(_io_out_4_0_bits_T_46, _io_out_4_0_bits_T_42) node _io_out_4_0_bits_T_48 = or(_io_out_4_0_bits_T_47, _io_out_4_0_bits_T_43) node _io_out_4_0_bits_T_49 = or(_io_out_4_0_bits_T_48, _io_out_4_0_bits_T_44) wire _io_out_4_0_bits_WIRE_5 : UInt<3> connect _io_out_4_0_bits_WIRE_5, _io_out_4_0_bits_T_49 connect _io_out_4_0_bits_WIRE_2.ingress_node_id, _io_out_4_0_bits_WIRE_5 node _io_out_4_0_bits_T_50 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_51 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_52 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_53 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_54 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_55 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_56 = or(_io_out_4_0_bits_T_50, _io_out_4_0_bits_T_51) node _io_out_4_0_bits_T_57 = or(_io_out_4_0_bits_T_56, _io_out_4_0_bits_T_52) node _io_out_4_0_bits_T_58 = or(_io_out_4_0_bits_T_57, _io_out_4_0_bits_T_53) node _io_out_4_0_bits_T_59 = or(_io_out_4_0_bits_T_58, _io_out_4_0_bits_T_54) node _io_out_4_0_bits_T_60 = or(_io_out_4_0_bits_T_59, _io_out_4_0_bits_T_55) wire _io_out_4_0_bits_WIRE_6 : UInt<4> connect _io_out_4_0_bits_WIRE_6, _io_out_4_0_bits_T_60 connect _io_out_4_0_bits_WIRE_2.ingress_node, _io_out_4_0_bits_WIRE_6 node _io_out_4_0_bits_T_61 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_62 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_63 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_64 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_65 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_66 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_67 = or(_io_out_4_0_bits_T_61, _io_out_4_0_bits_T_62) node _io_out_4_0_bits_T_68 = or(_io_out_4_0_bits_T_67, _io_out_4_0_bits_T_63) node _io_out_4_0_bits_T_69 = or(_io_out_4_0_bits_T_68, _io_out_4_0_bits_T_64) node _io_out_4_0_bits_T_70 = or(_io_out_4_0_bits_T_69, _io_out_4_0_bits_T_65) node _io_out_4_0_bits_T_71 = or(_io_out_4_0_bits_T_70, _io_out_4_0_bits_T_66) wire _io_out_4_0_bits_WIRE_7 : UInt<3> connect _io_out_4_0_bits_WIRE_7, _io_out_4_0_bits_T_71 connect _io_out_4_0_bits_WIRE_2.vnet_id, _io_out_4_0_bits_WIRE_7 connect _io_out_4_0_bits_WIRE.flow, _io_out_4_0_bits_WIRE_2 node _io_out_4_0_bits_T_72 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_73 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_74 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_75 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_76 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_77 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_78 = or(_io_out_4_0_bits_T_72, _io_out_4_0_bits_T_73) node _io_out_4_0_bits_T_79 = or(_io_out_4_0_bits_T_78, _io_out_4_0_bits_T_74) node _io_out_4_0_bits_T_80 = or(_io_out_4_0_bits_T_79, _io_out_4_0_bits_T_75) node _io_out_4_0_bits_T_81 = or(_io_out_4_0_bits_T_80, _io_out_4_0_bits_T_76) node _io_out_4_0_bits_T_82 = or(_io_out_4_0_bits_T_81, _io_out_4_0_bits_T_77) wire _io_out_4_0_bits_WIRE_8 : UInt<73> connect _io_out_4_0_bits_WIRE_8, _io_out_4_0_bits_T_82 connect _io_out_4_0_bits_WIRE.payload, _io_out_4_0_bits_WIRE_8 node _io_out_4_0_bits_T_83 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_84 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_85 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_86 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_87 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_88 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_89 = or(_io_out_4_0_bits_T_83, _io_out_4_0_bits_T_84) node _io_out_4_0_bits_T_90 = or(_io_out_4_0_bits_T_89, _io_out_4_0_bits_T_85) node _io_out_4_0_bits_T_91 = or(_io_out_4_0_bits_T_90, _io_out_4_0_bits_T_86) node _io_out_4_0_bits_T_92 = or(_io_out_4_0_bits_T_91, _io_out_4_0_bits_T_87) node _io_out_4_0_bits_T_93 = or(_io_out_4_0_bits_T_92, _io_out_4_0_bits_T_88) wire _io_out_4_0_bits_WIRE_9 : UInt<1> connect _io_out_4_0_bits_WIRE_9, _io_out_4_0_bits_T_93 connect _io_out_4_0_bits_WIRE.tail, _io_out_4_0_bits_WIRE_9 node _io_out_4_0_bits_T_94 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_95 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_96 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_97 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_98 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_99 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_100 = or(_io_out_4_0_bits_T_94, _io_out_4_0_bits_T_95) node _io_out_4_0_bits_T_101 = or(_io_out_4_0_bits_T_100, _io_out_4_0_bits_T_96) node _io_out_4_0_bits_T_102 = or(_io_out_4_0_bits_T_101, _io_out_4_0_bits_T_97) node _io_out_4_0_bits_T_103 = or(_io_out_4_0_bits_T_102, _io_out_4_0_bits_T_98) node _io_out_4_0_bits_T_104 = or(_io_out_4_0_bits_T_103, _io_out_4_0_bits_T_99) wire _io_out_4_0_bits_WIRE_10 : UInt<1> connect _io_out_4_0_bits_WIRE_10, _io_out_4_0_bits_T_104 connect _io_out_4_0_bits_WIRE.head, _io_out_4_0_bits_WIRE_10 connect io.out.`4`[0].bits, _io_out_4_0_bits_WIRE node _io_out_4_0_bits_virt_channel_id_T = bits(sel_flat_4, 0, 0) node _io_out_4_0_bits_virt_channel_id_T_1 = bits(sel_flat_4, 1, 1) node _io_out_4_0_bits_virt_channel_id_T_2 = bits(sel_flat_4, 2, 2) node _io_out_4_0_bits_virt_channel_id_T_3 = bits(sel_flat_4, 3, 3) node _io_out_4_0_bits_virt_channel_id_T_4 = bits(sel_flat_4, 4, 4) node _io_out_4_0_bits_virt_channel_id_T_5 = bits(sel_flat_4, 5, 5) node _io_out_4_0_bits_virt_channel_id_T_6 = mux(_io_out_4_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_7 = mux(_io_out_4_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_8 = mux(_io_out_4_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_9 = mux(_io_out_4_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_10 = mux(_io_out_4_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_11 = mux(_io_out_4_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_12 = or(_io_out_4_0_bits_virt_channel_id_T_6, _io_out_4_0_bits_virt_channel_id_T_7) node _io_out_4_0_bits_virt_channel_id_T_13 = or(_io_out_4_0_bits_virt_channel_id_T_12, _io_out_4_0_bits_virt_channel_id_T_8) node _io_out_4_0_bits_virt_channel_id_T_14 = or(_io_out_4_0_bits_virt_channel_id_T_13, _io_out_4_0_bits_virt_channel_id_T_9) node _io_out_4_0_bits_virt_channel_id_T_15 = or(_io_out_4_0_bits_virt_channel_id_T_14, _io_out_4_0_bits_virt_channel_id_T_10) node _io_out_4_0_bits_virt_channel_id_T_16 = or(_io_out_4_0_bits_virt_channel_id_T_15, _io_out_4_0_bits_virt_channel_id_T_11) wire _io_out_4_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_4_0_bits_virt_channel_id_WIRE, _io_out_4_0_bits_virt_channel_id_T_16 connect io.out.`4`[0].bits.virt_channel_id, _io_out_4_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_5 = cat(io.sel.`5`[0].`2`[0], io.sel.`5`[0].`1`[0]) node sel_flat_lo_5 = cat(sel_flat_lo_hi_5, io.sel.`5`[0].`0`[0]) node sel_flat_hi_hi_5 = cat(io.sel.`5`[0].`5`[0], io.sel.`5`[0].`4`[0]) node sel_flat_hi_5 = cat(sel_flat_hi_hi_5, io.sel.`5`[0].`3`[0]) node sel_flat_5 = cat(sel_flat_hi_5, sel_flat_lo_5) node _T_100 = bits(sel_flat_5, 0, 0) node _T_101 = bits(sel_flat_5, 1, 1) node _T_102 = bits(sel_flat_5, 2, 2) node _T_103 = bits(sel_flat_5, 3, 3) node _T_104 = bits(sel_flat_5, 4, 4) node _T_105 = bits(sel_flat_5, 5, 5) node _T_106 = add(_T_101, _T_102) node _T_107 = bits(_T_106, 1, 0) node _T_108 = add(_T_100, _T_107) node _T_109 = bits(_T_108, 1, 0) node _T_110 = add(_T_104, _T_105) node _T_111 = bits(_T_110, 1, 0) node _T_112 = add(_T_103, _T_111) node _T_113 = bits(_T_112, 1, 0) node _T_114 = add(_T_109, _T_113) node _T_115 = bits(_T_114, 2, 0) node _T_116 = leq(_T_115, UInt<1>(0h1)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_5 assert(clock, _T_116, UInt<1>(0h1), "") : assert_5 node _io_out_5_0_valid_T = bits(sel_flat_5, 0, 0) node _io_out_5_0_valid_T_1 = bits(sel_flat_5, 1, 1) node _io_out_5_0_valid_T_2 = bits(sel_flat_5, 2, 2) node _io_out_5_0_valid_T_3 = bits(sel_flat_5, 3, 3) node _io_out_5_0_valid_T_4 = bits(sel_flat_5, 4, 4) node _io_out_5_0_valid_T_5 = bits(sel_flat_5, 5, 5) node _io_out_5_0_valid_T_6 = mux(_io_out_5_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_7 = mux(_io_out_5_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_8 = mux(_io_out_5_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_9 = mux(_io_out_5_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_10 = mux(_io_out_5_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_11 = mux(_io_out_5_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_12 = or(_io_out_5_0_valid_T_6, _io_out_5_0_valid_T_7) node _io_out_5_0_valid_T_13 = or(_io_out_5_0_valid_T_12, _io_out_5_0_valid_T_8) node _io_out_5_0_valid_T_14 = or(_io_out_5_0_valid_T_13, _io_out_5_0_valid_T_9) node _io_out_5_0_valid_T_15 = or(_io_out_5_0_valid_T_14, _io_out_5_0_valid_T_10) node _io_out_5_0_valid_T_16 = or(_io_out_5_0_valid_T_15, _io_out_5_0_valid_T_11) wire _io_out_5_0_valid_WIRE : UInt<1> connect _io_out_5_0_valid_WIRE, _io_out_5_0_valid_T_16 node _io_out_5_0_valid_T_17 = neq(sel_flat_5, UInt<1>(0h0)) node _io_out_5_0_valid_T_18 = and(_io_out_5_0_valid_WIRE, _io_out_5_0_valid_T_17) connect io.out.`5`[0].valid, _io_out_5_0_valid_T_18 node _io_out_5_0_bits_T = bits(sel_flat_5, 0, 0) node _io_out_5_0_bits_T_1 = bits(sel_flat_5, 1, 1) node _io_out_5_0_bits_T_2 = bits(sel_flat_5, 2, 2) node _io_out_5_0_bits_T_3 = bits(sel_flat_5, 3, 3) node _io_out_5_0_bits_T_4 = bits(sel_flat_5, 4, 4) node _io_out_5_0_bits_T_5 = bits(sel_flat_5, 5, 5) wire _io_out_5_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_5_0_bits_T_6 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_7 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_8 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_9 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_10 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_11 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_12 = or(_io_out_5_0_bits_T_6, _io_out_5_0_bits_T_7) node _io_out_5_0_bits_T_13 = or(_io_out_5_0_bits_T_12, _io_out_5_0_bits_T_8) node _io_out_5_0_bits_T_14 = or(_io_out_5_0_bits_T_13, _io_out_5_0_bits_T_9) node _io_out_5_0_bits_T_15 = or(_io_out_5_0_bits_T_14, _io_out_5_0_bits_T_10) node _io_out_5_0_bits_T_16 = or(_io_out_5_0_bits_T_15, _io_out_5_0_bits_T_11) wire _io_out_5_0_bits_WIRE_1 : UInt<4> connect _io_out_5_0_bits_WIRE_1, _io_out_5_0_bits_T_16 connect _io_out_5_0_bits_WIRE.virt_channel_id, _io_out_5_0_bits_WIRE_1 wire _io_out_5_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_5_0_bits_T_17 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_18 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_19 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_20 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_21 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_22 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_23 = or(_io_out_5_0_bits_T_17, _io_out_5_0_bits_T_18) node _io_out_5_0_bits_T_24 = or(_io_out_5_0_bits_T_23, _io_out_5_0_bits_T_19) node _io_out_5_0_bits_T_25 = or(_io_out_5_0_bits_T_24, _io_out_5_0_bits_T_20) node _io_out_5_0_bits_T_26 = or(_io_out_5_0_bits_T_25, _io_out_5_0_bits_T_21) node _io_out_5_0_bits_T_27 = or(_io_out_5_0_bits_T_26, _io_out_5_0_bits_T_22) wire _io_out_5_0_bits_WIRE_3 : UInt<3> connect _io_out_5_0_bits_WIRE_3, _io_out_5_0_bits_T_27 connect _io_out_5_0_bits_WIRE_2.egress_node_id, _io_out_5_0_bits_WIRE_3 node _io_out_5_0_bits_T_28 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_29 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_30 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_31 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_32 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_33 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_34 = or(_io_out_5_0_bits_T_28, _io_out_5_0_bits_T_29) node _io_out_5_0_bits_T_35 = or(_io_out_5_0_bits_T_34, _io_out_5_0_bits_T_30) node _io_out_5_0_bits_T_36 = or(_io_out_5_0_bits_T_35, _io_out_5_0_bits_T_31) node _io_out_5_0_bits_T_37 = or(_io_out_5_0_bits_T_36, _io_out_5_0_bits_T_32) node _io_out_5_0_bits_T_38 = or(_io_out_5_0_bits_T_37, _io_out_5_0_bits_T_33) wire _io_out_5_0_bits_WIRE_4 : UInt<4> connect _io_out_5_0_bits_WIRE_4, _io_out_5_0_bits_T_38 connect _io_out_5_0_bits_WIRE_2.egress_node, _io_out_5_0_bits_WIRE_4 node _io_out_5_0_bits_T_39 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_40 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_41 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_42 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_43 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_44 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_45 = or(_io_out_5_0_bits_T_39, _io_out_5_0_bits_T_40) node _io_out_5_0_bits_T_46 = or(_io_out_5_0_bits_T_45, _io_out_5_0_bits_T_41) node _io_out_5_0_bits_T_47 = or(_io_out_5_0_bits_T_46, _io_out_5_0_bits_T_42) node _io_out_5_0_bits_T_48 = or(_io_out_5_0_bits_T_47, _io_out_5_0_bits_T_43) node _io_out_5_0_bits_T_49 = or(_io_out_5_0_bits_T_48, _io_out_5_0_bits_T_44) wire _io_out_5_0_bits_WIRE_5 : UInt<3> connect _io_out_5_0_bits_WIRE_5, _io_out_5_0_bits_T_49 connect _io_out_5_0_bits_WIRE_2.ingress_node_id, _io_out_5_0_bits_WIRE_5 node _io_out_5_0_bits_T_50 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_51 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_52 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_53 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_54 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_55 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_56 = or(_io_out_5_0_bits_T_50, _io_out_5_0_bits_T_51) node _io_out_5_0_bits_T_57 = or(_io_out_5_0_bits_T_56, _io_out_5_0_bits_T_52) node _io_out_5_0_bits_T_58 = or(_io_out_5_0_bits_T_57, _io_out_5_0_bits_T_53) node _io_out_5_0_bits_T_59 = or(_io_out_5_0_bits_T_58, _io_out_5_0_bits_T_54) node _io_out_5_0_bits_T_60 = or(_io_out_5_0_bits_T_59, _io_out_5_0_bits_T_55) wire _io_out_5_0_bits_WIRE_6 : UInt<4> connect _io_out_5_0_bits_WIRE_6, _io_out_5_0_bits_T_60 connect _io_out_5_0_bits_WIRE_2.ingress_node, _io_out_5_0_bits_WIRE_6 node _io_out_5_0_bits_T_61 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_62 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_63 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_64 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_65 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_66 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_67 = or(_io_out_5_0_bits_T_61, _io_out_5_0_bits_T_62) node _io_out_5_0_bits_T_68 = or(_io_out_5_0_bits_T_67, _io_out_5_0_bits_T_63) node _io_out_5_0_bits_T_69 = or(_io_out_5_0_bits_T_68, _io_out_5_0_bits_T_64) node _io_out_5_0_bits_T_70 = or(_io_out_5_0_bits_T_69, _io_out_5_0_bits_T_65) node _io_out_5_0_bits_T_71 = or(_io_out_5_0_bits_T_70, _io_out_5_0_bits_T_66) wire _io_out_5_0_bits_WIRE_7 : UInt<3> connect _io_out_5_0_bits_WIRE_7, _io_out_5_0_bits_T_71 connect _io_out_5_0_bits_WIRE_2.vnet_id, _io_out_5_0_bits_WIRE_7 connect _io_out_5_0_bits_WIRE.flow, _io_out_5_0_bits_WIRE_2 node _io_out_5_0_bits_T_72 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_73 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_74 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_75 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_76 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_77 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_78 = or(_io_out_5_0_bits_T_72, _io_out_5_0_bits_T_73) node _io_out_5_0_bits_T_79 = or(_io_out_5_0_bits_T_78, _io_out_5_0_bits_T_74) node _io_out_5_0_bits_T_80 = or(_io_out_5_0_bits_T_79, _io_out_5_0_bits_T_75) node _io_out_5_0_bits_T_81 = or(_io_out_5_0_bits_T_80, _io_out_5_0_bits_T_76) node _io_out_5_0_bits_T_82 = or(_io_out_5_0_bits_T_81, _io_out_5_0_bits_T_77) wire _io_out_5_0_bits_WIRE_8 : UInt<73> connect _io_out_5_0_bits_WIRE_8, _io_out_5_0_bits_T_82 connect _io_out_5_0_bits_WIRE.payload, _io_out_5_0_bits_WIRE_8 node _io_out_5_0_bits_T_83 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_84 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_85 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_86 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_87 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_88 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_89 = or(_io_out_5_0_bits_T_83, _io_out_5_0_bits_T_84) node _io_out_5_0_bits_T_90 = or(_io_out_5_0_bits_T_89, _io_out_5_0_bits_T_85) node _io_out_5_0_bits_T_91 = or(_io_out_5_0_bits_T_90, _io_out_5_0_bits_T_86) node _io_out_5_0_bits_T_92 = or(_io_out_5_0_bits_T_91, _io_out_5_0_bits_T_87) node _io_out_5_0_bits_T_93 = or(_io_out_5_0_bits_T_92, _io_out_5_0_bits_T_88) wire _io_out_5_0_bits_WIRE_9 : UInt<1> connect _io_out_5_0_bits_WIRE_9, _io_out_5_0_bits_T_93 connect _io_out_5_0_bits_WIRE.tail, _io_out_5_0_bits_WIRE_9 node _io_out_5_0_bits_T_94 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_95 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_96 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_97 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_98 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_99 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_100 = or(_io_out_5_0_bits_T_94, _io_out_5_0_bits_T_95) node _io_out_5_0_bits_T_101 = or(_io_out_5_0_bits_T_100, _io_out_5_0_bits_T_96) node _io_out_5_0_bits_T_102 = or(_io_out_5_0_bits_T_101, _io_out_5_0_bits_T_97) node _io_out_5_0_bits_T_103 = or(_io_out_5_0_bits_T_102, _io_out_5_0_bits_T_98) node _io_out_5_0_bits_T_104 = or(_io_out_5_0_bits_T_103, _io_out_5_0_bits_T_99) wire _io_out_5_0_bits_WIRE_10 : UInt<1> connect _io_out_5_0_bits_WIRE_10, _io_out_5_0_bits_T_104 connect _io_out_5_0_bits_WIRE.head, _io_out_5_0_bits_WIRE_10 connect io.out.`5`[0].bits, _io_out_5_0_bits_WIRE node _io_out_5_0_bits_virt_channel_id_T = bits(sel_flat_5, 0, 0) node _io_out_5_0_bits_virt_channel_id_T_1 = bits(sel_flat_5, 1, 1) node _io_out_5_0_bits_virt_channel_id_T_2 = bits(sel_flat_5, 2, 2) node _io_out_5_0_bits_virt_channel_id_T_3 = bits(sel_flat_5, 3, 3) node _io_out_5_0_bits_virt_channel_id_T_4 = bits(sel_flat_5, 4, 4) node _io_out_5_0_bits_virt_channel_id_T_5 = bits(sel_flat_5, 5, 5) node _io_out_5_0_bits_virt_channel_id_T_6 = mux(_io_out_5_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_7 = mux(_io_out_5_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_8 = mux(_io_out_5_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_9 = mux(_io_out_5_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_10 = mux(_io_out_5_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_11 = mux(_io_out_5_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_12 = or(_io_out_5_0_bits_virt_channel_id_T_6, _io_out_5_0_bits_virt_channel_id_T_7) node _io_out_5_0_bits_virt_channel_id_T_13 = or(_io_out_5_0_bits_virt_channel_id_T_12, _io_out_5_0_bits_virt_channel_id_T_8) node _io_out_5_0_bits_virt_channel_id_T_14 = or(_io_out_5_0_bits_virt_channel_id_T_13, _io_out_5_0_bits_virt_channel_id_T_9) node _io_out_5_0_bits_virt_channel_id_T_15 = or(_io_out_5_0_bits_virt_channel_id_T_14, _io_out_5_0_bits_virt_channel_id_T_10) node _io_out_5_0_bits_virt_channel_id_T_16 = or(_io_out_5_0_bits_virt_channel_id_T_15, _io_out_5_0_bits_virt_channel_id_T_11) wire _io_out_5_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_5_0_bits_virt_channel_id_WIRE, _io_out_5_0_bits_virt_channel_id_T_16 connect io.out.`5`[0].bits.virt_channel_id, _io_out_5_0_bits_virt_channel_id_WIRE	module Switch_4( // @[Switch.scala:16:7] input clock, // @[Switch.scala:16:7] input reset, // @[Switch.scala:16:7] input io_in_5_0_valid, // @[Switch.scala:27:14] input io_in_5_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_5_0_bits_flit_tail, // @[Switch.scala:27:14] input [72:0] io_in_5_0_bits_flit_payload, // @[Switch.scala:27:14] input [2:0] io_in_5_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_5_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [2:0] io_in_5_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_1_0_valid, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14] input [72:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14] input [2:0] io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [2:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_0_0_valid, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14] input [72:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14] input [2:0] io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [2:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14] output io_out_5_0_valid, // @[Switch.scala:27:14] output io_out_5_0_bits_head, // @[Switch.scala:27:14] output io_out_5_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_5_0_bits_payload, // @[Switch.scala:27:14] output io_out_4_0_valid, // @[Switch.scala:27:14] output io_out_4_0_bits_head, // @[Switch.scala:27:14] output io_out_4_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_4_0_bits_payload, // @[Switch.scala:27:14] output io_out_3_0_valid, // @[Switch.scala:27:14] output io_out_3_0_bits_head, // @[Switch.scala:27:14] output io_out_3_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_3_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_3_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_2_0_valid, // @[Switch.scala:27:14] output io_out_2_0_bits_head, // @[Switch.scala:27:14] output io_out_2_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_2_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_2_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_1_0_valid, // @[Switch.scala:27:14] output io_out_1_0_bits_head, // @[Switch.scala:27:14] output io_out_1_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14] output io_out_0_0_valid, // @[Switch.scala:27:14] output io_out_0_0_bits_head, // @[Switch.scala:27:14] output io_out_0_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14] output [2:0] io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [2:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14] input io_sel_5_0_5_0, // @[Switch.scala:27:14] input io_sel_5_0_1_0, // @[Switch.scala:27:14] input io_sel_5_0_0_0, // @[Switch.scala:27:14] input io_sel_4_0_5_0, // @[Switch.scala:27:14] input io_sel_4_0_1_0, // @[Switch.scala:27:14] input io_sel_4_0_0_0, // @[Switch.scala:27:14] input io_sel_3_0_5_0, // @[Switch.scala:27:14] input io_sel_3_0_1_0, // @[Switch.scala:27:14] input io_sel_3_0_0_0, // @[Switch.scala:27:14] input io_sel_2_0_5_0, // @[Switch.scala:27:14] input io_sel_2_0_1_0, // @[Switch.scala:27:14] input io_sel_2_0_0_0, // @[Switch.scala:27:14] input io_sel_1_0_5_0, // @[Switch.scala:27:14] input io_sel_1_0_1_0, // @[Switch.scala:27:14] input io_sel_1_0_0_0, // @[Switch.scala:27:14] input io_sel_0_0_5_0, // @[Switch.scala:27:14] input io_sel_0_0_1_0, // @[Switch.scala:27:14] input io_sel_0_0_0_0 // @[Switch.scala:27:14] );
Generate the Verilog code corresponding to this FIRRTL code module Tile_210 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_466 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_210( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_466 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_406 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_150 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_406( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_150 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s4k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_14 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s4k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s4k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a32d64s4k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_14 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_198 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_358 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_198( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_358 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_182 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_182( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_181 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_202 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_181( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_202 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_64 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_128 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_64 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = and(io.in.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail invalidate route_buffer.io.enq.bits.flow.egress_node_id invalidate route_buffer.io.enq.bits.flow.egress_node invalidate route_buffer.io.enq.bits.flow.ingress_node_id invalidate route_buffer.io.enq.bits.flow.ingress_node invalidate route_buffer.io.enq.bits.flow.vnet_id connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_6 = and(io.in.ready, io.in.valid) node _T_7 = and(_T_6, io.in.bits.head) node _T_8 = and(_T_7, at_dest) when _T_8 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_9 = eq(UInt<2>(0h2), io.in.bits.egress_id) when _T_9 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<2>(0h3), io.in.bits.egress_id) when _T_10 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(route_q.io.enq.valid, _T_11) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_129 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_64 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_17 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(vcalloc_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_19, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_14, _out_bundle_bits_out_virt_channel_T_13) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_15 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1 connect io.in.ready, UInt<1>(0h0) connect io.router_req.valid, UInt<1>(0h0) invalidate io.router_req.bits.flow.egress_node_id invalidate io.router_req.bits.flow.egress_node invalidate io.router_req.bits.flow.ingress_node_id invalidate io.router_req.bits.flow.ingress_node invalidate io.router_req.bits.flow.vnet_id invalidate io.router_req.bits.src_virt_id connect io.vcalloc_req.valid, UInt<1>(0h0) invalidate io.vcalloc_req.bits.vc_sel.`0`[0] invalidate io.vcalloc_req.bits.vc_sel.`0`[1] invalidate io.vcalloc_req.bits.vc_sel.`0`[2] invalidate io.vcalloc_req.bits.vc_sel.`0`[3] invalidate io.vcalloc_req.bits.vc_sel.`0`[4] invalidate io.vcalloc_req.bits.vc_sel.`0`[5] invalidate io.vcalloc_req.bits.vc_sel.`0`[6] invalidate io.vcalloc_req.bits.vc_sel.`0`[7] invalidate io.vcalloc_req.bits.vc_sel.`0`[8] invalidate io.vcalloc_req.bits.vc_sel.`0`[9] invalidate io.vcalloc_req.bits.vc_sel.`1`[0] invalidate io.vcalloc_req.bits.vc_sel.`2`[0] invalidate io.vcalloc_req.bits.in_vc invalidate io.vcalloc_req.bits.flow.egress_node_id invalidate io.vcalloc_req.bits.flow.egress_node invalidate io.vcalloc_req.bits.flow.ingress_node_id invalidate io.vcalloc_req.bits.flow.ingress_node invalidate io.vcalloc_req.bits.flow.vnet_id connect io.salloc_req[0].valid, UInt<1>(0h0) invalidate io.salloc_req[0].bits.tail invalidate io.salloc_req[0].bits.vc_sel.`0`[0] invalidate io.salloc_req[0].bits.vc_sel.`0`[1] invalidate io.salloc_req[0].bits.vc_sel.`0`[2] invalidate io.salloc_req[0].bits.vc_sel.`0`[3] invalidate io.salloc_req[0].bits.vc_sel.`0`[4] invalidate io.salloc_req[0].bits.vc_sel.`0`[5] invalidate io.salloc_req[0].bits.vc_sel.`0`[6] invalidate io.salloc_req[0].bits.vc_sel.`0`[7] invalidate io.salloc_req[0].bits.vc_sel.`0`[8] invalidate io.salloc_req[0].bits.vc_sel.`0`[9] invalidate io.salloc_req[0].bits.vc_sel.`1`[0] invalidate io.salloc_req[0].bits.vc_sel.`2`[0] connect io.out[0].valid, UInt<1>(0h0) invalidate io.out[0].bits.out_virt_channel invalidate io.out[0].bits.flit.virt_channel_id invalidate io.out[0].bits.flit.flow.egress_node_id invalidate io.out[0].bits.flit.flow.egress_node invalidate io.out[0].bits.flit.flow.ingress_node_id invalidate io.out[0].bits.flit.flow.ingress_node invalidate io.out[0].bits.flit.flow.vnet_id invalidate io.out[0].bits.flit.payload invalidate io.out[0].bits.flit.tail invalidate io.out[0].bits.flit.head	module IngressUnit_64( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_337 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_337( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_49 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_98 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_99 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_174 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_430 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_174( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_430 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget32_8 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_66 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a32d256s2k3z4u_2 connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 255, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<5>(0h1f), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 4, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<2>, clock, reset, UInt<2>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 4, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) node _repeat_anonOut_a_bits_data_mux_T_2 = bits(cated.bits.data, 191, 128) node _repeat_anonOut_a_bits_data_mux_T_3 = bits(cated.bits.data, 255, 192) wire repeat_anonOut_a_bits_data_mux : UInt<64>[4] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect repeat_anonOut_a_bits_data_mux[2], _repeat_anonOut_a_bits_data_mux_T_2 connect repeat_anonOut_a_bits_data_mux[3], _repeat_anonOut_a_bits_data_mux_T_3 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) node _repeat_anonOut_a_bits_mask_mux_T_2 = bits(cated.bits.mask, 23, 16) node _repeat_anonOut_a_bits_mask_mux_T_3 = bits(cated.bits.mask, 31, 24) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[4] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect repeat_anonOut_a_bits_mask_mux[2], _repeat_anonOut_a_bits_mask_mux_T_2 connect repeat_anonOut_a_bits_mask_mux[3], _repeat_anonOut_a_bits_mask_mux_T_3 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<5>(0h1f), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 4, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<2>, clock, reset, UInt<2>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) node _enable_T_6 = xor(count, UInt<2>(0h2)) node _enable_T_7 = and(_enable_T_6, limit) node _enable_T_8 = orr(_enable_T_7) node enable_2 = eq(_enable_T_8, UInt<1>(0h0)) node _enable_T_9 = xor(count, UInt<2>(0h3)) node _enable_T_10 = and(_enable_T_9, limit) node _enable_T_11 = orr(_enable_T_10) node enable_3 = eq(_enable_T_11, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) node _anonIn_d_bits_data_masked_enable_T_2 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_2 = or(enable_2, _anonIn_d_bits_data_masked_enable_T_2) node _anonIn_d_bits_data_masked_enable_T_3 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_3 = or(enable_3, _anonIn_d_bits_data_masked_enable_T_3) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data wire anonIn_d_bits_data_odata_2 : UInt connect anonIn_d_bits_data_odata_2, anonOut.d.bits.data wire anonIn_d_bits_data_odata_3 : UInt connect anonIn_d_bits_data_odata_3, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[3], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonIn_d_bits_data_rdata[1]) node anonIn_d_bits_data_mdata_2 = mux(anonIn_d_bits_data_masked_enable_2, anonIn_d_bits_data_odata_2, anonIn_d_bits_data_rdata[2]) node anonIn_d_bits_data_mdata_3 = mux(anonIn_d_bits_data_masked_enable_3, anonIn_d_bits_data_odata_3, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 connect anonIn_d_bits_data_rdata[1], anonIn_d_bits_data_mdata_1 connect anonIn_d_bits_data_rdata[2], anonIn_d_bits_data_mdata_2 node anonIn_d_bits_data_lo = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) node anonIn_d_bits_data_hi = cat(anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2) node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_hi, anonIn_d_bits_data_lo) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<2>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<2>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<2>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<2>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLWidthWidget32_8( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71] wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T \| _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24] wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24] wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25] wire [1:0] repeat_index = repeat_sel \| repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53] assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71] wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] count; // @[WidthWidget.scala:40:27] wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T \| _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = \|_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = \|_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = \|_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = \|_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt \| corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24] wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready \| _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 \| _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 \| _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_2 = enable_2 \| _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_3 = enable_3 \| _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 2'h0; // @[WidthWidget.scala:105:26] count <= 2'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 \| anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] end always @(posedge) TLMonitor_66 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a32d256s2k3z4u_2 repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BTBBranchPredictorBank : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 4) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask node _s0_pc_T = not(io.f0_pc) node _s0_pc_T_1 = or(_s0_pc_T, UInt<3>(0h7)) node s0_pc = not(_s0_pc_T_1) reg s1_pc : UInt, clock connect s1_pc, s0_pc reg s2_pc : UInt, clock connect s2_pc, s1_pc node s0_update_idx = shr(io.update.bits.pc, 4) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid node _s1_update_bits_pc_T = not(io.update.bits.pc) node _s1_update_bits_pc_T_1 = or(_s1_update_bits_pc_T, UInt<3>(0h7)) node _s1_update_bits_pc_T_2 = not(_s1_update_bits_pc_T_1) connect s1_update.bits.pc, _s1_update_bits_pc_T_2 reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire s1_meta : { write_way : UInt<1>} reg f3_meta_REG : { write_way : UInt<1>}, clock connect f3_meta_REG, s1_meta reg f3_meta : { write_way : UInt<1>}, clock connect f3_meta, f3_meta_REG connect io.f3_meta, f3_meta.write_way regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) wire s1_req_rmeta : { is_br : UInt<1>, tag : UInt<29>}[4][2] wire s1_req_rbtb : { offset : SInt<13>, extended : UInt<1>}[4][2] wire s1_req_rebtb : UInt<40> node s1_req_tag = shr(s1_idx, 7) wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4] wire s1_is_br : UInt<1>[4] wire s1_is_jal : UInt<1>[4] node _s1_hit_ohs_T = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_1 = eq(s1_req_rmeta[0][0].tag, _s1_hit_ohs_T) node _s1_hit_ohs_T_2 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_3 = eq(s1_req_rmeta[1][0].tag, _s1_hit_ohs_T_2) wire _s1_hit_ohs_WIRE : UInt<1>[2] connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1 connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3 node _s1_hit_ohs_T_4 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_5 = eq(s1_req_rmeta[0][1].tag, _s1_hit_ohs_T_4) node _s1_hit_ohs_T_6 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_7 = eq(s1_req_rmeta[1][1].tag, _s1_hit_ohs_T_6) wire _s1_hit_ohs_WIRE_1 : UInt<1>[2] connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_5 connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_7 node _s1_hit_ohs_T_8 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_9 = eq(s1_req_rmeta[0][2].tag, _s1_hit_ohs_T_8) node _s1_hit_ohs_T_10 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_11 = eq(s1_req_rmeta[1][2].tag, _s1_hit_ohs_T_10) wire _s1_hit_ohs_WIRE_2 : UInt<1>[2] connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_9 connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_11 node _s1_hit_ohs_T_12 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_13 = eq(s1_req_rmeta[0][3].tag, _s1_hit_ohs_T_12) node _s1_hit_ohs_T_14 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_15 = eq(s1_req_rmeta[1][3].tag, _s1_hit_ohs_T_14) wire _s1_hit_ohs_WIRE_3 : UInt<1>[2] connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_13 connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_15 wire s1_hit_ohs : UInt<1>[2][4] connect s1_hit_ohs[0], _s1_hit_ohs_WIRE connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1 connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2 connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3 node s1_hits_0 = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1]) node s1_hits_1 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1]) node s1_hits_2 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1]) node s1_hits_3 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1]) node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), UInt<1>(0h1)) wire s1_targs : UInt<40>[4][2] wire entry_btb : { offset : SInt<13>, extended : UInt<1>} connect entry_btb, s1_req_rbtb[0][0] node _s1_targs_0_0_T = asSInt(s1_pc) node _s1_targs_0_0_T_1 = add(_s1_targs_0_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_0_0_T_2 = tail(_s1_targs_0_0_T_1, 1) node _s1_targs_0_0_T_3 = asSInt(_s1_targs_0_0_T_2) node _s1_targs_0_0_T_4 = add(_s1_targs_0_0_T_3, entry_btb.offset) node _s1_targs_0_0_T_5 = tail(_s1_targs_0_0_T_4, 1) node _s1_targs_0_0_T_6 = asSInt(_s1_targs_0_0_T_5) node _s1_targs_0_0_T_7 = asUInt(_s1_targs_0_0_T_6) node _s1_targs_0_0_T_8 = mux(entry_btb.extended, s1_req_rebtb, _s1_targs_0_0_T_7) connect s1_targs[0][0], _s1_targs_0_0_T_8 wire entry_btb_1 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_1, s1_req_rbtb[1][0] node _s1_targs_1_0_T = asSInt(s1_pc) node _s1_targs_1_0_T_1 = add(_s1_targs_1_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_1_0_T_2 = tail(_s1_targs_1_0_T_1, 1) node _s1_targs_1_0_T_3 = asSInt(_s1_targs_1_0_T_2) node _s1_targs_1_0_T_4 = add(_s1_targs_1_0_T_3, entry_btb_1.offset) node _s1_targs_1_0_T_5 = tail(_s1_targs_1_0_T_4, 1) node _s1_targs_1_0_T_6 = asSInt(_s1_targs_1_0_T_5) node _s1_targs_1_0_T_7 = asUInt(_s1_targs_1_0_T_6) node _s1_targs_1_0_T_8 = mux(entry_btb_1.extended, s1_req_rebtb, _s1_targs_1_0_T_7) connect s1_targs[1][0], _s1_targs_1_0_T_8 node _s1_resp_0_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_0_valid_T_1 = and(_s1_resp_0_valid_T, s1_valid) node _s1_resp_0_valid_T_2 = and(_s1_resp_0_valid_T_1, s1_hits_0) connect s1_resp[0].valid, _s1_resp_0_valid_T_2 connect s1_resp[0].bits, s1_targs[s1_hit_ways_0][0] node _s1_is_br_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_0_T_1 = and(_s1_is_br_0_T, s1_resp[0].valid) node _s1_is_br_0_T_2 = and(_s1_is_br_0_T_1, s1_req_rmeta[s1_hit_ways_0][0].is_br) connect s1_is_br[0], _s1_is_br_0_T_2 node _s1_is_jal_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_0_T_1 = and(_s1_is_jal_0_T, s1_resp[0].valid) node _s1_is_jal_0_T_2 = eq(s1_req_rmeta[s1_hit_ways_0][0].is_br, UInt<1>(0h0)) node _s1_is_jal_0_T_3 = and(_s1_is_jal_0_T_1, _s1_is_jal_0_T_2) connect s1_is_jal[0], _s1_is_jal_0_T_3 connect io.resp.f1[0], io.resp_in[0].f1[0] connect io.resp.f2[0], io.resp_in[0].f2[0] connect io.resp.f3[0], io.resp_in[0].f3[0] reg REG : UInt<1>, clock connect REG, s1_hits_0 when REG : reg io_resp_f2_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_0_predicted_pc_REG, s1_resp[0] connect io.resp.f2[0].predicted_pc, io_resp_f2_0_predicted_pc_REG reg io_resp_f2_0_is_br_REG : UInt<1>, clock connect io_resp_f2_0_is_br_REG, s1_is_br[0] connect io.resp.f2[0].is_br, io_resp_f2_0_is_br_REG reg io_resp_f2_0_is_jal_REG : UInt<1>, clock connect io_resp_f2_0_is_jal_REG, s1_is_jal[0] connect io.resp.f2[0].is_jal, io_resp_f2_0_is_jal_REG reg REG_1 : UInt<1>, clock connect REG_1, s1_is_jal[0] when REG_1 : connect io.resp.f2[0].taken, UInt<1>(0h1) reg REG_2 : UInt<1>, clock connect REG_2, s1_hits_0 reg REG_3 : UInt<1>, clock connect REG_3, REG_2 when REG_3 : reg io_resp_f3_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_0_predicted_pc_REG.bits, io.resp.f2[0].predicted_pc.bits connect io_resp_f3_0_predicted_pc_REG.valid, io.resp.f2[0].predicted_pc.valid connect io.resp.f3[0].predicted_pc, io_resp_f3_0_predicted_pc_REG reg io_resp_f3_0_is_br_REG : UInt<1>, clock connect io_resp_f3_0_is_br_REG, io.resp.f2[0].is_br connect io.resp.f3[0].is_br, io_resp_f3_0_is_br_REG reg io_resp_f3_0_is_jal_REG : UInt<1>, clock connect io_resp_f3_0_is_jal_REG, io.resp.f2[0].is_jal connect io.resp.f3[0].is_jal, io_resp_f3_0_is_jal_REG reg REG_4 : UInt<1>, clock connect REG_4, s1_is_jal[0] reg REG_5 : UInt<1>, clock connect REG_5, REG_4 when REG_5 : connect io.resp.f3[0].taken, UInt<1>(0h1) wire entry_btb_2 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_2, s1_req_rbtb[0][1] node _s1_targs_0_1_T = asSInt(s1_pc) node _s1_targs_0_1_T_1 = add(_s1_targs_0_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_0_1_T_2 = tail(_s1_targs_0_1_T_1, 1) node _s1_targs_0_1_T_3 = asSInt(_s1_targs_0_1_T_2) node _s1_targs_0_1_T_4 = add(_s1_targs_0_1_T_3, entry_btb_2.offset) node _s1_targs_0_1_T_5 = tail(_s1_targs_0_1_T_4, 1) node _s1_targs_0_1_T_6 = asSInt(_s1_targs_0_1_T_5) node _s1_targs_0_1_T_7 = asUInt(_s1_targs_0_1_T_6) node _s1_targs_0_1_T_8 = mux(entry_btb_2.extended, s1_req_rebtb, _s1_targs_0_1_T_7) connect s1_targs[0][1], _s1_targs_0_1_T_8 wire entry_btb_3 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_3, s1_req_rbtb[1][1] node _s1_targs_1_1_T = asSInt(s1_pc) node _s1_targs_1_1_T_1 = add(_s1_targs_1_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_1_1_T_2 = tail(_s1_targs_1_1_T_1, 1) node _s1_targs_1_1_T_3 = asSInt(_s1_targs_1_1_T_2) node _s1_targs_1_1_T_4 = add(_s1_targs_1_1_T_3, entry_btb_3.offset) node _s1_targs_1_1_T_5 = tail(_s1_targs_1_1_T_4, 1) node _s1_targs_1_1_T_6 = asSInt(_s1_targs_1_1_T_5) node _s1_targs_1_1_T_7 = asUInt(_s1_targs_1_1_T_6) node _s1_targs_1_1_T_8 = mux(entry_btb_3.extended, s1_req_rebtb, _s1_targs_1_1_T_7) connect s1_targs[1][1], _s1_targs_1_1_T_8 node _s1_resp_1_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_1_valid_T_1 = and(_s1_resp_1_valid_T, s1_valid) node _s1_resp_1_valid_T_2 = and(_s1_resp_1_valid_T_1, s1_hits_1) connect s1_resp[1].valid, _s1_resp_1_valid_T_2 connect s1_resp[1].bits, s1_targs[s1_hit_ways_1][1] node _s1_is_br_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_1_T_1 = and(_s1_is_br_1_T, s1_resp[1].valid) node _s1_is_br_1_T_2 = and(_s1_is_br_1_T_1, s1_req_rmeta[s1_hit_ways_1][1].is_br) connect s1_is_br[1], _s1_is_br_1_T_2 node _s1_is_jal_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_1_T_1 = and(_s1_is_jal_1_T, s1_resp[1].valid) node _s1_is_jal_1_T_2 = eq(s1_req_rmeta[s1_hit_ways_1][1].is_br, UInt<1>(0h0)) node _s1_is_jal_1_T_3 = and(_s1_is_jal_1_T_1, _s1_is_jal_1_T_2) connect s1_is_jal[1], _s1_is_jal_1_T_3 connect io.resp.f1[1], io.resp_in[0].f1[1] connect io.resp.f2[1], io.resp_in[0].f2[1] connect io.resp.f3[1], io.resp_in[0].f3[1] reg REG_6 : UInt<1>, clock connect REG_6, s1_hits_1 when REG_6 : reg io_resp_f2_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_1_predicted_pc_REG, s1_resp[1] connect io.resp.f2[1].predicted_pc, io_resp_f2_1_predicted_pc_REG reg io_resp_f2_1_is_br_REG : UInt<1>, clock connect io_resp_f2_1_is_br_REG, s1_is_br[1] connect io.resp.f2[1].is_br, io_resp_f2_1_is_br_REG reg io_resp_f2_1_is_jal_REG : UInt<1>, clock connect io_resp_f2_1_is_jal_REG, s1_is_jal[1] connect io.resp.f2[1].is_jal, io_resp_f2_1_is_jal_REG reg REG_7 : UInt<1>, clock connect REG_7, s1_is_jal[1] when REG_7 : connect io.resp.f2[1].taken, UInt<1>(0h1) reg REG_8 : UInt<1>, clock connect REG_8, s1_hits_1 reg REG_9 : UInt<1>, clock connect REG_9, REG_8 when REG_9 : reg io_resp_f3_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_1_predicted_pc_REG.bits, io.resp.f2[1].predicted_pc.bits connect io_resp_f3_1_predicted_pc_REG.valid, io.resp.f2[1].predicted_pc.valid connect io.resp.f3[1].predicted_pc, io_resp_f3_1_predicted_pc_REG reg io_resp_f3_1_is_br_REG : UInt<1>, clock connect io_resp_f3_1_is_br_REG, io.resp.f2[1].is_br connect io.resp.f3[1].is_br, io_resp_f3_1_is_br_REG reg io_resp_f3_1_is_jal_REG : UInt<1>, clock connect io_resp_f3_1_is_jal_REG, io.resp.f2[1].is_jal connect io.resp.f3[1].is_jal, io_resp_f3_1_is_jal_REG reg REG_10 : UInt<1>, clock connect REG_10, s1_is_jal[1] reg REG_11 : UInt<1>, clock connect REG_11, REG_10 when REG_11 : connect io.resp.f3[1].taken, UInt<1>(0h1) wire entry_btb_4 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_4, s1_req_rbtb[0][2] node _s1_targs_0_2_T = asSInt(s1_pc) node _s1_targs_0_2_T_1 = add(_s1_targs_0_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_0_2_T_2 = tail(_s1_targs_0_2_T_1, 1) node _s1_targs_0_2_T_3 = asSInt(_s1_targs_0_2_T_2) node _s1_targs_0_2_T_4 = add(_s1_targs_0_2_T_3, entry_btb_4.offset) node _s1_targs_0_2_T_5 = tail(_s1_targs_0_2_T_4, 1) node _s1_targs_0_2_T_6 = asSInt(_s1_targs_0_2_T_5) node _s1_targs_0_2_T_7 = asUInt(_s1_targs_0_2_T_6) node _s1_targs_0_2_T_8 = mux(entry_btb_4.extended, s1_req_rebtb, _s1_targs_0_2_T_7) connect s1_targs[0][2], _s1_targs_0_2_T_8 wire entry_btb_5 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_5, s1_req_rbtb[1][2] node _s1_targs_1_2_T = asSInt(s1_pc) node _s1_targs_1_2_T_1 = add(_s1_targs_1_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_1_2_T_2 = tail(_s1_targs_1_2_T_1, 1) node _s1_targs_1_2_T_3 = asSInt(_s1_targs_1_2_T_2) node _s1_targs_1_2_T_4 = add(_s1_targs_1_2_T_3, entry_btb_5.offset) node _s1_targs_1_2_T_5 = tail(_s1_targs_1_2_T_4, 1) node _s1_targs_1_2_T_6 = asSInt(_s1_targs_1_2_T_5) node _s1_targs_1_2_T_7 = asUInt(_s1_targs_1_2_T_6) node _s1_targs_1_2_T_8 = mux(entry_btb_5.extended, s1_req_rebtb, _s1_targs_1_2_T_7) connect s1_targs[1][2], _s1_targs_1_2_T_8 node _s1_resp_2_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_2_valid_T_1 = and(_s1_resp_2_valid_T, s1_valid) node _s1_resp_2_valid_T_2 = and(_s1_resp_2_valid_T_1, s1_hits_2) connect s1_resp[2].valid, _s1_resp_2_valid_T_2 connect s1_resp[2].bits, s1_targs[s1_hit_ways_2][2] node _s1_is_br_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_2_T_1 = and(_s1_is_br_2_T, s1_resp[2].valid) node _s1_is_br_2_T_2 = and(_s1_is_br_2_T_1, s1_req_rmeta[s1_hit_ways_2][2].is_br) connect s1_is_br[2], _s1_is_br_2_T_2 node _s1_is_jal_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_2_T_1 = and(_s1_is_jal_2_T, s1_resp[2].valid) node _s1_is_jal_2_T_2 = eq(s1_req_rmeta[s1_hit_ways_2][2].is_br, UInt<1>(0h0)) node _s1_is_jal_2_T_3 = and(_s1_is_jal_2_T_1, _s1_is_jal_2_T_2) connect s1_is_jal[2], _s1_is_jal_2_T_3 connect io.resp.f1[2], io.resp_in[0].f1[2] connect io.resp.f2[2], io.resp_in[0].f2[2] connect io.resp.f3[2], io.resp_in[0].f3[2] reg REG_12 : UInt<1>, clock connect REG_12, s1_hits_2 when REG_12 : reg io_resp_f2_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_2_predicted_pc_REG, s1_resp[2] connect io.resp.f2[2].predicted_pc, io_resp_f2_2_predicted_pc_REG reg io_resp_f2_2_is_br_REG : UInt<1>, clock connect io_resp_f2_2_is_br_REG, s1_is_br[2] connect io.resp.f2[2].is_br, io_resp_f2_2_is_br_REG reg io_resp_f2_2_is_jal_REG : UInt<1>, clock connect io_resp_f2_2_is_jal_REG, s1_is_jal[2] connect io.resp.f2[2].is_jal, io_resp_f2_2_is_jal_REG reg REG_13 : UInt<1>, clock connect REG_13, s1_is_jal[2] when REG_13 : connect io.resp.f2[2].taken, UInt<1>(0h1) reg REG_14 : UInt<1>, clock connect REG_14, s1_hits_2 reg REG_15 : UInt<1>, clock connect REG_15, REG_14 when REG_15 : reg io_resp_f3_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_2_predicted_pc_REG.bits, io.resp.f2[2].predicted_pc.bits connect io_resp_f3_2_predicted_pc_REG.valid, io.resp.f2[2].predicted_pc.valid connect io.resp.f3[2].predicted_pc, io_resp_f3_2_predicted_pc_REG reg io_resp_f3_2_is_br_REG : UInt<1>, clock connect io_resp_f3_2_is_br_REG, io.resp.f2[2].is_br connect io.resp.f3[2].is_br, io_resp_f3_2_is_br_REG reg io_resp_f3_2_is_jal_REG : UInt<1>, clock connect io_resp_f3_2_is_jal_REG, io.resp.f2[2].is_jal connect io.resp.f3[2].is_jal, io_resp_f3_2_is_jal_REG reg REG_16 : UInt<1>, clock connect REG_16, s1_is_jal[2] reg REG_17 : UInt<1>, clock connect REG_17, REG_16 when REG_17 : connect io.resp.f3[2].taken, UInt<1>(0h1) wire entry_btb_6 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_6, s1_req_rbtb[0][3] node _s1_targs_0_3_T = asSInt(s1_pc) node _s1_targs_0_3_T_1 = add(_s1_targs_0_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_0_3_T_2 = tail(_s1_targs_0_3_T_1, 1) node _s1_targs_0_3_T_3 = asSInt(_s1_targs_0_3_T_2) node _s1_targs_0_3_T_4 = add(_s1_targs_0_3_T_3, entry_btb_6.offset) node _s1_targs_0_3_T_5 = tail(_s1_targs_0_3_T_4, 1) node _s1_targs_0_3_T_6 = asSInt(_s1_targs_0_3_T_5) node _s1_targs_0_3_T_7 = asUInt(_s1_targs_0_3_T_6) node _s1_targs_0_3_T_8 = mux(entry_btb_6.extended, s1_req_rebtb, _s1_targs_0_3_T_7) connect s1_targs[0][3], _s1_targs_0_3_T_8 wire entry_btb_7 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_7, s1_req_rbtb[1][3] node _s1_targs_1_3_T = asSInt(s1_pc) node _s1_targs_1_3_T_1 = add(_s1_targs_1_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_1_3_T_2 = tail(_s1_targs_1_3_T_1, 1) node _s1_targs_1_3_T_3 = asSInt(_s1_targs_1_3_T_2) node _s1_targs_1_3_T_4 = add(_s1_targs_1_3_T_3, entry_btb_7.offset) node _s1_targs_1_3_T_5 = tail(_s1_targs_1_3_T_4, 1) node _s1_targs_1_3_T_6 = asSInt(_s1_targs_1_3_T_5) node _s1_targs_1_3_T_7 = asUInt(_s1_targs_1_3_T_6) node _s1_targs_1_3_T_8 = mux(entry_btb_7.extended, s1_req_rebtb, _s1_targs_1_3_T_7) connect s1_targs[1][3], _s1_targs_1_3_T_8 node _s1_resp_3_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_3_valid_T_1 = and(_s1_resp_3_valid_T, s1_valid) node _s1_resp_3_valid_T_2 = and(_s1_resp_3_valid_T_1, s1_hits_3) connect s1_resp[3].valid, _s1_resp_3_valid_T_2 connect s1_resp[3].bits, s1_targs[s1_hit_ways_3][3] node _s1_is_br_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_3_T_1 = and(_s1_is_br_3_T, s1_resp[3].valid) node _s1_is_br_3_T_2 = and(_s1_is_br_3_T_1, s1_req_rmeta[s1_hit_ways_3][3].is_br) connect s1_is_br[3], _s1_is_br_3_T_2 node _s1_is_jal_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_3_T_1 = and(_s1_is_jal_3_T, s1_resp[3].valid) node _s1_is_jal_3_T_2 = eq(s1_req_rmeta[s1_hit_ways_3][3].is_br, UInt<1>(0h0)) node _s1_is_jal_3_T_3 = and(_s1_is_jal_3_T_1, _s1_is_jal_3_T_2) connect s1_is_jal[3], _s1_is_jal_3_T_3 connect io.resp.f1[3], io.resp_in[0].f1[3] connect io.resp.f2[3], io.resp_in[0].f2[3] connect io.resp.f3[3], io.resp_in[0].f3[3] reg REG_18 : UInt<1>, clock connect REG_18, s1_hits_3 when REG_18 : reg io_resp_f2_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_3_predicted_pc_REG, s1_resp[3] connect io.resp.f2[3].predicted_pc, io_resp_f2_3_predicted_pc_REG reg io_resp_f2_3_is_br_REG : UInt<1>, clock connect io_resp_f2_3_is_br_REG, s1_is_br[3] connect io.resp.f2[3].is_br, io_resp_f2_3_is_br_REG reg io_resp_f2_3_is_jal_REG : UInt<1>, clock connect io_resp_f2_3_is_jal_REG, s1_is_jal[3] connect io.resp.f2[3].is_jal, io_resp_f2_3_is_jal_REG reg REG_19 : UInt<1>, clock connect REG_19, s1_is_jal[3] when REG_19 : connect io.resp.f2[3].taken, UInt<1>(0h1) reg REG_20 : UInt<1>, clock connect REG_20, s1_hits_3 reg REG_21 : UInt<1>, clock connect REG_21, REG_20 when REG_21 : reg io_resp_f3_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_3_predicted_pc_REG.bits, io.resp.f2[3].predicted_pc.bits connect io_resp_f3_3_predicted_pc_REG.valid, io.resp.f2[3].predicted_pc.valid connect io.resp.f3[3].predicted_pc, io_resp_f3_3_predicted_pc_REG reg io_resp_f3_3_is_br_REG : UInt<1>, clock connect io_resp_f3_3_is_br_REG, io.resp.f2[3].is_br connect io.resp.f3[3].is_br, io_resp_f3_3_is_br_REG reg io_resp_f3_3_is_jal_REG : UInt<1>, clock connect io_resp_f3_3_is_jal_REG, io.resp.f2[3].is_jal connect io.resp.f3[3].is_jal, io_resp_f3_3_is_jal_REG reg REG_22 : UInt<1>, clock connect REG_22, s1_is_jal[3] reg REG_23 : UInt<1>, clock connect REG_23, REG_22 when REG_23 : connect io.resp.f3[3].taken, UInt<1>(0h1) wire _alloc_way_r_metas_WIRE : UInt<29>[4] connect _alloc_way_r_metas_WIRE[0], s1_req_rmeta[0][0].tag connect _alloc_way_r_metas_WIRE[1], s1_req_rmeta[0][1].tag connect _alloc_way_r_metas_WIRE[2], s1_req_rmeta[0][2].tag connect _alloc_way_r_metas_WIRE[3], s1_req_rmeta[0][3].tag wire _alloc_way_r_metas_WIRE_1 : UInt<29>[4] connect _alloc_way_r_metas_WIRE_1[0], s1_req_rmeta[1][0].tag connect _alloc_way_r_metas_WIRE_1[1], s1_req_rmeta[1][1].tag connect _alloc_way_r_metas_WIRE_1[2], s1_req_rmeta[1][2].tag connect _alloc_way_r_metas_WIRE_1[3], s1_req_rmeta[1][3].tag wire _alloc_way_r_metas_WIRE_2 : UInt<29>[4][2] connect _alloc_way_r_metas_WIRE_2[0], _alloc_way_r_metas_WIRE connect _alloc_way_r_metas_WIRE_2[1], _alloc_way_r_metas_WIRE_1 node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_2[0][1], _alloc_way_r_metas_WIRE_2[0][0]) node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_2[0][3], _alloc_way_r_metas_WIRE_2[0][2]) node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo) node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_2[1][1], _alloc_way_r_metas_WIRE_2[1][0]) node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_2[1][3], _alloc_way_r_metas_WIRE_2[1][2]) node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1) node _alloc_way_r_metas_T_2 = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T) node _alloc_way_r_metas_T_3 = bits(s1_req_tag, 28, 0) node alloc_way_r_metas = cat(_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3) node alloc_way_chunks_0 = bits(alloc_way_r_metas, 0, 0) node alloc_way_chunks_1 = bits(alloc_way_r_metas, 1, 1) node alloc_way_chunks_2 = bits(alloc_way_r_metas, 2, 2) node alloc_way_chunks_3 = bits(alloc_way_r_metas, 3, 3) node alloc_way_chunks_4 = bits(alloc_way_r_metas, 4, 4) node alloc_way_chunks_5 = bits(alloc_way_r_metas, 5, 5) node alloc_way_chunks_6 = bits(alloc_way_r_metas, 6, 6) node alloc_way_chunks_7 = bits(alloc_way_r_metas, 7, 7) node alloc_way_chunks_8 = bits(alloc_way_r_metas, 8, 8) node alloc_way_chunks_9 = bits(alloc_way_r_metas, 9, 9) node alloc_way_chunks_10 = bits(alloc_way_r_metas, 10, 10) node alloc_way_chunks_11 = bits(alloc_way_r_metas, 11, 11) node alloc_way_chunks_12 = bits(alloc_way_r_metas, 12, 12) node alloc_way_chunks_13 = bits(alloc_way_r_metas, 13, 13) node alloc_way_chunks_14 = bits(alloc_way_r_metas, 14, 14) node alloc_way_chunks_15 = bits(alloc_way_r_metas, 15, 15) node alloc_way_chunks_16 = bits(alloc_way_r_metas, 16, 16) node alloc_way_chunks_17 = bits(alloc_way_r_metas, 17, 17) node alloc_way_chunks_18 = bits(alloc_way_r_metas, 18, 18) node alloc_way_chunks_19 = bits(alloc_way_r_metas, 19, 19) node alloc_way_chunks_20 = bits(alloc_way_r_metas, 20, 20) node alloc_way_chunks_21 = bits(alloc_way_r_metas, 21, 21) node alloc_way_chunks_22 = bits(alloc_way_r_metas, 22, 22) node alloc_way_chunks_23 = bits(alloc_way_r_metas, 23, 23) node alloc_way_chunks_24 = bits(alloc_way_r_metas, 24, 24) node alloc_way_chunks_25 = bits(alloc_way_r_metas, 25, 25) node alloc_way_chunks_26 = bits(alloc_way_r_metas, 26, 26) node alloc_way_chunks_27 = bits(alloc_way_r_metas, 27, 27) node alloc_way_chunks_28 = bits(alloc_way_r_metas, 28, 28) node alloc_way_chunks_29 = bits(alloc_way_r_metas, 29, 29) node alloc_way_chunks_30 = bits(alloc_way_r_metas, 30, 30) node alloc_way_chunks_31 = bits(alloc_way_r_metas, 31, 31) node alloc_way_chunks_32 = bits(alloc_way_r_metas, 32, 32) node alloc_way_chunks_33 = bits(alloc_way_r_metas, 33, 33) node alloc_way_chunks_34 = bits(alloc_way_r_metas, 34, 34) node alloc_way_chunks_35 = bits(alloc_way_r_metas, 35, 35) node alloc_way_chunks_36 = bits(alloc_way_r_metas, 36, 36) node alloc_way_chunks_37 = bits(alloc_way_r_metas, 37, 37) node alloc_way_chunks_38 = bits(alloc_way_r_metas, 38, 38) node alloc_way_chunks_39 = bits(alloc_way_r_metas, 39, 39) node alloc_way_chunks_40 = bits(alloc_way_r_metas, 40, 40) node alloc_way_chunks_41 = bits(alloc_way_r_metas, 41, 41) node alloc_way_chunks_42 = bits(alloc_way_r_metas, 42, 42) node alloc_way_chunks_43 = bits(alloc_way_r_metas, 43, 43) node alloc_way_chunks_44 = bits(alloc_way_r_metas, 44, 44) node alloc_way_chunks_45 = bits(alloc_way_r_metas, 45, 45) node alloc_way_chunks_46 = bits(alloc_way_r_metas, 46, 46) node alloc_way_chunks_47 = bits(alloc_way_r_metas, 47, 47) node alloc_way_chunks_48 = bits(alloc_way_r_metas, 48, 48) node alloc_way_chunks_49 = bits(alloc_way_r_metas, 49, 49) node alloc_way_chunks_50 = bits(alloc_way_r_metas, 50, 50) node alloc_way_chunks_51 = bits(alloc_way_r_metas, 51, 51) node alloc_way_chunks_52 = bits(alloc_way_r_metas, 52, 52) node alloc_way_chunks_53 = bits(alloc_way_r_metas, 53, 53) node alloc_way_chunks_54 = bits(alloc_way_r_metas, 54, 54) node alloc_way_chunks_55 = bits(alloc_way_r_metas, 55, 55) node alloc_way_chunks_56 = bits(alloc_way_r_metas, 56, 56) node alloc_way_chunks_57 = bits(alloc_way_r_metas, 57, 57) node alloc_way_chunks_58 = bits(alloc_way_r_metas, 58, 58) node alloc_way_chunks_59 = bits(alloc_way_r_metas, 59, 59) node alloc_way_chunks_60 = bits(alloc_way_r_metas, 60, 60) node alloc_way_chunks_61 = bits(alloc_way_r_metas, 61, 61) node alloc_way_chunks_62 = bits(alloc_way_r_metas, 62, 62) node alloc_way_chunks_63 = bits(alloc_way_r_metas, 63, 63) node alloc_way_chunks_64 = bits(alloc_way_r_metas, 64, 64) node alloc_way_chunks_65 = bits(alloc_way_r_metas, 65, 65) node alloc_way_chunks_66 = bits(alloc_way_r_metas, 66, 66) node alloc_way_chunks_67 = bits(alloc_way_r_metas, 67, 67) node alloc_way_chunks_68 = bits(alloc_way_r_metas, 68, 68) node alloc_way_chunks_69 = bits(alloc_way_r_metas, 69, 69) node alloc_way_chunks_70 = bits(alloc_way_r_metas, 70, 70) node alloc_way_chunks_71 = bits(alloc_way_r_metas, 71, 71) node alloc_way_chunks_72 = bits(alloc_way_r_metas, 72, 72) node alloc_way_chunks_73 = bits(alloc_way_r_metas, 73, 73) node alloc_way_chunks_74 = bits(alloc_way_r_metas, 74, 74) node alloc_way_chunks_75 = bits(alloc_way_r_metas, 75, 75) node alloc_way_chunks_76 = bits(alloc_way_r_metas, 76, 76) node alloc_way_chunks_77 = bits(alloc_way_r_metas, 77, 77) node alloc_way_chunks_78 = bits(alloc_way_r_metas, 78, 78) node alloc_way_chunks_79 = bits(alloc_way_r_metas, 79, 79) node alloc_way_chunks_80 = bits(alloc_way_r_metas, 80, 80) node alloc_way_chunks_81 = bits(alloc_way_r_metas, 81, 81) node alloc_way_chunks_82 = bits(alloc_way_r_metas, 82, 82) node alloc_way_chunks_83 = bits(alloc_way_r_metas, 83, 83) node alloc_way_chunks_84 = bits(alloc_way_r_metas, 84, 84) node alloc_way_chunks_85 = bits(alloc_way_r_metas, 85, 85) node alloc_way_chunks_86 = bits(alloc_way_r_metas, 86, 86) node alloc_way_chunks_87 = bits(alloc_way_r_metas, 87, 87) node alloc_way_chunks_88 = bits(alloc_way_r_metas, 88, 88) node alloc_way_chunks_89 = bits(alloc_way_r_metas, 89, 89) node alloc_way_chunks_90 = bits(alloc_way_r_metas, 90, 90) node alloc_way_chunks_91 = bits(alloc_way_r_metas, 91, 91) node alloc_way_chunks_92 = bits(alloc_way_r_metas, 92, 92) node alloc_way_chunks_93 = bits(alloc_way_r_metas, 93, 93) node alloc_way_chunks_94 = bits(alloc_way_r_metas, 94, 94) node alloc_way_chunks_95 = bits(alloc_way_r_metas, 95, 95) node alloc_way_chunks_96 = bits(alloc_way_r_metas, 96, 96) node alloc_way_chunks_97 = bits(alloc_way_r_metas, 97, 97) node alloc_way_chunks_98 = bits(alloc_way_r_metas, 98, 98) node alloc_way_chunks_99 = bits(alloc_way_r_metas, 99, 99) node alloc_way_chunks_100 = bits(alloc_way_r_metas, 100, 100) node alloc_way_chunks_101 = bits(alloc_way_r_metas, 101, 101) node alloc_way_chunks_102 = bits(alloc_way_r_metas, 102, 102) node alloc_way_chunks_103 = bits(alloc_way_r_metas, 103, 103) node alloc_way_chunks_104 = bits(alloc_way_r_metas, 104, 104) node alloc_way_chunks_105 = bits(alloc_way_r_metas, 105, 105) node alloc_way_chunks_106 = bits(alloc_way_r_metas, 106, 106) node alloc_way_chunks_107 = bits(alloc_way_r_metas, 107, 107) node alloc_way_chunks_108 = bits(alloc_way_r_metas, 108, 108) node alloc_way_chunks_109 = bits(alloc_way_r_metas, 109, 109) node alloc_way_chunks_110 = bits(alloc_way_r_metas, 110, 110) node alloc_way_chunks_111 = bits(alloc_way_r_metas, 111, 111) node alloc_way_chunks_112 = bits(alloc_way_r_metas, 112, 112) node alloc_way_chunks_113 = bits(alloc_way_r_metas, 113, 113) node alloc_way_chunks_114 = bits(alloc_way_r_metas, 114, 114) node alloc_way_chunks_115 = bits(alloc_way_r_metas, 115, 115) node alloc_way_chunks_116 = bits(alloc_way_r_metas, 116, 116) node alloc_way_chunks_117 = bits(alloc_way_r_metas, 117, 117) node alloc_way_chunks_118 = bits(alloc_way_r_metas, 118, 118) node alloc_way_chunks_119 = bits(alloc_way_r_metas, 119, 119) node alloc_way_chunks_120 = bits(alloc_way_r_metas, 120, 120) node alloc_way_chunks_121 = bits(alloc_way_r_metas, 121, 121) node alloc_way_chunks_122 = bits(alloc_way_r_metas, 122, 122) node alloc_way_chunks_123 = bits(alloc_way_r_metas, 123, 123) node alloc_way_chunks_124 = bits(alloc_way_r_metas, 124, 124) node alloc_way_chunks_125 = bits(alloc_way_r_metas, 125, 125) node alloc_way_chunks_126 = bits(alloc_way_r_metas, 126, 126) node alloc_way_chunks_127 = bits(alloc_way_r_metas, 127, 127) node alloc_way_chunks_128 = bits(alloc_way_r_metas, 128, 128) node alloc_way_chunks_129 = bits(alloc_way_r_metas, 129, 129) node alloc_way_chunks_130 = bits(alloc_way_r_metas, 130, 130) node alloc_way_chunks_131 = bits(alloc_way_r_metas, 131, 131) node alloc_way_chunks_132 = bits(alloc_way_r_metas, 132, 132) node alloc_way_chunks_133 = bits(alloc_way_r_metas, 133, 133) node alloc_way_chunks_134 = bits(alloc_way_r_metas, 134, 134) node alloc_way_chunks_135 = bits(alloc_way_r_metas, 135, 135) node alloc_way_chunks_136 = bits(alloc_way_r_metas, 136, 136) node alloc_way_chunks_137 = bits(alloc_way_r_metas, 137, 137) node alloc_way_chunks_138 = bits(alloc_way_r_metas, 138, 138) node alloc_way_chunks_139 = bits(alloc_way_r_metas, 139, 139) node alloc_way_chunks_140 = bits(alloc_way_r_metas, 140, 140) node alloc_way_chunks_141 = bits(alloc_way_r_metas, 141, 141) node alloc_way_chunks_142 = bits(alloc_way_r_metas, 142, 142) node alloc_way_chunks_143 = bits(alloc_way_r_metas, 143, 143) node alloc_way_chunks_144 = bits(alloc_way_r_metas, 144, 144) node alloc_way_chunks_145 = bits(alloc_way_r_metas, 145, 145) node alloc_way_chunks_146 = bits(alloc_way_r_metas, 146, 146) node alloc_way_chunks_147 = bits(alloc_way_r_metas, 147, 147) node alloc_way_chunks_148 = bits(alloc_way_r_metas, 148, 148) node alloc_way_chunks_149 = bits(alloc_way_r_metas, 149, 149) node alloc_way_chunks_150 = bits(alloc_way_r_metas, 150, 150) node alloc_way_chunks_151 = bits(alloc_way_r_metas, 151, 151) node alloc_way_chunks_152 = bits(alloc_way_r_metas, 152, 152) node alloc_way_chunks_153 = bits(alloc_way_r_metas, 153, 153) node alloc_way_chunks_154 = bits(alloc_way_r_metas, 154, 154) node alloc_way_chunks_155 = bits(alloc_way_r_metas, 155, 155) node alloc_way_chunks_156 = bits(alloc_way_r_metas, 156, 156) node alloc_way_chunks_157 = bits(alloc_way_r_metas, 157, 157) node alloc_way_chunks_158 = bits(alloc_way_r_metas, 158, 158) node alloc_way_chunks_159 = bits(alloc_way_r_metas, 159, 159) node alloc_way_chunks_160 = bits(alloc_way_r_metas, 160, 160) node alloc_way_chunks_161 = bits(alloc_way_r_metas, 161, 161) node alloc_way_chunks_162 = bits(alloc_way_r_metas, 162, 162) node alloc_way_chunks_163 = bits(alloc_way_r_metas, 163, 163) node alloc_way_chunks_164 = bits(alloc_way_r_metas, 164, 164) node alloc_way_chunks_165 = bits(alloc_way_r_metas, 165, 165) node alloc_way_chunks_166 = bits(alloc_way_r_metas, 166, 166) node alloc_way_chunks_167 = bits(alloc_way_r_metas, 167, 167) node alloc_way_chunks_168 = bits(alloc_way_r_metas, 168, 168) node alloc_way_chunks_169 = bits(alloc_way_r_metas, 169, 169) node alloc_way_chunks_170 = bits(alloc_way_r_metas, 170, 170) node alloc_way_chunks_171 = bits(alloc_way_r_metas, 171, 171) node alloc_way_chunks_172 = bits(alloc_way_r_metas, 172, 172) node alloc_way_chunks_173 = bits(alloc_way_r_metas, 173, 173) node alloc_way_chunks_174 = bits(alloc_way_r_metas, 174, 174) node alloc_way_chunks_175 = bits(alloc_way_r_metas, 175, 175) node alloc_way_chunks_176 = bits(alloc_way_r_metas, 176, 176) node alloc_way_chunks_177 = bits(alloc_way_r_metas, 177, 177) node alloc_way_chunks_178 = bits(alloc_way_r_metas, 178, 178) node alloc_way_chunks_179 = bits(alloc_way_r_metas, 179, 179) node alloc_way_chunks_180 = bits(alloc_way_r_metas, 180, 180) node alloc_way_chunks_181 = bits(alloc_way_r_metas, 181, 181) node alloc_way_chunks_182 = bits(alloc_way_r_metas, 182, 182) node alloc_way_chunks_183 = bits(alloc_way_r_metas, 183, 183) node alloc_way_chunks_184 = bits(alloc_way_r_metas, 184, 184) node alloc_way_chunks_185 = bits(alloc_way_r_metas, 185, 185) node alloc_way_chunks_186 = bits(alloc_way_r_metas, 186, 186) node alloc_way_chunks_187 = bits(alloc_way_r_metas, 187, 187) node alloc_way_chunks_188 = bits(alloc_way_r_metas, 188, 188) node alloc_way_chunks_189 = bits(alloc_way_r_metas, 189, 189) node alloc_way_chunks_190 = bits(alloc_way_r_metas, 190, 190) node alloc_way_chunks_191 = bits(alloc_way_r_metas, 191, 191) node alloc_way_chunks_192 = bits(alloc_way_r_metas, 192, 192) node alloc_way_chunks_193 = bits(alloc_way_r_metas, 193, 193) node alloc_way_chunks_194 = bits(alloc_way_r_metas, 194, 194) node alloc_way_chunks_195 = bits(alloc_way_r_metas, 195, 195) node alloc_way_chunks_196 = bits(alloc_way_r_metas, 196, 196) node alloc_way_chunks_197 = bits(alloc_way_r_metas, 197, 197) node alloc_way_chunks_198 = bits(alloc_way_r_metas, 198, 198) node alloc_way_chunks_199 = bits(alloc_way_r_metas, 199, 199) node alloc_way_chunks_200 = bits(alloc_way_r_metas, 200, 200) node alloc_way_chunks_201 = bits(alloc_way_r_metas, 201, 201) node alloc_way_chunks_202 = bits(alloc_way_r_metas, 202, 202) node alloc_way_chunks_203 = bits(alloc_way_r_metas, 203, 203) node alloc_way_chunks_204 = bits(alloc_way_r_metas, 204, 204) node alloc_way_chunks_205 = bits(alloc_way_r_metas, 205, 205) node alloc_way_chunks_206 = bits(alloc_way_r_metas, 206, 206) node alloc_way_chunks_207 = bits(alloc_way_r_metas, 207, 207) node alloc_way_chunks_208 = bits(alloc_way_r_metas, 208, 208) node alloc_way_chunks_209 = bits(alloc_way_r_metas, 209, 209) node alloc_way_chunks_210 = bits(alloc_way_r_metas, 210, 210) node alloc_way_chunks_211 = bits(alloc_way_r_metas, 211, 211) node alloc_way_chunks_212 = bits(alloc_way_r_metas, 212, 212) node alloc_way_chunks_213 = bits(alloc_way_r_metas, 213, 213) node alloc_way_chunks_214 = bits(alloc_way_r_metas, 214, 214) node alloc_way_chunks_215 = bits(alloc_way_r_metas, 215, 215) node alloc_way_chunks_216 = bits(alloc_way_r_metas, 216, 216) node alloc_way_chunks_217 = bits(alloc_way_r_metas, 217, 217) node alloc_way_chunks_218 = bits(alloc_way_r_metas, 218, 218) node alloc_way_chunks_219 = bits(alloc_way_r_metas, 219, 219) node alloc_way_chunks_220 = bits(alloc_way_r_metas, 220, 220) node alloc_way_chunks_221 = bits(alloc_way_r_metas, 221, 221) node alloc_way_chunks_222 = bits(alloc_way_r_metas, 222, 222) node alloc_way_chunks_223 = bits(alloc_way_r_metas, 223, 223) node alloc_way_chunks_224 = bits(alloc_way_r_metas, 224, 224) node alloc_way_chunks_225 = bits(alloc_way_r_metas, 225, 225) node alloc_way_chunks_226 = bits(alloc_way_r_metas, 226, 226) node alloc_way_chunks_227 = bits(alloc_way_r_metas, 227, 227) node alloc_way_chunks_228 = bits(alloc_way_r_metas, 228, 228) node alloc_way_chunks_229 = bits(alloc_way_r_metas, 229, 229) node alloc_way_chunks_230 = bits(alloc_way_r_metas, 230, 230) node alloc_way_chunks_231 = bits(alloc_way_r_metas, 231, 231) node alloc_way_chunks_232 = bits(alloc_way_r_metas, 232, 232) node alloc_way_chunks_233 = bits(alloc_way_r_metas, 233, 233) node alloc_way_chunks_234 = bits(alloc_way_r_metas, 234, 234) node alloc_way_chunks_235 = bits(alloc_way_r_metas, 235, 235) node alloc_way_chunks_236 = bits(alloc_way_r_metas, 236, 236) node alloc_way_chunks_237 = bits(alloc_way_r_metas, 237, 237) node alloc_way_chunks_238 = bits(alloc_way_r_metas, 238, 238) node alloc_way_chunks_239 = bits(alloc_way_r_metas, 239, 239) node alloc_way_chunks_240 = bits(alloc_way_r_metas, 240, 240) node alloc_way_chunks_241 = bits(alloc_way_r_metas, 241, 241) node alloc_way_chunks_242 = bits(alloc_way_r_metas, 242, 242) node alloc_way_chunks_243 = bits(alloc_way_r_metas, 243, 243) node alloc_way_chunks_244 = bits(alloc_way_r_metas, 244, 244) node alloc_way_chunks_245 = bits(alloc_way_r_metas, 245, 245) node alloc_way_chunks_246 = bits(alloc_way_r_metas, 246, 246) node alloc_way_chunks_247 = bits(alloc_way_r_metas, 247, 247) node alloc_way_chunks_248 = bits(alloc_way_r_metas, 248, 248) node alloc_way_chunks_249 = bits(alloc_way_r_metas, 249, 249) node alloc_way_chunks_250 = bits(alloc_way_r_metas, 250, 250) node alloc_way_chunks_251 = bits(alloc_way_r_metas, 251, 251) node alloc_way_chunks_252 = bits(alloc_way_r_metas, 252, 252) node alloc_way_chunks_253 = bits(alloc_way_r_metas, 253, 253) node alloc_way_chunks_254 = bits(alloc_way_r_metas, 254, 254) node alloc_way_chunks_255 = bits(alloc_way_r_metas, 255, 255) node alloc_way_chunks_256 = bits(alloc_way_r_metas, 256, 256) node alloc_way_chunks_257 = bits(alloc_way_r_metas, 257, 257) node alloc_way_chunks_258 = bits(alloc_way_r_metas, 258, 258) node alloc_way_chunks_259 = bits(alloc_way_r_metas, 259, 259) node alloc_way_chunks_260 = bits(alloc_way_r_metas, 260, 260) node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1) node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2) node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3) node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4) node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5) node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6) node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7) node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8) node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9) node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10) node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11) node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12) node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13) node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14) node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15) node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16) node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17) node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18) node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19) node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20) node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21) node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22) node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23) node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24) node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25) node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26) node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27) node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28) node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29) node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30) node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31) node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32) node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33) node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34) node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35) node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36) node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37) node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38) node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39) node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40) node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41) node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42) node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43) node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44) node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45) node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46) node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47) node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48) node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49) node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50) node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51) node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52) node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53) node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54) node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55) node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56) node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57) node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58) node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59) node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60) node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61) node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62) node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63) node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64) node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65) node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66) node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67) node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68) node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69) node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70) node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71) node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72) node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73) node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74) node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75) node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76) node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77) node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78) node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79) node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80) node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81) node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82) node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83) node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84) node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85) node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86) node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87) node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88) node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89) node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90) node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91) node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92) node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93) node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94) node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95) node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96) node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97) node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98) node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99) node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100) node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101) node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102) node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103) node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104) node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105) node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106) node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107) node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108) node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109) node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110) node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111) node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112) node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113) node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114) node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115) node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116) node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117) node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118) node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119) node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120) node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121) node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122) node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123) node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124) node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125) node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126) node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127) node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128) node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129) node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130) node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131) node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132) node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133) node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134) node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135) node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136) node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137) node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138) node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139) node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140) node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141) node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142) node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143) node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144) node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145) node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146) node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147) node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148) node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149) node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150) node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151) node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152) node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153) node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154) node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155) node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156) node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157) node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158) node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159) node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160) node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161) node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162) node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163) node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164) node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165) node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166) node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167) node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168) node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169) node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170) node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171) node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172) node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173) node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174) node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175) node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176) node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177) node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178) node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179) node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180) node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181) node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182) node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183) node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184) node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185) node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186) node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187) node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188) node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189) node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190) node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191) node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192) node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193) node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194) node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195) node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196) node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197) node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198) node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199) node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200) node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201) node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202) node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203) node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204) node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205) node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206) node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207) node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208) node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209) node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210) node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211) node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212) node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213) node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214) node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215) node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216) node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217) node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218) node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219) node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220) node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221) node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222) node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223) node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224) node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225) node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226) node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227) node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228) node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229) node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230) node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231) node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232) node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233) node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234) node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235) node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236) node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237) node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238) node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239) node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240) node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241) node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242) node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243) node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244) node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245) node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246) node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247) node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248) node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249) node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250) node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251) node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252) node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253) node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254) node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255) node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256) node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257) node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258) node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259) node alloc_way = xor(_alloc_way_T_258, alloc_way_chunks_260) node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1) node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2) node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3) node _s1_meta_write_way_T_3 = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0]) node _s1_meta_write_way_T_4 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0]) node _s1_meta_write_way_T_5 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0]) node _s1_meta_write_way_T_6 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0]) node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4) node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5) node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6) node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0) node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1) node _s1_meta_write_way_T_12 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), UInt<1>(0h1)) node _s1_meta_write_way_T_13 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_12, alloc_way) connect s1_meta.write_way, _s1_meta_write_way_T_13 wire s1_update_meta : { write_way : UInt<1>} wire _s1_update_meta_WIRE : UInt<1> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 0, 0) connect s1_update_meta.write_way, _s1_update_meta_T node _max_offset_value_T = not(UInt<12>(0h0)) node _max_offset_value_T_1 = cat(UInt<1>(0h0), _max_offset_value_T) node max_offset_value = asSInt(_max_offset_value_T_1) node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0)) node min_offset_value = asSInt(_min_offset_value_T) node _new_offset_value_T = asSInt(s1_update.bits.target) node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1) node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1) node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1) node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3) node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4) node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1) node new_offset_value = asSInt(_new_offset_value_T_6) node _offset_is_extended_T = gt(new_offset_value, max_offset_value) node _offset_is_extended_T_1 = lt(new_offset_value, min_offset_value) node offset_is_extended = or(_offset_is_extended_T, _offset_is_extended_T_1) wire s1_update_wbtb_data : { offset : SInt<13>, extended : UInt<1>} connect s1_update_wbtb_data.extended, offset_is_extended connect s1_update_wbtb_data.offset, new_offset_value node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid) node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken) node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4) node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6) node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8) node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask) node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2) node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4) node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_7 = mux(s1_update.valid, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_8 = and(_s1_update_wmeta_mask_T_7, s1_update.bits.btb_mispredicts) node _s1_update_wmeta_mask_T_9 = or(_s1_update_wmeta_mask_T_6, _s1_update_wmeta_mask_T_8) node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_9) wire s1_update_wmeta_data : { is_br : UInt<1>, tag : UInt<29>}[4] node _s1_update_wmeta_data_0_tag_T = bits(s1_update.bits.btb_mispredicts, 0, 0) node _s1_update_wmeta_data_0_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_0_tag_T_2 = mux(_s1_update_wmeta_data_0_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_0_tag_T_1) connect s1_update_wmeta_data[0].tag, _s1_update_wmeta_data_0_tag_T_2 node _s1_update_wmeta_data_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0) connect s1_update_wmeta_data[0].is_br, _s1_update_wmeta_data_0_is_br_T node _s1_update_wmeta_data_1_tag_T = bits(s1_update.bits.btb_mispredicts, 1, 1) node _s1_update_wmeta_data_1_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_1_tag_T_2 = mux(_s1_update_wmeta_data_1_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_1_tag_T_1) connect s1_update_wmeta_data[1].tag, _s1_update_wmeta_data_1_tag_T_2 node _s1_update_wmeta_data_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1) connect s1_update_wmeta_data[1].is_br, _s1_update_wmeta_data_1_is_br_T node _s1_update_wmeta_data_2_tag_T = bits(s1_update.bits.btb_mispredicts, 2, 2) node _s1_update_wmeta_data_2_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_2_tag_T_2 = mux(_s1_update_wmeta_data_2_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_2_tag_T_1) connect s1_update_wmeta_data[2].tag, _s1_update_wmeta_data_2_tag_T_2 node _s1_update_wmeta_data_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2) connect s1_update_wmeta_data[2].is_br, _s1_update_wmeta_data_2_is_br_T node _s1_update_wmeta_data_3_tag_T = bits(s1_update.bits.btb_mispredicts, 3, 3) node _s1_update_wmeta_data_3_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_3_tag_T_2 = mux(_s1_update_wmeta_data_3_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_3_tag_T_1) connect s1_update_wmeta_data[3].tag, _s1_update_wmeta_data_3_tag_T_2 node _s1_update_wmeta_data_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3) connect s1_update_wmeta_data[3].is_br, _s1_update_wmeta_data_3_is_br_T smem btb_meta_way_0 : UInt<30>[4] [128] smem btb_data_way_0 : UInt<14>[4] [128] wire _WIRE : UInt<36> invalidate _WIRE when io.f0_valid : connect _WIRE, s0_idx node _T_1 = bits(_WIRE, 6, 0) read mport MPORT = btb_meta_way_0[_T_1], clock wire _WIRE_1 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_2 : UInt<30> connect _WIRE_2, MPORT[0] node _T_2 = bits(_WIRE_2, 28, 0) connect _WIRE_1.tag, _T_2 node _T_3 = bits(_WIRE_2, 29, 29) connect _WIRE_1.is_br, _T_3 wire _WIRE_3 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_4 : UInt<30> connect _WIRE_4, MPORT[1] node _T_4 = bits(_WIRE_4, 28, 0) connect _WIRE_3.tag, _T_4 node _T_5 = bits(_WIRE_4, 29, 29) connect _WIRE_3.is_br, _T_5 wire _WIRE_5 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_6 : UInt<30> connect _WIRE_6, MPORT[2] node _T_6 = bits(_WIRE_6, 28, 0) connect _WIRE_5.tag, _T_6 node _T_7 = bits(_WIRE_6, 29, 29) connect _WIRE_5.is_br, _T_7 wire _WIRE_7 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_8 : UInt<30> connect _WIRE_8, MPORT[3] node _T_8 = bits(_WIRE_8, 28, 0) connect _WIRE_7.tag, _T_8 node _T_9 = bits(_WIRE_8, 29, 29) connect _WIRE_7.is_br, _T_9 wire _WIRE_9 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].is_br, _WIRE_1.is_br connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].is_br, _WIRE_3.is_br connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].is_br, _WIRE_5.is_br connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].is_br, _WIRE_7.is_br connect s1_req_rmeta[0], _WIRE_9 wire _WIRE_10 : UInt<36> invalidate _WIRE_10 when io.f0_valid : connect _WIRE_10, s0_idx node _T_10 = bits(_WIRE_10, 6, 0) read mport MPORT_1 = btb_data_way_0[_T_10], clock wire _WIRE_11 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_12 : UInt<14> connect _WIRE_12, MPORT_1[0] node _T_11 = bits(_WIRE_12, 0, 0) connect _WIRE_11.extended, _T_11 node _T_12 = bits(_WIRE_12, 13, 1) node _T_13 = asSInt(_T_12) connect _WIRE_11.offset, _T_13 wire _WIRE_13 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_14 : UInt<14> connect _WIRE_14, MPORT_1[1] node _T_14 = bits(_WIRE_14, 0, 0) connect _WIRE_13.extended, _T_14 node _T_15 = bits(_WIRE_14, 13, 1) node _T_16 = asSInt(_T_15) connect _WIRE_13.offset, _T_16 wire _WIRE_15 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_16 : UInt<14> connect _WIRE_16, MPORT_1[2] node _T_17 = bits(_WIRE_16, 0, 0) connect _WIRE_15.extended, _T_17 node _T_18 = bits(_WIRE_16, 13, 1) node _T_19 = asSInt(_T_18) connect _WIRE_15.offset, _T_19 wire _WIRE_17 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_18 : UInt<14> connect _WIRE_18, MPORT_1[3] node _T_20 = bits(_WIRE_18, 0, 0) connect _WIRE_17.extended, _T_20 node _T_21 = bits(_WIRE_18, 13, 1) node _T_22 = asSInt(_T_21) connect _WIRE_17.offset, _T_22 wire _WIRE_19 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_19[0].extended, _WIRE_11.extended connect _WIRE_19[0].offset, _WIRE_11.offset connect _WIRE_19[1].extended, _WIRE_13.extended connect _WIRE_19[1].offset, _WIRE_13.offset connect _WIRE_19[2].extended, _WIRE_15.extended connect _WIRE_19[2].offset, _WIRE_15.offset connect _WIRE_19[3].extended, _WIRE_17.extended connect _WIRE_19[3].offset, _WIRE_17.offset connect s1_req_rbtb[0], _WIRE_19 node _T_23 = eq(s1_update_meta.write_way, UInt<1>(0h0)) node _T_24 = or(doing_reset, _T_23) node _T_25 = or(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_20 : UInt<14>[4] connect _WIRE_20[0], UInt<14>(0h0) connect _WIRE_20[1], UInt<14>(0h0) connect _WIRE_20[2], UInt<14>(0h0) connect _WIRE_20[3], UInt<14>(0h0) node _T_27 = asUInt(s1_update_wbtb_data.offset) node _T_28 = cat(_T_27, s1_update_wbtb_data.extended) node _T_29 = asUInt(s1_update_wbtb_data.offset) node _T_30 = cat(_T_29, s1_update_wbtb_data.extended) node _T_31 = asUInt(s1_update_wbtb_data.offset) node _T_32 = cat(_T_31, s1_update_wbtb_data.extended) node _T_33 = asUInt(s1_update_wbtb_data.offset) node _T_34 = cat(_T_33, s1_update_wbtb_data.extended) wire _WIRE_21 : UInt<14>[4] connect _WIRE_21[0], _T_28 connect _WIRE_21[1], _T_30 connect _WIRE_21[2], _T_32 connect _WIRE_21[3], _T_34 node _T_35 = mux(doing_reset, _WIRE_20, _WIRE_21) node _T_36 = not(UInt<4>(0h0)) node _T_37 = mux(doing_reset, _T_36, s1_update_wbtb_mask) node _T_38 = bits(_T_37, 0, 0) node _T_39 = bits(_T_37, 1, 1) node _T_40 = bits(_T_37, 2, 2) node _T_41 = bits(_T_37, 3, 3) node _T_42 = or(_T_26, UInt<7>(0h0)) node _T_43 = bits(_T_42, 6, 0) write mport MPORT_2 = btb_data_way_0[_T_43], clock when _T_38 : connect MPORT_2[0], _T_35[0] when _T_39 : connect MPORT_2[1], _T_35[1] when _T_40 : connect MPORT_2[2], _T_35[2] when _T_41 : connect MPORT_2[3], _T_35[3] node _T_44 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_22 : UInt<30>[4] connect _WIRE_22[0], UInt<30>(0h0) connect _WIRE_22[1], UInt<30>(0h0) connect _WIRE_22[2], UInt<30>(0h0) connect _WIRE_22[3], UInt<30>(0h0) node _T_45 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_46 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_47 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_48 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_23 : UInt<30>[4] connect _WIRE_23[0], _T_45 connect _WIRE_23[1], _T_46 connect _WIRE_23[2], _T_47 connect _WIRE_23[3], _T_48 node _T_49 = mux(doing_reset, _WIRE_22, _WIRE_23) node _T_50 = not(UInt<4>(0h0)) node _T_51 = mux(doing_reset, _T_50, s1_update_wmeta_mask) node _T_52 = bits(_T_51, 0, 0) node _T_53 = bits(_T_51, 1, 1) node _T_54 = bits(_T_51, 2, 2) node _T_55 = bits(_T_51, 3, 3) node _T_56 = or(_T_44, UInt<7>(0h0)) node _T_57 = bits(_T_56, 6, 0) write mport MPORT_3 = btb_meta_way_0[_T_57], clock when _T_52 : connect MPORT_3[0], _T_49[0] when _T_53 : connect MPORT_3[1], _T_49[1] when _T_54 : connect MPORT_3[2], _T_49[2] when _T_55 : connect MPORT_3[3], _T_49[3] smem btb_meta_way_1 : UInt<30>[4] [128] smem btb_data_way_1 : UInt<14>[4] [128] wire _WIRE_24 : UInt<36> invalidate _WIRE_24 when io.f0_valid : connect _WIRE_24, s0_idx node _T_58 = bits(_WIRE_24, 6, 0) read mport MPORT_4 = btb_meta_way_1[_T_58], clock wire _WIRE_25 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_26 : UInt<30> connect _WIRE_26, MPORT_4[0] node _T_59 = bits(_WIRE_26, 28, 0) connect _WIRE_25.tag, _T_59 node _T_60 = bits(_WIRE_26, 29, 29) connect _WIRE_25.is_br, _T_60 wire _WIRE_27 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_28 : UInt<30> connect _WIRE_28, MPORT_4[1] node _T_61 = bits(_WIRE_28, 28, 0) connect _WIRE_27.tag, _T_61 node _T_62 = bits(_WIRE_28, 29, 29) connect _WIRE_27.is_br, _T_62 wire _WIRE_29 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_30 : UInt<30> connect _WIRE_30, MPORT_4[2] node _T_63 = bits(_WIRE_30, 28, 0) connect _WIRE_29.tag, _T_63 node _T_64 = bits(_WIRE_30, 29, 29) connect _WIRE_29.is_br, _T_64 wire _WIRE_31 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_32 : UInt<30> connect _WIRE_32, MPORT_4[3] node _T_65 = bits(_WIRE_32, 28, 0) connect _WIRE_31.tag, _T_65 node _T_66 = bits(_WIRE_32, 29, 29) connect _WIRE_31.is_br, _T_66 wire _WIRE_33 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _WIRE_33[0].tag, _WIRE_25.tag connect _WIRE_33[0].is_br, _WIRE_25.is_br connect _WIRE_33[1].tag, _WIRE_27.tag connect _WIRE_33[1].is_br, _WIRE_27.is_br connect _WIRE_33[2].tag, _WIRE_29.tag connect _WIRE_33[2].is_br, _WIRE_29.is_br connect _WIRE_33[3].tag, _WIRE_31.tag connect _WIRE_33[3].is_br, _WIRE_31.is_br connect s1_req_rmeta[1], _WIRE_33 wire _WIRE_34 : UInt<36> invalidate _WIRE_34 when io.f0_valid : connect _WIRE_34, s0_idx node _T_67 = bits(_WIRE_34, 6, 0) read mport MPORT_5 = btb_data_way_1[_T_67], clock wire _WIRE_35 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_36 : UInt<14> connect _WIRE_36, MPORT_5[0] node _T_68 = bits(_WIRE_36, 0, 0) connect _WIRE_35.extended, _T_68 node _T_69 = bits(_WIRE_36, 13, 1) node _T_70 = asSInt(_T_69) connect _WIRE_35.offset, _T_70 wire _WIRE_37 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_38 : UInt<14> connect _WIRE_38, MPORT_5[1] node _T_71 = bits(_WIRE_38, 0, 0) connect _WIRE_37.extended, _T_71 node _T_72 = bits(_WIRE_38, 13, 1) node _T_73 = asSInt(_T_72) connect _WIRE_37.offset, _T_73 wire _WIRE_39 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_40 : UInt<14> connect _WIRE_40, MPORT_5[2] node _T_74 = bits(_WIRE_40, 0, 0) connect _WIRE_39.extended, _T_74 node _T_75 = bits(_WIRE_40, 13, 1) node _T_76 = asSInt(_T_75) connect _WIRE_39.offset, _T_76 wire _WIRE_41 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_42 : UInt<14> connect _WIRE_42, MPORT_5[3] node _T_77 = bits(_WIRE_42, 0, 0) connect _WIRE_41.extended, _T_77 node _T_78 = bits(_WIRE_42, 13, 1) node _T_79 = asSInt(_T_78) connect _WIRE_41.offset, _T_79 wire _WIRE_43 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_43[0].extended, _WIRE_35.extended connect _WIRE_43[0].offset, _WIRE_35.offset connect _WIRE_43[1].extended, _WIRE_37.extended connect _WIRE_43[1].offset, _WIRE_37.offset connect _WIRE_43[2].extended, _WIRE_39.extended connect _WIRE_43[2].offset, _WIRE_39.offset connect _WIRE_43[3].extended, _WIRE_41.extended connect _WIRE_43[3].offset, _WIRE_41.offset connect s1_req_rbtb[1], _WIRE_43 node _T_80 = eq(s1_update_meta.write_way, UInt<1>(0h1)) node _T_81 = or(doing_reset, _T_80) node _T_82 = or(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_44 : UInt<14>[4] connect _WIRE_44[0], UInt<14>(0h0) connect _WIRE_44[1], UInt<14>(0h0) connect _WIRE_44[2], UInt<14>(0h0) connect _WIRE_44[3], UInt<14>(0h0) node _T_84 = asUInt(s1_update_wbtb_data.offset) node _T_85 = cat(_T_84, s1_update_wbtb_data.extended) node _T_86 = asUInt(s1_update_wbtb_data.offset) node _T_87 = cat(_T_86, s1_update_wbtb_data.extended) node _T_88 = asUInt(s1_update_wbtb_data.offset) node _T_89 = cat(_T_88, s1_update_wbtb_data.extended) node _T_90 = asUInt(s1_update_wbtb_data.offset) node _T_91 = cat(_T_90, s1_update_wbtb_data.extended) wire _WIRE_45 : UInt<14>[4] connect _WIRE_45[0], _T_85 connect _WIRE_45[1], _T_87 connect _WIRE_45[2], _T_89 connect _WIRE_45[3], _T_91 node _T_92 = mux(doing_reset, _WIRE_44, _WIRE_45) node _T_93 = not(UInt<4>(0h0)) node _T_94 = mux(doing_reset, _T_93, s1_update_wbtb_mask) node _T_95 = bits(_T_94, 0, 0) node _T_96 = bits(_T_94, 1, 1) node _T_97 = bits(_T_94, 2, 2) node _T_98 = bits(_T_94, 3, 3) node _T_99 = or(_T_83, UInt<7>(0h0)) node _T_100 = bits(_T_99, 6, 0) write mport MPORT_6 = btb_data_way_1[_T_100], clock when _T_95 : connect MPORT_6[0], _T_92[0] when _T_96 : connect MPORT_6[1], _T_92[1] when _T_97 : connect MPORT_6[2], _T_92[2] when _T_98 : connect MPORT_6[3], _T_92[3] node _T_101 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_46 : UInt<30>[4] connect _WIRE_46[0], UInt<30>(0h0) connect _WIRE_46[1], UInt<30>(0h0) connect _WIRE_46[2], UInt<30>(0h0) connect _WIRE_46[3], UInt<30>(0h0) node _T_102 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_103 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_104 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_105 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_47 : UInt<30>[4] connect _WIRE_47[0], _T_102 connect _WIRE_47[1], _T_103 connect _WIRE_47[2], _T_104 connect _WIRE_47[3], _T_105 node _T_106 = mux(doing_reset, _WIRE_46, _WIRE_47) node _T_107 = not(UInt<4>(0h0)) node _T_108 = mux(doing_reset, _T_107, s1_update_wmeta_mask) node _T_109 = bits(_T_108, 0, 0) node _T_110 = bits(_T_108, 1, 1) node _T_111 = bits(_T_108, 2, 2) node _T_112 = bits(_T_108, 3, 3) node _T_113 = or(_T_101, UInt<7>(0h0)) node _T_114 = bits(_T_113, 6, 0) write mport MPORT_7 = btb_meta_way_1[_T_114], clock when _T_109 : connect MPORT_7[0], _T_106[0] when _T_110 : connect MPORT_7[1], _T_106[1] when _T_111 : connect MPORT_7[2], _T_106[2] when _T_112 : connect MPORT_7[3], _T_106[3] smem btb_ebtb : UInt<40> [128] wire _s1_req_rebtb_WIRE : UInt<36> invalidate _s1_req_rebtb_WIRE when io.f0_valid : connect _s1_req_rebtb_WIRE, s0_idx node _s1_req_rebtb_T = bits(_s1_req_rebtb_WIRE, 6, 0) read mport s1_req_rebtb_MPORT = btb_ebtb[_s1_req_rebtb_T], clock connect s1_req_rebtb, s1_req_rebtb_MPORT node _T_115 = neq(s1_update_wbtb_mask, UInt<1>(0h0)) node _T_116 = and(_T_115, offset_is_extended) when _T_116 : node _T_117 = or(s1_update_idx, UInt<7>(0h0)) node _T_118 = bits(_T_117, 6, 0) write mport MPORT_8 = btb_ebtb[_T_118], clock connect MPORT_8, s1_update.bits.target	module BTBBranchPredictorBank( // @[btb.scala:24:7] input clock, // @[btb.scala:24:7] input reset, // @[btb.scala:24:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [29:0] btb_meta_way_1_MPORT_7_data_3; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_2; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_1; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_1_MPORT_6_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_0; // @[btb.scala:201:14] wire [29:0] btb_meta_way_0_MPORT_3_data_3; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_2; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_1; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_0_MPORT_2_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_0; // @[btb.scala:201:14] wire _s1_update_meta_WIRE; // @[btb.scala:139:55] wire s1_req_rbtb_1_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_0_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_0_offset; // @[btb.scala:71:26] wire [28:0] s1_req_rmeta_1_3_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_2_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_1_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_0_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_3_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_2_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_1_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_0_tag; // @[btb.scala:70:26] wire [55:0] _btb_data_way_1_R0_data; // @[btb.scala:192:29] wire [119:0] _btb_meta_way_1_R0_data; // @[btb.scala:191:29] wire [55:0] _btb_data_way_0_R0_data; // @[btb.scala:192:29] wire [119:0] _btb_meta_way_0_R0_data; // @[btb.scala:191:29] wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:24:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:24:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:24:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:24:7] wire io_update_valid_0 = io_update_valid; // @[btb.scala:24:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:24:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:24:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:24:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:24:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:24:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:24:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:24:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:24:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:24:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:24:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:24:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:24:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:24:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:24:7] wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:141:35] wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:141:{29,59}] wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:141:59] wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:142:{29,59}] wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:142:59] wire io_f1_lhist = 1'h0; // @[btb.scala:24:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_taken_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_1_taken_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_2_taken_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_3_taken_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_0_taken_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_1_taken_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_2_taken_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_3_taken_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] wire [119:0] io_f3_meta_0; // @[btb.scala:24:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:149:35] wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:149:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] wire [39:0] _s0_pc_T = ~io_f0_pc_0; // @[frontend.scala:147:33] wire [39:0] _s0_pc_T_1 = {_s0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] s0_pc = ~_s0_pc_T_1; // @[frontend.scala:147:{31,39}] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_3_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_3_T = s1_pc; // @[predictor.scala:178:22] reg [39:0] s2_pc; // @[predictor.scala:179:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:149:35] reg s1_update_valid; // @[predictor.scala:185:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:185:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:185:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:185:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:185:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:185:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:185:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:185:30] reg s1_update_bits_lhist; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:185:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:185:30] wire [39:0] _s1_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _s1_update_bits_pc_T_1 = {_s1_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _s1_update_bits_pc_T_2 = ~_s1_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] reg [35:0] s1_update_idx; // @[predictor.scala:187:30] reg s1_update_valid_0; // @[predictor.scala:188:32] wire _s1_meta_write_way_T_13; // @[btb.scala:134:27] wire s1_meta_write_way; // @[btb.scala:53:21] reg f3_meta_REG_write_way; // @[btb.scala:54:32] reg f3_meta_write_way; // @[btb.scala:54:24] assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:24:7, :54:24, :57:14] reg doing_reset; // @[btb.scala:61:28] reg [6:0] reset_idx; // @[btb.scala:62:28] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:61:28, :62:28, :63:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:63:26] wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_0_is_br; // @[btb.scala:70:26] wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_3_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_0_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_3_is_br; // @[btb.scala:70:26] wire [12:0] entry_btb_offset = s1_req_rbtb_0_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_extended = s1_req_rbtb_0_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_2_offset = s1_req_rbtb_0_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_2_extended = s1_req_rbtb_0_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_4_offset = s1_req_rbtb_0_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_4_extended = s1_req_rbtb_0_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_6_offset = s1_req_rbtb_0_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_6_extended = s1_req_rbtb_0_3_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_1_offset = s1_req_rbtb_1_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_1_extended = s1_req_rbtb_1_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_3_offset = s1_req_rbtb_1_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_3_extended = s1_req_rbtb_1_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_5_offset = s1_req_rbtb_1_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_5_extended = s1_req_rbtb_1_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_7_offset = s1_req_rbtb_1_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_7_extended = s1_req_rbtb_1_3_extended; // @[btb.scala:71:26, :90:31] wire [39:0] s1_req_rebtb; // @[btb.scala:72:26] wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29] wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:74:29, :124:98] wire _s1_resp_0_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_1_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_2_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_3_valid_T_2; // @[btb.scala:97:50] wire s1_resp_0_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_0_bits; // @[btb.scala:76:23] wire s1_resp_1_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_1_bits; // @[btb.scala:76:23] wire s1_resp_2_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_2_bits; // @[btb.scala:76:23] wire s1_resp_3_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_3_bits; // @[btb.scala:76:23] wire _s1_is_br_0_T_2; // @[btb.scala:99:54] wire _s1_is_br_1_T_2; // @[btb.scala:99:54] wire _s1_is_br_2_T_2; // @[btb.scala:99:54] wire _s1_is_br_3_T_2; // @[btb.scala:99:54] wire s1_is_br_0; // @[btb.scala:77:23] wire s1_is_br_1; // @[btb.scala:77:23] wire s1_is_br_2; // @[btb.scala:77:23] wire s1_is_br_3; // @[btb.scala:77:23] wire _s1_is_jal_0_T_3; // @[btb.scala:100:54] wire _s1_is_jal_1_T_3; // @[btb.scala:100:54] wire _s1_is_jal_2_T_3; // @[btb.scala:100:54] wire _s1_is_jal_3_T_3; // @[btb.scala:100:54] wire s1_is_jal_0; // @[btb.scala:78:23] wire s1_is_jal_1; // @[btb.scala:78:23] wire s1_is_jal_2; // @[btb.scala:78:23] wire s1_is_jal_3; // @[btb.scala:78:23] wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:80:27, :81:12] wire s1_hits_0 = s1_hit_ohs_0_0 \| s1_hit_ohs_0_1; // @[btb.scala:80:27, :85:55] wire s1_hits_1 = s1_hit_ohs_1_0 \| s1_hit_ohs_1_1; // @[btb.scala:80:27, :85:55] wire s1_hits_2 = s1_hit_ohs_2_0 \| s1_hit_ohs_2_1; // @[btb.scala:80:27, :85:55] wire s1_hits_3 = s1_hit_ohs_3_0 \| s1_hit_ohs_3_1; // @[btb.scala:80:27, :85:55] wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70] wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70] wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70] wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70] wire [39:0] _s1_targs_0_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_3_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_3_T_8; // @[btb.scala:91:28] wire [39:0] s1_targs_0_0; // @[btb.scala:87:25] wire [39:0] s1_targs_0_1; // @[btb.scala:87:25] wire [39:0] s1_targs_0_2; // @[btb.scala:87:25] wire [39:0] s1_targs_0_3; // @[btb.scala:87:25] wire [39:0] s1_targs_1_0; // @[btb.scala:87:25] wire [39:0] s1_targs_1_1; // @[btb.scala:87:25] wire [39:0] s1_targs_1_2; // @[btb.scala:87:25] wire [39:0] s1_targs_1_3; // @[btb.scala:87:25] wire [40:0] _s1_targs_0_0_T_1 = {_s1_targs_0_0_T[39], _s1_targs_0_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_0_T_2 = _s1_targs_0_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_0_T_3 = _s1_targs_0_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_0_T_4 = {_s1_targs_0_0_T_3[39], _s1_targs_0_0_T_3} + {{28{entry_btb_offset[12]}}, entry_btb_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_0_T_5 = _s1_targs_0_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_6 = _s1_targs_0_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_7 = _s1_targs_0_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_0_T_8 = entry_btb_extended ? s1_req_rebtb : _s1_targs_0_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_0 = _s1_targs_0_0_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_0_T_1 = {_s1_targs_1_0_T[39], _s1_targs_1_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_0_T_2 = _s1_targs_1_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_0_T_3 = _s1_targs_1_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_0_T_4 = {_s1_targs_1_0_T_3[39], _s1_targs_1_0_T_3} + {{28{entry_btb_1_offset[12]}}, entry_btb_1_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_0_T_5 = _s1_targs_1_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_6 = _s1_targs_1_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_7 = _s1_targs_1_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_0_T_8 = entry_btb_1_extended ? s1_req_rebtb : _s1_targs_1_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_0 = _s1_targs_1_0_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_0_bits = s1_hit_ways_0 ? s1_targs_1_0 : s1_targs_0_0; // @[Mux.scala:50:70] wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70] assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN; // @[btb.scala:99:{34,54}] assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_0_T_2 = ~_GEN; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:78:23, :100:54] reg REG; // @[btb.scala:105:18] reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_0_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_0_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_1; // @[btb.scala:109:20] assign io_resp_f2_0_taken_0 = REG & REG_1 \| io_resp_in_0_f2_0_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_2; // @[btb.scala:113:26] reg REG_3; // @[btb.scala:113:18] reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_0_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_0_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_4; // @[btb.scala:117:28] reg REG_5; // @[btb.scala:117:20] assign io_resp_f3_0_taken_0 = REG_3 & REG_5 \| io_resp_in_0_f3_0_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_1_T_1 = {_s1_targs_0_1_T[39], _s1_targs_0_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_1_T_2 = _s1_targs_0_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_1_T_3 = _s1_targs_0_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_1_T_4 = {_s1_targs_0_1_T_3[39], _s1_targs_0_1_T_3} + {{28{entry_btb_2_offset[12]}}, entry_btb_2_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_1_T_5 = _s1_targs_0_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_6 = _s1_targs_0_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_7 = _s1_targs_0_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_1_T_8 = entry_btb_2_extended ? s1_req_rebtb : _s1_targs_0_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_1 = _s1_targs_0_1_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_1_T_1 = {_s1_targs_1_1_T[39], _s1_targs_1_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_1_T_2 = _s1_targs_1_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_1_T_3 = _s1_targs_1_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_1_T_4 = {_s1_targs_1_1_T_3[39], _s1_targs_1_1_T_3} + {{28{entry_btb_3_offset[12]}}, entry_btb_3_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_1_T_5 = _s1_targs_1_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_6 = _s1_targs_1_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_7 = _s1_targs_1_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_1_T_8 = entry_btb_3_extended ? s1_req_rebtb : _s1_targs_1_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_1 = _s1_targs_1_1_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_1_bits = s1_hit_ways_1 ? s1_targs_1_1 : s1_targs_0_1; // @[Mux.scala:50:70] wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_0 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70] assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_0; // @[btb.scala:99:{34,54}] assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_1_T_2 = ~_GEN_0; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:78:23, :100:54] reg REG_6; // @[btb.scala:105:18] reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_1_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_1_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_7; // @[btb.scala:109:20] assign io_resp_f2_1_taken_0 = REG_6 & REG_7 \| io_resp_in_0_f2_1_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_8; // @[btb.scala:113:26] reg REG_9; // @[btb.scala:113:18] reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_1_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_1_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_10; // @[btb.scala:117:28] reg REG_11; // @[btb.scala:117:20] assign io_resp_f3_1_taken_0 = REG_9 & REG_11 \| io_resp_in_0_f3_1_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_2_T_1 = {_s1_targs_0_2_T[39], _s1_targs_0_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_2_T_2 = _s1_targs_0_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_2_T_3 = _s1_targs_0_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_2_T_4 = {_s1_targs_0_2_T_3[39], _s1_targs_0_2_T_3} + {{28{entry_btb_4_offset[12]}}, entry_btb_4_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_2_T_5 = _s1_targs_0_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_6 = _s1_targs_0_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_7 = _s1_targs_0_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_2_T_8 = entry_btb_4_extended ? s1_req_rebtb : _s1_targs_0_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_2 = _s1_targs_0_2_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_2_T_1 = {_s1_targs_1_2_T[39], _s1_targs_1_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_2_T_2 = _s1_targs_1_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_2_T_3 = _s1_targs_1_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_2_T_4 = {_s1_targs_1_2_T_3[39], _s1_targs_1_2_T_3} + {{28{entry_btb_5_offset[12]}}, entry_btb_5_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_2_T_5 = _s1_targs_1_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_6 = _s1_targs_1_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_7 = _s1_targs_1_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_2_T_8 = entry_btb_5_extended ? s1_req_rebtb : _s1_targs_1_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_2 = _s1_targs_1_2_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_2_bits = s1_hit_ways_2 ? s1_targs_1_2 : s1_targs_0_2; // @[Mux.scala:50:70] wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_1 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70] assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_1; // @[btb.scala:99:{34,54}] assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_2_T_2 = ~_GEN_1; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:78:23, :100:54] reg REG_12; // @[btb.scala:105:18] reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_2_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_2_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_13; // @[btb.scala:109:20] assign io_resp_f2_2_taken_0 = REG_12 & REG_13 \| io_resp_in_0_f2_2_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_14; // @[btb.scala:113:26] reg REG_15; // @[btb.scala:113:18] reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_2_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_2_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_16; // @[btb.scala:117:28] reg REG_17; // @[btb.scala:117:20] assign io_resp_f3_2_taken_0 = REG_15 & REG_17 \| io_resp_in_0_f3_2_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_3_T_1 = {_s1_targs_0_3_T[39], _s1_targs_0_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_3_T_2 = _s1_targs_0_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_3_T_3 = _s1_targs_0_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_3_T_4 = {_s1_targs_0_3_T_3[39], _s1_targs_0_3_T_3} + {{28{entry_btb_6_offset[12]}}, entry_btb_6_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_3_T_5 = _s1_targs_0_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_6 = _s1_targs_0_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_7 = _s1_targs_0_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_3_T_8 = entry_btb_6_extended ? s1_req_rebtb : _s1_targs_0_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_3 = _s1_targs_0_3_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_3_T_1 = {_s1_targs_1_3_T[39], _s1_targs_1_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_3_T_2 = _s1_targs_1_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_3_T_3 = _s1_targs_1_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_3_T_4 = {_s1_targs_1_3_T_3[39], _s1_targs_1_3_T_3} + {{28{entry_btb_7_offset[12]}}, entry_btb_7_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_3_T_5 = _s1_targs_1_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_6 = _s1_targs_1_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_7 = _s1_targs_1_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_3_T_8 = entry_btb_7_extended ? s1_req_rebtb : _s1_targs_1_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_3 = _s1_targs_1_3_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_3_bits = s1_hit_ways_3 ? s1_targs_1_3 : s1_targs_0_3; // @[Mux.scala:50:70] wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_2 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70] assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_2; // @[btb.scala:99:{34,54}] assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_3_T_2 = ~_GEN_2; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:78:23, :100:54] reg REG_18; // @[btb.scala:105:18] reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_3_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_3_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_19; // @[btb.scala:109:20] assign io_resp_f2_3_taken_0 = REG_18 & REG_19 \| io_resp_in_0_f2_3_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_20; // @[btb.scala:113:26] reg REG_21; // @[btb.scala:113:18] reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_3_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_3_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_22; // @[btb.scala:117:28] reg REG_23; // @[btb.scala:117:20] assign io_resp_f3_3_taken_0 = REG_21 & REG_23 \| io_resp_in_0_f3_3_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:124:{30,62}] wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:124:{30,80}] wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:124:{30,80}] wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:124:80] wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:124:{30,80}] wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:124:{30,80}] wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:124:80] wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:124:80] wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:124:{22,80,98}] wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:124:22, :128:14] wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:128:14, :130:20] wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:128:14, :130:20] wire _s1_meta_write_way_T = s1_hits_0 \| s1_hits_1; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T \| s1_hits_2; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 \| s1_hits_3; // @[btb.scala:85:55, :134:44] wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 \| _s1_meta_write_way_T_4; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 \| _s1_meta_write_way_T_5; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 \| _s1_meta_write_way_T_6; // @[btb.scala:135:{38,54}] wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45] assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70] assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:53:21, :134:27] wire _s1_update_meta_T; // @[btb.scala:139:55] wire s1_update_meta_write_way; // @[btb.scala:139:55] assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:139:55] assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:185:30] assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:139:55] wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:185:30] wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:144:24] wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:144:{24,62}] wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:143:{49,56}, :144:62] wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:143:56] wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:143:56] wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:143:56, :145:46] wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:143:56, :146:46] wire offset_is_extended = _offset_is_extended_T \| _offset_is_extended_T_1; // @[btb.scala:145:{46,65}, :146:46] wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:145:65, :149:34] wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:149:34] assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:143:56, :149:34, :151:32] wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:185:30] wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _GEN_3 = s1_update_bits_is_mispredict_update \| s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :185:30] wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49] assign _s1_update_wbtb_mask_T_3 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49] assign _s1_update_wmeta_mask_T_1 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wbtb_mask_T_4 = \|s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 \| _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}] wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26] wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:153:{9,97}] wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35] wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask \| s1_update_bits_br_mask; // @[predictor.scala:185:30] wire _s1_update_wmeta_mask_T_2 = \|s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 \| _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}] wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :185:30] wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:156:{10,38}] wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 \| _s1_update_wmeta_mask_T_8; // @[btb.scala:156:{10,74}, :157:40] wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:155:{52,78}, :156:74] wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:163:43] wire s1_update_wmeta_data_0_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_1_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_2_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_3_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:160:34] wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:160:34, :164:62] assign s1_req_rmeta_0_0_tag = _btb_meta_way_0_R0_data[28:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_0_is_br = _btb_meta_way_0_R0_data[29]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_tag = _btb_meta_way_0_R0_data[58:30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_is_br = _btb_meta_way_0_R0_data[59]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_tag = _btb_meta_way_0_R0_data[88:60]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_is_br = _btb_meta_way_0_R0_data[89]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_tag = _btb_meta_way_0_R0_data[118:90]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_is_br = _btb_meta_way_0_R0_data[119]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_0_0_extended = _btb_data_way_0_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_0_offset = _btb_data_way_0_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_extended = _btb_data_way_0_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_offset = _btb_data_way_0_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_extended = _btb_data_way_0_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_offset = _btb_data_way_0_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_extended = _btb_data_way_0_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_offset = _btb_data_way_0_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_0_MPORT_2_en = doing_reset \| ~s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:{25,53}] wire [6:0] _T_56 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_0_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_0_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign s1_req_rmeta_1_0_tag = _btb_meta_way_1_R0_data[28:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_0_is_br = _btb_meta_way_1_R0_data[29]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_tag = _btb_meta_way_1_R0_data[58:30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_is_br = _btb_meta_way_1_R0_data[59]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_tag = _btb_meta_way_1_R0_data[88:60]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_is_br = _btb_meta_way_1_R0_data[89]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_tag = _btb_meta_way_1_R0_data[118:90]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_is_br = _btb_meta_way_1_R0_data[119]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_1_0_extended = _btb_data_way_1_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_0_offset = _btb_data_way_1_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_extended = _btb_data_way_1_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_offset = _btb_data_way_1_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_extended = _btb_data_way_1_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_offset = _btb_data_way_1_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_extended = _btb_data_way_1_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_offset = _btb_data_way_1_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_1_MPORT_6_en = doing_reset \| s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:25] wire [6:0] _T_113 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_1_MPORT_6_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_1_MPORT_7_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:215:30] always @(posedge clock) begin // @[btb.scala:24:7] s1_idx <= s0_idx; // @[frontend.scala:149:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= s0_pc; // @[frontend.scala:147:31] s2_pc <= s1_pc; // @[predictor.scala:178:22, :179:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:185:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:185:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:185:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:185:30] s1_update_bits_pc <= _s1_update_bits_pc_T_2; // @[frontend.scala:147:31] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:185:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:185:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:185:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:185:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:185:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:185:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:185:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:149:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:188:32] f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:53:21, :54:32] f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:54:{24,32}] REG <= s1_hits_0; // @[btb.scala:85:55, :105:18] io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:77:23, :107:44] io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:78:23, :108:44] REG_1 <= s1_is_jal_0; // @[btb.scala:78:23, :109:20] REG_2 <= s1_hits_0; // @[btb.scala:85:55, :113:26] REG_3 <= REG_2; // @[btb.scala:113:{18,26}] io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:24:7, :116:44] REG_4 <= s1_is_jal_0; // @[btb.scala:78:23, :117:28] REG_5 <= REG_4; // @[btb.scala:117:{20,28}] REG_6 <= s1_hits_1; // @[btb.scala:85:55, :105:18] io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:77:23, :107:44] io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:78:23, :108:44] REG_7 <= s1_is_jal_1; // @[btb.scala:78:23, :109:20] REG_8 <= s1_hits_1; // @[btb.scala:85:55, :113:26] REG_9 <= REG_8; // @[btb.scala:113:{18,26}] io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:24:7, :116:44] REG_10 <= s1_is_jal_1; // @[btb.scala:78:23, :117:28] REG_11 <= REG_10; // @[btb.scala:117:{20,28}] REG_12 <= s1_hits_2; // @[btb.scala:85:55, :105:18] io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:77:23, :107:44] io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:78:23, :108:44] REG_13 <= s1_is_jal_2; // @[btb.scala:78:23, :109:20] REG_14 <= s1_hits_2; // @[btb.scala:85:55, :113:26] REG_15 <= REG_14; // @[btb.scala:113:{18,26}] io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:24:7, :116:44] REG_16 <= s1_is_jal_2; // @[btb.scala:78:23, :117:28] REG_17 <= REG_16; // @[btb.scala:117:{20,28}] REG_18 <= s1_hits_3; // @[btb.scala:85:55, :105:18] io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:77:23, :107:44] io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:78:23, :108:44] REG_19 <= s1_is_jal_3; // @[btb.scala:78:23, :109:20] REG_20 <= s1_hits_3; // @[btb.scala:85:55, :113:26] REG_21 <= REG_20; // @[btb.scala:113:{18,26}] io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:24:7, :116:44] REG_22 <= s1_is_jal_3; // @[btb.scala:78:23, :117:28] REG_23 <= REG_22; // @[btb.scala:117:{20,28}] if (reset) begin // @[btb.scala:24:7] doing_reset <= 1'h1; // @[btb.scala:61:28] reset_idx <= 7'h0; // @[btb.scala:62:28] end else begin // @[btb.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:61:28, :62:28, :64:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[btb.scala:62:28, :63:26] end always @(posedge) btb_meta_way_0 btb_meta_way_0 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_0_MPORT_3_data_3, btb_meta_way_0_MPORT_3_data_2, btb_meta_way_0_MPORT_3_data_1, btb_meta_way_0_MPORT_3_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_0 btb_data_way_0 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_0_MPORT_2_data_3, btb_data_way_0_MPORT_2_data_2, btb_data_way_0_MPORT_2_data_1, btb_data_way_0_MPORT_2_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_meta_way_1 btb_meta_way_1 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_1_MPORT_7_data_3, btb_meta_way_1_MPORT_7_data_2, btb_meta_way_1_MPORT_7_data_1, btb_meta_way_1_MPORT_7_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_1 btb_data_way_1 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_1_MPORT_6_data_3, btb_data_way_1_MPORT_6_data_2, btb_data_way_1_MPORT_6_data_1, btb_data_way_1_MPORT_6_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_ebtb btb_ebtb ( // @[btb.scala:213:27] .R0_addr (_s1_req_rebtb_T), // @[btb.scala:215:30] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (s1_req_rebtb), .W0_addr (s1_update_idx[6:0]), // @[predictor.scala:187:30] .W0_en ((\|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:145:65, :152:58, :216:{31,39}] .W0_clk (clock), .W0_data (s1_update_bits_target) // @[predictor.scala:185:30] ); // @[btb.scala:213:27] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_f3_meta = io_f3_meta_0; // @[btb.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_51 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_51( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ProbeUnit : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, rep : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<2>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, flip way_en : UInt<8>, flip mshr_rdy : UInt<1>, flip block_state : { state : UInt<2>}} regreset state : UInt<4>, clock, reset, UInt<4>(0h0) reg req : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node req_idx = bits(req.address, 11, 6) node req_tag = shr(req.address, 12) reg way_en : UInt, clock node tag_matches = orr(way_en) reg old_coh : { state : UInt<2>}, clock wire miss_coh : { state : UInt<2>} connect miss_coh.state, UInt<2>(0h0) node reply_coh = mux(tag_matches, old_coh, miss_coh) node _r_T = cat(req.param, reply_coh.state) node _r_T_1 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_2 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_3 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_4 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_5 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_6 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_7 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_8 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_9 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_10 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_11 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_12 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_13 = eq(_r_T_12, _r_T) node _r_T_14 = mux(_r_T_13, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_15 = mux(_r_T_13, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_16 = mux(_r_T_13, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_17 = eq(_r_T_11, _r_T) node _r_T_18 = mux(_r_T_17, UInt<1>(0h0), _r_T_14) node _r_T_19 = mux(_r_T_17, UInt<3>(0h2), _r_T_15) node _r_T_20 = mux(_r_T_17, UInt<2>(0h0), _r_T_16) node _r_T_21 = eq(_r_T_10, _r_T) node _r_T_22 = mux(_r_T_21, UInt<1>(0h0), _r_T_18) node _r_T_23 = mux(_r_T_21, UInt<3>(0h1), _r_T_19) node _r_T_24 = mux(_r_T_21, UInt<2>(0h0), _r_T_20) node _r_T_25 = eq(_r_T_9, _r_T) node _r_T_26 = mux(_r_T_25, UInt<1>(0h1), _r_T_22) node _r_T_27 = mux(_r_T_25, UInt<3>(0h1), _r_T_23) node _r_T_28 = mux(_r_T_25, UInt<2>(0h0), _r_T_24) node _r_T_29 = eq(_r_T_8, _r_T) node _r_T_30 = mux(_r_T_29, UInt<1>(0h0), _r_T_26) node _r_T_31 = mux(_r_T_29, UInt<3>(0h5), _r_T_27) node _r_T_32 = mux(_r_T_29, UInt<2>(0h0), _r_T_28) node _r_T_33 = eq(_r_T_7, _r_T) node _r_T_34 = mux(_r_T_33, UInt<1>(0h0), _r_T_30) node _r_T_35 = mux(_r_T_33, UInt<3>(0h4), _r_T_31) node _r_T_36 = mux(_r_T_33, UInt<2>(0h1), _r_T_32) node _r_T_37 = eq(_r_T_6, _r_T) node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_34) node _r_T_39 = mux(_r_T_37, UInt<3>(0h0), _r_T_35) node _r_T_40 = mux(_r_T_37, UInt<2>(0h1), _r_T_36) node _r_T_41 = eq(_r_T_5, _r_T) node _r_T_42 = mux(_r_T_41, UInt<1>(0h1), _r_T_38) node _r_T_43 = mux(_r_T_41, UInt<3>(0h0), _r_T_39) node _r_T_44 = mux(_r_T_41, UInt<2>(0h1), _r_T_40) node _r_T_45 = eq(_r_T_4, _r_T) node _r_T_46 = mux(_r_T_45, UInt<1>(0h0), _r_T_42) node _r_T_47 = mux(_r_T_45, UInt<3>(0h5), _r_T_43) node _r_T_48 = mux(_r_T_45, UInt<2>(0h0), _r_T_44) node _r_T_49 = eq(_r_T_3, _r_T) node _r_T_50 = mux(_r_T_49, UInt<1>(0h0), _r_T_46) node _r_T_51 = mux(_r_T_49, UInt<3>(0h4), _r_T_47) node _r_T_52 = mux(_r_T_49, UInt<2>(0h1), _r_T_48) node _r_T_53 = eq(_r_T_2, _r_T) node _r_T_54 = mux(_r_T_53, UInt<1>(0h0), _r_T_50) node _r_T_55 = mux(_r_T_53, UInt<3>(0h3), _r_T_51) node _r_T_56 = mux(_r_T_53, UInt<2>(0h2), _r_T_52) node _r_T_57 = eq(_r_T_1, _r_T) node is_dirty = mux(_r_T_57, UInt<1>(0h1), _r_T_54) node report_param = mux(_r_T_57, UInt<3>(0h3), _r_T_55) node r_3 = mux(_r_T_57, UInt<2>(0h2), _r_T_56) wire new_coh : { state : UInt<2>} connect new_coh.state, r_3 node _io_req_ready_T = eq(state, UInt<4>(0h0)) connect io.req.ready, _io_req_ready_T node _io_rep_valid_T = eq(state, UInt<4>(0h5)) connect io.rep.valid, _io_rep_valid_T wire io_rep_bits_c : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect io_rep_bits_c.opcode, UInt<3>(0h4) connect io_rep_bits_c.param, report_param connect io_rep_bits_c.size, req.size connect io_rep_bits_c.source, req.source connect io_rep_bits_c.address, req.address invalidate io_rep_bits_c.data connect io_rep_bits_c.corrupt, UInt<1>(0h0) connect io.rep.bits, io_rep_bits_c node _T = eq(io.rep.valid, UInt<1>(0h0)) node opdata = bits(io.rep.bits.opcode, 0, 0) node _T_1 = eq(opdata, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it\n at NBDcache.scala:580 assert(!io.rep.valid \|\| !edge.hasData(io.rep.bits),\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_meta_read_valid_T = eq(state, UInt<4>(0h1)) connect io.meta_read.valid, _io_meta_read_valid_T connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag node _io_meta_read_bits_way_en_T = not(UInt<8>(0h0)) connect io.meta_read.bits.way_en, _io_meta_read_bits_way_en_T node _io_meta_write_valid_T = eq(state, UInt<4>(0h8)) connect io.meta_write.valid, _io_meta_write_valid_T connect io.meta_write.bits.way_en, way_en connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.tag, req_tag connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.data.coh, new_coh node _io_wb_req_valid_T = eq(state, UInt<4>(0h6)) connect io.wb_req.valid, _io_wb_req_valid_T connect io.wb_req.bits.source, req.source connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.tag, req_tag connect io.wb_req.bits.param, report_param connect io.wb_req.bits.way_en, way_en connect io.wb_req.bits.voluntary, UInt<1>(0h0) node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect state, UInt<4>(0h1) connect req, io.req.bits node _T_7 = and(io.meta_read.ready, io.meta_read.valid) when _T_7 : connect state, UInt<4>(0h2) node _T_8 = eq(state, UInt<4>(0h2)) when _T_8 : connect state, UInt<4>(0h3) node _T_9 = eq(state, UInt<4>(0h3)) when _T_9 : connect old_coh, io.block_state connect way_en, io.way_en node _state_T = mux(io.mshr_rdy, UInt<4>(0h4), UInt<4>(0h1)) connect state, _state_T node _T_10 = eq(state, UInt<4>(0h4)) when _T_10 : node _state_T_1 = and(tag_matches, is_dirty) node _state_T_2 = mux(_state_T_1, UInt<4>(0h6), UInt<4>(0h5)) connect state, _state_T_2 node _T_11 = eq(state, UInt<4>(0h5)) node _T_12 = and(_T_11, io.rep.ready) when _T_12 : node _state_T_3 = mux(tag_matches, UInt<4>(0h8), UInt<4>(0h0)) connect state, _state_T_3 node _T_13 = and(io.wb_req.ready, io.wb_req.valid) when _T_13 : connect state, UInt<4>(0h7) node _T_14 = eq(state, UInt<4>(0h7)) node _T_15 = and(_T_14, io.wb_req.ready) when _T_15 : connect state, UInt<4>(0h8) node _T_16 = and(io.meta_write.ready, io.meta_write.valid) when _T_16 : connect state, UInt<4>(0h0)	module ProbeUnit( // @[NBDcache.scala:548:7] input clock, // @[NBDcache.scala:548:7] input reset, // @[NBDcache.scala:548:7] output io_req_ready, // @[NBDcache.scala:549:14] input io_req_valid, // @[NBDcache.scala:549:14] input [2:0] io_req_bits_opcode, // @[NBDcache.scala:549:14] input [1:0] io_req_bits_param, // @[NBDcache.scala:549:14] input [3:0] io_req_bits_size, // @[NBDcache.scala:549:14] input [1:0] io_req_bits_source, // @[NBDcache.scala:549:14] input [31:0] io_req_bits_address, // @[NBDcache.scala:549:14] input [7:0] io_req_bits_mask, // @[NBDcache.scala:549:14] input [63:0] io_req_bits_data, // @[NBDcache.scala:549:14] input io_req_bits_corrupt, // @[NBDcache.scala:549:14] input io_rep_ready, // @[NBDcache.scala:549:14] output io_rep_valid, // @[NBDcache.scala:549:14] output [2:0] io_rep_bits_param, // @[NBDcache.scala:549:14] output [3:0] io_rep_bits_size, // @[NBDcache.scala:549:14] output [1:0] io_rep_bits_source, // @[NBDcache.scala:549:14] output [31:0] io_rep_bits_address, // @[NBDcache.scala:549:14] input io_meta_read_ready, // @[NBDcache.scala:549:14] output io_meta_read_valid, // @[NBDcache.scala:549:14] output [5:0] io_meta_read_bits_idx, // @[NBDcache.scala:549:14] output [19:0] io_meta_read_bits_tag, // @[NBDcache.scala:549:14] input io_meta_write_ready, // @[NBDcache.scala:549:14] output io_meta_write_valid, // @[NBDcache.scala:549:14] output [5:0] io_meta_write_bits_idx, // @[NBDcache.scala:549:14] output [7:0] io_meta_write_bits_way_en, // @[NBDcache.scala:549:14] output [19:0] io_meta_write_bits_tag, // @[NBDcache.scala:549:14] output [1:0] io_meta_write_bits_data_coh_state, // @[NBDcache.scala:549:14] output [19:0] io_meta_write_bits_data_tag, // @[NBDcache.scala:549:14] input io_wb_req_ready, // @[NBDcache.scala:549:14] output io_wb_req_valid, // @[NBDcache.scala:549:14] output [19:0] io_wb_req_bits_tag, // @[NBDcache.scala:549:14] output [5:0] io_wb_req_bits_idx, // @[NBDcache.scala:549:14] output [1:0] io_wb_req_bits_source, // @[NBDcache.scala:549:14] output [2:0] io_wb_req_bits_param, // @[NBDcache.scala:549:14] output [7:0] io_wb_req_bits_way_en, // @[NBDcache.scala:549:14] input [7:0] io_way_en, // @[NBDcache.scala:549:14] input io_mshr_rdy, // @[NBDcache.scala:549:14] input [1:0] io_block_state_state // @[NBDcache.scala:549:14] ); wire io_req_valid_0 = io_req_valid; // @[NBDcache.scala:548:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[NBDcache.scala:548:7] wire [1:0] io_req_bits_param_0 = io_req_bits_param; // @[NBDcache.scala:548:7] wire [3:0] io_req_bits_size_0 = io_req_bits_size; // @[NBDcache.scala:548:7] wire [1:0] io_req_bits_source_0 = io_req_bits_source; // @[NBDcache.scala:548:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[NBDcache.scala:548:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[NBDcache.scala:548:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[NBDcache.scala:548:7] wire io_req_bits_corrupt_0 = io_req_bits_corrupt; // @[NBDcache.scala:548:7] wire io_rep_ready_0 = io_rep_ready; // @[NBDcache.scala:548:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[NBDcache.scala:548:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[NBDcache.scala:548:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[NBDcache.scala:548:7] wire [7:0] io_way_en_0 = io_way_en; // @[NBDcache.scala:548:7] wire io_mshr_rdy_0 = io_mshr_rdy; // @[NBDcache.scala:548:7] wire [1:0] io_block_state_state_0 = io_block_state_state; // @[NBDcache.scala:548:7] wire [3:0] _r_T_1 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_2 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_3 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_4 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_5 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_6 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_7 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_8 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_9 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_10 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_11 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_12 = 4'h8; // @[Metadata.scala:133:10] wire [1:0] miss_coh_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_16 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_20 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_24 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_28 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_32 = 2'h0; // @[Misc.scala:38:63] wire [7:0] io_meta_read_bits_way_en = 8'hFF; // @[NBDcache.scala:548:7] wire [7:0] _io_meta_read_bits_way_en_T = 8'hFF; // @[NBDcache.scala:586:31] wire io_rep_bits_corrupt = 1'h0; // @[NBDcache.scala:548:7] wire io_wb_req_bits_voluntary = 1'h0; // @[NBDcache.scala:548:7] wire _r_T_14 = 1'h0; // @[Misc.scala:38:9] wire _r_T_18 = 1'h0; // @[Misc.scala:38:9] wire _r_T_22 = 1'h0; // @[Misc.scala:38:9] wire io_rep_bits_c_corrupt = 1'h0; // @[Edges.scala:416:17] wire opdata = 1'h0; // @[Edges.scala:102:36] wire [63:0] io_rep_bits_data = 64'h0; // @[NBDcache.scala:548:7] wire [63:0] io_rep_bits_c_data = 64'h0; // @[Edges.scala:416:17] wire [2:0] io_rep_bits_opcode = 3'h4; // @[NBDcache.scala:548:7] wire _io_req_ready_T; // @[NBDcache.scala:576:25] wire [2:0] io_rep_bits_c_opcode = 3'h4; // @[Edges.scala:416:17] wire _io_rep_valid_T; // @[NBDcache.scala:577:25] wire [2:0] io_rep_bits_c_param; // @[Edges.scala:416:17] wire [3:0] io_rep_bits_c_size; // @[Edges.scala:416:17] wire [1:0] io_rep_bits_c_source; // @[Edges.scala:416:17] wire [31:0] io_rep_bits_c_address; // @[Edges.scala:416:17] wire _io_meta_read_valid_T; // @[NBDcache.scala:583:31] wire [5:0] req_idx; // @[NBDcache.scala:566:28] wire [19:0] req_tag; // @[NBDcache.scala:567:29] wire _io_meta_write_valid_T; // @[NBDcache.scala:588:32] wire [1:0] new_coh_state; // @[Metadata.scala:160:20] wire _io_wb_req_valid_T; // @[NBDcache.scala:595:28] wire [2:0] report_param; // @[Misc.scala:38:36] wire io_req_ready_0; // @[NBDcache.scala:548:7] wire [2:0] io_rep_bits_param_0; // @[NBDcache.scala:548:7] wire [3:0] io_rep_bits_size_0; // @[NBDcache.scala:548:7] wire [1:0] io_rep_bits_source_0; // @[NBDcache.scala:548:7] wire [31:0] io_rep_bits_address_0; // @[NBDcache.scala:548:7] wire io_rep_valid_0; // @[NBDcache.scala:548:7] wire [5:0] io_meta_read_bits_idx_0; // @[NBDcache.scala:548:7] wire [19:0] io_meta_read_bits_tag_0; // @[NBDcache.scala:548:7] wire io_meta_read_valid_0; // @[NBDcache.scala:548:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:548:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[NBDcache.scala:548:7] wire [5:0] io_meta_write_bits_idx_0; // @[NBDcache.scala:548:7] wire [7:0] io_meta_write_bits_way_en_0; // @[NBDcache.scala:548:7] wire [19:0] io_meta_write_bits_tag_0; // @[NBDcache.scala:548:7] wire io_meta_write_valid_0; // @[NBDcache.scala:548:7] wire [19:0] io_wb_req_bits_tag_0; // @[NBDcache.scala:548:7] wire [5:0] io_wb_req_bits_idx_0; // @[NBDcache.scala:548:7] wire [1:0] io_wb_req_bits_source_0; // @[NBDcache.scala:548:7] wire [2:0] io_wb_req_bits_param_0; // @[NBDcache.scala:548:7] wire [7:0] io_wb_req_bits_way_en_0; // @[NBDcache.scala:548:7] wire io_wb_req_valid_0; // @[NBDcache.scala:548:7] reg [3:0] state; // @[NBDcache.scala:563:22] reg [2:0] req_opcode; // @[NBDcache.scala:565:16] reg [1:0] req_param; // @[NBDcache.scala:565:16] reg [3:0] req_size; // @[NBDcache.scala:565:16] assign io_rep_bits_c_size = req_size; // @[Edges.scala:416:17] reg [1:0] req_source; // @[NBDcache.scala:565:16] assign io_wb_req_bits_source_0 = req_source; // @[NBDcache.scala:548:7, :565:16] assign io_rep_bits_c_source = req_source; // @[Edges.scala:416:17] reg [31:0] req_address; // @[NBDcache.scala:565:16] assign io_rep_bits_c_address = req_address; // @[Edges.scala:416:17] reg [7:0] req_mask; // @[NBDcache.scala:565:16] reg [63:0] req_data; // @[NBDcache.scala:565:16] reg req_corrupt; // @[NBDcache.scala:565:16] assign req_idx = req_address[11:6]; // @[NBDcache.scala:565:16, :566:28] assign io_meta_read_bits_idx_0 = req_idx; // @[NBDcache.scala:548:7, :566:28] assign io_meta_write_bits_idx_0 = req_idx; // @[NBDcache.scala:548:7, :566:28] assign io_wb_req_bits_idx_0 = req_idx; // @[NBDcache.scala:548:7, :566:28] assign req_tag = req_address[31:12]; // @[NBDcache.scala:565:16, :567:29] assign io_meta_read_bits_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] assign io_meta_write_bits_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] assign io_meta_write_bits_data_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] assign io_wb_req_bits_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] reg [7:0] way_en; // @[NBDcache.scala:569:19] assign io_meta_write_bits_way_en_0 = way_en; // @[NBDcache.scala:548:7, :569:19] assign io_wb_req_bits_way_en_0 = way_en; // @[NBDcache.scala:548:7, :569:19] wire tag_matches = \|way_en; // @[NBDcache.scala:569:19, :570:28] reg [1:0] old_coh_state; // @[NBDcache.scala:571:20] wire [1:0] reply_coh_state = tag_matches ? old_coh_state : 2'h0; // @[NBDcache.scala:570:28, :571:20, :573:22] wire [3:0] _r_T = {req_param, reply_coh_state}; // @[Metadata.scala:120:19] wire _r_T_13 = _r_T == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_15 = _r_T_13 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_17 = _r_T == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_19 = _r_T_17 ? 3'h2 : _r_T_15; // @[Misc.scala:38:36, :56:20] wire _r_T_21 = _r_T == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_23 = _r_T_21 ? 3'h1 : _r_T_19; // @[Misc.scala:38:36, :56:20] wire _r_T_25 = _r_T == 4'hB; // @[Misc.scala:56:20] wire _r_T_26 = _r_T_25; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_27 = _r_T_25 ? 3'h1 : _r_T_23; // @[Misc.scala:38:36, :56:20] wire _r_T_29 = _r_T == 4'h4; // @[Misc.scala:56:20] wire _r_T_30 = ~_r_T_29 & _r_T_26; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_31 = _r_T_29 ? 3'h5 : _r_T_27; // @[Misc.scala:38:36, :56:20] wire _r_T_33 = _r_T == 4'h5; // @[Misc.scala:56:20] wire _r_T_34 = ~_r_T_33 & _r_T_30; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_35 = _r_T_33 ? 3'h4 : _r_T_31; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_36 = {1'h0, _r_T_33}; // @[Misc.scala:38:63, :56:20] wire _r_T_37 = _r_T == 4'h6; // @[Misc.scala:56:20] wire _r_T_38 = ~_r_T_37 & _r_T_34; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_39 = _r_T_37 ? 3'h0 : _r_T_35; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_40 = _r_T_37 ? 2'h1 : _r_T_36; // @[Misc.scala:38:63, :56:20] wire _r_T_41 = _r_T == 4'h7; // @[Misc.scala:56:20] wire _r_T_42 = _r_T_41 \| _r_T_38; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_43 = _r_T_41 ? 3'h0 : _r_T_39; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_44 = _r_T_41 ? 2'h1 : _r_T_40; // @[Misc.scala:38:63, :56:20] wire _r_T_45 = _r_T == 4'h0; // @[Misc.scala:56:20] wire _r_T_46 = ~_r_T_45 & _r_T_42; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_47 = _r_T_45 ? 3'h5 : _r_T_43; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_48 = _r_T_45 ? 2'h0 : _r_T_44; // @[Misc.scala:38:63, :56:20] wire _r_T_49 = _r_T == 4'h1; // @[Misc.scala:56:20] wire _r_T_50 = ~_r_T_49 & _r_T_46; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_51 = _r_T_49 ? 3'h4 : _r_T_47; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_52 = _r_T_49 ? 2'h1 : _r_T_48; // @[Misc.scala:38:63, :56:20] wire _r_T_53 = _r_T == 4'h2; // @[Misc.scala:56:20] wire _r_T_54 = ~_r_T_53 & _r_T_50; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_55 = _r_T_53 ? 3'h3 : _r_T_51; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_56 = _r_T_53 ? 2'h2 : _r_T_52; // @[Misc.scala:38:63, :56:20] wire _r_T_57 = _r_T == 4'h3; // @[Misc.scala:56:20] wire is_dirty = _r_T_57 \| _r_T_54; // @[Misc.scala:38:9, :56:20] assign report_param = _r_T_57 ? 3'h3 : _r_T_55; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = report_param; // @[Misc.scala:38:36] assign io_rep_bits_c_param = report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_57 ? 2'h2 : _r_T_56; // @[Misc.scala:38:63, :56:20] assign new_coh_state = r_3; // @[Misc.scala:38:63] assign io_meta_write_bits_data_coh_state_0 = new_coh_state; // @[Metadata.scala:160:20] assign _io_req_ready_T = state == 4'h0; // @[NBDcache.scala:563:22, :576:25] assign io_req_ready_0 = _io_req_ready_T; // @[NBDcache.scala:548:7, :576:25] assign _io_rep_valid_T = state == 4'h5; // @[NBDcache.scala:563:22, :577:25] assign io_rep_valid_0 = _io_rep_valid_T; // @[NBDcache.scala:548:7, :577:25] assign io_rep_bits_param_0 = io_rep_bits_c_param; // @[Edges.scala:416:17] assign io_rep_bits_size_0 = io_rep_bits_c_size; // @[Edges.scala:416:17] assign io_rep_bits_source_0 = io_rep_bits_c_source; // @[Edges.scala:416:17] assign io_rep_bits_address_0 = io_rep_bits_c_address; // @[Edges.scala:416:17] assign _io_meta_read_valid_T = state == 4'h1; // @[NBDcache.scala:563:22, :583:31] assign io_meta_read_valid_0 = _io_meta_read_valid_T; // @[NBDcache.scala:548:7, :583:31] assign _io_meta_write_valid_T = state == 4'h8; // @[NBDcache.scala:563:22, :588:32] assign io_meta_write_valid_0 = _io_meta_write_valid_T; // @[NBDcache.scala:548:7, :588:32] assign _io_wb_req_valid_T = state == 4'h6; // @[NBDcache.scala:563:22, :595:28] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[NBDcache.scala:548:7, :595:28] wire [3:0] _state_T = io_mshr_rdy_0 ? 4'h4 : 4'h1; // @[NBDcache.scala:548:7, :623:17] wire _state_T_1 = tag_matches & is_dirty; // @[Misc.scala:38:9] wire [3:0] _state_T_2 = _state_T_1 ? 4'h6 : 4'h5; // @[NBDcache.scala:627:{17,30}] wire [3:0] _state_T_3 = {tag_matches, 3'h0}; // @[NBDcache.scala:570:28, :631:17] wire _T_6 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _T_9 = state == 4'h3; // @[NBDcache.scala:563:22, :619:15] always @(posedge clock) begin // @[NBDcache.scala:548:7] if (reset) // @[NBDcache.scala:548:7] state <= 4'h0; // @[NBDcache.scala:563:22] else if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] state <= 4'h0; // @[NBDcache.scala:563:22] else if (state == 4'h7 & io_wb_req_ready_0) // @[NBDcache.scala:548:7, :563:22, :640:{15,36}] state <= 4'h8; // @[NBDcache.scala:563:22] else if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h7; // @[NBDcache.scala:563:22] else if (_io_rep_valid_T & io_rep_ready_0) // @[NBDcache.scala:548:7, :577:25, :630:29] state <= _state_T_3; // @[NBDcache.scala:563:22, :631:17] else if (state == 4'h4) // @[NBDcache.scala:563:22, :626:15] state <= _state_T_2; // @[NBDcache.scala:563:22, :627:17] else if (_T_9) // @[NBDcache.scala:619:15] state <= _state_T; // @[NBDcache.scala:563:22, :623:17] else if (state == 4'h2) // @[NBDcache.scala:563:22, :615:15] state <= 4'h3; // @[NBDcache.scala:563:22] else if (io_meta_read_ready_0 & io_meta_read_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[NBDcache.scala:563:22] else if (_T_6) // @[Decoupled.scala:51:35] state <= 4'h1; // @[NBDcache.scala:563:22] if (_T_6) begin // @[Decoupled.scala:51:35] req_opcode <= io_req_bits_opcode_0; // @[NBDcache.scala:548:7, :565:16] req_param <= io_req_bits_param_0; // @[NBDcache.scala:548:7, :565:16] req_size <= io_req_bits_size_0; // @[NBDcache.scala:548:7, :565:16] req_source <= io_req_bits_source_0; // @[NBDcache.scala:548:7, :565:16] req_address <= io_req_bits_address_0; // @[NBDcache.scala:548:7, :565:16] req_mask <= io_req_bits_mask_0; // @[NBDcache.scala:548:7, :565:16] req_data <= io_req_bits_data_0; // @[NBDcache.scala:548:7, :565:16] req_corrupt <= io_req_bits_corrupt_0; // @[NBDcache.scala:548:7, :565:16] end if (_T_9) begin // @[NBDcache.scala:619:15] way_en <= io_way_en_0; // @[NBDcache.scala:548:7, :569:19] old_coh_state <= io_block_state_state_0; // @[NBDcache.scala:548:7, :571:20] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[NBDcache.scala:548:7] assign io_rep_valid = io_rep_valid_0; // @[NBDcache.scala:548:7] assign io_rep_bits_param = io_rep_bits_param_0; // @[NBDcache.scala:548:7] assign io_rep_bits_size = io_rep_bits_size_0; // @[NBDcache.scala:548:7] assign io_rep_bits_source = io_rep_bits_source_0; // @[NBDcache.scala:548:7] assign io_rep_bits_address = io_rep_bits_address_0; // @[NBDcache.scala:548:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[NBDcache.scala:548:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[NBDcache.scala:548:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[NBDcache.scala:548:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[NBDcache.scala:548:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_source = io_wb_req_bits_source_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[NBDcache.scala:548:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AccPipe_8 : input clock : Clock input reset : Reset output io : { flip op1 : SInt<32>, flip op2 : SInt<32>, sum : SInt<32>} node _io_sum_T = add(io.op1, io.op2) node _io_sum_T_1 = tail(_io_sum_T, 1) node _io_sum_T_2 = asSInt(_io_sum_T_1) reg io_sum_r : SInt<32>, clock when UInt<1>(0h1) : connect io_sum_r, _io_sum_T_2 connect io.sum, io_sum_r	module AccPipe_8( // @[AccumulatorMem.scala:63:7] input clock, // @[AccumulatorMem.scala:63:7] input reset, // @[AccumulatorMem.scala:63:7] input [31:0] io_op1, // @[AccumulatorMem.scala:64:14] input [31:0] io_op2, // @[AccumulatorMem.scala:64:14] output [31:0] io_sum // @[AccumulatorMem.scala:64:14] ); wire [31:0] io_op1_0 = io_op1; // @[AccumulatorMem.scala:63:7] wire [31:0] io_op2_0 = io_op2; // @[AccumulatorMem.scala:63:7] wire [31:0] io_sum_0; // @[AccumulatorMem.scala:63:7] wire [32:0] _io_sum_T = {io_op1_0[31], io_op1_0} + {io_op2_0[31], io_op2_0}; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_1 = _io_sum_T[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_2 = _io_sum_T_1; // @[Arithmetic.scala:94:38] reg [31:0] io_sum_r; // @[AccumulatorMem.scala:70:26] assign io_sum_0 = io_sum_r; // @[AccumulatorMem.scala:63:7, :70:26] always @(posedge clock) // @[AccumulatorMem.scala:63:7] io_sum_r <= _io_sum_T_2; // @[Arithmetic.scala:94:38] assign io_sum = io_sum_0; // @[AccumulatorMem.scala:63:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_40 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_86 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_87 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_88 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_2 of InputUnit_86 connect input_unit_0_from_2.clock, clock connect input_unit_0_from_2.reset, reset inst input_unit_1_from_10 of InputUnit_87 connect input_unit_1_from_10.clock, clock connect input_unit_1_from_10.reset, reset inst input_unit_2_from_12 of InputUnit_88 connect input_unit_2_from_12.clock, clock connect input_unit_2_from_12.reset, reset inst output_unit_0_to_2 of OutputUnit_86 connect output_unit_0_to_2.clock, clock connect output_unit_0_to_2.reset, reset inst output_unit_1_to_10 of OutputUnit_87 connect output_unit_1_to_10.clock, clock connect output_unit_1_to_10.reset, reset inst output_unit_2_to_12 of OutputUnit_88 connect output_unit_2_to_12.clock, clock connect output_unit_2_to_12.reset, reset inst switch of Switch_40 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_40 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_40 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_40 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_6 connect input_unit_0_from_2.io.in, destNodesIn connect input_unit_1_from_10.io.in, destNodesIn_1 connect input_unit_2_from_12.io.in, destNodesIn_2 connect output_unit_0_to_2.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_2.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_2.io.out.flit connect output_unit_1_to_10.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_10.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_10.io.out.flit connect output_unit_2_to_12.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_12.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_12.io.out.flit connect route_computer.io.req.`0`, input_unit_0_from_2.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_10.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_12.io.router_req connect input_unit_0_from_2.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_10.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_12.io.router_resp, route_computer.io.resp.`2` connect vc_allocator.io.req.`0`, input_unit_0_from_2.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_10.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_12.io.vcalloc_req connect input_unit_0_from_2.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_10.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_12.io.vcalloc_resp, vc_allocator.io.resp.`2` connect output_unit_0_to_2.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_10.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_12.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_2.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_2.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_2.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_2.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_2.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_2.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_2.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_2.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_2.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_2.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_2.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_2.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_2.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_2.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_2.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_2.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_2.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_2.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_2.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_2.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_2.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_2.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_2.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_2.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_2.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_10.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_10.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_10.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_10.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_10.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_10.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_10.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_10.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_10.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_10.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_10.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_10.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_10.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_10.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_10.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_10.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_10.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_10.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_10.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_10.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_10.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_10.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_10.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_10.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_10.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_12.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_12.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_12.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_12.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_12.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_12.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_12.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_12.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_12.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_12.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_12.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_12.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_12.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_12.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_12.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_12.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_12.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_12.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_12.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_12.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_12.io.channel_status[4].occupied connect input_unit_0_from_2.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`0`[3], output_unit_0_to_2.io.credit_available[3] connect input_unit_0_from_2.io.out_credit_available.`0`[4], output_unit_0_to_2.io.credit_available[4] connect input_unit_0_from_2.io.out_credit_available.`1`[0], output_unit_1_to_10.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`1`[1], output_unit_1_to_10.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`1`[2], output_unit_1_to_10.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`1`[3], output_unit_1_to_10.io.credit_available[3] connect input_unit_0_from_2.io.out_credit_available.`1`[4], output_unit_1_to_10.io.credit_available[4] connect input_unit_0_from_2.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`2`[3], output_unit_2_to_12.io.credit_available[3] connect input_unit_0_from_2.io.out_credit_available.`2`[4], output_unit_2_to_12.io.credit_available[4] connect input_unit_1_from_10.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_1_from_10.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_1_from_10.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_1_from_10.io.out_credit_available.`0`[3], output_unit_0_to_2.io.credit_available[3] connect input_unit_1_from_10.io.out_credit_available.`0`[4], output_unit_0_to_2.io.credit_available[4] connect input_unit_1_from_10.io.out_credit_available.`1`[0], output_unit_1_to_10.io.credit_available[0] connect input_unit_1_from_10.io.out_credit_available.`1`[1], output_unit_1_to_10.io.credit_available[1] connect input_unit_1_from_10.io.out_credit_available.`1`[2], output_unit_1_to_10.io.credit_available[2] connect input_unit_1_from_10.io.out_credit_available.`1`[3], output_unit_1_to_10.io.credit_available[3] connect input_unit_1_from_10.io.out_credit_available.`1`[4], output_unit_1_to_10.io.credit_available[4] connect input_unit_1_from_10.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_1_from_10.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_1_from_10.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_1_from_10.io.out_credit_available.`2`[3], output_unit_2_to_12.io.credit_available[3] connect input_unit_1_from_10.io.out_credit_available.`2`[4], output_unit_2_to_12.io.credit_available[4] connect input_unit_2_from_12.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`0`[3], output_unit_0_to_2.io.credit_available[3] connect input_unit_2_from_12.io.out_credit_available.`0`[4], output_unit_0_to_2.io.credit_available[4] connect input_unit_2_from_12.io.out_credit_available.`1`[0], output_unit_1_to_10.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`1`[1], output_unit_1_to_10.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`1`[2], output_unit_1_to_10.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`1`[3], output_unit_1_to_10.io.credit_available[3] connect input_unit_2_from_12.io.out_credit_available.`1`[4], output_unit_1_to_10.io.credit_available[4] connect input_unit_2_from_12.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`2`[3], output_unit_2_to_12.io.credit_available[3] connect input_unit_2_from_12.io.out_credit_available.`2`[4], output_unit_2_to_12.io.credit_available[4] connect switch_allocator.io.req.`0`[0], input_unit_0_from_2.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_10.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_12.io.salloc_req[0] connect output_unit_0_to_2.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_2.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_2.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_2.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_2.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_2.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_2.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_2.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_2.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_2.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_1_to_10.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_10.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_10.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_10.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_10.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_10.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_1_to_10.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail connect output_unit_1_to_10.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc connect output_unit_1_to_10.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail connect output_unit_1_to_10.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc connect output_unit_2_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect output_unit_2_to_12.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail connect output_unit_2_to_12.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc connect output_unit_2_to_12.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail connect output_unit_2_to_12.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc connect switch.io.in.`0`[0], input_unit_0_from_2.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_10.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_12.io.out[0] connect output_unit_0_to_2.io.in, switch.io.out.`0` connect output_unit_1_to_10.io.in, switch.io.out.`1` connect output_unit_2_to_12.io.in, switch.io.out.`2` reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect input_unit_0_from_2.io.block, UInt<1>(0h0) connect input_unit_1_from_10.io.block, UInt<1>(0h0) connect input_unit_2_from_12.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_2.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_10.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_12.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_2.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_10.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_12.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_88 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 2 11 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 10 11 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 12 11 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid	module Router_40( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_12_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_12_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_channel_status_4_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_2_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_2_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_2_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_10_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_12_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_127 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_127( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_198 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_198( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_157 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_171 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_157( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_171 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_9 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_18 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_9 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h13), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h3) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h7), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h4), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h3)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_18 = eq(UInt<4>(0h8), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(UInt<4>(0h9), io.in.bits.egress_id) when _T_19 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_21 = and(route_q.io.enq.valid, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_22, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_19 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_9 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_27 = and(vcalloc_q.io.enq.valid, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_14, _out_bundle_bits_out_virt_channel_T_13) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_15 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_9( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hA; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_1, {3{_route_buffer_io_enq_bits_flow_egress_node_id_T}} \| {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, 2'h0} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0)}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h3; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h3; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_179 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_323 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_179( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_323 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_118 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_118( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_228 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_228( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_33 : output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync	module IntSyncSyncCrossingSink_n1x1_33( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN : output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} node rawA_exp = bits(io.a, 63, 52) node _rawA_isZero_T = bits(rawA_exp, 11, 9) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 11, 10) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 9, 9) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 64, 64) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 63, 52) node _rawB_isZero_T = bits(rawB_exp, 11, 9) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 11, 10) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 9, 9) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 64, 64) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0)) node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0)) node ordered = and(_ordered_T, _ordered_T_1) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) node _common_ltMags_T = lt(rawA.sExp, rawB.sExp) node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig) node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1) node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2) node _common_eqMags_T = eq(rawA.sig, rawB.sig) node common_eqMags = and(eqExps, _common_eqMags_T) node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0)) node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1) node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0)) node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0)) node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4) node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0)) node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6) node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags) node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9) node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10) node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11) node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12) node _ordered_eq_T = eq(rawA.sign, rawB.sign) node _ordered_eq_T_1 = or(bothInfs, common_eqMags) node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1) node ordered_eq = or(bothZeros, _ordered_eq_T_2) node _invalid_T = bits(rawA.sig, 51, 51) node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0)) node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1) node _invalid_T_3 = bits(rawB.sig, 51, 51) node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0)) node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4) node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5) node _invalid_T_7 = eq(ordered, UInt<1>(0h0)) node _invalid_T_8 = and(io.signaling, _invalid_T_7) node invalid = or(_invalid_T_6, _invalid_T_8) node _io_lt_T = and(ordered, ordered_lt) connect io.lt, _io_lt_T node _io_eq_T = and(ordered, ordered_eq) connect io.eq, _io_eq_T node _io_gt_T = eq(ordered_lt, UInt<1>(0h0)) node _io_gt_T_1 = and(ordered, _io_gt_T) node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0)) node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2) connect io.gt, _io_gt_T_3 node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T	module CompareRecFN( // @[CompareRecFN.scala:42:7] input [64:0] io_a, // @[CompareRecFN.scala:44:16] input [64:0] io_b, // @[CompareRecFN.scala:44:16] input io_signaling, // @[CompareRecFN.scala:44:16] output io_lt, // @[CompareRecFN.scala:44:16] output io_eq, // @[CompareRecFN.scala:44:16] output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16] ); wire rawA_isNaN = (&(io_a[63:62])) & io_a[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] wire rawB_isNaN = (&(io_b[63:62])) & io_b[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] wire ordered = ~rawA_isNaN & ~rawB_isNaN; // @[rawFloatFromRecFN.scala:56:33] wire bothInfs = (&(io_a[63:62])) & ~(io_a[61]) & (&(io_b[63:62])) & ~(io_b[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}] wire bothZeros = ~(\|(io_a[63:61])) & ~(\|(io_b[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}] wire eqExps = io_a[63:52] == io_b[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [52:0] _GEN = {\|(io_a[63:61]), io_a[51:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}] wire [52:0] _GEN_0 = {\|(io_b[63:61]), io_b[51:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}] wire common_ltMags = $signed({1'h0, io_a[63:52]}) < $signed({1'h0, io_b[63:52]}) \| eqExps & _GEN < _GEN_0; // @[rawFloatFromRecFN.scala:51:21, :60:27, :61:44] wire common_eqMags = eqExps & _GEN == _GEN_0; // @[rawFloatFromRecFN.scala:61:44] assign io_lt = ordered & ~bothZeros & (io_a[64] & ~(io_b[64]) \| ~bothInfs & (io_a[64] & ~common_ltMags & ~common_eqMags \| ~(io_b[64]) & common_ltMags)); // @[rawFloatFromRecFN.scala:57:33, :59:25] assign io_eq = ordered & (bothZeros \| io_a[64] == io_b[64] & (bothInfs \| common_eqMags)); // @[rawFloatFromRecFN.scala:57:33, :59:25] assign io_exceptionFlags = {rawA_isNaN & ~(io_a[51]) \| rawB_isNaN & ~(io_b[51]) \| io_signaling & ~ordered, 4'h0}; // @[rawFloatFromRecFN.scala:56:33] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_458 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_458( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_161 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_176 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_161( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_176 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = and(_T_11, _T_24) node _T_94 = and(_T_93, _T_37) node _T_95 = and(_T_94, _T_50) node _T_96 = and(_T_95, _T_63) node _T_97 = and(_T_96, _T_76) node _T_98 = and(_T_97, _T_84) node _T_99 = and(_T_98, _T_92) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_99, UInt<1>(0h1), "") : assert_1 node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_103 : node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_108 = shr(io.in.a.bits.source, 2) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = leq(UInt<1>(0h0), uncommonBits_5) node _T_111 = and(_T_109, _T_110) node _T_112 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_113 = and(_T_111, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_114 = shr(io.in.a.bits.source, 2) node _T_115 = eq(_T_114, UInt<1>(0h1)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_119 = and(_T_117, _T_118) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_120 = shr(io.in.a.bits.source, 2) node _T_121 = eq(_T_120, UInt<2>(0h2)) node _T_122 = leq(UInt<1>(0h0), uncommonBits_7) node _T_123 = and(_T_121, _T_122) node _T_124 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_125 = and(_T_123, _T_124) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<2>(0h3)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_8) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_132 = shr(io.in.a.bits.source, 3) node _T_133 = eq(_T_132, UInt<3>(0h4)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_9) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_140 = or(_T_107, _T_113) node _T_141 = or(_T_140, _T_119) node _T_142 = or(_T_141, _T_125) node _T_143 = or(_T_142, _T_131) node _T_144 = or(_T_143, _T_137) node _T_145 = or(_T_144, _T_138) node _T_146 = or(_T_145, _T_139) node _T_147 = and(_T_106, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_150 = or(UInt<1>(0h0), _T_149) node _T_151 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h101c0))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<29>(0h100001c0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = and(_T_150, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = and(_T_148, _T_163) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_164, UInt<1>(0h1), "") : assert_2 node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_10) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<1>(0h1)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_11) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h2)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_12) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_187 = shr(io.in.a.bits.source, 2) node _T_188 = eq(_T_187, UInt<2>(0h3)) node _T_189 = leq(UInt<1>(0h0), uncommonBits_13) node _T_190 = and(_T_188, _T_189) node _T_191 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_192 = and(_T_190, _T_191) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_193 = shr(io.in.a.bits.source, 3) node _T_194 = eq(_T_193, UInt<3>(0h4)) node _T_195 = leq(UInt<1>(0h0), uncommonBits_14) node _T_196 = and(_T_194, _T_195) node _T_197 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_168 connect _WIRE[1], _T_174 connect _WIRE[2], _T_180 connect _WIRE[3], _T_186 connect _WIRE[4], _T_192 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 node _T_201 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_202 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_204 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[6], _T_201, UInt<1>(0h0)) node _T_209 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = or(_T_202, _T_203) node _T_211 = or(_T_210, _T_204) node _T_212 = or(_T_211, _T_205) node _T_213 = or(_T_212, _T_206) node _T_214 = or(_T_213, _T_207) node _T_215 = or(_T_214, _T_208) node _T_216 = or(_T_215, _T_209) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_216 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<17>(0h101c0))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<29>(0h100001c0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = and(_T_220, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_15) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_16) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_17) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_18) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_290 = shr(io.in.a.bits.source, 3) node _T_291 = eq(_T_290, UInt<3>(0h4)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_19) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_298 = or(_T_265, _T_271) node _T_299 = or(_T_298, _T_277) node _T_300 = or(_T_299, _T_283) node _T_301 = or(_T_300, _T_289) node _T_302 = or(_T_301, _T_295) node _T_303 = or(_T_302, _T_296) node _T_304 = or(_T_303, _T_297) node _T_305 = and(_T_264, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h101c0))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<29>(0h100001c0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = and(_T_308, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = and(_T_306, _T_321) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_322, UInt<1>(0h1), "") : assert_10 node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_327 = shr(io.in.a.bits.source, 2) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_20) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_333 = shr(io.in.a.bits.source, 2) node _T_334 = eq(_T_333, UInt<1>(0h1)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_21) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_338 = and(_T_336, _T_337) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<2>(0h2)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_22) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<2>(0h3)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_23) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_351 = shr(io.in.a.bits.source, 3) node _T_352 = eq(_T_351, UInt<3>(0h4)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_24) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_326 connect _WIRE_2[1], _T_332 connect _WIRE_2[2], _T_338 connect _WIRE_2[3], _T_344 connect _WIRE_2[4], _T_350 connect _WIRE_2[5], _T_356 connect _WIRE_2[6], _T_357 connect _WIRE_2[7], _T_358 node _T_359 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_360 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = mux(_WIRE_2[6], _T_359, UInt<1>(0h0)) node _T_367 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = or(_T_360, _T_361) node _T_369 = or(_T_368, _T_362) node _T_370 = or(_T_369, _T_363) node _T_371 = or(_T_370, _T_364) node _T_372 = or(_T_371, _T_365) node _T_373 = or(_T_372, _T_366) node _T_374 = or(_T_373, _T_367) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_374 node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h101c0))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<29>(0h100001c0))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = or(_T_383, _T_388) node _T_390 = and(_T_378, _T_389) node _T_391 = or(UInt<1>(0h0), _T_390) node _T_392 = and(_WIRE_3, _T_391) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_392, UInt<1>(0h1), "") : assert_11 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(source_ok, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_399 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_399, UInt<1>(0h1), "") : assert_13 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(is_aligned, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_406 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_406, UInt<1>(0h1), "") : assert_15 node _T_410 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_410, UInt<1>(0h1), "") : assert_16 node _T_414 = not(io.in.a.bits.mask) node _T_415 = eq(_T_414, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_415, UInt<1>(0h1), "") : assert_17 node _T_419 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_419, UInt<1>(0h1), "") : assert_18 node _T_423 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_423 : node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_428 = shr(io.in.a.bits.source, 2) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_25) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_433 = and(_T_431, _T_432) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_434 = shr(io.in.a.bits.source, 2) node _T_435 = eq(_T_434, UInt<1>(0h1)) node _T_436 = leq(UInt<1>(0h0), uncommonBits_26) node _T_437 = and(_T_435, _T_436) node _T_438 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_439 = and(_T_437, _T_438) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<2>(0h2)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_27) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<2>(0h3)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_28) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_452 = shr(io.in.a.bits.source, 3) node _T_453 = eq(_T_452, UInt<3>(0h4)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_29) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_460 = or(_T_427, _T_433) node _T_461 = or(_T_460, _T_439) node _T_462 = or(_T_461, _T_445) node _T_463 = or(_T_462, _T_451) node _T_464 = or(_T_463, _T_457) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = and(_T_426, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_468, UInt<1>(0h1), "") : assert_19 node _T_472 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_473 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_474 = and(_T_472, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<17>(0h101c0))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_482 = cvt(_T_481) node _T_483 = and(_T_482, asSInt(UInt<29>(0h100001c0))) node _T_484 = asSInt(_T_483) node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0))) node _T_486 = or(_T_480, _T_485) node _T_487 = and(_T_475, _T_486) node _T_488 = or(UInt<1>(0h0), _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_488, UInt<1>(0h1), "") : assert_20 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(source_ok, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_498 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_498, UInt<1>(0h1), "") : assert_23 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_502, UInt<1>(0h1), "") : assert_24 node _T_506 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_T_506, UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_506, UInt<1>(0h1), "") : assert_25 node _T_510 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_510 : node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_512 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_30) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<1>(0h1)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_31) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h2)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_32) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_533 = shr(io.in.a.bits.source, 2) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_33) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<3>(0h4)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_34) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_547 = or(_T_514, _T_520) node _T_548 = or(_T_547, _T_526) node _T_549 = or(_T_548, _T_532) node _T_550 = or(_T_549, _T_538) node _T_551 = or(_T_550, _T_544) node _T_552 = or(_T_551, _T_545) node _T_553 = or(_T_552, _T_546) node _T_554 = and(_T_513, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_557 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_561 = cvt(_T_560) node _T_562 = and(_T_561, asSInt(UInt<17>(0h101c0))) node _T_563 = asSInt(_T_562) node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0))) node _T_565 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_566 = cvt(_T_565) node _T_567 = and(_T_566, asSInt(UInt<29>(0h100001c0))) node _T_568 = asSInt(_T_567) node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0))) node _T_570 = or(_T_564, _T_569) node _T_571 = and(_T_559, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = and(_T_555, _T_572) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_573, UInt<1>(0h1), "") : assert_26 node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(source_ok, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(is_aligned, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_583, UInt<1>(0h1), "") : assert_29 node _T_587 = eq(io.in.a.bits.mask, mask) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_587, UInt<1>(0h1), "") : assert_30 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_35) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_620 = shr(io.in.a.bits.source, 3) node _T_621 = eq(_T_620, UInt<3>(0h4)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_625 = and(_T_623, _T_624) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_625) node _T_633 = or(_T_632, _T_626) node _T_634 = or(_T_633, _T_627) node _T_635 = and(_T_594, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_639 = and(_T_637, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_642 = cvt(_T_641) node _T_643 = and(_T_642, asSInt(UInt<17>(0h101c0))) node _T_644 = asSInt(_T_643) node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0))) node _T_646 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<29>(0h100001c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = or(_T_645, _T_650) node _T_652 = and(_T_640, _T_651) node _T_653 = or(UInt<1>(0h0), _T_652) node _T_654 = and(_T_636, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_654, UInt<1>(0h1), "") : assert_31 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(source_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(is_aligned, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(_T_664, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_664, UInt<1>(0h1), "") : assert_34 node _T_668 = not(mask) node _T_669 = and(io.in.a.bits.mask, _T_668) node _T_670 = eq(_T_669, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_670, UInt<1>(0h1), "") : assert_35 node _T_674 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_674 : node _T_675 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_676 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_679 = shr(io.in.a.bits.source, 2) node _T_680 = eq(_T_679, UInt<1>(0h0)) node _T_681 = leq(UInt<1>(0h0), uncommonBits_40) node _T_682 = and(_T_680, _T_681) node _T_683 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_684 = and(_T_682, _T_683) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h1)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_41) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<2>(0h2)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_42) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h3)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_43) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_703 = shr(io.in.a.bits.source, 3) node _T_704 = eq(_T_703, UInt<3>(0h4)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_44) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_711 = or(_T_678, _T_684) node _T_712 = or(_T_711, _T_690) node _T_713 = or(_T_712, _T_696) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_708) node _T_716 = or(_T_715, _T_709) node _T_717 = or(_T_716, _T_710) node _T_718 = and(_T_677, _T_717) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_721 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_722 = and(_T_720, _T_721) node _T_723 = or(UInt<1>(0h0), _T_722) node _T_724 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_725 = cvt(_T_724) node _T_726 = and(_T_725, asSInt(UInt<17>(0h101c0))) node _T_727 = asSInt(_T_726) node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) node _T_729 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<29>(0h100001c0))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = or(_T_728, _T_733) node _T_735 = and(_T_723, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = and(_T_719, _T_736) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_737, UInt<1>(0h1), "") : assert_36 node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(source_ok, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(is_aligned, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_747 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_747, UInt<1>(0h1), "") : assert_39 node _T_751 = eq(io.in.a.bits.mask, mask) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_751, UInt<1>(0h1), "") : assert_40 node _T_755 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_755 : node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_45) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<1>(0h1)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_46) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<2>(0h2)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_47) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<2>(0h3)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_48) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_784 = shr(io.in.a.bits.source, 3) node _T_785 = eq(_T_784, UInt<3>(0h4)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_49) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_792 = or(_T_759, _T_765) node _T_793 = or(_T_792, _T_771) node _T_794 = or(_T_793, _T_777) node _T_795 = or(_T_794, _T_783) node _T_796 = or(_T_795, _T_789) node _T_797 = or(_T_796, _T_790) node _T_798 = or(_T_797, _T_791) node _T_799 = and(_T_758, _T_798) node _T_800 = or(UInt<1>(0h0), _T_799) node _T_801 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_802 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_803 = and(_T_801, _T_802) node _T_804 = or(UInt<1>(0h0), _T_803) node _T_805 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h101c0))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<29>(0h100001c0))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = or(_T_809, _T_814) node _T_816 = and(_T_804, _T_815) node _T_817 = or(UInt<1>(0h0), _T_816) node _T_818 = and(_T_800, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(source_ok, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_841 = shr(io.in.a.bits.source, 2) node _T_842 = eq(_T_841, UInt<1>(0h0)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_50) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_846 = and(_T_844, _T_845) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h1)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_51) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<2>(0h2)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_52) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h3)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_53) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_865 = shr(io.in.a.bits.source, 3) node _T_866 = eq(_T_865, UInt<3>(0h4)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_54) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_873 = or(_T_840, _T_846) node _T_874 = or(_T_873, _T_852) node _T_875 = or(_T_874, _T_858) node _T_876 = or(_T_875, _T_864) node _T_877 = or(_T_876, _T_870) node _T_878 = or(_T_877, _T_871) node _T_879 = or(_T_878, _T_872) node _T_880 = and(_T_839, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_883 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_884 = and(_T_882, _T_883) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<17>(0h101c0))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<29>(0h100001c0))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = or(_T_890, _T_895) node _T_897 = and(_T_885, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_881, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_40 = shr(io.in.d.bits.source, 2) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_46 = shr(io.in.d.bits.source, 2) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 3) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_39 connect _source_ok_WIRE_1[1], _source_ok_T_45 connect _source_ok_WIRE_1[2], _source_ok_T_51 connect _source_ok_WIRE_1[3], _source_ok_T_57 connect _source_ok_WIRE_1[4], _source_ok_T_63 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h1), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h1), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h1), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h1), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h1), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1054 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 node _T_1058 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) node _T_1060 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1061 = cvt(_T_1060) node _T_1062 = and(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = asSInt(_T_1062) node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0))) node _T_1065 = or(_T_1059, _T_1064) node _uncommonBits_T_55 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1066 = shr(io.in.b.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = or(_T_1072, _T_1077) node _uncommonBits_T_56 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1079 = shr(io.in.b.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h1)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<1>(0h0))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1085, _T_1090) node _uncommonBits_T_57 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1092 = shr(io.in.b.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) node _T_1099 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1100 = cvt(_T_1099) node _T_1101 = and(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = asSInt(_T_1101) node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0))) node _T_1104 = or(_T_1098, _T_1103) node _uncommonBits_T_58 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1105 = shr(io.in.b.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = or(_T_1111, _T_1116) node _uncommonBits_T_59 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1118 = shr(io.in.b.bits.source, 3) node _T_1119 = eq(_T_1118, UInt<3>(0h4)) node _T_1120 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = leq(uncommonBits_59, UInt<3>(0h7)) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) node _T_1125 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<1>(0h0))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1124, _T_1129) node _T_1131 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) node _T_1133 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1134 = cvt(_T_1133) node _T_1135 = and(_T_1134, asSInt(UInt<1>(0h0))) node _T_1136 = asSInt(_T_1135) node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0))) node _T_1138 = or(_T_1132, _T_1137) node _T_1139 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) node _T_1141 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = or(_T_1140, _T_1145) node _T_1147 = and(_T_1065, _T_1078) node _T_1148 = and(_T_1147, _T_1091) node _T_1149 = and(_T_1148, _T_1104) node _T_1150 = and(_T_1149, _T_1117) node _T_1151 = and(_T_1150, _T_1130) node _T_1152 = and(_T_1151, _T_1138) node _T_1153 = and(_T_1152, _T_1146) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0) node _legal_source_T_25 = shr(io.in.b.bits.source, 3) node _legal_source_T_26 = eq(_legal_source_T_25, UInt<3>(0h4)) node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4) node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27) node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7)) node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _legal_source_WIRE : UInt<1>[8] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_30 connect _legal_source_WIRE[6], _legal_source_T_31 connect _legal_source_WIRE[7], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_41 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_35) node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_36) node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_37) node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_38) node _legal_source_T_46 = or(_legal_source_T_45, _legal_source_T_39) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_40) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_47 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1157 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1157 : node _T_1158 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1159 = shr(io.in.b.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_61 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1165 = shr(io.in.b.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_62 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1171 = shr(io.in.b.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_63 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1177 = shr(io.in.b.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _uncommonBits_T_64 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1183 = shr(io.in.b.bits.source, 3) node _T_1184 = eq(_T_1183, UInt<3>(0h4)) node _T_1185 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = leq(uncommonBits_64, UInt<3>(0h7)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1190 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _WIRE_4 : UInt<1>[8] connect _WIRE_4[0], _T_1158 connect _WIRE_4[1], _T_1164 connect _WIRE_4[2], _T_1170 connect _WIRE_4[3], _T_1176 connect _WIRE_4[4], _T_1182 connect _WIRE_4[5], _T_1188 connect _WIRE_4[6], _T_1189 connect _WIRE_4[7], _T_1190 node _T_1191 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1192 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1194 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1195 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1196 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1197 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1198 = mux(_WIRE_4[6], _T_1191, UInt<1>(0h0)) node _T_1199 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1200 = or(_T_1192, _T_1193) node _T_1201 = or(_T_1200, _T_1194) node _T_1202 = or(_T_1201, _T_1195) node _T_1203 = or(_T_1202, _T_1196) node _T_1204 = or(_T_1203, _T_1197) node _T_1205 = or(_T_1204, _T_1198) node _T_1206 = or(_T_1205, _T_1199) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1206 node _T_1207 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1208 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = or(UInt<1>(0h0), _T_1209) node _T_1211 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1212 = cvt(_T_1211) node _T_1213 = and(_T_1212, asSInt(UInt<17>(0h101c0))) node _T_1214 = asSInt(_T_1213) node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0))) node _T_1216 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1217 = cvt(_T_1216) node _T_1218 = and(_T_1217, asSInt(UInt<29>(0h100001c0))) node _T_1219 = asSInt(_T_1218) node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = or(_T_1215, _T_1220) node _T_1222 = and(_T_1210, _T_1221) node _T_1223 = or(UInt<1>(0h0), _T_1222) node _T_1224 = and(_WIRE_5, _T_1223) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_86 node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(address_ok, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(legal_source, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1237 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_90 node _T_1241 = eq(io.in.b.bits.mask, mask_1) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_91 node _T_1245 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_92 node _T_1249 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1249 : node _T_1250 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1251 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1252 = and(_T_1250, _T_1251) node _T_1253 = or(UInt<1>(0h0), _T_1252) node _T_1254 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<17>(0h101c0))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1260 = cvt(_T_1259) node _T_1261 = and(_T_1260, asSInt(UInt<29>(0h100001c0))) node _T_1262 = asSInt(_T_1261) node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0))) node _T_1264 = or(_T_1258, _T_1263) node _T_1265 = and(_T_1253, _T_1264) node _T_1266 = or(UInt<1>(0h0), _T_1265) node _T_1267 = and(UInt<1>(0h0), _T_1266) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_93 node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(address_ok, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(legal_source, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1280 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_97 node _T_1284 = eq(io.in.b.bits.mask, mask_1) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_98 node _T_1288 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_99 node _T_1292 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1292 : node _T_1293 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1294 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<17>(0h101c0))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<29>(0h100001c0))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = or(_T_1301, _T_1306) node _T_1308 = and(_T_1296, _T_1307) node _T_1309 = or(UInt<1>(0h0), _T_1308) node _T_1310 = and(UInt<1>(0h0), _T_1309) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_100 node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(address_ok, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(legal_source, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1323 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_104 node _T_1327 = eq(io.in.b.bits.mask, mask_1) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_105 node _T_1331 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1331 : node _T_1332 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1333 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = or(UInt<1>(0h0), _T_1334) node _T_1336 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1337 = cvt(_T_1336) node _T_1338 = and(_T_1337, asSInt(UInt<17>(0h101c0))) node _T_1339 = asSInt(_T_1338) node _T_1340 = eq(_T_1339, asSInt(UInt<1>(0h0))) node _T_1341 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<29>(0h100001c0))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = or(_T_1340, _T_1345) node _T_1347 = and(_T_1335, _T_1346) node _T_1348 = or(UInt<1>(0h0), _T_1347) node _T_1349 = and(UInt<1>(0h0), _T_1348) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_106 node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(address_ok, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(legal_source, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1362 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_110 node _T_1366 = not(mask_1) node _T_1367 = and(io.in.b.bits.mask, _T_1366) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_111 node _T_1372 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1372 : node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1375 = and(_T_1373, _T_1374) node _T_1376 = or(UInt<1>(0h0), _T_1375) node _T_1377 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h101c0))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<29>(0h100001c0))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = or(_T_1381, _T_1386) node _T_1388 = and(_T_1376, _T_1387) node _T_1389 = or(UInt<1>(0h0), _T_1388) node _T_1390 = and(UInt<1>(0h0), _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112 node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(address_ok, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(legal_source, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1403 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_116 node _T_1407 = eq(io.in.b.bits.mask, mask_1) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_117 node _T_1411 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1411 : node _T_1412 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1413 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = or(UInt<1>(0h0), _T_1414) node _T_1416 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<17>(0h101c0))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<29>(0h100001c0))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = or(_T_1420, _T_1425) node _T_1427 = and(_T_1415, _T_1426) node _T_1428 = or(UInt<1>(0h0), _T_1427) node _T_1429 = and(UInt<1>(0h0), _T_1428) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_118 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(address_ok, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(legal_source, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1442 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_122 node _T_1446 = eq(io.in.b.bits.mask, mask_1) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_123 node _T_1450 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1450 : node _T_1451 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1452 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1453 = and(_T_1451, _T_1452) node _T_1454 = or(UInt<1>(0h0), _T_1453) node _T_1455 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1456 = cvt(_T_1455) node _T_1457 = and(_T_1456, asSInt(UInt<17>(0h101c0))) node _T_1458 = asSInt(_T_1457) node _T_1459 = eq(_T_1458, asSInt(UInt<1>(0h0))) node _T_1460 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1461 = cvt(_T_1460) node _T_1462 = and(_T_1461, asSInt(UInt<29>(0h100001c0))) node _T_1463 = asSInt(_T_1462) node _T_1464 = eq(_T_1463, asSInt(UInt<1>(0h0))) node _T_1465 = or(_T_1459, _T_1464) node _T_1466 = and(_T_1454, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1466) node _T_1468 = and(UInt<1>(0h0), _T_1467) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_124 node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(address_ok, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(legal_source, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1481 = eq(io.in.b.bits.mask, mask_1) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_128 node _T_1485 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1489 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_130 node _source_ok_T_78 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_79 = shr(io.in.c.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_85 = shr(io.in.c.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_91 = shr(io.in.c.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_97 = shr(io.in.c.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 2, 0) node _source_ok_T_103 = shr(io.in.c.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<3>(0h7)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_110 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_2 : UInt<1>[8] connect _source_ok_WIRE_2[0], _source_ok_T_78 connect _source_ok_WIRE_2[1], _source_ok_T_84 connect _source_ok_WIRE_2[2], _source_ok_T_90 connect _source_ok_WIRE_2[3], _source_ok_T_96 connect _source_ok_WIRE_2[4], _source_ok_T_102 connect _source_ok_WIRE_2[5], _source_ok_T_108 connect _source_ok_WIRE_2[6], _source_ok_T_109 connect _source_ok_WIRE_2[7], _source_ok_T_110 node _source_ok_T_111 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_2[2]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_2[3]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_2[4]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_2[5]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_2[6]) node source_ok_2 = or(_source_ok_T_116, _source_ok_WIRE_2[7]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1493 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = or(_T_1494, _T_1499) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1501 = shr(io.in.c.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) node _T_1508 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = or(_T_1507, _T_1512) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1514 = shr(io.in.c.bits.source, 2) node _T_1515 = eq(_T_1514, UInt<1>(0h1)) node _T_1516 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1519 = and(_T_1517, _T_1518) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) node _T_1521 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1520, _T_1525) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_1527 = shr(io.in.c.bits.source, 2) node _T_1528 = eq(_T_1527, UInt<2>(0h2)) node _T_1529 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_1532 = and(_T_1530, _T_1531) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<1>(0h0))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = or(_T_1533, _T_1538) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_1540 = shr(io.in.c.bits.source, 2) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_1545 = and(_T_1543, _T_1544) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) node _T_1547 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1546, _T_1551) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1553 = shr(io.in.c.bits.source, 3) node _T_1554 = eq(_T_1553, UInt<3>(0h4)) node _T_1555 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1556 = and(_T_1554, _T_1555) node _T_1557 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = or(_T_1559, _T_1564) node _T_1566 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) node _T_1568 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<1>(0h0))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = or(_T_1567, _T_1572) node _T_1574 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) node _T_1576 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1577 = cvt(_T_1576) node _T_1578 = and(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = asSInt(_T_1578) node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = or(_T_1575, _T_1580) node _T_1582 = and(_T_1500, _T_1513) node _T_1583 = and(_T_1582, _T_1526) node _T_1584 = and(_T_1583, _T_1539) node _T_1585 = and(_T_1584, _T_1552) node _T_1586 = and(_T_1585, _T_1565) node _T_1587 = and(_T_1586, _T_1573) node _T_1588 = and(_T_1587, _T_1581) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_131 node _T_1592 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1592 : node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(address_ok_1, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(source_ok_2, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1599 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_134 node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1606 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_136 node _T_1610 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(_T_1610, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1610, UInt<1>(0h1), "") : assert_137 node _T_1614 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1614 : node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(address_ok_1, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(source_ok_2, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1621 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_140 node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1628 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1629 = asUInt(reset) node _T_1630 = eq(_T_1629, UInt<1>(0h0)) when _T_1630 : node _T_1631 = eq(_T_1628, UInt<1>(0h0)) when _T_1631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1628, UInt<1>(0h1), "") : assert_142 node _T_1632 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1632 : node _T_1633 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1634 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1637 = shr(io.in.c.bits.source, 2) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) node _T_1639 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1640 = and(_T_1638, _T_1639) node _T_1641 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1642 = and(_T_1640, _T_1641) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1643 = shr(io.in.c.bits.source, 2) node _T_1644 = eq(_T_1643, UInt<1>(0h1)) node _T_1645 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1646 = and(_T_1644, _T_1645) node _T_1647 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1648 = and(_T_1646, _T_1647) node _uncommonBits_T_72 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1649 = shr(io.in.c.bits.source, 2) node _T_1650 = eq(_T_1649, UInt<2>(0h2)) node _T_1651 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1652 = and(_T_1650, _T_1651) node _T_1653 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1654 = and(_T_1652, _T_1653) node _uncommonBits_T_73 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1655 = shr(io.in.c.bits.source, 2) node _T_1656 = eq(_T_1655, UInt<2>(0h3)) node _T_1657 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1658 = and(_T_1656, _T_1657) node _T_1659 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1660 = and(_T_1658, _T_1659) node _uncommonBits_T_74 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1661 = shr(io.in.c.bits.source, 3) node _T_1662 = eq(_T_1661, UInt<3>(0h4)) node _T_1663 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1664 = and(_T_1662, _T_1663) node _T_1665 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1666 = and(_T_1664, _T_1665) node _T_1667 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1669 = or(_T_1636, _T_1642) node _T_1670 = or(_T_1669, _T_1648) node _T_1671 = or(_T_1670, _T_1654) node _T_1672 = or(_T_1671, _T_1660) node _T_1673 = or(_T_1672, _T_1666) node _T_1674 = or(_T_1673, _T_1667) node _T_1675 = or(_T_1674, _T_1668) node _T_1676 = and(_T_1635, _T_1675) node _T_1677 = or(UInt<1>(0h0), _T_1676) node _T_1678 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1679 = or(UInt<1>(0h0), _T_1678) node _T_1680 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<17>(0h101c0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1686 = cvt(_T_1685) node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h100001c0))) node _T_1688 = asSInt(_T_1687) node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0))) node _T_1690 = or(_T_1684, _T_1689) node _T_1691 = and(_T_1679, _T_1690) node _T_1692 = or(UInt<1>(0h0), _T_1691) node _T_1693 = and(_T_1677, _T_1692) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_143 node _T_1697 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_75 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1698 = shr(io.in.c.bits.source, 2) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1703 = and(_T_1701, _T_1702) node _uncommonBits_T_76 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 1, 0) node _T_1704 = shr(io.in.c.bits.source, 2) node _T_1705 = eq(_T_1704, UInt<1>(0h1)) node _T_1706 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = leq(uncommonBits_76, UInt<2>(0h3)) node _T_1709 = and(_T_1707, _T_1708) node _uncommonBits_T_77 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0) node _T_1710 = shr(io.in.c.bits.source, 2) node _T_1711 = eq(_T_1710, UInt<2>(0h2)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_77, UInt<2>(0h3)) node _T_1715 = and(_T_1713, _T_1714) node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_1716 = shr(io.in.c.bits.source, 2) node _T_1717 = eq(_T_1716, UInt<2>(0h3)) node _T_1718 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1719 = and(_T_1717, _T_1718) node _T_1720 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_1721 = and(_T_1719, _T_1720) node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 2, 0) node _T_1722 = shr(io.in.c.bits.source, 3) node _T_1723 = eq(_T_1722, UInt<3>(0h4)) node _T_1724 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1725 = and(_T_1723, _T_1724) node _T_1726 = leq(uncommonBits_79, UInt<3>(0h7)) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_6 : UInt<1>[8] connect _WIRE_6[0], _T_1697 connect _WIRE_6[1], _T_1703 connect _WIRE_6[2], _T_1709 connect _WIRE_6[3], _T_1715 connect _WIRE_6[4], _T_1721 connect _WIRE_6[5], _T_1727 connect _WIRE_6[6], _T_1728 connect _WIRE_6[7], _T_1729 node _T_1730 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1731 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1732 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1733 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1734 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1735 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1736 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1737 = mux(_WIRE_6[6], _T_1730, UInt<1>(0h0)) node _T_1738 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1739 = or(_T_1731, _T_1732) node _T_1740 = or(_T_1739, _T_1733) node _T_1741 = or(_T_1740, _T_1734) node _T_1742 = or(_T_1741, _T_1735) node _T_1743 = or(_T_1742, _T_1736) node _T_1744 = or(_T_1743, _T_1737) node _T_1745 = or(_T_1744, _T_1738) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1745 node _T_1746 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1747 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1748 = and(_T_1746, _T_1747) node _T_1749 = or(UInt<1>(0h0), _T_1748) node _T_1750 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<17>(0h101c0))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1756 = cvt(_T_1755) node _T_1757 = and(_T_1756, asSInt(UInt<29>(0h100001c0))) node _T_1758 = asSInt(_T_1757) node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0))) node _T_1760 = or(_T_1754, _T_1759) node _T_1761 = and(_T_1749, _T_1760) node _T_1762 = or(UInt<1>(0h0), _T_1761) node _T_1763 = and(_WIRE_7, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_144 node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(source_ok_2, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1770 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1771 = asUInt(reset) node _T_1772 = eq(_T_1771, UInt<1>(0h0)) when _T_1772 : node _T_1773 = eq(_T_1770, UInt<1>(0h0)) when _T_1773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1770, UInt<1>(0h1), "") : assert_146 node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1777 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1778 = asUInt(reset) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) when _T_1779 : node _T_1780 = eq(_T_1777, UInt<1>(0h0)) when _T_1780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1777, UInt<1>(0h1), "") : assert_148 node _T_1781 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_149 node _T_1785 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1785 : node _T_1786 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1787 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1788 = and(_T_1786, _T_1787) node _T_1789 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0) node _T_1790 = shr(io.in.c.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_80, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0) node _T_1796 = shr(io.in.c.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<1>(0h1)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_81, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 1, 0) node _T_1802 = shr(io.in.c.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<2>(0h2)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_82, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 1, 0) node _T_1808 = shr(io.in.c.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<2>(0h3)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_83, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 2, 0) node _T_1814 = shr(io.in.c.bits.source, 3) node _T_1815 = eq(_T_1814, UInt<3>(0h4)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_84, UInt<3>(0h7)) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1821 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1822 = or(_T_1789, _T_1795) node _T_1823 = or(_T_1822, _T_1801) node _T_1824 = or(_T_1823, _T_1807) node _T_1825 = or(_T_1824, _T_1813) node _T_1826 = or(_T_1825, _T_1819) node _T_1827 = or(_T_1826, _T_1820) node _T_1828 = or(_T_1827, _T_1821) node _T_1829 = and(_T_1788, _T_1828) node _T_1830 = or(UInt<1>(0h0), _T_1829) node _T_1831 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1832 = or(UInt<1>(0h0), _T_1831) node _T_1833 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1834 = cvt(_T_1833) node _T_1835 = and(_T_1834, asSInt(UInt<17>(0h101c0))) node _T_1836 = asSInt(_T_1835) node _T_1837 = eq(_T_1836, asSInt(UInt<1>(0h0))) node _T_1838 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1839 = cvt(_T_1838) node _T_1840 = and(_T_1839, asSInt(UInt<29>(0h100001c0))) node _T_1841 = asSInt(_T_1840) node _T_1842 = eq(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = or(_T_1837, _T_1842) node _T_1844 = and(_T_1832, _T_1843) node _T_1845 = or(UInt<1>(0h0), _T_1844) node _T_1846 = and(_T_1830, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_150 node _T_1850 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1851 = shr(io.in.c.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1857 = shr(io.in.c.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<1>(0h1)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1863 = shr(io.in.c.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<2>(0h2)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_1869 = shr(io.in.c.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<2>(0h3)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0) node _T_1875 = shr(io.in.c.bits.source, 3) node _T_1876 = eq(_T_1875, UInt<3>(0h4)) node _T_1877 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1878 = and(_T_1876, _T_1877) node _T_1879 = leq(uncommonBits_89, UInt<3>(0h7)) node _T_1880 = and(_T_1878, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1882 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_8 : UInt<1>[8] connect _WIRE_8[0], _T_1850 connect _WIRE_8[1], _T_1856 connect _WIRE_8[2], _T_1862 connect _WIRE_8[3], _T_1868 connect _WIRE_8[4], _T_1874 connect _WIRE_8[5], _T_1880 connect _WIRE_8[6], _T_1881 connect _WIRE_8[7], _T_1882 node _T_1883 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1884 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1885 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1886 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1887 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1888 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1889 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1890 = mux(_WIRE_8[6], _T_1883, UInt<1>(0h0)) node _T_1891 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1892 = or(_T_1884, _T_1885) node _T_1893 = or(_T_1892, _T_1886) node _T_1894 = or(_T_1893, _T_1887) node _T_1895 = or(_T_1894, _T_1888) node _T_1896 = or(_T_1895, _T_1889) node _T_1897 = or(_T_1896, _T_1890) node _T_1898 = or(_T_1897, _T_1891) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1898 node _T_1899 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1900 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = or(UInt<1>(0h0), _T_1901) node _T_1903 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h101c0))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<29>(0h100001c0))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = or(_T_1907, _T_1912) node _T_1914 = and(_T_1902, _T_1913) node _T_1915 = or(UInt<1>(0h0), _T_1914) node _T_1916 = and(_WIRE_9, _T_1915) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_151 node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(source_ok_2, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1923 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_153 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1930 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_155 node _T_1934 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1941 = asUInt(reset) node _T_1942 = eq(_T_1941, UInt<1>(0h0)) when _T_1942 : node _T_1943 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1944 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_159 node _T_1948 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_160 node _T_1952 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(address_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(source_ok_2, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1962 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_164 node _T_1966 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1966 : node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(address_ok_1, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_2, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1976 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_168 node _T_1980 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1987 = eq(a_first, UInt<1>(0h0)) node _T_1988 = and(io.in.a.valid, _T_1987) when _T_1988 : node _T_1989 = eq(io.in.a.bits.opcode, opcode) node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(_T_1989, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1989, UInt<1>(0h1), "") : assert_171 node _T_1993 = eq(io.in.a.bits.param, param) node _T_1994 = asUInt(reset) node _T_1995 = eq(_T_1994, UInt<1>(0h0)) when _T_1995 : node _T_1996 = eq(_T_1993, UInt<1>(0h0)) when _T_1996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1993, UInt<1>(0h1), "") : assert_172 node _T_1997 = eq(io.in.a.bits.size, size) node _T_1998 = asUInt(reset) node _T_1999 = eq(_T_1998, UInt<1>(0h0)) when _T_1999 : node _T_2000 = eq(_T_1997, UInt<1>(0h0)) when _T_2000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1997, UInt<1>(0h1), "") : assert_173 node _T_2001 = eq(io.in.a.bits.source, source) node _T_2002 = asUInt(reset) node _T_2003 = eq(_T_2002, UInt<1>(0h0)) when _T_2003 : node _T_2004 = eq(_T_2001, UInt<1>(0h0)) when _T_2004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2001, UInt<1>(0h1), "") : assert_174 node _T_2005 = eq(io.in.a.bits.address, address) node _T_2006 = asUInt(reset) node _T_2007 = eq(_T_2006, UInt<1>(0h0)) when _T_2007 : node _T_2008 = eq(_T_2005, UInt<1>(0h0)) when _T_2008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2005, UInt<1>(0h1), "") : assert_175 node _T_2009 = and(io.in.a.ready, io.in.a.valid) node _T_2010 = and(_T_2009, a_first) when _T_2010 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2011 = eq(d_first, UInt<1>(0h0)) node _T_2012 = and(io.in.d.valid, _T_2011) when _T_2012 : node _T_2013 = eq(io.in.d.bits.opcode, opcode_1) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_176 node _T_2017 = eq(io.in.d.bits.param, param_1) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_177 node _T_2021 = eq(io.in.d.bits.size, size_1) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_178 node _T_2025 = eq(io.in.d.bits.source, source_1) node _T_2026 = asUInt(reset) node _T_2027 = eq(_T_2026, UInt<1>(0h0)) when _T_2027 : node _T_2028 = eq(_T_2025, UInt<1>(0h0)) when _T_2028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2025, UInt<1>(0h1), "") : assert_179 node _T_2029 = eq(io.in.d.bits.sink, sink) node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(_T_2029, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2029, UInt<1>(0h1), "") : assert_180 node _T_2033 = eq(io.in.d.bits.denied, denied) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_181 node _T_2037 = and(io.in.d.ready, io.in.d.valid) node _T_2038 = and(_T_2037, d_first) when _T_2038 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2039 = eq(b_first, UInt<1>(0h0)) node _T_2040 = and(io.in.b.valid, _T_2039) when _T_2040 : node _T_2041 = eq(io.in.b.bits.opcode, opcode_2) node _T_2042 = asUInt(reset) node _T_2043 = eq(_T_2042, UInt<1>(0h0)) when _T_2043 : node _T_2044 = eq(_T_2041, UInt<1>(0h0)) when _T_2044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2041, UInt<1>(0h1), "") : assert_182 node _T_2045 = eq(io.in.b.bits.param, param_2) node _T_2046 = asUInt(reset) node _T_2047 = eq(_T_2046, UInt<1>(0h0)) when _T_2047 : node _T_2048 = eq(_T_2045, UInt<1>(0h0)) when _T_2048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2045, UInt<1>(0h1), "") : assert_183 node _T_2049 = eq(io.in.b.bits.size, size_2) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_184 node _T_2053 = eq(io.in.b.bits.source, source_2) node _T_2054 = asUInt(reset) node _T_2055 = eq(_T_2054, UInt<1>(0h0)) when _T_2055 : node _T_2056 = eq(_T_2053, UInt<1>(0h0)) when _T_2056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2053, UInt<1>(0h1), "") : assert_185 node _T_2057 = eq(io.in.b.bits.address, address_1) node _T_2058 = asUInt(reset) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) when _T_2059 : node _T_2060 = eq(_T_2057, UInt<1>(0h0)) when _T_2060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2057, UInt<1>(0h1), "") : assert_186 node _T_2061 = and(io.in.b.ready, io.in.b.valid) node _T_2062 = and(_T_2061, b_first) when _T_2062 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2063 = eq(c_first, UInt<1>(0h0)) node _T_2064 = and(io.in.c.valid, _T_2063) when _T_2064 : node _T_2065 = eq(io.in.c.bits.opcode, opcode_3) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_187 node _T_2069 = eq(io.in.c.bits.param, param_3) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_188 node _T_2073 = eq(io.in.c.bits.size, size_3) node _T_2074 = asUInt(reset) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) when _T_2075 : node _T_2076 = eq(_T_2073, UInt<1>(0h0)) when _T_2076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2073, UInt<1>(0h1), "") : assert_189 node _T_2077 = eq(io.in.c.bits.source, source_3) node _T_2078 = asUInt(reset) node _T_2079 = eq(_T_2078, UInt<1>(0h0)) when _T_2079 : node _T_2080 = eq(_T_2077, UInt<1>(0h0)) when _T_2080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2077, UInt<1>(0h1), "") : assert_190 node _T_2081 = eq(io.in.c.bits.address, address_2) node _T_2082 = asUInt(reset) node _T_2083 = eq(_T_2082, UInt<1>(0h0)) when _T_2083 : node _T_2084 = eq(_T_2081, UInt<1>(0h0)) when _T_2084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2081, UInt<1>(0h1), "") : assert_191 node _T_2085 = and(io.in.c.ready, io.in.c.valid) node _T_2086 = and(_T_2085, c_first) when _T_2086 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes : UInt<172>, clock, reset, UInt<172>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<43> connect a_set, UInt<43>(0h0) wire a_set_wo_ready : UInt<43> connect a_set_wo_ready, UInt<43>(0h0) wire a_opcodes_set : UInt<172> connect a_opcodes_set, UInt<172>(0h0) wire a_sizes_set : UInt<172> connect a_sizes_set, UInt<172>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2087 = and(io.in.a.valid, a_first_1) node _T_2088 = and(_T_2087, UInt<1>(0h1)) when _T_2088 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2089 = and(io.in.a.ready, io.in.a.valid) node _T_2090 = and(_T_2089, a_first_1) node _T_2091 = and(_T_2090, UInt<1>(0h1)) when _T_2091 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2092 = dshr(inflight, io.in.a.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<43> connect d_clr, UInt<43>(0h0) wire d_clr_wo_ready : UInt<43> connect d_clr_wo_ready, UInt<43>(0h0) wire d_opcodes_clr : UInt<172> connect d_opcodes_clr, UInt<172>(0h0) wire d_sizes_clr : UInt<172> connect d_sizes_clr, UInt<172>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2098 = and(io.in.d.valid, d_first_1) node _T_2099 = and(_T_2098, UInt<1>(0h1)) node _T_2100 = eq(d_release_ack, UInt<1>(0h0)) node _T_2101 = and(_T_2099, _T_2100) when _T_2101 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2102 = and(io.in.d.ready, io.in.d.valid) node _T_2103 = and(_T_2102, d_first_1) node _T_2104 = and(_T_2103, UInt<1>(0h1)) node _T_2105 = eq(d_release_ack, UInt<1>(0h0)) node _T_2106 = and(_T_2104, _T_2105) when _T_2106 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2107 = and(io.in.d.valid, d_first_1) node _T_2108 = and(_T_2107, UInt<1>(0h1)) node _T_2109 = eq(d_release_ack, UInt<1>(0h0)) node _T_2110 = and(_T_2108, _T_2109) when _T_2110 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2111 = dshr(inflight, io.in.d.bits.source) node _T_2112 = bits(_T_2111, 0, 0) node _T_2113 = or(_T_2112, same_cycle_resp) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2119 = or(_T_2117, _T_2118) node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(_T_2119, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2119, UInt<1>(0h1), "") : assert_194 node _T_2123 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_195 else : node _T_2127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2129 = or(_T_2127, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_196 node _T_2133 = eq(io.in.d.bits.size, a_size_lookup) node _T_2134 = asUInt(reset) node _T_2135 = eq(_T_2134, UInt<1>(0h0)) when _T_2135 : node _T_2136 = eq(_T_2133, UInt<1>(0h0)) when _T_2136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2133, UInt<1>(0h1), "") : assert_197 node _T_2137 = and(io.in.d.valid, d_first_1) node _T_2138 = and(_T_2137, a_first_1) node _T_2139 = and(_T_2138, io.in.a.valid) node _T_2140 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2141 = and(_T_2139, _T_2140) node _T_2142 = eq(d_release_ack, UInt<1>(0h0)) node _T_2143 = and(_T_2141, _T_2142) when _T_2143 : node _T_2144 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2145 = or(_T_2144, io.in.a.ready) node _T_2146 = asUInt(reset) node _T_2147 = eq(_T_2146, UInt<1>(0h0)) when _T_2147 : node _T_2148 = eq(_T_2145, UInt<1>(0h0)) when _T_2148 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2145, UInt<1>(0h1), "") : assert_198 node _T_2149 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2150 = orr(a_set_wo_ready) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) node _T_2152 = or(_T_2149, _T_2151) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_112 node _T_2156 = orr(inflight) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2159 = or(_T_2157, _T_2158) node _T_2160 = lt(watchdog, plusarg_reader.out) node _T_2161 = or(_T_2159, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2165 = and(io.in.a.ready, io.in.a.valid) node _T_2166 = and(io.in.d.ready, io.in.d.valid) node _T_2167 = or(_T_2165, _T_2166) when _T_2167 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes_1 : UInt<172>, clock, reset, UInt<172>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<43> connect c_set, UInt<43>(0h0) wire c_set_wo_ready : UInt<43> connect c_set_wo_ready, UInt<43>(0h0) wire c_opcodes_set : UInt<172> connect c_opcodes_set, UInt<172>(0h0) wire c_sizes_set : UInt<172> connect c_sizes_set, UInt<172>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2168 = and(io.in.c.valid, c_first_1) node _T_2169 = bits(io.in.c.bits.opcode, 2, 2) node _T_2170 = bits(io.in.c.bits.opcode, 1, 1) node _T_2171 = and(_T_2169, _T_2170) node _T_2172 = and(_T_2168, _T_2171) when _T_2172 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2173 = and(io.in.c.ready, io.in.c.valid) node _T_2174 = and(_T_2173, c_first_1) node _T_2175 = bits(io.in.c.bits.opcode, 2, 2) node _T_2176 = bits(io.in.c.bits.opcode, 1, 1) node _T_2177 = and(_T_2175, _T_2176) node _T_2178 = and(_T_2174, _T_2177) when _T_2178 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2179 = dshr(inflight_1, io.in.c.bits.source) node _T_2180 = bits(_T_2179, 0, 0) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = asUInt(reset) node _T_2183 = eq(_T_2182, UInt<1>(0h0)) when _T_2183 : node _T_2184 = eq(_T_2181, UInt<1>(0h0)) when _T_2184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2181, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<43> connect d_clr_1, UInt<43>(0h0) wire d_clr_wo_ready_1 : UInt<43> connect d_clr_wo_ready_1, UInt<43>(0h0) wire d_opcodes_clr_1 : UInt<172> connect d_opcodes_clr_1, UInt<172>(0h0) wire d_sizes_clr_1 : UInt<172> connect d_sizes_clr_1, UInt<172>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2185 = and(io.in.d.valid, d_first_2) node _T_2186 = and(_T_2185, UInt<1>(0h1)) node _T_2187 = and(_T_2186, d_release_ack_1) when _T_2187 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2188 = and(io.in.d.ready, io.in.d.valid) node _T_2189 = and(_T_2188, d_first_2) node _T_2190 = and(_T_2189, UInt<1>(0h1)) node _T_2191 = and(_T_2190, d_release_ack_1) when _T_2191 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2192 = and(io.in.d.valid, d_first_2) node _T_2193 = and(_T_2192, UInt<1>(0h1)) node _T_2194 = and(_T_2193, d_release_ack_1) when _T_2194 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2195 = dshr(inflight_1, io.in.d.bits.source) node _T_2196 = bits(_T_2195, 0, 0) node _T_2197 = or(_T_2196, same_cycle_resp_1) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2201 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_203 else : node _T_2205 = eq(io.in.d.bits.size, c_size_lookup) node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(_T_2205, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2205, UInt<1>(0h1), "") : assert_204 node _T_2209 = and(io.in.d.valid, d_first_2) node _T_2210 = and(_T_2209, c_first_1) node _T_2211 = and(_T_2210, io.in.c.valid) node _T_2212 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2213 = and(_T_2211, _T_2212) node _T_2214 = and(_T_2213, d_release_ack_1) node _T_2215 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2216 = and(_T_2214, _T_2215) when _T_2216 : node _T_2217 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2218 = or(_T_2217, io.in.c.ready) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(_T_2218, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2218, UInt<1>(0h1), "") : assert_205 node _T_2222 = orr(c_set_wo_ready) when _T_2222 : node _T_2223 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(_T_2223, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2223, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_113 node _T_2227 = orr(inflight_1) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) node _T_2229 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2230 = or(_T_2228, _T_2229) node _T_2231 = lt(watchdog_1, plusarg_reader_1.out) node _T_2232 = or(_T_2230, _T_2231) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2236 = and(io.in.c.ready, io.in.c.valid) node _T_2237 = and(io.in.d.ready, io.in.d.valid) node _T_2238 = or(_T_2236, _T_2237) when _T_2238 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<12> connect d_set, UInt<12>(0h0) node _T_2239 = and(io.in.d.ready, io.in.d.valid) node _T_2240 = and(_T_2239, d_first_3) node _T_2241 = bits(io.in.d.bits.opcode, 2, 2) node _T_2242 = bits(io.in.d.bits.opcode, 1, 1) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) node _T_2244 = and(_T_2241, _T_2243) node _T_2245 = and(_T_2240, _T_2244) when _T_2245 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2246 = dshr(inflight_2, io.in.d.bits.sink) node _T_2247 = bits(_T_2246, 0, 0) node _T_2248 = eq(_T_2247, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<12> connect e_clr, UInt<12>(0h0) node _T_2252 = and(io.in.e.ready, io.in.e.valid) node _T_2253 = and(_T_2252, UInt<1>(0h1)) node _T_2254 = and(_T_2253, UInt<1>(0h1)) when _T_2254 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2255 = or(d_set, inflight_2) node _T_2256 = dshr(_T_2255, io.in.e.bits.sink) node _T_2257 = bits(_T_2256, 0, 0) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_114 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_115 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_6 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] io_in_b_bits_source = 6'h28; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_56 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_57 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_58 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_59 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_1 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_2 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_3 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_4 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_T_39 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_46 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_47 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _uncommonBits_T_60 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_61 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_62 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_63 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_64 = 6'h28; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _legal_source_T_25 = 3'h5; // @[Parameters.scala:54:10] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_35 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_40 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] _legal_source_T_33 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_43 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_44 = 5'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_37 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_1 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_7 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_13 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_19 = 4'hA; // @[Parameters.scala:54:10] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000180; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000180; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_78 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_97 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_103 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_104 = _source_ok_T_103 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 \| _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 \| _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 \| _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 \| _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_116 \| _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000180; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000180; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31] wire _T_2165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2165; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2165; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2239 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2239; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [1:0] b_first_counter; // @[Edges.scala:229:27] wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2236 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2236; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2236; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [42:0] inflight; // @[Monitor.scala:614:27] reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [171:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] a_set; // @[Monitor.scala:626:34] wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [171:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [171:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [171:0] _a_size_lookup_T_6 = {168'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [171:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[171:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2091 = _T_2165 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2091 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2091 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2091 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2091 ? _a_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [42:0] d_clr; // @[Monitor.scala:664:34] wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [171:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2137 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2106 = _T_2239 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2106 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2106 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2106 ? _d_sizes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [42:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [171:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [171:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [171:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [171:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [42:0] inflight_1; // @[Monitor.scala:726:35] reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [171:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] c_set; // @[Monitor.scala:738:34] wire [42:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [171:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [171:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [171:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [171:0] _c_size_lookup_T_6 = {168'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [171:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[171:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2178 = _T_2236 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2178 ? _c_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2178 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2178 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2178 ? _c_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2178 ? _c_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [42:0] d_clr_1; // @[Monitor.scala:774:34] wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [171:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2191 = _T_2239 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2191 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2191 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2191 ? _d_sizes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [42:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [171:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [171:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [171:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [11:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_set; // @[Monitor.scala:833:25] wire _T_2245 = _T_2239 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2245 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35] wire [11:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = or(UInt<1>(0h0), _T_70) node _T_72 = and(_T_21, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<14>(0h2000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<13>(0h1000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<17>(0h10000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<18>(0h2f000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<17>(0h10000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<13>(0h1000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<13>(0h1000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = or(_T_84, _T_89) node _T_121 = or(_T_120, _T_94) node _T_122 = or(_T_121, _T_99) node _T_123 = or(_T_122, _T_104) node _T_124 = or(_T_123, _T_109) node _T_125 = or(_T_124, _T_114) node _T_126 = or(_T_125, _T_119) node _T_127 = and(_T_79, _T_126) node _T_128 = or(UInt<1>(0h0), _T_127) node _T_129 = and(UInt<1>(0h0), _T_128) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_129, UInt<1>(0h1), "") : assert_3 node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_136 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_136, UInt<1>(0h1), "") : assert_5 node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(is_aligned, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_143 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_143, UInt<1>(0h1), "") : assert_7 node _T_147 = not(io.in.a.bits.mask) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_148, UInt<1>(0h1), "") : assert_8 node _T_152 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_152, UInt<1>(0h1), "") : assert_9 node _T_156 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_156 : node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<27>(0h4000000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<13>(0h1000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = or(_T_168, _T_173) node _T_205 = or(_T_204, _T_178) node _T_206 = or(_T_205, _T_183) node _T_207 = or(_T_206, _T_188) node _T_208 = or(_T_207, _T_193) node _T_209 = or(_T_208, _T_198) node _T_210 = or(_T_209, _T_203) node _T_211 = and(_T_163, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = and(_T_162, _T_212) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_213, UInt<1>(0h1), "") : assert_10 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<14>(0h2000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<18>(0h2f000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<27>(0h4000000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_225, _T_230) node _T_262 = or(_T_261, _T_235) node _T_263 = or(_T_262, _T_240) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_250) node _T_266 = or(_T_265, _T_255) node _T_267 = or(_T_266, _T_260) node _T_268 = and(_T_220, _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = and(UInt<1>(0h0), _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_270, UInt<1>(0h1), "") : assert_11 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_277, UInt<1>(0h1), "") : assert_13 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(is_aligned, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_284, UInt<1>(0h1), "") : assert_15 node _T_288 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_288, UInt<1>(0h1), "") : assert_16 node _T_292 = not(io.in.a.bits.mask) node _T_293 = eq(_T_292, UInt<1>(0h0)) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_293, UInt<1>(0h1), "") : assert_17 node _T_297 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_297, UInt<1>(0h1), "") : assert_18 node _T_301 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_301 : node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_307, UInt<1>(0h1), "") : assert_19 node _T_311 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_312 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(UInt<1>(0h0), _T_313) node _T_315 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = and(_T_314, _T_319) node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_323 = and(_T_321, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<14>(0h2000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = or(_T_329, _T_334) node _T_361 = or(_T_360, _T_339) node _T_362 = or(_T_361, _T_344) node _T_363 = or(_T_362, _T_349) node _T_364 = or(_T_363, _T_354) node _T_365 = or(_T_364, _T_359) node _T_366 = and(_T_324, _T_365) node _T_367 = or(UInt<1>(0h0), _T_320) node _T_368 = or(_T_367, _T_366) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_398 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_399 = and(_T_397, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = and(_T_400, _T_405) node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_409 = and(_T_407, _T_408) node _T_410 = or(UInt<1>(0h0), _T_409) node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<27>(0h4000000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = or(_T_415, _T_420) node _T_442 = or(_T_441, _T_425) node _T_443 = or(_T_442, _T_430) node _T_444 = or(_T_443, _T_435) node _T_445 = or(_T_444, _T_440) node _T_446 = and(_T_410, _T_445) node _T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = or(UInt<1>(0h0), _T_406) node _T_455 = or(_T_454, _T_446) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_396, _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_457, UInt<1>(0h1), "") : assert_26 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(is_aligned, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_467 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_467, UInt<1>(0h1), "") : assert_29 node _T_471 = eq(io.in.a.bits.mask, mask) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_471, UInt<1>(0h1), "") : assert_30 node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_475 : node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_483 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_484 = and(_T_482, _T_483) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<13>(0h1000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = and(_T_485, _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<14>(0h2000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<18>(0h2f000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = or(_T_500, _T_505) node _T_527 = or(_T_526, _T_510) node _T_528 = or(_T_527, _T_515) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_525) node _T_531 = and(_T_495, _T_530) node _T_532 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = and(_T_532, _T_537) node _T_539 = or(UInt<1>(0h0), _T_491) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_538) node _T_542 = and(_T_481, _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_542, UInt<1>(0h1), "") : assert_31 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_552, UInt<1>(0h1), "") : assert_34 node _T_556 = not(mask) node _T_557 = and(io.in.a.bits.mask, _T_556) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_558, UInt<1>(0h1), "") : assert_35 node _T_562 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_562 : node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<14>(0h2000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<13>(0h1000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<18>(0h2f000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<13>(0h1000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<27>(0h4000000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = or(_T_577, _T_582) node _T_609 = or(_T_608, _T_587) node _T_610 = or(_T_609, _T_592) node _T_611 = or(_T_610, _T_597) node _T_612 = or(_T_611, _T_602) node _T_613 = or(_T_612, _T_607) node _T_614 = and(_T_572, _T_613) node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = and(_T_615, _T_620) node _T_622 = or(UInt<1>(0h0), _T_614) node _T_623 = or(_T_622, _T_621) node _T_624 = and(_T_568, _T_623) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_624, UInt<1>(0h1), "") : assert_36 node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(is_aligned, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_634 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_634, UInt<1>(0h1), "") : assert_39 node _T_638 = eq(io.in.a.bits.mask, mask) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_638, UInt<1>(0h1), "") : assert_40 node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_642 : node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_645 = and(_T_643, _T_644) node _T_646 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_647 = and(_T_645, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<18>(0h2f000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<13>(0h1000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = or(_T_657, _T_662) node _T_689 = or(_T_688, _T_667) node _T_690 = or(_T_689, _T_672) node _T_691 = or(_T_690, _T_677) node _T_692 = or(_T_691, _T_682) node _T_693 = or(_T_692, _T_687) node _T_694 = and(_T_652, _T_693) node _T_695 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = or(UInt<1>(0h0), _T_694) node _T_703 = or(_T_702, _T_701) node _T_704 = and(_T_648, _T_703) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_704, UInt<1>(0h1), "") : assert_41 node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(is_aligned, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_714 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_714, UInt<1>(0h1), "") : assert_44 node _T_718 = eq(io.in.a.bits.mask, mask) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_718, UInt<1>(0h1), "") : assert_45 node _T_722 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_722 : node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = and(_T_725, _T_726) node _T_728 = or(UInt<1>(0h0), _T_727) node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = and(_T_732, _T_737) node _T_739 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_740 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<14>(0h2000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<18>(0h2f000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<17>(0h10000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<27>(0h4000000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<13>(0h1000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = or(_T_744, _T_749) node _T_776 = or(_T_775, _T_754) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_764) node _T_779 = or(_T_778, _T_769) node _T_780 = or(_T_779, _T_774) node _T_781 = and(_T_739, _T_780) node _T_782 = or(UInt<1>(0h0), _T_738) node _T_783 = or(_T_782, _T_781) node _T_784 = and(_T_728, _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_784, UInt<1>(0h1), "") : assert_46 node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(is_aligned, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_794 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_794, UInt<1>(0h1), "") : assert_49 node _T_798 = eq(io.in.a.bits.mask, mask) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_798, UInt<1>(0h1), "") : assert_50 node _T_802 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_802, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_806 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_806, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_810 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_810 : node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_814 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_814, UInt<1>(0h1), "") : assert_54 node _T_818 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_818, UInt<1>(0h1), "") : assert_55 node _T_822 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_822, UInt<1>(0h1), "") : assert_56 node _T_826 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_826, UInt<1>(0h1), "") : assert_57 node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(sink_ok, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_837 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_837, UInt<1>(0h1), "") : assert_60 node _T_841 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_841, UInt<1>(0h1), "") : assert_61 node _T_845 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_845, UInt<1>(0h1), "") : assert_62 node _T_849 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_849, UInt<1>(0h1), "") : assert_63 node _T_853 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_854 = or(UInt<1>(0h1), _T_853) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_854, UInt<1>(0h1), "") : assert_64 node _T_858 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_858 : node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(sink_ok, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_865, UInt<1>(0h1), "") : assert_67 node _T_869 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_869, UInt<1>(0h1), "") : assert_68 node _T_873 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_873, UInt<1>(0h1), "") : assert_69 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = or(_T_877, io.in.d.bits.corrupt) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_878, UInt<1>(0h1), "") : assert_70 node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_883 = or(UInt<1>(0h1), _T_882) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_883, UInt<1>(0h1), "") : assert_71 node _T_887 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_887 : node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_891 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_891, UInt<1>(0h1), "") : assert_73 node _T_895 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_895, UInt<1>(0h1), "") : assert_74 node _T_899 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_900 = or(UInt<1>(0h1), _T_899) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_900, UInt<1>(0h1), "") : assert_75 node _T_904 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_904 : node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_908 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_908, UInt<1>(0h1), "") : assert_77 node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_913 = or(_T_912, io.in.d.bits.corrupt) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_913, UInt<1>(0h1), "") : assert_78 node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_918 = or(UInt<1>(0h1), _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_918, UInt<1>(0h1), "") : assert_79 node _T_922 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_926, UInt<1>(0h1), "") : assert_81 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_930, UInt<1>(0h1), "") : assert_82 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h1), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_935, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_939 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_939, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_943 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_943, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_947 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_947, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_951 = eq(a_first, UInt<1>(0h0)) node _T_952 = and(io.in.a.valid, _T_951) when _T_952 : node _T_953 = eq(io.in.a.bits.opcode, opcode) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_953, UInt<1>(0h1), "") : assert_87 node _T_957 = eq(io.in.a.bits.param, param) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_957, UInt<1>(0h1), "") : assert_88 node _T_961 = eq(io.in.a.bits.size, size) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_961, UInt<1>(0h1), "") : assert_89 node _T_965 = eq(io.in.a.bits.source, source) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_965, UInt<1>(0h1), "") : assert_90 node _T_969 = eq(io.in.a.bits.address, address) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_969, UInt<1>(0h1), "") : assert_91 node _T_973 = and(io.in.a.ready, io.in.a.valid) node _T_974 = and(_T_973, a_first) when _T_974 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_975 = eq(d_first, UInt<1>(0h0)) node _T_976 = and(io.in.d.valid, _T_975) when _T_976 : node _T_977 = eq(io.in.d.bits.opcode, opcode_1) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_977, UInt<1>(0h1), "") : assert_92 node _T_981 = eq(io.in.d.bits.param, param_1) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_981, UInt<1>(0h1), "") : assert_93 node _T_985 = eq(io.in.d.bits.size, size_1) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_985, UInt<1>(0h1), "") : assert_94 node _T_989 = eq(io.in.d.bits.source, source_1) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_989, UInt<1>(0h1), "") : assert_95 node _T_993 = eq(io.in.d.bits.sink, sink) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_993, UInt<1>(0h1), "") : assert_96 node _T_997 = eq(io.in.d.bits.denied, denied) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_997, UInt<1>(0h1), "") : assert_97 node _T_1001 = and(io.in.d.ready, io.in.d.valid) node _T_1002 = and(_T_1001, d_first) when _T_1002 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1003 = and(io.in.a.valid, a_first_1) node _T_1004 = and(_T_1003, UInt<1>(0h1)) when _T_1004 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1005 = and(io.in.a.ready, io.in.a.valid) node _T_1006 = and(_T_1005, a_first_1) node _T_1007 = and(_T_1006, UInt<1>(0h1)) when _T_1007 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1008 = dshr(inflight, io.in.a.bits.source) node _T_1009 = bits(_T_1008, 0, 0) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1014 = and(io.in.d.valid, d_first_1) node _T_1015 = and(_T_1014, UInt<1>(0h1)) node _T_1016 = eq(d_release_ack, UInt<1>(0h0)) node _T_1017 = and(_T_1015, _T_1016) when _T_1017 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1018 = and(io.in.d.ready, io.in.d.valid) node _T_1019 = and(_T_1018, d_first_1) node _T_1020 = and(_T_1019, UInt<1>(0h1)) node _T_1021 = eq(d_release_ack, UInt<1>(0h0)) node _T_1022 = and(_T_1020, _T_1021) when _T_1022 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1023 = and(io.in.d.valid, d_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1027 = dshr(inflight, io.in.d.bits.source) node _T_1028 = bits(_T_1027, 0, 0) node _T_1029 = or(_T_1028, same_cycle_resp) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1033 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1034 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_100 node _T_1039 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_101 else : node _T_1043 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1044 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1045 = or(_T_1043, _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_102 node _T_1049 = eq(io.in.d.bits.size, a_size_lookup) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_103 node _T_1053 = and(io.in.d.valid, d_first_1) node _T_1054 = and(_T_1053, a_first_1) node _T_1055 = and(_T_1054, io.in.a.valid) node _T_1056 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = eq(d_release_ack, UInt<1>(0h0)) node _T_1059 = and(_T_1057, _T_1058) when _T_1059 : node _T_1060 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1061 = or(_T_1060, io.in.a.ready) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_104 node _T_1065 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1066 = orr(a_set_wo_ready) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = or(_T_1065, _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_66 node _T_1072 = orr(inflight) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) node _T_1074 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1075 = or(_T_1073, _T_1074) node _T_1076 = lt(watchdog, plusarg_reader.out) node _T_1077 = or(_T_1075, _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1081 = and(io.in.a.ready, io.in.a.valid) node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = or(_T_1081, _T_1082) when _T_1083 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1084 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1085 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1086 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1087 = and(_T_1085, _T_1086) node _T_1088 = and(_T_1084, _T_1087) when _T_1088 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1089 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1090 = and(_T_1089, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1091 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1092 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1093 = and(_T_1091, _T_1092) node _T_1094 = and(_T_1090, _T_1093) when _T_1094 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1095 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1096 = bits(_T_1095, 0, 0) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1101 = and(io.in.d.valid, d_first_2) node _T_1102 = and(_T_1101, UInt<1>(0h1)) node _T_1103 = and(_T_1102, d_release_ack_1) when _T_1103 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1104 = and(io.in.d.ready, io.in.d.valid) node _T_1105 = and(_T_1104, d_first_2) node _T_1106 = and(_T_1105, UInt<1>(0h1)) node _T_1107 = and(_T_1106, d_release_ack_1) when _T_1107 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1108 = and(io.in.d.valid, d_first_2) node _T_1109 = and(_T_1108, UInt<1>(0h1)) node _T_1110 = and(_T_1109, d_release_ack_1) when _T_1110 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1111 = dshr(inflight_1, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp_1) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1117 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_109 else : node _T_1121 = eq(io.in.d.bits.size, c_size_lookup) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_110 node _T_1125 = and(io.in.d.valid, d_first_2) node _T_1126 = and(_T_1125, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1127 = and(_T_1126, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1128 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = and(_T_1129, d_release_ack_1) node _T_1131 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _T_1133 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1134 = or(_T_1133, _WIRE_23.ready) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_111 node _T_1138 = orr(c_set_wo_ready) when _T_1138 : node _T_1139 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_67 node _T_1143 = orr(inflight_1) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) node _T_1145 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1146 = or(_T_1144, _T_1145) node _T_1147 = lt(watchdog_1, plusarg_reader_1.out) node _T_1148 = or(_T_1146, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1152 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = or(_T_1152, _T_1153) when _T_1154 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h0; // @[Edges.scala:92:37] wire _a_first_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire a_first_beats1_opdata = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire a_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h2; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] io_in_a_bits_mask = 8'hF; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:657:53] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:657:61] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [4:0] _a_sizes_set_interm_T_1 = 5'h5; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'h4; // @[Monitor.scala:658:51] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [28:0] _is_aligned_T = {27'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_0_1 = _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_0_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire mask_sub_1_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_1 = _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_3_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [28:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = {3'h0, a_set}; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'h5 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1053 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_mbus_i1_o2_a32d64s5k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_33 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<5>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<5>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<5>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<5>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<5>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<5>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<5>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<5>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<28>(0h0) connect _WIRE_50.bits.source, UInt<5>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<5>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<28>(0h0) connect _WIRE_54.bits.source, UInt<5>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<5>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<28>(0h0) connect _WIRE_58.bits.source, UInt<5>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<5>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<28>(0h0) connect _WIRE_62.bits.source, UInt<5>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<5>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 5) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 4, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 5) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<5>(0h1f)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) node _requestDOI_T = shr(out[0].d.bits.source, 5) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 4, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 5) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<5>(0h1f)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<5>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<5>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<5>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<5>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<5>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<5>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<5>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<5>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<32>(0h0) connect _WIRE_80.bits.source, UInt<5>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<5> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)	module TLXbar_mbus_i1_o2_a32d64s5k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [4:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [4:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [4:0] _addressC_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _addressC_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _requestBOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _requestBOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _requestBOI_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29] wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _requestBOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _requestBOI_uncommonBits_T_1 = 5'h0; // @[Parameters.scala:52:29] wire [4:0] requestBOI_uncommonBits_1 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _beatsBO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _beatsBO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _beatsBO_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _beatsBO_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _beatsCI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _beatsCI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _portsBIO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _portsBIO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] portsBIO_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsBIO_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _portsBIO_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] portsBIO_filtered_1_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsCOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _portsCOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] portsCOI_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] portsCOI_filtered_1_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [27:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [4:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [4:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [4:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [4:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [4:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [4:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [4:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [4:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [31:0] _requestAIO_T = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d32s1k3z4u_3 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_44 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d32s1k3z4u_2 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d32s1k3z4u_2 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a32d32s1k3z4u_3( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_44 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d32s1k3z4u_2 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d32s1k3z4u_2 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_316 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_316( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_2 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<17> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<6> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_38_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_7_2, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_34_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_12_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_10_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_12_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_22_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_12_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_7_6, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_29_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_10_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_12_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_12_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_7_8, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_28_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_12_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_7_9, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_37_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_10_10, decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_12_8) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_12, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_9_10) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_30_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_10_11, decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_12_9) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_7_13, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_6_13) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_10_12, decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_12_10) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_14, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_9_12) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_6_14) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_39_2 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_10_13, decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_andMatrixInput_12_11) node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_7_15, decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_9_13) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_4_15, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_andMatrixInput_6_15) node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_15) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_11) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_21_2 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_33_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_15_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_10_16, decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_12_12) node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_7_18, decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_andMatrixInput_9_16) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_6_18) node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_2_18, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_12) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_31_2 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_10_17, decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_andMatrixInput_12_13) node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_7_19, decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_9_17) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_4_19, decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_andMatrixInput_6_19) node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_2_19, decoded_andMatrixOutputs_andMatrixInput_3_19) node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_hi_hi_lo_13) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_20_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_10_18, decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_12_14) node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_9_18) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_4_20, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_6_20) node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_20) node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_14) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_32_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_10_19, decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_12_15) node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_7_21, decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_9_19) node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21) node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_4_21, decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_6_21) node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_2_21, decoded_andMatrixOutputs_andMatrixInput_3_21) node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_15) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21) node decoded_andMatrixOutputs_17_2 = andr(_decoded_andMatrixOutputs_T_21) node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_10_20, decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_12_16) node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_7_22, decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_9_20) node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22) node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_4_22, decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_6_22) node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_22, decoded_andMatrixOutputs_andMatrixInput_3_22) node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_hi_hi_lo_16) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_10_21, decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_lo_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_12_17) node decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_7_23, decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_9_21) node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23) node decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_4_23, decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_hi_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_6_23) node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_2_23, decoded_andMatrixOutputs_andMatrixInput_3_23) node decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_hi_hi_lo_17) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23) node decoded_andMatrixOutputs_25_2 = andr(_decoded_andMatrixOutputs_T_23) node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_andMatrixOutputs_lo_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_andMatrixOutputs_lo_24 = cat(decoded_andMatrixOutputs_lo_hi_24, decoded_andMatrixOutputs_lo_lo_24) node decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_andMatrixOutputs_hi_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_andMatrixOutputs_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_24, decoded_andMatrixOutputs_hi_lo_24) node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_24, decoded_andMatrixOutputs_lo_24) node decoded_andMatrixOutputs_18_2 = andr(_decoded_andMatrixOutputs_T_24) node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_andMatrixOutputs_lo_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_andMatrixOutputs_lo_25 = cat(decoded_andMatrixOutputs_lo_hi_25, decoded_andMatrixOutputs_lo_lo_25) node decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_andMatrixOutputs_hi_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_andMatrixOutputs_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_25, decoded_andMatrixOutputs_hi_lo_25) node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_25, decoded_andMatrixOutputs_lo_25) node decoded_andMatrixOutputs_24_2 = andr(_decoded_andMatrixOutputs_T_25) node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_7_26, decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_5_26, decoded_andMatrixOutputs_andMatrixInput_6_26) node decoded_andMatrixOutputs_lo_26 = cat(decoded_andMatrixOutputs_lo_hi_26, decoded_andMatrixOutputs_lo_lo_26) node decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_24, decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_andMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_26, decoded_andMatrixOutputs_hi_lo_26) node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_26, decoded_andMatrixOutputs_lo_26) node decoded_andMatrixOutputs_36_2 = andr(_decoded_andMatrixOutputs_T_26) node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_7_27, decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_5_27, decoded_andMatrixOutputs_andMatrixInput_6_27) node decoded_andMatrixOutputs_lo_27 = cat(decoded_andMatrixOutputs_lo_hi_27, decoded_andMatrixOutputs_lo_lo_27) node decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_25, decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_andMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_27, decoded_andMatrixOutputs_hi_lo_27) node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_hi_27, decoded_andMatrixOutputs_lo_27) node decoded_andMatrixOutputs_16_2 = andr(_decoded_andMatrixOutputs_T_27) node decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_7_28, decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_5_28, decoded_andMatrixOutputs_andMatrixInput_6_28) node decoded_andMatrixOutputs_lo_28 = cat(decoded_andMatrixOutputs_lo_hi_28, decoded_andMatrixOutputs_lo_lo_28) node decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_26, decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_andMatrixOutputs_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_28, decoded_andMatrixOutputs_hi_lo_28) node _decoded_andMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_hi_28, decoded_andMatrixOutputs_lo_28) node decoded_andMatrixOutputs_35_2 = andr(_decoded_andMatrixOutputs_T_28) node decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_7_29, decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_5_29, decoded_andMatrixOutputs_andMatrixInput_6_29) node decoded_andMatrixOutputs_lo_29 = cat(decoded_andMatrixOutputs_lo_hi_29, decoded_andMatrixOutputs_lo_lo_29) node decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_hi_27, decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_andMatrixOutputs_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_29, decoded_andMatrixOutputs_hi_lo_29) node _decoded_andMatrixOutputs_T_29 = cat(decoded_andMatrixOutputs_hi_29, decoded_andMatrixOutputs_lo_29) node decoded_andMatrixOutputs_27_2 = andr(_decoded_andMatrixOutputs_T_29) node decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_7_30, decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_5_30, decoded_andMatrixOutputs_andMatrixInput_6_30) node decoded_andMatrixOutputs_lo_30 = cat(decoded_andMatrixOutputs_lo_hi_30, decoded_andMatrixOutputs_lo_lo_30) node decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_hi_28, decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_andMatrixOutputs_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_30, decoded_andMatrixOutputs_hi_lo_30) node _decoded_andMatrixOutputs_T_30 = cat(decoded_andMatrixOutputs_hi_30, decoded_andMatrixOutputs_lo_30) node decoded_andMatrixOutputs_26_2 = andr(_decoded_andMatrixOutputs_T_30) node decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_7_31, decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_5_31, decoded_andMatrixOutputs_andMatrixInput_6_31) node decoded_andMatrixOutputs_lo_31 = cat(decoded_andMatrixOutputs_lo_hi_31, decoded_andMatrixOutputs_lo_lo_31) node decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_hi_29, decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_andMatrixOutputs_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_31, decoded_andMatrixOutputs_hi_lo_31) node _decoded_andMatrixOutputs_T_31 = cat(decoded_andMatrixOutputs_hi_31, decoded_andMatrixOutputs_lo_31) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_31) node decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_2_32, decoded_andMatrixOutputs_andMatrixInput_3_32) node decoded_andMatrixOutputs_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_andMatrixOutputs_andMatrixInput_1_32) node _decoded_andMatrixOutputs_T_32 = cat(decoded_andMatrixOutputs_hi_32, decoded_andMatrixOutputs_lo_32) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_32) node decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_2_33, decoded_andMatrixOutputs_andMatrixInput_3_33) node decoded_andMatrixOutputs_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_andMatrixOutputs_andMatrixInput_1_33) node _decoded_andMatrixOutputs_T_33 = cat(decoded_andMatrixOutputs_hi_33, decoded_andMatrixOutputs_lo_33) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_33) node decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_7_32, decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_5_32, decoded_andMatrixOutputs_andMatrixInput_6_32) node decoded_andMatrixOutputs_lo_34 = cat(decoded_andMatrixOutputs_lo_hi_32, decoded_andMatrixOutputs_lo_lo_32) node decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_hi_30, decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_andMatrixOutputs_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_32, decoded_andMatrixOutputs_hi_lo_32) node _decoded_andMatrixOutputs_T_34 = cat(decoded_andMatrixOutputs_hi_34, decoded_andMatrixOutputs_lo_34) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_34) node decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_7_33, decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_5_33, decoded_andMatrixOutputs_andMatrixInput_6_33) node decoded_andMatrixOutputs_lo_35 = cat(decoded_andMatrixOutputs_lo_hi_33, decoded_andMatrixOutputs_lo_lo_33) node decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_hi_31, decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_andMatrixOutputs_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_33, decoded_andMatrixOutputs_hi_lo_33) node _decoded_andMatrixOutputs_T_35 = cat(decoded_andMatrixOutputs_hi_35, decoded_andMatrixOutputs_lo_35) node decoded_andMatrixOutputs_23_2 = andr(_decoded_andMatrixOutputs_T_35) node decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_7_34, decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_5_34, decoded_andMatrixOutputs_andMatrixInput_6_34) node decoded_andMatrixOutputs_lo_36 = cat(decoded_andMatrixOutputs_lo_hi_34, decoded_andMatrixOutputs_lo_lo_34) node decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_hi_32, decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_andMatrixOutputs_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_34, decoded_andMatrixOutputs_hi_lo_34) node _decoded_andMatrixOutputs_T_36 = cat(decoded_andMatrixOutputs_hi_36, decoded_andMatrixOutputs_lo_36) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_36) node decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_7_35, decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_5_35, decoded_andMatrixOutputs_andMatrixInput_6_35) node decoded_andMatrixOutputs_lo_37 = cat(decoded_andMatrixOutputs_lo_hi_35, decoded_andMatrixOutputs_lo_lo_35) node decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_hi_33, decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_andMatrixOutputs_hi_37 = cat(decoded_andMatrixOutputs_hi_hi_35, decoded_andMatrixOutputs_hi_lo_35) node _decoded_andMatrixOutputs_T_37 = cat(decoded_andMatrixOutputs_hi_37, decoded_andMatrixOutputs_lo_37) node decoded_andMatrixOutputs_19_2 = andr(_decoded_andMatrixOutputs_T_37) node decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_7_36, decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_5_36, decoded_andMatrixOutputs_andMatrixInput_6_36) node decoded_andMatrixOutputs_lo_38 = cat(decoded_andMatrixOutputs_lo_hi_36, decoded_andMatrixOutputs_lo_lo_36) node decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_hi_34, decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_andMatrixOutputs_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_36, decoded_andMatrixOutputs_hi_lo_36) node _decoded_andMatrixOutputs_T_38 = cat(decoded_andMatrixOutputs_hi_38, decoded_andMatrixOutputs_lo_38) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_38) node decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_7_37, decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_5_37, decoded_andMatrixOutputs_andMatrixInput_6_37) node decoded_andMatrixOutputs_lo_39 = cat(decoded_andMatrixOutputs_lo_hi_37, decoded_andMatrixOutputs_lo_lo_37) node decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_andMatrixOutputs_hi_hi_hi_35, decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_andMatrixOutputs_hi_39 = cat(decoded_andMatrixOutputs_hi_hi_37, decoded_andMatrixOutputs_hi_lo_37) node _decoded_andMatrixOutputs_T_39 = cat(decoded_andMatrixOutputs_hi_39, decoded_andMatrixOutputs_lo_39) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_39) node decoded_orMatrixOutputs_lo = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_4_2) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_5_2, decoded_andMatrixOutputs_19_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_26_2, decoded_andMatrixOutputs_11_2) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_35_2, decoded_andMatrixOutputs_27_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_14_2, decoded_andMatrixOutputs_23_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_36_2, decoded_andMatrixOutputs_16_2) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_13_2, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_18_2) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_andMatrixOutputs_24_2) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_andMatrixOutputs_32_2, decoded_andMatrixOutputs_17_2) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_andMatrixOutputs_15_2, decoded_andMatrixOutputs_31_2) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_andMatrixOutputs_20_2) node decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_andMatrixOutputs_21_2, decoded_andMatrixOutputs_33_2) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_39_2) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_andMatrixOutputs_37_2, decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_andMatrixOutputs_30_2) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_28_2) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_andMatrixOutputs_2_2) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_22_2) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_andMatrixOutputs_29_2) node decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_34_2) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_38_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_1, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_1, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 3, 0) node _decoded_T_1 = bits(_decoded_T, 1, 0) node _decoded_T_2 = bits(_decoded_T_1, 0, 0) node _decoded_T_3 = bits(_decoded_T_1, 1, 1) node _decoded_T_4 = cat(_decoded_T_2, _decoded_T_3) node _decoded_T_5 = bits(_decoded_T, 3, 2) node _decoded_T_6 = bits(_decoded_T_5, 0, 0) node _decoded_T_7 = bits(_decoded_T_5, 1, 1) node _decoded_T_8 = cat(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = cat(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(decoded_plaOutput, 5, 4) node _decoded_T_11 = bits(_decoded_T_10, 0, 0) node _decoded_T_12 = bits(_decoded_T_10, 1, 1) node _decoded_T_13 = cat(_decoded_T_11, _decoded_T_12) node decoded = cat(_decoded_T_9, _decoded_T_13) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<17> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<6> node decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_10_24, decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_andMatrixOutputs_lo_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_12_18) node decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_7_38, decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_andMatrixOutputs_lo_hi_hi_24, decoded_andMatrixOutputs_andMatrixInput_9_24) node decoded_andMatrixOutputs_lo_40 = cat(decoded_andMatrixOutputs_lo_hi_38, decoded_andMatrixOutputs_lo_lo_38) node decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_4_38, decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_andMatrixOutputs_hi_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_6_38) node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_2_40, decoded_andMatrixOutputs_andMatrixInput_3_40) node decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_hi_36, decoded_andMatrixOutputs_hi_hi_lo_18) node decoded_andMatrixOutputs_hi_40 = cat(decoded_andMatrixOutputs_hi_hi_38, decoded_andMatrixOutputs_hi_lo_38) node _decoded_andMatrixOutputs_T_40 = cat(decoded_andMatrixOutputs_hi_40, decoded_andMatrixOutputs_lo_40) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_40) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_2, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 5, 5) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_14 = bits(decoded_plaOutput_1, 3, 0) node _decoded_T_15 = bits(_decoded_T_14, 1, 0) node _decoded_T_16 = bits(_decoded_T_15, 0, 0) node _decoded_T_17 = bits(_decoded_T_15, 1, 1) node _decoded_T_18 = cat(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = bits(_decoded_T_14, 3, 2) node _decoded_T_20 = bits(_decoded_T_19, 0, 0) node _decoded_T_21 = bits(_decoded_T_19, 1, 1) node _decoded_T_22 = cat(_decoded_T_20, _decoded_T_21) node _decoded_T_23 = cat(_decoded_T_18, _decoded_T_22) node _decoded_T_24 = bits(decoded_plaOutput_1, 5, 4) node _decoded_T_25 = bits(_decoded_T_24, 0, 0) node _decoded_T_26 = bits(_decoded_T_24, 1, 1) node _decoded_T_27 = cat(_decoded_T_25, _decoded_T_26) node decoded_1 = cat(_decoded_T_23, _decoded_T_27) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<17> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<6> node _decoded_orMatrixOutputs_T_13 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_hi_3 = cat(_decoded_orMatrixOutputs_T_13, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_2, 5, 5) node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_28 = bits(decoded_plaOutput_2, 3, 0) node _decoded_T_29 = bits(_decoded_T_28, 1, 0) node _decoded_T_30 = bits(_decoded_T_29, 0, 0) node _decoded_T_31 = bits(_decoded_T_29, 1, 1) node _decoded_T_32 = cat(_decoded_T_30, _decoded_T_31) node _decoded_T_33 = bits(_decoded_T_28, 3, 2) node _decoded_T_34 = bits(_decoded_T_33, 0, 0) node _decoded_T_35 = bits(_decoded_T_33, 1, 1) node _decoded_T_36 = cat(_decoded_T_34, _decoded_T_35) node _decoded_T_37 = cat(_decoded_T_32, _decoded_T_36) node _decoded_T_38 = bits(decoded_plaOutput_2, 5, 4) node _decoded_T_39 = bits(_decoded_T_38, 0, 0) node _decoded_T_40 = bits(_decoded_T_38, 1, 1) node _decoded_T_41 = cat(_decoded_T_39, _decoded_T_40) node decoded_2 = cat(_decoded_T_37, _decoded_T_41) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T connect io.resp.`2`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_20 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_2( // @[RouteComputer.scala:29:7] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_5 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [25:0] _decoded_orMatrixOutputs_T_10 = {&{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_3 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_4 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_5 = &{~(io_req_1_bits_flow_egress_node_id[1]), io_req_1_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :98:{53,70}] assign io_resp_0_vc_sel_0_0 = \|_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_0_1 = \|{&{decoded_invInputs[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_2 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_3 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_4 = \|{&{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}, &{decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_5 = \|{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}, &{decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[21] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[10]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[11]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[12]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[13]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[14]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[15]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[16]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[17]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[18]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[19]) node source_ok = or(_source_ok_T_59, _source_ok_WIRE[20]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = and(_T_11, _T_24) node _T_193 = and(_T_192, _T_37) node _T_194 = and(_T_193, _T_50) node _T_195 = and(_T_194, _T_63) node _T_196 = and(_T_195, _T_71) node _T_197 = and(_T_196, _T_79) node _T_198 = and(_T_197, _T_87) node _T_199 = and(_T_198, _T_95) node _T_200 = and(_T_199, _T_103) node _T_201 = and(_T_200, _T_111) node _T_202 = and(_T_201, _T_119) node _T_203 = and(_T_202, _T_127) node _T_204 = and(_T_203, _T_135) node _T_205 = and(_T_204, _T_143) node _T_206 = and(_T_205, _T_151) node _T_207 = and(_T_206, _T_159) node _T_208 = and(_T_207, _T_167) node _T_209 = and(_T_208, _T_175) node _T_210 = and(_T_209, _T_183) node _T_211 = and(_T_210, _T_191) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_211, UInt<1>(0h1), "") : assert_1 node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_215 : node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_4) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<1>(0h1)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_5) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h2)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_6) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_238 = shr(io.in.a.bits.source, 2) node _T_239 = eq(_T_238, UInt<2>(0h3)) node _T_240 = leq(UInt<1>(0h0), uncommonBits_7) node _T_241 = and(_T_239, _T_240) node _T_242 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_249 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_250 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_251 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_252 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_253 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_257 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_258 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_259 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_260 = or(_T_219, _T_225) node _T_261 = or(_T_260, _T_231) node _T_262 = or(_T_261, _T_237) node _T_263 = or(_T_262, _T_243) node _T_264 = or(_T_263, _T_244) node _T_265 = or(_T_264, _T_245) node _T_266 = or(_T_265, _T_246) node _T_267 = or(_T_266, _T_247) node _T_268 = or(_T_267, _T_248) node _T_269 = or(_T_268, _T_249) node _T_270 = or(_T_269, _T_250) node _T_271 = or(_T_270, _T_251) node _T_272 = or(_T_271, _T_252) node _T_273 = or(_T_272, _T_253) node _T_274 = or(_T_273, _T_254) node _T_275 = or(_T_274, _T_255) node _T_276 = or(_T_275, _T_256) node _T_277 = or(_T_276, _T_257) node _T_278 = or(_T_277, _T_258) node _T_279 = or(_T_278, _T_259) node _T_280 = and(_T_218, _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<17>(0h100c0))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_290 = cvt(_T_289) node _T_291 = and(_T_290, asSInt(UInt<29>(0h100000c0))) node _T_292 = asSInt(_T_291) node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0))) node _T_294 = or(_T_288, _T_293) node _T_295 = and(_T_283, _T_294) node _T_296 = or(UInt<1>(0h0), _T_295) node _T_297 = and(_T_281, _T_296) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_297, UInt<1>(0h1), "") : assert_2 node _T_301 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_302 = shr(io.in.a.bits.source, 2) node _T_303 = eq(_T_302, UInt<1>(0h0)) node _T_304 = leq(UInt<1>(0h0), uncommonBits_8) node _T_305 = and(_T_303, _T_304) node _T_306 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_307 = and(_T_305, _T_306) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_308 = shr(io.in.a.bits.source, 2) node _T_309 = eq(_T_308, UInt<1>(0h1)) node _T_310 = leq(UInt<1>(0h0), uncommonBits_9) node _T_311 = and(_T_309, _T_310) node _T_312 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_313 = and(_T_311, _T_312) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_314 = shr(io.in.a.bits.source, 2) node _T_315 = eq(_T_314, UInt<2>(0h2)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_10) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_319 = and(_T_317, _T_318) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_320 = shr(io.in.a.bits.source, 2) node _T_321 = eq(_T_320, UInt<2>(0h3)) node _T_322 = leq(UInt<1>(0h0), uncommonBits_11) node _T_323 = and(_T_321, _T_322) node _T_324 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_325 = and(_T_323, _T_324) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[21] connect _WIRE[0], _T_301 connect _WIRE[1], _T_307 connect _WIRE[2], _T_313 connect _WIRE[3], _T_319 connect _WIRE[4], _T_325 connect _WIRE[5], _T_326 connect _WIRE[6], _T_327 connect _WIRE[7], _T_328 connect _WIRE[8], _T_329 connect _WIRE[9], _T_330 connect _WIRE[10], _T_331 connect _WIRE[11], _T_332 connect _WIRE[12], _T_333 connect _WIRE[13], _T_334 connect _WIRE[14], _T_335 connect _WIRE[15], _T_336 connect _WIRE[16], _T_337 connect _WIRE[17], _T_338 connect _WIRE[18], _T_339 connect _WIRE[19], _T_340 connect _WIRE[20], _T_341 node _T_342 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_343 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_344 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_345 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_346 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_347 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_349 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_350 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE[5], _T_342, UInt<1>(0h0)) node _T_356 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE[7], _T_343, UInt<1>(0h0)) node _T_358 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE[9], _T_344, UInt<1>(0h0)) node _T_360 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE[11], _T_345, UInt<1>(0h0)) node _T_362 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE[13], _T_346, UInt<1>(0h0)) node _T_364 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE[15], _T_347, UInt<1>(0h0)) node _T_366 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_367 = mux(_WIRE[17], _T_348, UInt<1>(0h0)) node _T_368 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_369 = mux(_WIRE[19], _T_349, UInt<1>(0h0)) node _T_370 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_371 = or(_T_350, _T_351) node _T_372 = or(_T_371, _T_352) node _T_373 = or(_T_372, _T_353) node _T_374 = or(_T_373, _T_354) node _T_375 = or(_T_374, _T_355) node _T_376 = or(_T_375, _T_356) node _T_377 = or(_T_376, _T_357) node _T_378 = or(_T_377, _T_358) node _T_379 = or(_T_378, _T_359) node _T_380 = or(_T_379, _T_360) node _T_381 = or(_T_380, _T_361) node _T_382 = or(_T_381, _T_362) node _T_383 = or(_T_382, _T_363) node _T_384 = or(_T_383, _T_364) node _T_385 = or(_T_384, _T_365) node _T_386 = or(_T_385, _T_366) node _T_387 = or(_T_386, _T_367) node _T_388 = or(_T_387, _T_368) node _T_389 = or(_T_388, _T_369) node _T_390 = or(_T_389, _T_370) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_390 node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h100c0))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<29>(0h100000c0))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = or(_T_399, _T_404) node _T_406 = and(_T_394, _T_405) node _T_407 = or(UInt<1>(0h0), _T_406) node _T_408 = and(_WIRE_1, _T_407) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_408, UInt<1>(0h1), "") : assert_3 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(source_ok, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_415, UInt<1>(0h1), "") : assert_5 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_422, UInt<1>(0h1), "") : assert_7 node _T_426 = not(io.in.a.bits.mask) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_427, UInt<1>(0h1), "") : assert_8 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_431, UInt<1>(0h1), "") : assert_9 node _T_435 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_12) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<1>(0h1)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_13) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_452 = shr(io.in.a.bits.source, 2) node _T_453 = eq(_T_452, UInt<2>(0h2)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_14) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<2>(0h3)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_15) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_473 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_480 = or(_T_439, _T_445) node _T_481 = or(_T_480, _T_451) node _T_482 = or(_T_481, _T_457) node _T_483 = or(_T_482, _T_463) node _T_484 = or(_T_483, _T_464) node _T_485 = or(_T_484, _T_465) node _T_486 = or(_T_485, _T_466) node _T_487 = or(_T_486, _T_467) node _T_488 = or(_T_487, _T_468) node _T_489 = or(_T_488, _T_469) node _T_490 = or(_T_489, _T_470) node _T_491 = or(_T_490, _T_471) node _T_492 = or(_T_491, _T_472) node _T_493 = or(_T_492, _T_473) node _T_494 = or(_T_493, _T_474) node _T_495 = or(_T_494, _T_475) node _T_496 = or(_T_495, _T_476) node _T_497 = or(_T_496, _T_477) node _T_498 = or(_T_497, _T_478) node _T_499 = or(_T_498, _T_479) node _T_500 = and(_T_438, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<17>(0h100c0))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<29>(0h100000c0))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = or(_T_508, _T_513) node _T_515 = and(_T_503, _T_514) node _T_516 = or(UInt<1>(0h0), _T_515) node _T_517 = and(_T_501, _T_516) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_517, UInt<1>(0h1), "") : assert_10 node _T_521 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<1>(0h0)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_16) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<1>(0h1)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_17) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_533 = and(_T_531, _T_532) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_534 = shr(io.in.a.bits.source, 2) node _T_535 = eq(_T_534, UInt<2>(0h2)) node _T_536 = leq(UInt<1>(0h0), uncommonBits_18) node _T_537 = and(_T_535, _T_536) node _T_538 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_539 = and(_T_537, _T_538) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_540 = shr(io.in.a.bits.source, 2) node _T_541 = eq(_T_540, UInt<2>(0h3)) node _T_542 = leq(UInt<1>(0h0), uncommonBits_19) node _T_543 = and(_T_541, _T_542) node _T_544 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_545 = and(_T_543, _T_544) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_547 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_548 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_549 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_550 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_551 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_552 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_553 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_554 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_557 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_558 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_559 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_560 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_561 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[21] connect _WIRE_2[0], _T_521 connect _WIRE_2[1], _T_527 connect _WIRE_2[2], _T_533 connect _WIRE_2[3], _T_539 connect _WIRE_2[4], _T_545 connect _WIRE_2[5], _T_546 connect _WIRE_2[6], _T_547 connect _WIRE_2[7], _T_548 connect _WIRE_2[8], _T_549 connect _WIRE_2[9], _T_550 connect _WIRE_2[10], _T_551 connect _WIRE_2[11], _T_552 connect _WIRE_2[12], _T_553 connect _WIRE_2[13], _T_554 connect _WIRE_2[14], _T_555 connect _WIRE_2[15], _T_556 connect _WIRE_2[16], _T_557 connect _WIRE_2[17], _T_558 connect _WIRE_2[18], _T_559 connect _WIRE_2[19], _T_560 connect _WIRE_2[20], _T_561 node _T_562 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_563 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_564 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_565 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_566 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_567 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_568 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_569 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_570 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_572 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_573 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_574 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_575 = mux(_WIRE_2[5], _T_562, UInt<1>(0h0)) node _T_576 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_577 = mux(_WIRE_2[7], _T_563, UInt<1>(0h0)) node _T_578 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_579 = mux(_WIRE_2[9], _T_564, UInt<1>(0h0)) node _T_580 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_581 = mux(_WIRE_2[11], _T_565, UInt<1>(0h0)) node _T_582 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_583 = mux(_WIRE_2[13], _T_566, UInt<1>(0h0)) node _T_584 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_585 = mux(_WIRE_2[15], _T_567, UInt<1>(0h0)) node _T_586 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_587 = mux(_WIRE_2[17], _T_568, UInt<1>(0h0)) node _T_588 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_589 = mux(_WIRE_2[19], _T_569, UInt<1>(0h0)) node _T_590 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_591 = or(_T_570, _T_571) node _T_592 = or(_T_591, _T_572) node _T_593 = or(_T_592, _T_573) node _T_594 = or(_T_593, _T_574) node _T_595 = or(_T_594, _T_575) node _T_596 = or(_T_595, _T_576) node _T_597 = or(_T_596, _T_577) node _T_598 = or(_T_597, _T_578) node _T_599 = or(_T_598, _T_579) node _T_600 = or(_T_599, _T_580) node _T_601 = or(_T_600, _T_581) node _T_602 = or(_T_601, _T_582) node _T_603 = or(_T_602, _T_583) node _T_604 = or(_T_603, _T_584) node _T_605 = or(_T_604, _T_585) node _T_606 = or(_T_605, _T_586) node _T_607 = or(_T_606, _T_587) node _T_608 = or(_T_607, _T_588) node _T_609 = or(_T_608, _T_589) node _T_610 = or(_T_609, _T_590) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_610 node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_613 = and(_T_611, _T_612) node _T_614 = or(UInt<1>(0h0), _T_613) node _T_615 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<17>(0h100c0))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<29>(0h100000c0))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = or(_T_619, _T_624) node _T_626 = and(_T_614, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = and(_WIRE_3, _T_627) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_628, UInt<1>(0h1), "") : assert_11 node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(source_ok, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_635 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_635, UInt<1>(0h1), "") : assert_13 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_642 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_642, UInt<1>(0h1), "") : assert_15 node _T_646 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_646, UInt<1>(0h1), "") : assert_16 node _T_650 = not(io.in.a.bits.mask) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_651, UInt<1>(0h1), "") : assert_17 node _T_655 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_655, UInt<1>(0h1), "") : assert_18 node _T_659 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_659 : node _T_660 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_661 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_662 = and(_T_660, _T_661) node _T_663 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_20) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_670 = shr(io.in.a.bits.source, 2) node _T_671 = eq(_T_670, UInt<1>(0h1)) node _T_672 = leq(UInt<1>(0h0), uncommonBits_21) node _T_673 = and(_T_671, _T_672) node _T_674 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_675 = and(_T_673, _T_674) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_676 = shr(io.in.a.bits.source, 2) node _T_677 = eq(_T_676, UInt<2>(0h2)) node _T_678 = leq(UInt<1>(0h0), uncommonBits_22) node _T_679 = and(_T_677, _T_678) node _T_680 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_681 = and(_T_679, _T_680) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<2>(0h3)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_23) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_702 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_703 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_704 = or(_T_663, _T_669) node _T_705 = or(_T_704, _T_675) node _T_706 = or(_T_705, _T_681) node _T_707 = or(_T_706, _T_687) node _T_708 = or(_T_707, _T_688) node _T_709 = or(_T_708, _T_689) node _T_710 = or(_T_709, _T_690) node _T_711 = or(_T_710, _T_691) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_693) node _T_714 = or(_T_713, _T_694) node _T_715 = or(_T_714, _T_695) node _T_716 = or(_T_715, _T_696) node _T_717 = or(_T_716, _T_697) node _T_718 = or(_T_717, _T_698) node _T_719 = or(_T_718, _T_699) node _T_720 = or(_T_719, _T_700) node _T_721 = or(_T_720, _T_701) node _T_722 = or(_T_721, _T_702) node _T_723 = or(_T_722, _T_703) node _T_724 = and(_T_662, _T_723) node _T_725 = or(UInt<1>(0h0), _T_724) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_725, UInt<1>(0h1), "") : assert_19 node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<17>(0h100c0))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h100000c0))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_737, _T_742) node _T_744 = and(_T_732, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_745, UInt<1>(0h1), "") : assert_20 node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(source_ok, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(is_aligned, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_755 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_755, UInt<1>(0h1), "") : assert_23 node _T_759 = eq(io.in.a.bits.mask, mask) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_759, UInt<1>(0h1), "") : assert_24 node _T_763 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_763, UInt<1>(0h1), "") : assert_25 node _T_767 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_767 : node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_770 = and(_T_768, _T_769) node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_24) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_25) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_26) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_27) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_806 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_809 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_810 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_811 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_812 = or(_T_771, _T_777) node _T_813 = or(_T_812, _T_783) node _T_814 = or(_T_813, _T_789) node _T_815 = or(_T_814, _T_795) node _T_816 = or(_T_815, _T_796) node _T_817 = or(_T_816, _T_797) node _T_818 = or(_T_817, _T_798) node _T_819 = or(_T_818, _T_799) node _T_820 = or(_T_819, _T_800) node _T_821 = or(_T_820, _T_801) node _T_822 = or(_T_821, _T_802) node _T_823 = or(_T_822, _T_803) node _T_824 = or(_T_823, _T_804) node _T_825 = or(_T_824, _T_805) node _T_826 = or(_T_825, _T_806) node _T_827 = or(_T_826, _T_807) node _T_828 = or(_T_827, _T_808) node _T_829 = or(_T_828, _T_809) node _T_830 = or(_T_829, _T_810) node _T_831 = or(_T_830, _T_811) node _T_832 = and(_T_770, _T_831) node _T_833 = or(UInt<1>(0h0), _T_832) node _T_834 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_835 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_836 = and(_T_834, _T_835) node _T_837 = or(UInt<1>(0h0), _T_836) node _T_838 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<17>(0h100c0))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<29>(0h100000c0))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = or(_T_842, _T_847) node _T_849 = and(_T_837, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = and(_T_833, _T_850) node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(_T_851, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_851, UInt<1>(0h1), "") : assert_26 node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(source_ok, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(is_aligned, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_861 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_861, UInt<1>(0h1), "") : assert_29 node _T_865 = eq(io.in.a.bits.mask, mask) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_865, UInt<1>(0h1), "") : assert_30 node _T_869 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_869 : node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_872 = and(_T_870, _T_871) node _T_873 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<1>(0h0)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_28) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h1)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_29) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_886 = shr(io.in.a.bits.source, 2) node _T_887 = eq(_T_886, UInt<2>(0h2)) node _T_888 = leq(UInt<1>(0h0), uncommonBits_30) node _T_889 = and(_T_887, _T_888) node _T_890 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_891 = and(_T_889, _T_890) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_892 = shr(io.in.a.bits.source, 2) node _T_893 = eq(_T_892, UInt<2>(0h3)) node _T_894 = leq(UInt<1>(0h0), uncommonBits_31) node _T_895 = and(_T_893, _T_894) node _T_896 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_897 = and(_T_895, _T_896) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_902 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_903 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_904 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_911 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_912 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_913 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_914 = or(_T_873, _T_879) node _T_915 = or(_T_914, _T_885) node _T_916 = or(_T_915, _T_891) node _T_917 = or(_T_916, _T_897) node _T_918 = or(_T_917, _T_898) node _T_919 = or(_T_918, _T_899) node _T_920 = or(_T_919, _T_900) node _T_921 = or(_T_920, _T_901) node _T_922 = or(_T_921, _T_902) node _T_923 = or(_T_922, _T_903) node _T_924 = or(_T_923, _T_904) node _T_925 = or(_T_924, _T_905) node _T_926 = or(_T_925, _T_906) node _T_927 = or(_T_926, _T_907) node _T_928 = or(_T_927, _T_908) node _T_929 = or(_T_928, _T_909) node _T_930 = or(_T_929, _T_910) node _T_931 = or(_T_930, _T_911) node _T_932 = or(_T_931, _T_912) node _T_933 = or(_T_932, _T_913) node _T_934 = and(_T_872, _T_933) node _T_935 = or(UInt<1>(0h0), _T_934) node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_938 = and(_T_936, _T_937) node _T_939 = or(UInt<1>(0h0), _T_938) node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<17>(0h100c0))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<29>(0h100000c0))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_944, _T_949) node _T_951 = and(_T_939, _T_950) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = and(_T_935, _T_952) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_953, UInt<1>(0h1), "") : assert_31 node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(source_ok, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(is_aligned, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_963 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_963, UInt<1>(0h1), "") : assert_34 node _T_967 = not(mask) node _T_968 = and(io.in.a.bits.mask, _T_967) node _T_969 = eq(_T_968, UInt<1>(0h0)) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_969, UInt<1>(0h1), "") : assert_35 node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_973 : node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_976 = and(_T_974, _T_975) node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<1>(0h0)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_32) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<1>(0h1)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_33) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_990 = shr(io.in.a.bits.source, 2) node _T_991 = eq(_T_990, UInt<2>(0h2)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_34) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<2>(0h3)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_35) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1018 = or(_T_977, _T_983) node _T_1019 = or(_T_1018, _T_989) node _T_1020 = or(_T_1019, _T_995) node _T_1021 = or(_T_1020, _T_1001) node _T_1022 = or(_T_1021, _T_1002) node _T_1023 = or(_T_1022, _T_1003) node _T_1024 = or(_T_1023, _T_1004) node _T_1025 = or(_T_1024, _T_1005) node _T_1026 = or(_T_1025, _T_1006) node _T_1027 = or(_T_1026, _T_1007) node _T_1028 = or(_T_1027, _T_1008) node _T_1029 = or(_T_1028, _T_1009) node _T_1030 = or(_T_1029, _T_1010) node _T_1031 = or(_T_1030, _T_1011) node _T_1032 = or(_T_1031, _T_1012) node _T_1033 = or(_T_1032, _T_1013) node _T_1034 = or(_T_1033, _T_1014) node _T_1035 = or(_T_1034, _T_1015) node _T_1036 = or(_T_1035, _T_1016) node _T_1037 = or(_T_1036, _T_1017) node _T_1038 = and(_T_976, _T_1037) node _T_1039 = or(UInt<1>(0h0), _T_1038) node _T_1040 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1041 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = or(UInt<1>(0h0), _T_1042) node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<17>(0h100c0))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<29>(0h100000c0))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = or(_T_1048, _T_1053) node _T_1055 = and(_T_1043, _T_1054) node _T_1056 = or(UInt<1>(0h0), _T_1055) node _T_1057 = and(_T_1039, _T_1056) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_36 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(source_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(is_aligned, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_39 node _T_1071 = eq(io.in.a.bits.mask, mask) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_40 node _T_1075 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1075 : node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1080 = shr(io.in.a.bits.source, 2) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) node _T_1082 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1085 = and(_T_1083, _T_1084) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1086 = shr(io.in.a.bits.source, 2) node _T_1087 = eq(_T_1086, UInt<1>(0h1)) node _T_1088 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1091 = and(_T_1089, _T_1090) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1092 = shr(io.in.a.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1098 = shr(io.in.a.bits.source, 2) node _T_1099 = eq(_T_1098, UInt<2>(0h3)) node _T_1100 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1103 = and(_T_1101, _T_1102) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1120 = or(_T_1079, _T_1085) node _T_1121 = or(_T_1120, _T_1091) node _T_1122 = or(_T_1121, _T_1097) node _T_1123 = or(_T_1122, _T_1103) node _T_1124 = or(_T_1123, _T_1104) node _T_1125 = or(_T_1124, _T_1105) node _T_1126 = or(_T_1125, _T_1106) node _T_1127 = or(_T_1126, _T_1107) node _T_1128 = or(_T_1127, _T_1108) node _T_1129 = or(_T_1128, _T_1109) node _T_1130 = or(_T_1129, _T_1110) node _T_1131 = or(_T_1130, _T_1111) node _T_1132 = or(_T_1131, _T_1112) node _T_1133 = or(_T_1132, _T_1113) node _T_1134 = or(_T_1133, _T_1114) node _T_1135 = or(_T_1134, _T_1115) node _T_1136 = or(_T_1135, _T_1116) node _T_1137 = or(_T_1136, _T_1117) node _T_1138 = or(_T_1137, _T_1118) node _T_1139 = or(_T_1138, _T_1119) node _T_1140 = and(_T_1078, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1140) node _T_1142 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1143 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _T_1145 = or(UInt<1>(0h0), _T_1144) node _T_1146 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1147 = cvt(_T_1146) node _T_1148 = and(_T_1147, asSInt(UInt<17>(0h100c0))) node _T_1149 = asSInt(_T_1148) node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0))) node _T_1151 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1152 = cvt(_T_1151) node _T_1153 = and(_T_1152, asSInt(UInt<29>(0h100000c0))) node _T_1154 = asSInt(_T_1153) node _T_1155 = eq(_T_1154, asSInt(UInt<1>(0h0))) node _T_1156 = or(_T_1150, _T_1155) node _T_1157 = and(_T_1145, _T_1156) node _T_1158 = or(UInt<1>(0h0), _T_1157) node _T_1159 = and(_T_1141, _T_1158) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_41 node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(source_ok, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(is_aligned, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1169 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_44 node _T_1173 = eq(io.in.a.bits.mask, mask) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_45 node _T_1177 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1177 : node _T_1178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1179 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1182 = shr(io.in.a.bits.source, 2) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) node _T_1184 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1185 = and(_T_1183, _T_1184) node _T_1186 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1187 = and(_T_1185, _T_1186) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1188 = shr(io.in.a.bits.source, 2) node _T_1189 = eq(_T_1188, UInt<1>(0h1)) node _T_1190 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1193 = and(_T_1191, _T_1192) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<2>(0h2)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<2>(0h3)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1207 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1208 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1209 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1210 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1211 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1212 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1213 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1214 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1215 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1216 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1219 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1220 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1221 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1222 = or(_T_1181, _T_1187) node _T_1223 = or(_T_1222, _T_1193) node _T_1224 = or(_T_1223, _T_1199) node _T_1225 = or(_T_1224, _T_1205) node _T_1226 = or(_T_1225, _T_1206) node _T_1227 = or(_T_1226, _T_1207) node _T_1228 = or(_T_1227, _T_1208) node _T_1229 = or(_T_1228, _T_1209) node _T_1230 = or(_T_1229, _T_1210) node _T_1231 = or(_T_1230, _T_1211) node _T_1232 = or(_T_1231, _T_1212) node _T_1233 = or(_T_1232, _T_1213) node _T_1234 = or(_T_1233, _T_1214) node _T_1235 = or(_T_1234, _T_1215) node _T_1236 = or(_T_1235, _T_1216) node _T_1237 = or(_T_1236, _T_1217) node _T_1238 = or(_T_1237, _T_1218) node _T_1239 = or(_T_1238, _T_1219) node _T_1240 = or(_T_1239, _T_1220) node _T_1241 = or(_T_1240, _T_1221) node _T_1242 = and(_T_1180, _T_1241) node _T_1243 = or(UInt<1>(0h0), _T_1242) node _T_1244 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1245 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1246 = and(_T_1244, _T_1245) node _T_1247 = or(UInt<1>(0h0), _T_1246) node _T_1248 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<17>(0h100c0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<29>(0h100000c0))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = or(_T_1252, _T_1257) node _T_1259 = and(_T_1247, _T_1258) node _T_1260 = or(UInt<1>(0h0), _T_1259) node _T_1261 = and(_T_1243, _T_1260) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_46 node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(source_ok, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(is_aligned, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1271 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_49 node _T_1275 = eq(io.in.a.bits.mask, mask) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_50 node _T_1279 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1283 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_52 node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[21] connect _source_ok_WIRE_1[0], _source_ok_T_60 connect _source_ok_WIRE_1[1], _source_ok_T_66 connect _source_ok_WIRE_1[2], _source_ok_T_72 connect _source_ok_WIRE_1[3], _source_ok_T_78 connect _source_ok_WIRE_1[4], _source_ok_T_84 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_86 connect _source_ok_WIRE_1[7], _source_ok_T_87 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 connect _source_ok_WIRE_1[11], _source_ok_T_91 connect _source_ok_WIRE_1[12], _source_ok_T_92 connect _source_ok_WIRE_1[13], _source_ok_T_93 connect _source_ok_WIRE_1[14], _source_ok_T_94 connect _source_ok_WIRE_1[15], _source_ok_T_95 connect _source_ok_WIRE_1[16], _source_ok_T_96 connect _source_ok_WIRE_1[17], _source_ok_T_97 connect _source_ok_WIRE_1[18], _source_ok_T_98 connect _source_ok_WIRE_1[19], _source_ok_T_99 connect _source_ok_WIRE_1[20], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[11]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[12]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[13]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[14]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[15]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[16]) node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[17]) node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[18]) node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[19]) node source_ok_1 = or(_source_ok_T_119, _source_ok_WIRE_1[20]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1287 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1287 : node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(source_ok_1, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1291 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_54 node _T_1295 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_55 node _T_1299 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_56 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_57 node _T_1307 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1307 : node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok_1, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(sink_ok, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1314 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_60 node _T_1318 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_61 node _T_1322 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_62 node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_63 node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1331 = or(UInt<1>(0h1), _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_64 node _T_1335 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1335 : node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(source_ok_1, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(sink_ok, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1342 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_67 node _T_1346 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(_T_1346, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1346, UInt<1>(0h1), "") : assert_68 node _T_1350 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_69 node _T_1354 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1355 = or(_T_1354, io.in.d.bits.corrupt) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_70 node _T_1359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1360 = or(UInt<1>(0h1), _T_1359) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_71 node _T_1364 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1364 : node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(source_ok_1, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1368 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_73 node _T_1372 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_74 node _T_1376 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1377 = or(UInt<1>(0h1), _T_1376) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_75 node _T_1381 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1381 : node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(source_ok_1, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1385 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_77 node _T_1389 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1390 = or(_T_1389, io.in.d.bits.corrupt) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_78 node _T_1394 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1395 = or(UInt<1>(0h1), _T_1394) node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(_T_1395, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1395, UInt<1>(0h1), "") : assert_79 node _T_1399 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1399 : node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(source_ok_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_81 node _T_1407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_82 node _T_1411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1412 = or(UInt<1>(0h1), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1416 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_84 node _T_1420 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) node _T_1422 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1423 = cvt(_T_1422) node _T_1424 = and(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = asSInt(_T_1424) node _T_1426 = eq(_T_1425, asSInt(UInt<1>(0h0))) node _T_1427 = or(_T_1421, _T_1426) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1428 = shr(io.in.b.bits.source, 2) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) node _T_1435 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<1>(0h0))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1434, _T_1439) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1441 = shr(io.in.b.bits.source, 2) node _T_1442 = eq(_T_1441, UInt<1>(0h1)) node _T_1443 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1444 = and(_T_1442, _T_1443) node _T_1445 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1446 = and(_T_1444, _T_1445) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) node _T_1448 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = or(_T_1447, _T_1452) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1454 = shr(io.in.b.bits.source, 2) node _T_1455 = eq(_T_1454, UInt<2>(0h2)) node _T_1456 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1457 = and(_T_1455, _T_1456) node _T_1458 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) node _T_1461 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = or(_T_1460, _T_1465) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1467 = shr(io.in.b.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<2>(0h3)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) node _T_1474 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = or(_T_1473, _T_1478) node _T_1480 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) node _T_1482 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<1>(0h0))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = or(_T_1481, _T_1486) node _T_1488 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) node _T_1490 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1491 = cvt(_T_1490) node _T_1492 = and(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = asSInt(_T_1492) node _T_1494 = eq(_T_1493, asSInt(UInt<1>(0h0))) node _T_1495 = or(_T_1489, _T_1494) node _T_1496 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) node _T_1498 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = or(_T_1497, _T_1502) node _T_1504 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) node _T_1506 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<1>(0h0))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = or(_T_1505, _T_1510) node _T_1512 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) node _T_1514 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1515 = cvt(_T_1514) node _T_1516 = and(_T_1515, asSInt(UInt<1>(0h0))) node _T_1517 = asSInt(_T_1516) node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0))) node _T_1519 = or(_T_1513, _T_1518) node _T_1520 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1523 = cvt(_T_1522) node _T_1524 = and(_T_1523, asSInt(UInt<1>(0h0))) node _T_1525 = asSInt(_T_1524) node _T_1526 = eq(_T_1525, asSInt(UInt<1>(0h0))) node _T_1527 = or(_T_1521, _T_1526) node _T_1528 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) node _T_1530 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1531 = cvt(_T_1530) node _T_1532 = and(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = asSInt(_T_1532) node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0))) node _T_1535 = or(_T_1529, _T_1534) node _T_1536 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) node _T_1538 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1537, _T_1542) node _T_1544 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) node _T_1546 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1547 = cvt(_T_1546) node _T_1548 = and(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = asSInt(_T_1548) node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0))) node _T_1551 = or(_T_1545, _T_1550) node _T_1552 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) node _T_1554 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<1>(0h0))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = or(_T_1553, _T_1558) node _T_1560 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) node _T_1562 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1563 = cvt(_T_1562) node _T_1564 = and(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = asSInt(_T_1564) node _T_1566 = eq(_T_1565, asSInt(UInt<1>(0h0))) node _T_1567 = or(_T_1561, _T_1566) node _T_1568 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) node _T_1570 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1571 = cvt(_T_1570) node _T_1572 = and(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = asSInt(_T_1572) node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0))) node _T_1575 = or(_T_1569, _T_1574) node _T_1576 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) node _T_1578 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = or(_T_1577, _T_1582) node _T_1584 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) node _T_1586 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1587 = cvt(_T_1586) node _T_1588 = and(_T_1587, asSInt(UInt<1>(0h0))) node _T_1589 = asSInt(_T_1588) node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0))) node _T_1591 = or(_T_1585, _T_1590) node _T_1592 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) node _T_1594 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1595 = cvt(_T_1594) node _T_1596 = and(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = asSInt(_T_1596) node _T_1598 = eq(_T_1597, asSInt(UInt<1>(0h0))) node _T_1599 = or(_T_1593, _T_1598) node _T_1600 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) node _T_1602 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<1>(0h0))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = or(_T_1601, _T_1606) node _T_1608 = and(_T_1427, _T_1440) node _T_1609 = and(_T_1608, _T_1453) node _T_1610 = and(_T_1609, _T_1466) node _T_1611 = and(_T_1610, _T_1479) node _T_1612 = and(_T_1611, _T_1487) node _T_1613 = and(_T_1612, _T_1495) node _T_1614 = and(_T_1613, _T_1503) node _T_1615 = and(_T_1614, _T_1511) node _T_1616 = and(_T_1615, _T_1519) node _T_1617 = and(_T_1616, _T_1527) node _T_1618 = and(_T_1617, _T_1535) node _T_1619 = and(_T_1618, _T_1543) node _T_1620 = and(_T_1619, _T_1551) node _T_1621 = and(_T_1620, _T_1559) node _T_1622 = and(_T_1621, _T_1567) node _T_1623 = and(_T_1622, _T_1575) node _T_1624 = and(_T_1623, _T_1583) node _T_1625 = and(_T_1624, _T_1591) node _T_1626 = and(_T_1625, _T_1599) node _T_1627 = and(_T_1626, _T_1607) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _legal_source_T_33 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_34 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_35 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_36 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_37 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_39 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_40 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[21] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 connect _legal_source_WIRE[13], _legal_source_T_33 connect _legal_source_WIRE[14], _legal_source_T_34 connect _legal_source_WIRE[15], _legal_source_T_35 connect _legal_source_WIRE[16], _legal_source_T_36 connect _legal_source_WIRE[17], _legal_source_T_37 connect _legal_source_WIRE[18], _legal_source_T_38 connect _legal_source_WIRE[19], _legal_source_T_39 connect _legal_source_WIRE[20], _legal_source_T_40 node _legal_source_T_41 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_46 = mux(_legal_source_WIRE[5], UInt<6>(0h3c), UInt<1>(0h0)) node _legal_source_T_47 = mux(_legal_source_WIRE[6], UInt<6>(0h3e), UInt<1>(0h0)) node _legal_source_T_48 = mux(_legal_source_WIRE[7], UInt<6>(0h38), UInt<1>(0h0)) node _legal_source_T_49 = mux(_legal_source_WIRE[8], UInt<6>(0h3a), UInt<1>(0h0)) node _legal_source_T_50 = mux(_legal_source_WIRE[9], UInt<6>(0h34), UInt<1>(0h0)) node _legal_source_T_51 = mux(_legal_source_WIRE[10], UInt<6>(0h36), UInt<1>(0h0)) node _legal_source_T_52 = mux(_legal_source_WIRE[11], UInt<6>(0h30), UInt<1>(0h0)) node _legal_source_T_53 = mux(_legal_source_WIRE[12], UInt<6>(0h32), UInt<1>(0h0)) node _legal_source_T_54 = mux(_legal_source_WIRE[13], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_55 = mux(_legal_source_WIRE[14], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_56 = mux(_legal_source_WIRE[15], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_57 = mux(_legal_source_WIRE[16], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_58 = mux(_legal_source_WIRE[17], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_59 = mux(_legal_source_WIRE[18], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_60 = mux(_legal_source_WIRE[19], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_61 = mux(_legal_source_WIRE[20], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_62 = or(_legal_source_T_41, _legal_source_T_42) node _legal_source_T_63 = or(_legal_source_T_62, _legal_source_T_43) node _legal_source_T_64 = or(_legal_source_T_63, _legal_source_T_44) node _legal_source_T_65 = or(_legal_source_T_64, _legal_source_T_45) node _legal_source_T_66 = or(_legal_source_T_65, _legal_source_T_46) node _legal_source_T_67 = or(_legal_source_T_66, _legal_source_T_47) node _legal_source_T_68 = or(_legal_source_T_67, _legal_source_T_48) node _legal_source_T_69 = or(_legal_source_T_68, _legal_source_T_49) node _legal_source_T_70 = or(_legal_source_T_69, _legal_source_T_50) node _legal_source_T_71 = or(_legal_source_T_70, _legal_source_T_51) node _legal_source_T_72 = or(_legal_source_T_71, _legal_source_T_52) node _legal_source_T_73 = or(_legal_source_T_72, _legal_source_T_53) node _legal_source_T_74 = or(_legal_source_T_73, _legal_source_T_54) node _legal_source_T_75 = or(_legal_source_T_74, _legal_source_T_55) node _legal_source_T_76 = or(_legal_source_T_75, _legal_source_T_56) node _legal_source_T_77 = or(_legal_source_T_76, _legal_source_T_57) node _legal_source_T_78 = or(_legal_source_T_77, _legal_source_T_58) node _legal_source_T_79 = or(_legal_source_T_78, _legal_source_T_59) node _legal_source_T_80 = or(_legal_source_T_79, _legal_source_T_60) node _legal_source_T_81 = or(_legal_source_T_80, _legal_source_T_61) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_81 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1631 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1631 : node _T_1632 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1633 = shr(io.in.b.bits.source, 2) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) node _T_1635 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1636 = and(_T_1634, _T_1635) node _T_1637 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1638 = and(_T_1636, _T_1637) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1639 = shr(io.in.b.bits.source, 2) node _T_1640 = eq(_T_1639, UInt<1>(0h1)) node _T_1641 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1642 = and(_T_1640, _T_1641) node _T_1643 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1644 = and(_T_1642, _T_1643) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1645 = shr(io.in.b.bits.source, 2) node _T_1646 = eq(_T_1645, UInt<2>(0h2)) node _T_1647 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1648 = and(_T_1646, _T_1647) node _T_1649 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1650 = and(_T_1648, _T_1649) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1651 = shr(io.in.b.bits.source, 2) node _T_1652 = eq(_T_1651, UInt<2>(0h3)) node _T_1653 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1654 = and(_T_1652, _T_1653) node _T_1655 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1656 = and(_T_1654, _T_1655) node _T_1657 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1658 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1659 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1660 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1661 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1662 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1663 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_1664 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_1665 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1666 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1667 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1669 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1670 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1671 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1672 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[21] connect _WIRE_4[0], _T_1632 connect _WIRE_4[1], _T_1638 connect _WIRE_4[2], _T_1644 connect _WIRE_4[3], _T_1650 connect _WIRE_4[4], _T_1656 connect _WIRE_4[5], _T_1657 connect _WIRE_4[6], _T_1658 connect _WIRE_4[7], _T_1659 connect _WIRE_4[8], _T_1660 connect _WIRE_4[9], _T_1661 connect _WIRE_4[10], _T_1662 connect _WIRE_4[11], _T_1663 connect _WIRE_4[12], _T_1664 connect _WIRE_4[13], _T_1665 connect _WIRE_4[14], _T_1666 connect _WIRE_4[15], _T_1667 connect _WIRE_4[16], _T_1668 connect _WIRE_4[17], _T_1669 connect _WIRE_4[18], _T_1670 connect _WIRE_4[19], _T_1671 connect _WIRE_4[20], _T_1672 node _T_1673 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1674 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1675 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1676 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1677 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1678 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1679 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1680 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1681 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1682 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1683 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1684 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1685 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1686 = mux(_WIRE_4[5], _T_1673, UInt<1>(0h0)) node _T_1687 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1688 = mux(_WIRE_4[7], _T_1674, UInt<1>(0h0)) node _T_1689 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1690 = mux(_WIRE_4[9], _T_1675, UInt<1>(0h0)) node _T_1691 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1692 = mux(_WIRE_4[11], _T_1676, UInt<1>(0h0)) node _T_1693 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1694 = mux(_WIRE_4[13], _T_1677, UInt<1>(0h0)) node _T_1695 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_1696 = mux(_WIRE_4[15], _T_1678, UInt<1>(0h0)) node _T_1697 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1698 = mux(_WIRE_4[17], _T_1679, UInt<1>(0h0)) node _T_1699 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1700 = mux(_WIRE_4[19], _T_1680, UInt<1>(0h0)) node _T_1701 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_1702 = or(_T_1681, _T_1682) node _T_1703 = or(_T_1702, _T_1683) node _T_1704 = or(_T_1703, _T_1684) node _T_1705 = or(_T_1704, _T_1685) node _T_1706 = or(_T_1705, _T_1686) node _T_1707 = or(_T_1706, _T_1687) node _T_1708 = or(_T_1707, _T_1688) node _T_1709 = or(_T_1708, _T_1689) node _T_1710 = or(_T_1709, _T_1690) node _T_1711 = or(_T_1710, _T_1691) node _T_1712 = or(_T_1711, _T_1692) node _T_1713 = or(_T_1712, _T_1693) node _T_1714 = or(_T_1713, _T_1694) node _T_1715 = or(_T_1714, _T_1695) node _T_1716 = or(_T_1715, _T_1696) node _T_1717 = or(_T_1716, _T_1697) node _T_1718 = or(_T_1717, _T_1698) node _T_1719 = or(_T_1718, _T_1699) node _T_1720 = or(_T_1719, _T_1700) node _T_1721 = or(_T_1720, _T_1701) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1721 node _T_1722 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1723 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1724 = and(_T_1722, _T_1723) node _T_1725 = or(UInt<1>(0h0), _T_1724) node _T_1726 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1727 = cvt(_T_1726) node _T_1728 = and(_T_1727, asSInt(UInt<17>(0h100c0))) node _T_1729 = asSInt(_T_1728) node _T_1730 = eq(_T_1729, asSInt(UInt<1>(0h0))) node _T_1731 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1732 = cvt(_T_1731) node _T_1733 = and(_T_1732, asSInt(UInt<29>(0h100000c0))) node _T_1734 = asSInt(_T_1733) node _T_1735 = eq(_T_1734, asSInt(UInt<1>(0h0))) node _T_1736 = or(_T_1730, _T_1735) node _T_1737 = and(_T_1725, _T_1736) node _T_1738 = or(UInt<1>(0h0), _T_1737) node _T_1739 = and(_WIRE_5, _T_1738) node _T_1740 = asUInt(reset) node _T_1741 = eq(_T_1740, UInt<1>(0h0)) when _T_1741 : node _T_1742 = eq(_T_1739, UInt<1>(0h0)) when _T_1742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1739, UInt<1>(0h1), "") : assert_86 node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(address_ok, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1746 = asUInt(reset) node _T_1747 = eq(_T_1746, UInt<1>(0h0)) when _T_1747 : node _T_1748 = eq(legal_source, UInt<1>(0h0)) when _T_1748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1752 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_90 node _T_1756 = eq(io.in.b.bits.mask, mask_1) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_91 node _T_1760 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1761 = asUInt(reset) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) when _T_1762 : node _T_1763 = eq(_T_1760, UInt<1>(0h0)) when _T_1763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1760, UInt<1>(0h1), "") : assert_92 node _T_1764 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1764 : node _T_1765 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1766 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1767 = and(_T_1765, _T_1766) node _T_1768 = or(UInt<1>(0h0), _T_1767) node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1770 = cvt(_T_1769) node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h100c0))) node _T_1772 = asSInt(_T_1771) node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0))) node _T_1774 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1775 = cvt(_T_1774) node _T_1776 = and(_T_1775, asSInt(UInt<29>(0h100000c0))) node _T_1777 = asSInt(_T_1776) node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = or(_T_1773, _T_1778) node _T_1780 = and(_T_1768, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = and(UInt<1>(0h0), _T_1781) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_93 node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(address_ok, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1789 = asUInt(reset) node _T_1790 = eq(_T_1789, UInt<1>(0h0)) when _T_1790 : node _T_1791 = eq(legal_source, UInt<1>(0h0)) when _T_1791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1795 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_97 node _T_1799 = eq(io.in.b.bits.mask, mask_1) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_98 node _T_1803 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(_T_1803, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1803, UInt<1>(0h1), "") : assert_99 node _T_1807 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1807 : node _T_1808 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1809 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1810 = and(_T_1808, _T_1809) node _T_1811 = or(UInt<1>(0h0), _T_1810) node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h100c0))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<29>(0h100000c0))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = or(_T_1816, _T_1821) node _T_1823 = and(_T_1811, _T_1822) node _T_1824 = or(UInt<1>(0h0), _T_1823) node _T_1825 = and(UInt<1>(0h0), _T_1824) node _T_1826 = asUInt(reset) node _T_1827 = eq(_T_1826, UInt<1>(0h0)) when _T_1827 : node _T_1828 = eq(_T_1825, UInt<1>(0h0)) when _T_1828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1825, UInt<1>(0h1), "") : assert_100 node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(address_ok, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1832 = asUInt(reset) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) when _T_1833 : node _T_1834 = eq(legal_source, UInt<1>(0h0)) when _T_1834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1838 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_104 node _T_1842 = eq(io.in.b.bits.mask, mask_1) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_105 node _T_1846 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1846 : node _T_1847 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1848 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = or(UInt<1>(0h0), _T_1849) node _T_1851 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1852 = cvt(_T_1851) node _T_1853 = and(_T_1852, asSInt(UInt<17>(0h100c0))) node _T_1854 = asSInt(_T_1853) node _T_1855 = eq(_T_1854, asSInt(UInt<1>(0h0))) node _T_1856 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1857 = cvt(_T_1856) node _T_1858 = and(_T_1857, asSInt(UInt<29>(0h100000c0))) node _T_1859 = asSInt(_T_1858) node _T_1860 = eq(_T_1859, asSInt(UInt<1>(0h0))) node _T_1861 = or(_T_1855, _T_1860) node _T_1862 = and(_T_1850, _T_1861) node _T_1863 = or(UInt<1>(0h0), _T_1862) node _T_1864 = and(UInt<1>(0h0), _T_1863) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_106 node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(address_ok, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(legal_source, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1874 = asUInt(reset) node _T_1875 = eq(_T_1874, UInt<1>(0h0)) when _T_1875 : node _T_1876 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1877 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1878 = asUInt(reset) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) when _T_1879 : node _T_1880 = eq(_T_1877, UInt<1>(0h0)) when _T_1880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1877, UInt<1>(0h1), "") : assert_110 node _T_1881 = not(mask_1) node _T_1882 = and(io.in.b.bits.mask, _T_1881) node _T_1883 = eq(_T_1882, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_111 node _T_1887 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1887 : node _T_1888 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1889 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1890 = and(_T_1888, _T_1889) node _T_1891 = or(UInt<1>(0h0), _T_1890) node _T_1892 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1893 = cvt(_T_1892) node _T_1894 = and(_T_1893, asSInt(UInt<17>(0h100c0))) node _T_1895 = asSInt(_T_1894) node _T_1896 = eq(_T_1895, asSInt(UInt<1>(0h0))) node _T_1897 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1898 = cvt(_T_1897) node _T_1899 = and(_T_1898, asSInt(UInt<29>(0h100000c0))) node _T_1900 = asSInt(_T_1899) node _T_1901 = eq(_T_1900, asSInt(UInt<1>(0h0))) node _T_1902 = or(_T_1896, _T_1901) node _T_1903 = and(_T_1891, _T_1902) node _T_1904 = or(UInt<1>(0h0), _T_1903) node _T_1905 = and(UInt<1>(0h0), _T_1904) node _T_1906 = asUInt(reset) node _T_1907 = eq(_T_1906, UInt<1>(0h0)) when _T_1907 : node _T_1908 = eq(_T_1905, UInt<1>(0h0)) when _T_1908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1905, UInt<1>(0h1), "") : assert_112 node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(address_ok, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1912 = asUInt(reset) node _T_1913 = eq(_T_1912, UInt<1>(0h0)) when _T_1913 : node _T_1914 = eq(legal_source, UInt<1>(0h0)) when _T_1914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1918 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(_T_1918, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1918, UInt<1>(0h1), "") : assert_116 node _T_1922 = eq(io.in.b.bits.mask, mask_1) node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(_T_1922, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1922, UInt<1>(0h1), "") : assert_117 node _T_1926 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1926 : node _T_1927 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1928 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1929 = and(_T_1927, _T_1928) node _T_1930 = or(UInt<1>(0h0), _T_1929) node _T_1931 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<17>(0h100c0))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h100000c0))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1935, _T_1940) node _T_1942 = and(_T_1930, _T_1941) node _T_1943 = or(UInt<1>(0h0), _T_1942) node _T_1944 = and(UInt<1>(0h0), _T_1943) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_118 node _T_1948 = asUInt(reset) node _T_1949 = eq(_T_1948, UInt<1>(0h0)) when _T_1949 : node _T_1950 = eq(address_ok, UInt<1>(0h0)) when _T_1950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1951 = asUInt(reset) node _T_1952 = eq(_T_1951, UInt<1>(0h0)) when _T_1952 : node _T_1953 = eq(legal_source, UInt<1>(0h0)) when _T_1953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1957 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_122 node _T_1961 = eq(io.in.b.bits.mask, mask_1) node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(_T_1961, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1961, UInt<1>(0h1), "") : assert_123 node _T_1965 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1965 : node _T_1966 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1967 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1968 = and(_T_1966, _T_1967) node _T_1969 = or(UInt<1>(0h0), _T_1968) node _T_1970 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<17>(0h100c0))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<29>(0h100000c0))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = or(_T_1974, _T_1979) node _T_1981 = and(_T_1969, _T_1980) node _T_1982 = or(UInt<1>(0h0), _T_1981) node _T_1983 = and(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_124 node _T_1987 = asUInt(reset) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) when _T_1988 : node _T_1989 = eq(address_ok, UInt<1>(0h0)) when _T_1989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(legal_source, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1993 = asUInt(reset) node _T_1994 = eq(_T_1993, UInt<1>(0h0)) when _T_1994 : node _T_1995 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1996 = eq(io.in.b.bits.mask, mask_1) node _T_1997 = asUInt(reset) node _T_1998 = eq(_T_1997, UInt<1>(0h0)) when _T_1998 : node _T_1999 = eq(_T_1996, UInt<1>(0h0)) when _T_1999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1996, UInt<1>(0h1), "") : assert_128 node _T_2000 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_2004 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_130 node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_121 = shr(io.in.c.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h0)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_127 = shr(io.in.c.bits.source, 2) node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h1)) node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129) node _source_ok_T_131 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_133 = shr(io.in.c.bits.source, 2) node _source_ok_T_134 = eq(_source_ok_T_133, UInt<2>(0h2)) node _source_ok_T_135 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_136 = and(_source_ok_T_134, _source_ok_T_135) node _source_ok_T_137 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_138 = and(_source_ok_T_136, _source_ok_T_137) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_139 = shr(io.in.c.bits.source, 2) node _source_ok_T_140 = eq(_source_ok_T_139, UInt<2>(0h3)) node _source_ok_T_141 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_142 = and(_source_ok_T_140, _source_ok_T_141) node _source_ok_T_143 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_144 = and(_source_ok_T_142, _source_ok_T_143) node _source_ok_T_145 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _source_ok_T_146 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _source_ok_T_147 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _source_ok_T_148 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _source_ok_T_149 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _source_ok_T_150 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _source_ok_T_151 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _source_ok_T_152 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _source_ok_T_153 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_154 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_155 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_156 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_159 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_160 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[21] connect _source_ok_WIRE_2[0], _source_ok_T_120 connect _source_ok_WIRE_2[1], _source_ok_T_126 connect _source_ok_WIRE_2[2], _source_ok_T_132 connect _source_ok_WIRE_2[3], _source_ok_T_138 connect _source_ok_WIRE_2[4], _source_ok_T_144 connect _source_ok_WIRE_2[5], _source_ok_T_145 connect _source_ok_WIRE_2[6], _source_ok_T_146 connect _source_ok_WIRE_2[7], _source_ok_T_147 connect _source_ok_WIRE_2[8], _source_ok_T_148 connect _source_ok_WIRE_2[9], _source_ok_T_149 connect _source_ok_WIRE_2[10], _source_ok_T_150 connect _source_ok_WIRE_2[11], _source_ok_T_151 connect _source_ok_WIRE_2[12], _source_ok_T_152 connect _source_ok_WIRE_2[13], _source_ok_T_153 connect _source_ok_WIRE_2[14], _source_ok_T_154 connect _source_ok_WIRE_2[15], _source_ok_T_155 connect _source_ok_WIRE_2[16], _source_ok_T_156 connect _source_ok_WIRE_2[17], _source_ok_T_157 connect _source_ok_WIRE_2[18], _source_ok_T_158 connect _source_ok_WIRE_2[19], _source_ok_T_159 connect _source_ok_WIRE_2[20], _source_ok_T_160 node _source_ok_T_161 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_162 = or(_source_ok_T_161, _source_ok_WIRE_2[2]) node _source_ok_T_163 = or(_source_ok_T_162, _source_ok_WIRE_2[3]) node _source_ok_T_164 = or(_source_ok_T_163, _source_ok_WIRE_2[4]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_2[5]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_2[6]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_2[7]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_2[8]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_2[9]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_2[10]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_2[11]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_2[12]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_2[13]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_2[14]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_2[15]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_2[16]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_2[17]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_2[18]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_2[19]) node source_ok_2 = or(_source_ok_T_179, _source_ok_WIRE_2[20]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_2008 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_2009 = eq(_T_2008, UInt<1>(0h0)) node _T_2010 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<1>(0h0))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_2009, _T_2014) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_2016 = shr(io.in.c.bits.source, 2) node _T_2017 = eq(_T_2016, UInt<1>(0h0)) node _T_2018 = leq(UInt<1>(0h0), uncommonBits_52) node _T_2019 = and(_T_2017, _T_2018) node _T_2020 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_2021 = and(_T_2019, _T_2020) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) node _T_2023 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2024 = cvt(_T_2023) node _T_2025 = and(_T_2024, asSInt(UInt<1>(0h0))) node _T_2026 = asSInt(_T_2025) node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0))) node _T_2028 = or(_T_2022, _T_2027) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_2029 = shr(io.in.c.bits.source, 2) node _T_2030 = eq(_T_2029, UInt<1>(0h1)) node _T_2031 = leq(UInt<1>(0h0), uncommonBits_53) node _T_2032 = and(_T_2030, _T_2031) node _T_2033 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_2034 = and(_T_2032, _T_2033) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) node _T_2036 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2037 = cvt(_T_2036) node _T_2038 = and(_T_2037, asSInt(UInt<1>(0h0))) node _T_2039 = asSInt(_T_2038) node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0))) node _T_2041 = or(_T_2035, _T_2040) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_2042 = shr(io.in.c.bits.source, 2) node _T_2043 = eq(_T_2042, UInt<2>(0h2)) node _T_2044 = leq(UInt<1>(0h0), uncommonBits_54) node _T_2045 = and(_T_2043, _T_2044) node _T_2046 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_2047 = and(_T_2045, _T_2046) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<1>(0h0))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = or(_T_2048, _T_2053) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_2055 = shr(io.in.c.bits.source, 2) node _T_2056 = eq(_T_2055, UInt<2>(0h3)) node _T_2057 = leq(UInt<1>(0h0), uncommonBits_55) node _T_2058 = and(_T_2056, _T_2057) node _T_2059 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_2060 = and(_T_2058, _T_2059) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) node _T_2062 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2063 = cvt(_T_2062) node _T_2064 = and(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = asSInt(_T_2064) node _T_2066 = eq(_T_2065, asSInt(UInt<1>(0h0))) node _T_2067 = or(_T_2061, _T_2066) node _T_2068 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) node _T_2070 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<1>(0h0))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = or(_T_2069, _T_2074) node _T_2076 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) node _T_2078 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2079 = cvt(_T_2078) node _T_2080 = and(_T_2079, asSInt(UInt<1>(0h0))) node _T_2081 = asSInt(_T_2080) node _T_2082 = eq(_T_2081, asSInt(UInt<1>(0h0))) node _T_2083 = or(_T_2077, _T_2082) node _T_2084 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = or(_T_2085, _T_2090) node _T_2092 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2093 = eq(_T_2092, UInt<1>(0h0)) node _T_2094 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<1>(0h0))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2093, _T_2098) node _T_2100 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2101 = eq(_T_2100, UInt<1>(0h0)) node _T_2102 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2103 = cvt(_T_2102) node _T_2104 = and(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = asSInt(_T_2104) node _T_2106 = eq(_T_2105, asSInt(UInt<1>(0h0))) node _T_2107 = or(_T_2101, _T_2106) node _T_2108 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2109 = eq(_T_2108, UInt<1>(0h0)) node _T_2110 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<1>(0h0))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = or(_T_2109, _T_2114) node _T_2116 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2117 = eq(_T_2116, UInt<1>(0h0)) node _T_2118 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2119 = cvt(_T_2118) node _T_2120 = and(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = asSInt(_T_2120) node _T_2122 = eq(_T_2121, asSInt(UInt<1>(0h0))) node _T_2123 = or(_T_2117, _T_2122) node _T_2124 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) node _T_2126 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2127 = cvt(_T_2126) node _T_2128 = and(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = asSInt(_T_2128) node _T_2130 = eq(_T_2129, asSInt(UInt<1>(0h0))) node _T_2131 = or(_T_2125, _T_2130) node _T_2132 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2133 = eq(_T_2132, UInt<1>(0h0)) node _T_2134 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2135 = cvt(_T_2134) node _T_2136 = and(_T_2135, asSInt(UInt<1>(0h0))) node _T_2137 = asSInt(_T_2136) node _T_2138 = eq(_T_2137, asSInt(UInt<1>(0h0))) node _T_2139 = or(_T_2133, _T_2138) node _T_2140 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2141 = eq(_T_2140, UInt<1>(0h0)) node _T_2142 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2143 = cvt(_T_2142) node _T_2144 = and(_T_2143, asSInt(UInt<1>(0h0))) node _T_2145 = asSInt(_T_2144) node _T_2146 = eq(_T_2145, asSInt(UInt<1>(0h0))) node _T_2147 = or(_T_2141, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) node _T_2150 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<1>(0h0))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = or(_T_2149, _T_2154) node _T_2156 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2159 = cvt(_T_2158) node _T_2160 = and(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = asSInt(_T_2160) node _T_2162 = eq(_T_2161, asSInt(UInt<1>(0h0))) node _T_2163 = or(_T_2157, _T_2162) node _T_2164 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2165 = eq(_T_2164, UInt<1>(0h0)) node _T_2166 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = or(_T_2165, _T_2170) node _T_2172 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) node _T_2174 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<1>(0h0))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = or(_T_2173, _T_2178) node _T_2180 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2183 = cvt(_T_2182) node _T_2184 = and(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = asSInt(_T_2184) node _T_2186 = eq(_T_2185, asSInt(UInt<1>(0h0))) node _T_2187 = or(_T_2181, _T_2186) node _T_2188 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) node _T_2190 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<1>(0h0))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2189, _T_2194) node _T_2196 = and(_T_2015, _T_2028) node _T_2197 = and(_T_2196, _T_2041) node _T_2198 = and(_T_2197, _T_2054) node _T_2199 = and(_T_2198, _T_2067) node _T_2200 = and(_T_2199, _T_2075) node _T_2201 = and(_T_2200, _T_2083) node _T_2202 = and(_T_2201, _T_2091) node _T_2203 = and(_T_2202, _T_2099) node _T_2204 = and(_T_2203, _T_2107) node _T_2205 = and(_T_2204, _T_2115) node _T_2206 = and(_T_2205, _T_2123) node _T_2207 = and(_T_2206, _T_2131) node _T_2208 = and(_T_2207, _T_2139) node _T_2209 = and(_T_2208, _T_2147) node _T_2210 = and(_T_2209, _T_2155) node _T_2211 = and(_T_2210, _T_2163) node _T_2212 = and(_T_2211, _T_2171) node _T_2213 = and(_T_2212, _T_2179) node _T_2214 = and(_T_2213, _T_2187) node _T_2215 = and(_T_2214, _T_2195) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_131 node _T_2219 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_2219 : node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(address_ok_1, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(source_ok_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2226 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_134 node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2233 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(_T_2233, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2233, UInt<1>(0h1), "") : assert_136 node _T_2237 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_137 node _T_2241 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2241 : node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(address_ok_1, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(source_ok_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2248 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_140 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2255 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(_T_2255, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2255, UInt<1>(0h1), "") : assert_142 node _T_2259 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2259 : node _T_2260 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2261 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2262 = and(_T_2260, _T_2261) node _T_2263 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_2264 = shr(io.in.c.bits.source, 2) node _T_2265 = eq(_T_2264, UInt<1>(0h0)) node _T_2266 = leq(UInt<1>(0h0), uncommonBits_56) node _T_2267 = and(_T_2265, _T_2266) node _T_2268 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_2269 = and(_T_2267, _T_2268) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_2270 = shr(io.in.c.bits.source, 2) node _T_2271 = eq(_T_2270, UInt<1>(0h1)) node _T_2272 = leq(UInt<1>(0h0), uncommonBits_57) node _T_2273 = and(_T_2271, _T_2272) node _T_2274 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_2275 = and(_T_2273, _T_2274) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_2276 = shr(io.in.c.bits.source, 2) node _T_2277 = eq(_T_2276, UInt<2>(0h2)) node _T_2278 = leq(UInt<1>(0h0), uncommonBits_58) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_2281 = and(_T_2279, _T_2280) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_2282 = shr(io.in.c.bits.source, 2) node _T_2283 = eq(_T_2282, UInt<2>(0h3)) node _T_2284 = leq(UInt<1>(0h0), uncommonBits_59) node _T_2285 = and(_T_2283, _T_2284) node _T_2286 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_2287 = and(_T_2285, _T_2286) node _T_2288 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2289 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2290 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2291 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2292 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2293 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2294 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2295 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2296 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2297 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2298 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2299 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2300 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2301 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2302 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2303 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2304 = or(_T_2263, _T_2269) node _T_2305 = or(_T_2304, _T_2275) node _T_2306 = or(_T_2305, _T_2281) node _T_2307 = or(_T_2306, _T_2287) node _T_2308 = or(_T_2307, _T_2288) node _T_2309 = or(_T_2308, _T_2289) node _T_2310 = or(_T_2309, _T_2290) node _T_2311 = or(_T_2310, _T_2291) node _T_2312 = or(_T_2311, _T_2292) node _T_2313 = or(_T_2312, _T_2293) node _T_2314 = or(_T_2313, _T_2294) node _T_2315 = or(_T_2314, _T_2295) node _T_2316 = or(_T_2315, _T_2296) node _T_2317 = or(_T_2316, _T_2297) node _T_2318 = or(_T_2317, _T_2298) node _T_2319 = or(_T_2318, _T_2299) node _T_2320 = or(_T_2319, _T_2300) node _T_2321 = or(_T_2320, _T_2301) node _T_2322 = or(_T_2321, _T_2302) node _T_2323 = or(_T_2322, _T_2303) node _T_2324 = and(_T_2262, _T_2323) node _T_2325 = or(UInt<1>(0h0), _T_2324) node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = or(UInt<1>(0h0), _T_2326) node _T_2328 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2329 = cvt(_T_2328) node _T_2330 = and(_T_2329, asSInt(UInt<17>(0h100c0))) node _T_2331 = asSInt(_T_2330) node _T_2332 = eq(_T_2331, asSInt(UInt<1>(0h0))) node _T_2333 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2334 = cvt(_T_2333) node _T_2335 = and(_T_2334, asSInt(UInt<29>(0h100000c0))) node _T_2336 = asSInt(_T_2335) node _T_2337 = eq(_T_2336, asSInt(UInt<1>(0h0))) node _T_2338 = or(_T_2332, _T_2337) node _T_2339 = and(_T_2327, _T_2338) node _T_2340 = or(UInt<1>(0h0), _T_2339) node _T_2341 = and(_T_2325, _T_2340) node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(_T_2341, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2341, UInt<1>(0h1), "") : assert_143 node _T_2345 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_2346 = shr(io.in.c.bits.source, 2) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) node _T_2348 = leq(UInt<1>(0h0), uncommonBits_60) node _T_2349 = and(_T_2347, _T_2348) node _T_2350 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_2351 = and(_T_2349, _T_2350) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_2352 = shr(io.in.c.bits.source, 2) node _T_2353 = eq(_T_2352, UInt<1>(0h1)) node _T_2354 = leq(UInt<1>(0h0), uncommonBits_61) node _T_2355 = and(_T_2353, _T_2354) node _T_2356 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_2357 = and(_T_2355, _T_2356) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_2358 = shr(io.in.c.bits.source, 2) node _T_2359 = eq(_T_2358, UInt<2>(0h2)) node _T_2360 = leq(UInt<1>(0h0), uncommonBits_62) node _T_2361 = and(_T_2359, _T_2360) node _T_2362 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_2363 = and(_T_2361, _T_2362) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_2364 = shr(io.in.c.bits.source, 2) node _T_2365 = eq(_T_2364, UInt<2>(0h3)) node _T_2366 = leq(UInt<1>(0h0), uncommonBits_63) node _T_2367 = and(_T_2365, _T_2366) node _T_2368 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_2369 = and(_T_2367, _T_2368) node _T_2370 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2371 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2372 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2373 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2374 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2375 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2376 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2377 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2378 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2379 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2380 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2381 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2382 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2383 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2384 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2385 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[21] connect _WIRE_6[0], _T_2345 connect _WIRE_6[1], _T_2351 connect _WIRE_6[2], _T_2357 connect _WIRE_6[3], _T_2363 connect _WIRE_6[4], _T_2369 connect _WIRE_6[5], _T_2370 connect _WIRE_6[6], _T_2371 connect _WIRE_6[7], _T_2372 connect _WIRE_6[8], _T_2373 connect _WIRE_6[9], _T_2374 connect _WIRE_6[10], _T_2375 connect _WIRE_6[11], _T_2376 connect _WIRE_6[12], _T_2377 connect _WIRE_6[13], _T_2378 connect _WIRE_6[14], _T_2379 connect _WIRE_6[15], _T_2380 connect _WIRE_6[16], _T_2381 connect _WIRE_6[17], _T_2382 connect _WIRE_6[18], _T_2383 connect _WIRE_6[19], _T_2384 connect _WIRE_6[20], _T_2385 node _T_2386 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2387 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2388 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2389 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2390 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2391 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2392 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2393 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2394 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2395 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2396 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2397 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2398 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2399 = mux(_WIRE_6[5], _T_2386, UInt<1>(0h0)) node _T_2400 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2401 = mux(_WIRE_6[7], _T_2387, UInt<1>(0h0)) node _T_2402 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2403 = mux(_WIRE_6[9], _T_2388, UInt<1>(0h0)) node _T_2404 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2405 = mux(_WIRE_6[11], _T_2389, UInt<1>(0h0)) node _T_2406 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2407 = mux(_WIRE_6[13], _T_2390, UInt<1>(0h0)) node _T_2408 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2409 = mux(_WIRE_6[15], _T_2391, UInt<1>(0h0)) node _T_2410 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2411 = mux(_WIRE_6[17], _T_2392, UInt<1>(0h0)) node _T_2412 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2413 = mux(_WIRE_6[19], _T_2393, UInt<1>(0h0)) node _T_2414 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2415 = or(_T_2394, _T_2395) node _T_2416 = or(_T_2415, _T_2396) node _T_2417 = or(_T_2416, _T_2397) node _T_2418 = or(_T_2417, _T_2398) node _T_2419 = or(_T_2418, _T_2399) node _T_2420 = or(_T_2419, _T_2400) node _T_2421 = or(_T_2420, _T_2401) node _T_2422 = or(_T_2421, _T_2402) node _T_2423 = or(_T_2422, _T_2403) node _T_2424 = or(_T_2423, _T_2404) node _T_2425 = or(_T_2424, _T_2405) node _T_2426 = or(_T_2425, _T_2406) node _T_2427 = or(_T_2426, _T_2407) node _T_2428 = or(_T_2427, _T_2408) node _T_2429 = or(_T_2428, _T_2409) node _T_2430 = or(_T_2429, _T_2410) node _T_2431 = or(_T_2430, _T_2411) node _T_2432 = or(_T_2431, _T_2412) node _T_2433 = or(_T_2432, _T_2413) node _T_2434 = or(_T_2433, _T_2414) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2434 node _T_2435 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2436 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = or(UInt<1>(0h0), _T_2437) node _T_2439 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2440 = cvt(_T_2439) node _T_2441 = and(_T_2440, asSInt(UInt<17>(0h100c0))) node _T_2442 = asSInt(_T_2441) node _T_2443 = eq(_T_2442, asSInt(UInt<1>(0h0))) node _T_2444 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2445 = cvt(_T_2444) node _T_2446 = and(_T_2445, asSInt(UInt<29>(0h100000c0))) node _T_2447 = asSInt(_T_2446) node _T_2448 = eq(_T_2447, asSInt(UInt<1>(0h0))) node _T_2449 = or(_T_2443, _T_2448) node _T_2450 = and(_T_2438, _T_2449) node _T_2451 = or(UInt<1>(0h0), _T_2450) node _T_2452 = and(_WIRE_7, _T_2451) node _T_2453 = asUInt(reset) node _T_2454 = eq(_T_2453, UInt<1>(0h0)) when _T_2454 : node _T_2455 = eq(_T_2452, UInt<1>(0h0)) when _T_2455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2452, UInt<1>(0h1), "") : assert_144 node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(source_ok_2, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2459 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_146 node _T_2463 = asUInt(reset) node _T_2464 = eq(_T_2463, UInt<1>(0h0)) when _T_2464 : node _T_2465 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2466 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_148 node _T_2470 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(_T_2470, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2470, UInt<1>(0h1), "") : assert_149 node _T_2474 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2474 : node _T_2475 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2476 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2477 = and(_T_2475, _T_2476) node _T_2478 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2479 = shr(io.in.c.bits.source, 2) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2482 = and(_T_2480, _T_2481) node _T_2483 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2484 = and(_T_2482, _T_2483) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2485 = shr(io.in.c.bits.source, 2) node _T_2486 = eq(_T_2485, UInt<1>(0h1)) node _T_2487 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2488 = and(_T_2486, _T_2487) node _T_2489 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2490 = and(_T_2488, _T_2489) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2491 = shr(io.in.c.bits.source, 2) node _T_2492 = eq(_T_2491, UInt<2>(0h2)) node _T_2493 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2494 = and(_T_2492, _T_2493) node _T_2495 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2496 = and(_T_2494, _T_2495) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2497 = shr(io.in.c.bits.source, 2) node _T_2498 = eq(_T_2497, UInt<2>(0h3)) node _T_2499 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2500 = and(_T_2498, _T_2499) node _T_2501 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2502 = and(_T_2500, _T_2501) node _T_2503 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2504 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2505 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2506 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2507 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2508 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2509 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2510 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2511 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2512 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2513 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2514 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2515 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2516 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2517 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2518 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2519 = or(_T_2478, _T_2484) node _T_2520 = or(_T_2519, _T_2490) node _T_2521 = or(_T_2520, _T_2496) node _T_2522 = or(_T_2521, _T_2502) node _T_2523 = or(_T_2522, _T_2503) node _T_2524 = or(_T_2523, _T_2504) node _T_2525 = or(_T_2524, _T_2505) node _T_2526 = or(_T_2525, _T_2506) node _T_2527 = or(_T_2526, _T_2507) node _T_2528 = or(_T_2527, _T_2508) node _T_2529 = or(_T_2528, _T_2509) node _T_2530 = or(_T_2529, _T_2510) node _T_2531 = or(_T_2530, _T_2511) node _T_2532 = or(_T_2531, _T_2512) node _T_2533 = or(_T_2532, _T_2513) node _T_2534 = or(_T_2533, _T_2514) node _T_2535 = or(_T_2534, _T_2515) node _T_2536 = or(_T_2535, _T_2516) node _T_2537 = or(_T_2536, _T_2517) node _T_2538 = or(_T_2537, _T_2518) node _T_2539 = and(_T_2477, _T_2538) node _T_2540 = or(UInt<1>(0h0), _T_2539) node _T_2541 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2542 = or(UInt<1>(0h0), _T_2541) node _T_2543 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2544 = cvt(_T_2543) node _T_2545 = and(_T_2544, asSInt(UInt<17>(0h100c0))) node _T_2546 = asSInt(_T_2545) node _T_2547 = eq(_T_2546, asSInt(UInt<1>(0h0))) node _T_2548 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2549 = cvt(_T_2548) node _T_2550 = and(_T_2549, asSInt(UInt<29>(0h100000c0))) node _T_2551 = asSInt(_T_2550) node _T_2552 = eq(_T_2551, asSInt(UInt<1>(0h0))) node _T_2553 = or(_T_2547, _T_2552) node _T_2554 = and(_T_2542, _T_2553) node _T_2555 = or(UInt<1>(0h0), _T_2554) node _T_2556 = and(_T_2540, _T_2555) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_150 node _T_2560 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2561 = shr(io.in.c.bits.source, 2) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) node _T_2563 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2564 = and(_T_2562, _T_2563) node _T_2565 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2566 = and(_T_2564, _T_2565) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2567 = shr(io.in.c.bits.source, 2) node _T_2568 = eq(_T_2567, UInt<1>(0h1)) node _T_2569 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2570 = and(_T_2568, _T_2569) node _T_2571 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2572 = and(_T_2570, _T_2571) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2573 = shr(io.in.c.bits.source, 2) node _T_2574 = eq(_T_2573, UInt<2>(0h2)) node _T_2575 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2576 = and(_T_2574, _T_2575) node _T_2577 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2578 = and(_T_2576, _T_2577) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2579 = shr(io.in.c.bits.source, 2) node _T_2580 = eq(_T_2579, UInt<2>(0h3)) node _T_2581 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2582 = and(_T_2580, _T_2581) node _T_2583 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2584 = and(_T_2582, _T_2583) node _T_2585 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2586 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2587 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2588 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2589 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2590 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2591 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2592 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2593 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2594 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2595 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2596 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2597 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2598 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2599 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2600 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[21] connect _WIRE_8[0], _T_2560 connect _WIRE_8[1], _T_2566 connect _WIRE_8[2], _T_2572 connect _WIRE_8[3], _T_2578 connect _WIRE_8[4], _T_2584 connect _WIRE_8[5], _T_2585 connect _WIRE_8[6], _T_2586 connect _WIRE_8[7], _T_2587 connect _WIRE_8[8], _T_2588 connect _WIRE_8[9], _T_2589 connect _WIRE_8[10], _T_2590 connect _WIRE_8[11], _T_2591 connect _WIRE_8[12], _T_2592 connect _WIRE_8[13], _T_2593 connect _WIRE_8[14], _T_2594 connect _WIRE_8[15], _T_2595 connect _WIRE_8[16], _T_2596 connect _WIRE_8[17], _T_2597 connect _WIRE_8[18], _T_2598 connect _WIRE_8[19], _T_2599 connect _WIRE_8[20], _T_2600 node _T_2601 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2602 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2603 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2604 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2605 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2606 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2607 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2608 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2609 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2610 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2611 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2612 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2613 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2614 = mux(_WIRE_8[5], _T_2601, UInt<1>(0h0)) node _T_2615 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2616 = mux(_WIRE_8[7], _T_2602, UInt<1>(0h0)) node _T_2617 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2618 = mux(_WIRE_8[9], _T_2603, UInt<1>(0h0)) node _T_2619 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2620 = mux(_WIRE_8[11], _T_2604, UInt<1>(0h0)) node _T_2621 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2622 = mux(_WIRE_8[13], _T_2605, UInt<1>(0h0)) node _T_2623 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2624 = mux(_WIRE_8[15], _T_2606, UInt<1>(0h0)) node _T_2625 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2626 = mux(_WIRE_8[17], _T_2607, UInt<1>(0h0)) node _T_2627 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2628 = mux(_WIRE_8[19], _T_2608, UInt<1>(0h0)) node _T_2629 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2630 = or(_T_2609, _T_2610) node _T_2631 = or(_T_2630, _T_2611) node _T_2632 = or(_T_2631, _T_2612) node _T_2633 = or(_T_2632, _T_2613) node _T_2634 = or(_T_2633, _T_2614) node _T_2635 = or(_T_2634, _T_2615) node _T_2636 = or(_T_2635, _T_2616) node _T_2637 = or(_T_2636, _T_2617) node _T_2638 = or(_T_2637, _T_2618) node _T_2639 = or(_T_2638, _T_2619) node _T_2640 = or(_T_2639, _T_2620) node _T_2641 = or(_T_2640, _T_2621) node _T_2642 = or(_T_2641, _T_2622) node _T_2643 = or(_T_2642, _T_2623) node _T_2644 = or(_T_2643, _T_2624) node _T_2645 = or(_T_2644, _T_2625) node _T_2646 = or(_T_2645, _T_2626) node _T_2647 = or(_T_2646, _T_2627) node _T_2648 = or(_T_2647, _T_2628) node _T_2649 = or(_T_2648, _T_2629) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2649 node _T_2650 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2651 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2652 = and(_T_2650, _T_2651) node _T_2653 = or(UInt<1>(0h0), _T_2652) node _T_2654 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2655 = cvt(_T_2654) node _T_2656 = and(_T_2655, asSInt(UInt<17>(0h100c0))) node _T_2657 = asSInt(_T_2656) node _T_2658 = eq(_T_2657, asSInt(UInt<1>(0h0))) node _T_2659 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2660 = cvt(_T_2659) node _T_2661 = and(_T_2660, asSInt(UInt<29>(0h100000c0))) node _T_2662 = asSInt(_T_2661) node _T_2663 = eq(_T_2662, asSInt(UInt<1>(0h0))) node _T_2664 = or(_T_2658, _T_2663) node _T_2665 = and(_T_2653, _T_2664) node _T_2666 = or(UInt<1>(0h0), _T_2665) node _T_2667 = and(_WIRE_9, _T_2666) node _T_2668 = asUInt(reset) node _T_2669 = eq(_T_2668, UInt<1>(0h0)) when _T_2669 : node _T_2670 = eq(_T_2667, UInt<1>(0h0)) when _T_2670 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2667, UInt<1>(0h1), "") : assert_151 node _T_2671 = asUInt(reset) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) when _T_2672 : node _T_2673 = eq(source_ok_2, UInt<1>(0h0)) when _T_2673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2674 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2675 = asUInt(reset) node _T_2676 = eq(_T_2675, UInt<1>(0h0)) when _T_2676 : node _T_2677 = eq(_T_2674, UInt<1>(0h0)) when _T_2677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2674, UInt<1>(0h1), "") : assert_153 node _T_2678 = asUInt(reset) node _T_2679 = eq(_T_2678, UInt<1>(0h0)) when _T_2679 : node _T_2680 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2681 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2682 = asUInt(reset) node _T_2683 = eq(_T_2682, UInt<1>(0h0)) when _T_2683 : node _T_2684 = eq(_T_2681, UInt<1>(0h0)) when _T_2684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2681, UInt<1>(0h1), "") : assert_155 node _T_2685 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2685 : node _T_2686 = asUInt(reset) node _T_2687 = eq(_T_2686, UInt<1>(0h0)) when _T_2687 : node _T_2688 = eq(address_ok_1, UInt<1>(0h0)) when _T_2688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(source_ok_2, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2692 = asUInt(reset) node _T_2693 = eq(_T_2692, UInt<1>(0h0)) when _T_2693 : node _T_2694 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2695 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2696 = asUInt(reset) node _T_2697 = eq(_T_2696, UInt<1>(0h0)) when _T_2697 : node _T_2698 = eq(_T_2695, UInt<1>(0h0)) when _T_2698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2695, UInt<1>(0h1), "") : assert_159 node _T_2699 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2700 = asUInt(reset) node _T_2701 = eq(_T_2700, UInt<1>(0h0)) when _T_2701 : node _T_2702 = eq(_T_2699, UInt<1>(0h0)) when _T_2702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2699, UInt<1>(0h1), "") : assert_160 node _T_2703 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2703 : node _T_2704 = asUInt(reset) node _T_2705 = eq(_T_2704, UInt<1>(0h0)) when _T_2705 : node _T_2706 = eq(address_ok_1, UInt<1>(0h0)) when _T_2706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2707 = asUInt(reset) node _T_2708 = eq(_T_2707, UInt<1>(0h0)) when _T_2708 : node _T_2709 = eq(source_ok_2, UInt<1>(0h0)) when _T_2709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2713 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2714 = asUInt(reset) node _T_2715 = eq(_T_2714, UInt<1>(0h0)) when _T_2715 : node _T_2716 = eq(_T_2713, UInt<1>(0h0)) when _T_2716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2713, UInt<1>(0h1), "") : assert_164 node _T_2717 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2717 : node _T_2718 = asUInt(reset) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) when _T_2719 : node _T_2720 = eq(address_ok_1, UInt<1>(0h0)) when _T_2720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2721 = asUInt(reset) node _T_2722 = eq(_T_2721, UInt<1>(0h0)) when _T_2722 : node _T_2723 = eq(source_ok_2, UInt<1>(0h0)) when _T_2723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2727 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2728 = asUInt(reset) node _T_2729 = eq(_T_2728, UInt<1>(0h0)) when _T_2729 : node _T_2730 = eq(_T_2727, UInt<1>(0h0)) when _T_2730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2727, UInt<1>(0h1), "") : assert_168 node _T_2731 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2732 = asUInt(reset) node _T_2733 = eq(_T_2732, UInt<1>(0h0)) when _T_2733 : node _T_2734 = eq(_T_2731, UInt<1>(0h0)) when _T_2734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2731, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2735 = asUInt(reset) node _T_2736 = eq(_T_2735, UInt<1>(0h0)) when _T_2736 : node _T_2737 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2738 = eq(a_first, UInt<1>(0h0)) node _T_2739 = and(io.in.a.valid, _T_2738) when _T_2739 : node _T_2740 = eq(io.in.a.bits.opcode, opcode) node _T_2741 = asUInt(reset) node _T_2742 = eq(_T_2741, UInt<1>(0h0)) when _T_2742 : node _T_2743 = eq(_T_2740, UInt<1>(0h0)) when _T_2743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2740, UInt<1>(0h1), "") : assert_171 node _T_2744 = eq(io.in.a.bits.param, param) node _T_2745 = asUInt(reset) node _T_2746 = eq(_T_2745, UInt<1>(0h0)) when _T_2746 : node _T_2747 = eq(_T_2744, UInt<1>(0h0)) when _T_2747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2744, UInt<1>(0h1), "") : assert_172 node _T_2748 = eq(io.in.a.bits.size, size) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_173 node _T_2752 = eq(io.in.a.bits.source, source) node _T_2753 = asUInt(reset) node _T_2754 = eq(_T_2753, UInt<1>(0h0)) when _T_2754 : node _T_2755 = eq(_T_2752, UInt<1>(0h0)) when _T_2755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2752, UInt<1>(0h1), "") : assert_174 node _T_2756 = eq(io.in.a.bits.address, address) node _T_2757 = asUInt(reset) node _T_2758 = eq(_T_2757, UInt<1>(0h0)) when _T_2758 : node _T_2759 = eq(_T_2756, UInt<1>(0h0)) when _T_2759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2756, UInt<1>(0h1), "") : assert_175 node _T_2760 = and(io.in.a.ready, io.in.a.valid) node _T_2761 = and(_T_2760, a_first) when _T_2761 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2762 = eq(d_first, UInt<1>(0h0)) node _T_2763 = and(io.in.d.valid, _T_2762) when _T_2763 : node _T_2764 = eq(io.in.d.bits.opcode, opcode_1) node _T_2765 = asUInt(reset) node _T_2766 = eq(_T_2765, UInt<1>(0h0)) when _T_2766 : node _T_2767 = eq(_T_2764, UInt<1>(0h0)) when _T_2767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2764, UInt<1>(0h1), "") : assert_176 node _T_2768 = eq(io.in.d.bits.param, param_1) node _T_2769 = asUInt(reset) node _T_2770 = eq(_T_2769, UInt<1>(0h0)) when _T_2770 : node _T_2771 = eq(_T_2768, UInt<1>(0h0)) when _T_2771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2768, UInt<1>(0h1), "") : assert_177 node _T_2772 = eq(io.in.d.bits.size, size_1) node _T_2773 = asUInt(reset) node _T_2774 = eq(_T_2773, UInt<1>(0h0)) when _T_2774 : node _T_2775 = eq(_T_2772, UInt<1>(0h0)) when _T_2775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2772, UInt<1>(0h1), "") : assert_178 node _T_2776 = eq(io.in.d.bits.source, source_1) node _T_2777 = asUInt(reset) node _T_2778 = eq(_T_2777, UInt<1>(0h0)) when _T_2778 : node _T_2779 = eq(_T_2776, UInt<1>(0h0)) when _T_2779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2776, UInt<1>(0h1), "") : assert_179 node _T_2780 = eq(io.in.d.bits.sink, sink) node _T_2781 = asUInt(reset) node _T_2782 = eq(_T_2781, UInt<1>(0h0)) when _T_2782 : node _T_2783 = eq(_T_2780, UInt<1>(0h0)) when _T_2783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2780, UInt<1>(0h1), "") : assert_180 node _T_2784 = eq(io.in.d.bits.denied, denied) node _T_2785 = asUInt(reset) node _T_2786 = eq(_T_2785, UInt<1>(0h0)) when _T_2786 : node _T_2787 = eq(_T_2784, UInt<1>(0h0)) when _T_2787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2784, UInt<1>(0h1), "") : assert_181 node _T_2788 = and(io.in.d.ready, io.in.d.valid) node _T_2789 = and(_T_2788, d_first) when _T_2789 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2790 = eq(b_first, UInt<1>(0h0)) node _T_2791 = and(io.in.b.valid, _T_2790) when _T_2791 : node _T_2792 = eq(io.in.b.bits.opcode, opcode_2) node _T_2793 = asUInt(reset) node _T_2794 = eq(_T_2793, UInt<1>(0h0)) when _T_2794 : node _T_2795 = eq(_T_2792, UInt<1>(0h0)) when _T_2795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2792, UInt<1>(0h1), "") : assert_182 node _T_2796 = eq(io.in.b.bits.param, param_2) node _T_2797 = asUInt(reset) node _T_2798 = eq(_T_2797, UInt<1>(0h0)) when _T_2798 : node _T_2799 = eq(_T_2796, UInt<1>(0h0)) when _T_2799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2796, UInt<1>(0h1), "") : assert_183 node _T_2800 = eq(io.in.b.bits.size, size_2) node _T_2801 = asUInt(reset) node _T_2802 = eq(_T_2801, UInt<1>(0h0)) when _T_2802 : node _T_2803 = eq(_T_2800, UInt<1>(0h0)) when _T_2803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2800, UInt<1>(0h1), "") : assert_184 node _T_2804 = eq(io.in.b.bits.source, source_2) node _T_2805 = asUInt(reset) node _T_2806 = eq(_T_2805, UInt<1>(0h0)) when _T_2806 : node _T_2807 = eq(_T_2804, UInt<1>(0h0)) when _T_2807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2804, UInt<1>(0h1), "") : assert_185 node _T_2808 = eq(io.in.b.bits.address, address_1) node _T_2809 = asUInt(reset) node _T_2810 = eq(_T_2809, UInt<1>(0h0)) when _T_2810 : node _T_2811 = eq(_T_2808, UInt<1>(0h0)) when _T_2811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2808, UInt<1>(0h1), "") : assert_186 node _T_2812 = and(io.in.b.ready, io.in.b.valid) node _T_2813 = and(_T_2812, b_first) when _T_2813 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2814 = eq(c_first, UInt<1>(0h0)) node _T_2815 = and(io.in.c.valid, _T_2814) when _T_2815 : node _T_2816 = eq(io.in.c.bits.opcode, opcode_3) node _T_2817 = asUInt(reset) node _T_2818 = eq(_T_2817, UInt<1>(0h0)) when _T_2818 : node _T_2819 = eq(_T_2816, UInt<1>(0h0)) when _T_2819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2816, UInt<1>(0h1), "") : assert_187 node _T_2820 = eq(io.in.c.bits.param, param_3) node _T_2821 = asUInt(reset) node _T_2822 = eq(_T_2821, UInt<1>(0h0)) when _T_2822 : node _T_2823 = eq(_T_2820, UInt<1>(0h0)) when _T_2823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2820, UInt<1>(0h1), "") : assert_188 node _T_2824 = eq(io.in.c.bits.size, size_3) node _T_2825 = asUInt(reset) node _T_2826 = eq(_T_2825, UInt<1>(0h0)) when _T_2826 : node _T_2827 = eq(_T_2824, UInt<1>(0h0)) when _T_2827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2824, UInt<1>(0h1), "") : assert_189 node _T_2828 = eq(io.in.c.bits.source, source_3) node _T_2829 = asUInt(reset) node _T_2830 = eq(_T_2829, UInt<1>(0h0)) when _T_2830 : node _T_2831 = eq(_T_2828, UInt<1>(0h0)) when _T_2831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2828, UInt<1>(0h1), "") : assert_190 node _T_2832 = eq(io.in.c.bits.address, address_2) node _T_2833 = asUInt(reset) node _T_2834 = eq(_T_2833, UInt<1>(0h0)) when _T_2834 : node _T_2835 = eq(_T_2832, UInt<1>(0h0)) when _T_2835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2832, UInt<1>(0h1), "") : assert_191 node _T_2836 = and(io.in.c.ready, io.in.c.valid) node _T_2837 = and(_T_2836, c_first) when _T_2837 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<63>, clock, reset, UInt<63>(0h0) regreset inflight_opcodes : UInt<252>, clock, reset, UInt<252>(0h0) regreset inflight_sizes : UInt<252>, clock, reset, UInt<252>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<63> connect a_set, UInt<63>(0h0) wire a_set_wo_ready : UInt<63> connect a_set_wo_ready, UInt<63>(0h0) wire a_opcodes_set : UInt<252> connect a_opcodes_set, UInt<252>(0h0) wire a_sizes_set : UInt<252> connect a_sizes_set, UInt<252>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2838 = and(io.in.a.valid, a_first_1) node _T_2839 = and(_T_2838, UInt<1>(0h1)) when _T_2839 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2840 = and(io.in.a.ready, io.in.a.valid) node _T_2841 = and(_T_2840, a_first_1) node _T_2842 = and(_T_2841, UInt<1>(0h1)) when _T_2842 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2843 = dshr(inflight, io.in.a.bits.source) node _T_2844 = bits(_T_2843, 0, 0) node _T_2845 = eq(_T_2844, UInt<1>(0h0)) node _T_2846 = asUInt(reset) node _T_2847 = eq(_T_2846, UInt<1>(0h0)) when _T_2847 : node _T_2848 = eq(_T_2845, UInt<1>(0h0)) when _T_2848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2845, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<63> connect d_clr, UInt<63>(0h0) wire d_clr_wo_ready : UInt<63> connect d_clr_wo_ready, UInt<63>(0h0) wire d_opcodes_clr : UInt<252> connect d_opcodes_clr, UInt<252>(0h0) wire d_sizes_clr : UInt<252> connect d_sizes_clr, UInt<252>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2849 = and(io.in.d.valid, d_first_1) node _T_2850 = and(_T_2849, UInt<1>(0h1)) node _T_2851 = eq(d_release_ack, UInt<1>(0h0)) node _T_2852 = and(_T_2850, _T_2851) when _T_2852 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2853 = and(io.in.d.ready, io.in.d.valid) node _T_2854 = and(_T_2853, d_first_1) node _T_2855 = and(_T_2854, UInt<1>(0h1)) node _T_2856 = eq(d_release_ack, UInt<1>(0h0)) node _T_2857 = and(_T_2855, _T_2856) when _T_2857 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2858 = and(io.in.d.valid, d_first_1) node _T_2859 = and(_T_2858, UInt<1>(0h1)) node _T_2860 = eq(d_release_ack, UInt<1>(0h0)) node _T_2861 = and(_T_2859, _T_2860) when _T_2861 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2862 = dshr(inflight, io.in.d.bits.source) node _T_2863 = bits(_T_2862, 0, 0) node _T_2864 = or(_T_2863, same_cycle_resp) node _T_2865 = asUInt(reset) node _T_2866 = eq(_T_2865, UInt<1>(0h0)) when _T_2866 : node _T_2867 = eq(_T_2864, UInt<1>(0h0)) when _T_2867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2864, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2868 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2869 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2870 = or(_T_2868, _T_2869) node _T_2871 = asUInt(reset) node _T_2872 = eq(_T_2871, UInt<1>(0h0)) when _T_2872 : node _T_2873 = eq(_T_2870, UInt<1>(0h0)) when _T_2873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2870, UInt<1>(0h1), "") : assert_194 node _T_2874 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2875 = asUInt(reset) node _T_2876 = eq(_T_2875, UInt<1>(0h0)) when _T_2876 : node _T_2877 = eq(_T_2874, UInt<1>(0h0)) when _T_2877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2874, UInt<1>(0h1), "") : assert_195 else : node _T_2878 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2879 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2880 = or(_T_2878, _T_2879) node _T_2881 = asUInt(reset) node _T_2882 = eq(_T_2881, UInt<1>(0h0)) when _T_2882 : node _T_2883 = eq(_T_2880, UInt<1>(0h0)) when _T_2883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2880, UInt<1>(0h1), "") : assert_196 node _T_2884 = eq(io.in.d.bits.size, a_size_lookup) node _T_2885 = asUInt(reset) node _T_2886 = eq(_T_2885, UInt<1>(0h0)) when _T_2886 : node _T_2887 = eq(_T_2884, UInt<1>(0h0)) when _T_2887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2884, UInt<1>(0h1), "") : assert_197 node _T_2888 = and(io.in.d.valid, d_first_1) node _T_2889 = and(_T_2888, a_first_1) node _T_2890 = and(_T_2889, io.in.a.valid) node _T_2891 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2892 = and(_T_2890, _T_2891) node _T_2893 = eq(d_release_ack, UInt<1>(0h0)) node _T_2894 = and(_T_2892, _T_2893) when _T_2894 : node _T_2895 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2896 = or(_T_2895, io.in.a.ready) node _T_2897 = asUInt(reset) node _T_2898 = eq(_T_2897, UInt<1>(0h0)) when _T_2898 : node _T_2899 = eq(_T_2896, UInt<1>(0h0)) when _T_2899 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2896, UInt<1>(0h1), "") : assert_198 node _T_2900 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2901 = orr(a_set_wo_ready) node _T_2902 = eq(_T_2901, UInt<1>(0h0)) node _T_2903 = or(_T_2900, _T_2902) node _T_2904 = asUInt(reset) node _T_2905 = eq(_T_2904, UInt<1>(0h0)) when _T_2905 : node _T_2906 = eq(_T_2903, UInt<1>(0h0)) when _T_2906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2903, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_169 node _T_2907 = orr(inflight) node _T_2908 = eq(_T_2907, UInt<1>(0h0)) node _T_2909 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2910 = or(_T_2908, _T_2909) node _T_2911 = lt(watchdog, plusarg_reader.out) node _T_2912 = or(_T_2910, _T_2911) node _T_2913 = asUInt(reset) node _T_2914 = eq(_T_2913, UInt<1>(0h0)) when _T_2914 : node _T_2915 = eq(_T_2912, UInt<1>(0h0)) when _T_2915 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2912, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2916 = and(io.in.a.ready, io.in.a.valid) node _T_2917 = and(io.in.d.ready, io.in.d.valid) node _T_2918 = or(_T_2916, _T_2917) when _T_2918 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<63>, clock, reset, UInt<63>(0h0) regreset inflight_opcodes_1 : UInt<252>, clock, reset, UInt<252>(0h0) regreset inflight_sizes_1 : UInt<252>, clock, reset, UInt<252>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<63> connect c_set, UInt<63>(0h0) wire c_set_wo_ready : UInt<63> connect c_set_wo_ready, UInt<63>(0h0) wire c_opcodes_set : UInt<252> connect c_opcodes_set, UInt<252>(0h0) wire c_sizes_set : UInt<252> connect c_sizes_set, UInt<252>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2919 = and(io.in.c.valid, c_first_1) node _T_2920 = bits(io.in.c.bits.opcode, 2, 2) node _T_2921 = bits(io.in.c.bits.opcode, 1, 1) node _T_2922 = and(_T_2920, _T_2921) node _T_2923 = and(_T_2919, _T_2922) when _T_2923 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2924 = and(io.in.c.ready, io.in.c.valid) node _T_2925 = and(_T_2924, c_first_1) node _T_2926 = bits(io.in.c.bits.opcode, 2, 2) node _T_2927 = bits(io.in.c.bits.opcode, 1, 1) node _T_2928 = and(_T_2926, _T_2927) node _T_2929 = and(_T_2925, _T_2928) when _T_2929 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2930 = dshr(inflight_1, io.in.c.bits.source) node _T_2931 = bits(_T_2930, 0, 0) node _T_2932 = eq(_T_2931, UInt<1>(0h0)) node _T_2933 = asUInt(reset) node _T_2934 = eq(_T_2933, UInt<1>(0h0)) when _T_2934 : node _T_2935 = eq(_T_2932, UInt<1>(0h0)) when _T_2935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2932, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<63> connect d_clr_1, UInt<63>(0h0) wire d_clr_wo_ready_1 : UInt<63> connect d_clr_wo_ready_1, UInt<63>(0h0) wire d_opcodes_clr_1 : UInt<252> connect d_opcodes_clr_1, UInt<252>(0h0) wire d_sizes_clr_1 : UInt<252> connect d_sizes_clr_1, UInt<252>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2936 = and(io.in.d.valid, d_first_2) node _T_2937 = and(_T_2936, UInt<1>(0h1)) node _T_2938 = and(_T_2937, d_release_ack_1) when _T_2938 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2939 = and(io.in.d.ready, io.in.d.valid) node _T_2940 = and(_T_2939, d_first_2) node _T_2941 = and(_T_2940, UInt<1>(0h1)) node _T_2942 = and(_T_2941, d_release_ack_1) when _T_2942 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2943 = and(io.in.d.valid, d_first_2) node _T_2944 = and(_T_2943, UInt<1>(0h1)) node _T_2945 = and(_T_2944, d_release_ack_1) when _T_2945 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2946 = dshr(inflight_1, io.in.d.bits.source) node _T_2947 = bits(_T_2946, 0, 0) node _T_2948 = or(_T_2947, same_cycle_resp_1) node _T_2949 = asUInt(reset) node _T_2950 = eq(_T_2949, UInt<1>(0h0)) when _T_2950 : node _T_2951 = eq(_T_2948, UInt<1>(0h0)) when _T_2951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2948, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2952 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2953 = asUInt(reset) node _T_2954 = eq(_T_2953, UInt<1>(0h0)) when _T_2954 : node _T_2955 = eq(_T_2952, UInt<1>(0h0)) when _T_2955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2952, UInt<1>(0h1), "") : assert_203 else : node _T_2956 = eq(io.in.d.bits.size, c_size_lookup) node _T_2957 = asUInt(reset) node _T_2958 = eq(_T_2957, UInt<1>(0h0)) when _T_2958 : node _T_2959 = eq(_T_2956, UInt<1>(0h0)) when _T_2959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2956, UInt<1>(0h1), "") : assert_204 node _T_2960 = and(io.in.d.valid, d_first_2) node _T_2961 = and(_T_2960, c_first_1) node _T_2962 = and(_T_2961, io.in.c.valid) node _T_2963 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2964 = and(_T_2962, _T_2963) node _T_2965 = and(_T_2964, d_release_ack_1) node _T_2966 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2967 = and(_T_2965, _T_2966) when _T_2967 : node _T_2968 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2969 = or(_T_2968, io.in.c.ready) node _T_2970 = asUInt(reset) node _T_2971 = eq(_T_2970, UInt<1>(0h0)) when _T_2971 : node _T_2972 = eq(_T_2969, UInt<1>(0h0)) when _T_2972 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2969, UInt<1>(0h1), "") : assert_205 node _T_2973 = orr(c_set_wo_ready) when _T_2973 : node _T_2974 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2975 = asUInt(reset) node _T_2976 = eq(_T_2975, UInt<1>(0h0)) when _T_2976 : node _T_2977 = eq(_T_2974, UInt<1>(0h0)) when _T_2977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2974, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_170 node _T_2978 = orr(inflight_1) node _T_2979 = eq(_T_2978, UInt<1>(0h0)) node _T_2980 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2981 = or(_T_2979, _T_2980) node _T_2982 = lt(watchdog_1, plusarg_reader_1.out) node _T_2983 = or(_T_2981, _T_2982) node _T_2984 = asUInt(reset) node _T_2985 = eq(_T_2984, UInt<1>(0h0)) when _T_2985 : node _T_2986 = eq(_T_2983, UInt<1>(0h0)) when _T_2986 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2983, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2987 = and(io.in.c.ready, io.in.c.valid) node _T_2988 = and(io.in.d.ready, io.in.d.valid) node _T_2989 = or(_T_2987, _T_2988) when _T_2989 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2990 = and(io.in.d.ready, io.in.d.valid) node _T_2991 = and(_T_2990, d_first_3) node _T_2992 = bits(io.in.d.bits.opcode, 2, 2) node _T_2993 = bits(io.in.d.bits.opcode, 1, 1) node _T_2994 = eq(_T_2993, UInt<1>(0h0)) node _T_2995 = and(_T_2992, _T_2994) node _T_2996 = and(_T_2991, _T_2995) when _T_2996 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2997 = dshr(inflight_2, io.in.d.bits.sink) node _T_2998 = bits(_T_2997, 0, 0) node _T_2999 = eq(_T_2998, UInt<1>(0h0)) node _T_3000 = asUInt(reset) node _T_3001 = eq(_T_3000, UInt<1>(0h0)) when _T_3001 : node _T_3002 = eq(_T_2999, UInt<1>(0h0)) when _T_3002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2999, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_3003 = and(io.in.e.ready, io.in.e.valid) node _T_3004 = and(_T_3003, UInt<1>(0h1)) node _T_3005 = and(_T_3004, UInt<1>(0h1)) when _T_3005 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_3006 = or(d_set, inflight_2) node _T_3007 = dshr(_T_3006, io.in.e.bits.sink) node _T_3008 = bits(_T_3007, 0, 0) node _T_3009 = asUInt(reset) node _T_3010 = eq(_T_3009, UInt<1>(0h0)) when _T_3010 : node _T_3011 = eq(_T_3008, UInt<1>(0h0)) when _T_3011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_3008, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [62:0] inflight; // @[Monitor.scala:614:27] reg [251:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [251:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [62:0] inflight_1; // @[Monitor.scala:726:35] reg [251:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_80 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_80( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_3 : output auto : { flip rerocc_tile_ctrl_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rerocc_tile_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip rerocc_tile_re_ro_cc_in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, flip rerocc_tile_rerocc_manager_id_sink_in : UInt<7>, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst rerocc_tile of ReRoCCManagerTile_1 connect rerocc_tile.clock, childClock connect rerocc_tile.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect rerocc_tile.auto.rerocc_manager_id_sink_in, auto.rerocc_tile_rerocc_manager_id_sink_in connect rerocc_tile.auto.re_ro_cc_in, auto.rerocc_tile_re_ro_cc_in connect auto.rerocc_tile_buffer_out.e.bits, rerocc_tile.auto.buffer_out.e.bits connect auto.rerocc_tile_buffer_out.e.valid, rerocc_tile.auto.buffer_out.e.valid connect rerocc_tile.auto.buffer_out.e.ready, auto.rerocc_tile_buffer_out.e.ready connect rerocc_tile.auto.buffer_out.d, auto.rerocc_tile_buffer_out.d connect auto.rerocc_tile_buffer_out.c.bits, rerocc_tile.auto.buffer_out.c.bits connect auto.rerocc_tile_buffer_out.c.valid, rerocc_tile.auto.buffer_out.c.valid connect rerocc_tile.auto.buffer_out.c.ready, auto.rerocc_tile_buffer_out.c.ready connect rerocc_tile.auto.buffer_out.b, auto.rerocc_tile_buffer_out.b connect auto.rerocc_tile_buffer_out.a.bits, rerocc_tile.auto.buffer_out.a.bits connect auto.rerocc_tile_buffer_out.a.valid, rerocc_tile.auto.buffer_out.a.valid connect rerocc_tile.auto.buffer_out.a.ready, auto.rerocc_tile_buffer_out.a.ready connect rerocc_tile.auto.ctrl_ctrl_in, auto.rerocc_tile_ctrl_ctrl_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module ClockSinkDomain_3( // @[ClockDomain.scala:14:9] output auto_rerocc_tile_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_rerocc_tile_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_rerocc_tile_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire auto_rerocc_tile_ctrl_ctrl_in_a_valid_0 = auto_rerocc_tile_ctrl_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_ready_0 = auto_rerocc_tile_ctrl_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_ready_0 = auto_rerocc_tile_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_valid_0 = auto_rerocc_tile_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode_0 = auto_rerocc_tile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_b_bits_param_0 = auto_rerocc_tile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_b_bits_size_0 = auto_rerocc_tile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_source_0 = auto_rerocc_tile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_b_bits_address_0 = auto_rerocc_tile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_b_bits_mask_0 = auto_rerocc_tile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_b_bits_data_0 = auto_rerocc_tile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_corrupt_0 = auto_rerocc_tile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_ready_0 = auto_rerocc_tile_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_valid_0 = auto_rerocc_tile_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode_0 = auto_rerocc_tile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_d_bits_param_0 = auto_rerocc_tile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_d_bits_size_0 = auto_rerocc_tile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_source_0 = auto_rerocc_tile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_sink_0 = auto_rerocc_tile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_denied_0 = auto_rerocc_tile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_d_bits_data_0 = auto_rerocc_tile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_corrupt_0 = auto_rerocc_tile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_ready_0 = auto_rerocc_tile_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_valid_0 = auto_rerocc_tile_re_ro_cc_in_req_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_opcode; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_client_id; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_ready_0 = auto_rerocc_tile_re_ro_cc_in_resp_ready; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in_0 = auto_rerocc_tile_rerocc_manager_id_sink_in; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] ReRoCCManagerTile_1 rerocc_tile ( // @[Integration.scala:45:54] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrl_ctrl_in_a_ready (auto_rerocc_tile_ctrl_ctrl_in_a_ready_0), .auto_ctrl_ctrl_in_a_valid (auto_rerocc_tile_ctrl_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_param (auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_size (auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_source (auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_address (auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_mask (auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_data (auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_corrupt (auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_ready (auto_rerocc_tile_ctrl_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_valid (auto_rerocc_tile_ctrl_ctrl_in_d_valid_0), .auto_ctrl_ctrl_in_d_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0), .auto_ctrl_ctrl_in_d_bits_size (auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0), .auto_ctrl_ctrl_in_d_bits_source (auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0), .auto_ctrl_ctrl_in_d_bits_data (auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0), .auto_buffer_out_a_ready (auto_rerocc_tile_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_rerocc_tile_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_rerocc_tile_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_rerocc_tile_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_rerocc_tile_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_rerocc_tile_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_rerocc_tile_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_rerocc_tile_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_rerocc_tile_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_rerocc_tile_buffer_out_a_bits_corrupt_0), .auto_buffer_out_b_ready (auto_rerocc_tile_buffer_out_b_ready_0), .auto_buffer_out_b_valid (auto_rerocc_tile_buffer_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (auto_rerocc_tile_buffer_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (auto_rerocc_tile_buffer_out_b_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (auto_rerocc_tile_buffer_out_b_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (auto_rerocc_tile_buffer_out_b_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (auto_rerocc_tile_buffer_out_b_bits_address_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (auto_rerocc_tile_buffer_out_b_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (auto_rerocc_tile_buffer_out_b_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (auto_rerocc_tile_buffer_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (auto_rerocc_tile_buffer_out_c_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (auto_rerocc_tile_buffer_out_c_valid_0), .auto_buffer_out_c_bits_opcode (auto_rerocc_tile_buffer_out_c_bits_opcode_0), .auto_buffer_out_c_bits_param (auto_rerocc_tile_buffer_out_c_bits_param_0), .auto_buffer_out_c_bits_size (auto_rerocc_tile_buffer_out_c_bits_size_0), .auto_buffer_out_c_bits_source (auto_rerocc_tile_buffer_out_c_bits_source_0), .auto_buffer_out_c_bits_address (auto_rerocc_tile_buffer_out_c_bits_address_0), .auto_buffer_out_c_bits_data (auto_rerocc_tile_buffer_out_c_bits_data_0), .auto_buffer_out_c_bits_corrupt (auto_rerocc_tile_buffer_out_c_bits_corrupt_0), .auto_buffer_out_d_ready (auto_rerocc_tile_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_rerocc_tile_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_rerocc_tile_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (auto_rerocc_tile_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_rerocc_tile_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_rerocc_tile_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (auto_rerocc_tile_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (auto_rerocc_tile_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_rerocc_tile_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (auto_rerocc_tile_buffer_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (auto_rerocc_tile_buffer_out_e_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (auto_rerocc_tile_buffer_out_e_valid_0), .auto_buffer_out_e_bits_sink (auto_rerocc_tile_buffer_out_e_bits_sink_0), .auto_re_ro_cc_in_req_ready (auto_rerocc_tile_re_ro_cc_in_req_ready_0), .auto_re_ro_cc_in_req_valid (auto_rerocc_tile_re_ro_cc_in_req_valid_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_opcode (auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_client_id (auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_data (auto_rerocc_tile_re_ro_cc_in_req_bits_data_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_ready (auto_rerocc_tile_re_ro_cc_in_resp_ready_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_valid (auto_rerocc_tile_re_ro_cc_in_resp_valid_0), .auto_re_ro_cc_in_resp_bits_opcode (auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0), .auto_re_ro_cc_in_resp_bits_client_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0), .auto_re_ro_cc_in_resp_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0), .auto_re_ro_cc_in_resp_bits_data (auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0), .auto_rerocc_manager_id_sink_in (auto_rerocc_tile_rerocc_manager_id_sink_in_0) // @[ClockDomain.scala:14:9] ); // @[Integration.scala:45:54] assign auto_rerocc_tile_ctrl_ctrl_in_a_ready = auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_valid = auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode = auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_size = auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_source = auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_data = auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_valid = auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_opcode = auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_param = auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_size = auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_source = auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_address = auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_mask = auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_data = auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_corrupt = auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_b_ready = auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_valid = auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_opcode = auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_param = auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_size = auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_source = auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_address = auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_data = auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_corrupt = auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_d_ready = auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_valid = auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_bits_sink = auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_req_ready = auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_valid = auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode = auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_data = auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_20 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_276 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_20( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_276 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_79 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_79( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DTLB_4 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}, flip kill : UInt<1>} node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_70 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_4 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.prv, mpu_priv inst pma of PMAChecker_5 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<18>(0h20000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<15>(0h4000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<18>(0h24000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<13>(0h1000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<13>(0h1000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<17>(0h10000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_51 = cvt(_homogeneous_T_50) node _homogeneous_T_52 = and(_homogeneous_T_51, asSInt(UInt<13>(0h1000))) node _homogeneous_T_53 = asSInt(_homogeneous_T_52) node _homogeneous_T_54 = eq(_homogeneous_T_53, asSInt(UInt<1>(0h0))) node _homogeneous_T_55 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_56 = cvt(_homogeneous_T_55) node _homogeneous_T_57 = and(_homogeneous_T_56, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_58 = asSInt(_homogeneous_T_57) node _homogeneous_T_59 = eq(_homogeneous_T_58, asSInt(UInt<1>(0h0))) node _homogeneous_T_60 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_61 = or(_homogeneous_T_60, _homogeneous_T_9) node _homogeneous_T_62 = or(_homogeneous_T_61, _homogeneous_T_14) node _homogeneous_T_63 = or(_homogeneous_T_62, _homogeneous_T_19) node _homogeneous_T_64 = or(_homogeneous_T_63, _homogeneous_T_24) node _homogeneous_T_65 = or(_homogeneous_T_64, _homogeneous_T_29) node _homogeneous_T_66 = or(_homogeneous_T_65, _homogeneous_T_34) node _homogeneous_T_67 = or(_homogeneous_T_66, _homogeneous_T_39) node _homogeneous_T_68 = or(_homogeneous_T_67, _homogeneous_T_44) node _homogeneous_T_69 = or(_homogeneous_T_68, _homogeneous_T_49) node _homogeneous_T_70 = or(_homogeneous_T_69, _homogeneous_T_54) node homogeneous = or(_homogeneous_T_70, _homogeneous_T_59) node _homogeneous_T_71 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = or(UInt<1>(0h0), _homogeneous_T_76) node _homogeneous_T_78 = eq(_homogeneous_T_77, UInt<1>(0h0)) node _homogeneous_T_79 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_80 = cvt(_homogeneous_T_79) node _homogeneous_T_81 = and(_homogeneous_T_80, asSInt(UInt<33>(0hffff3000))) node _homogeneous_T_82 = asSInt(_homogeneous_T_81) node _homogeneous_T_83 = eq(_homogeneous_T_82, asSInt(UInt<1>(0h0))) node _homogeneous_T_84 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_85 = cvt(_homogeneous_T_84) node _homogeneous_T_86 = and(_homogeneous_T_85, asSInt(UInt<33>(0hffff3000))) node _homogeneous_T_87 = asSInt(_homogeneous_T_86) node _homogeneous_T_88 = eq(_homogeneous_T_87, asSInt(UInt<1>(0h0))) node _homogeneous_T_89 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_90 = cvt(_homogeneous_T_89) node _homogeneous_T_91 = and(_homogeneous_T_90, asSInt(UInt<33>(0hffff0000))) node _homogeneous_T_92 = asSInt(_homogeneous_T_91) node _homogeneous_T_93 = eq(_homogeneous_T_92, asSInt(UInt<1>(0h0))) node _homogeneous_T_94 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_95 = cvt(_homogeneous_T_94) node _homogeneous_T_96 = and(_homogeneous_T_95, asSInt(UInt<33>(0hffff0000))) node _homogeneous_T_97 = asSInt(_homogeneous_T_96) node _homogeneous_T_98 = eq(_homogeneous_T_97, asSInt(UInt<1>(0h0))) node _homogeneous_T_99 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_100 = cvt(_homogeneous_T_99) node _homogeneous_T_101 = and(_homogeneous_T_100, asSInt(UInt<33>(0hf0000000))) node _homogeneous_T_102 = asSInt(_homogeneous_T_101) node _homogeneous_T_103 = eq(_homogeneous_T_102, asSInt(UInt<1>(0h0))) node _homogeneous_T_104 = or(UInt<1>(0h0), _homogeneous_T_83) node _homogeneous_T_105 = or(_homogeneous_T_104, _homogeneous_T_88) node _homogeneous_T_106 = or(_homogeneous_T_105, _homogeneous_T_93) node _homogeneous_T_107 = or(_homogeneous_T_106, _homogeneous_T_98) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_103) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8e020000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_115 = cvt(_homogeneous_T_114) node _homogeneous_T_116 = and(_homogeneous_T_115, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_117 = asSInt(_homogeneous_T_116) node _homogeneous_T_118 = eq(_homogeneous_T_117, asSInt(UInt<1>(0h0))) node _homogeneous_T_119 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_120 = or(_homogeneous_T_119, _homogeneous_T_118) node _homogeneous_T_121 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_122 = cvt(_homogeneous_T_121) node _homogeneous_T_123 = and(_homogeneous_T_122, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_124 = asSInt(_homogeneous_T_123) node _homogeneous_T_125 = eq(_homogeneous_T_124, asSInt(UInt<1>(0h0))) node _homogeneous_T_126 = or(UInt<1>(0h0), _homogeneous_T_125) node _homogeneous_T_127 = eq(_homogeneous_T_126, UInt<1>(0h0)) node _homogeneous_T_128 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_129 = cvt(_homogeneous_T_128) node _homogeneous_T_130 = and(_homogeneous_T_129, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_131 = asSInt(_homogeneous_T_130) node _homogeneous_T_132 = eq(_homogeneous_T_131, asSInt(UInt<1>(0h0))) node _homogeneous_T_133 = or(UInt<1>(0h0), _homogeneous_T_132) node _homogeneous_T_134 = eq(_homogeneous_T_133, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_71 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_72 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_73 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_74 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_75 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_76 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_77 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_78 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_79 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_80 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_81 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_82 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_83 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, UInt<1>(0h0)) node pal_array_if_cached = or(pal_array, UInt<1>(0h0)) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h0), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h0), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h0), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)	module DTLB_4( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input io_req_bits_passthrough, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_st, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_st, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_ma_st, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_must_alloc, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] output [1:0] io_resp_size, // @[TLB.scala:320:14] output [4:0] io_resp_cmd, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [15:0] io_ptw_ptbr_asid, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [15:0] io_ptw_ptbr_asid_0 = io_ptw_ptbr_asid; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _homogeneous_T_71 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire _io_req_ready_T; // @[TLB.scala:631:25] wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [15:0] satp_asid = io_ptw_ptbr_asid_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_st_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_st_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_ma_st_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_must_alloc_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64] wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_79 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T = do_refill \| io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_60 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_84; // @[Parameters.scala:137:31] assign _homogeneous_T_84 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_89; // @[Parameters.scala:137:31] assign _homogeneous_T_89 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_121; // @[Parameters.scala:137:31] assign _homogeneous_T_121 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_128; // @[Parameters.scala:137:31] assign _homogeneous_T_128 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h20000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFFC000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h24000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_30 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_40; // @[Parameters.scala:137:31] assign _homogeneous_T_40 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_94; // @[Parameters.scala:137:31] assign _homogeneous_T_94 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_45 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_50 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_51 = {1'h0, _homogeneous_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_52 = _homogeneous_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_53 = _homogeneous_T_52; // @[Parameters.scala:137:46] wire _homogeneous_T_54 = _homogeneous_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_55; // @[Parameters.scala:137:31] assign _homogeneous_T_55 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_99; // @[Parameters.scala:137:31] assign _homogeneous_T_99 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_114; // @[Parameters.scala:137:31] assign _homogeneous_T_114 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_56 = {1'h0, _homogeneous_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_57 = _homogeneous_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_58 = _homogeneous_T_57; // @[Parameters.scala:137:46] wire _homogeneous_T_59 = _homogeneous_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_61 = _homogeneous_T_60 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_62 = _homogeneous_T_61 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_63 = _homogeneous_T_62 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_64 = _homogeneous_T_63 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_65 = _homogeneous_T_64 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_66 = _homogeneous_T_65 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_67 = _homogeneous_T_66 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_68 = _homogeneous_T_67 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_69 = _homogeneous_T_68 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_70 = _homogeneous_T_69 \| _homogeneous_T_54; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_70 \| _homogeneous_T_59; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_77 = _homogeneous_T_76; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_78 = ~_homogeneous_T_77; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_80 = {1'h0, _homogeneous_T_79}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_81 = _homogeneous_T_80 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_82 = _homogeneous_T_81; // @[Parameters.scala:137:46] wire _homogeneous_T_83 = _homogeneous_T_82 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_104 = _homogeneous_T_83; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_85 = {1'h0, _homogeneous_T_84}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_86 = _homogeneous_T_85 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_87 = _homogeneous_T_86; // @[Parameters.scala:137:46] wire _homogeneous_T_88 = _homogeneous_T_87 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_90 = {1'h0, _homogeneous_T_89}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_91 = _homogeneous_T_90 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_92 = _homogeneous_T_91; // @[Parameters.scala:137:46] wire _homogeneous_T_93 = _homogeneous_T_92 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_95 = {1'h0, _homogeneous_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_96 = _homogeneous_T_95 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_97 = _homogeneous_T_96; // @[Parameters.scala:137:46] wire _homogeneous_T_98 = _homogeneous_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_100 = {1'h0, _homogeneous_T_99}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_101 = _homogeneous_T_100 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_102 = _homogeneous_T_101; // @[Parameters.scala:137:46] wire _homogeneous_T_103 = _homogeneous_T_102 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_105 = _homogeneous_T_104 \| _homogeneous_T_88; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_106 = _homogeneous_T_105 \| _homogeneous_T_93; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_107 = _homogeneous_T_106 \| _homogeneous_T_98; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_103; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8E020000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_119 = _homogeneous_T_113; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_115 = {1'h0, _homogeneous_T_114}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_116 = _homogeneous_T_115 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_117 = _homogeneous_T_116; // @[Parameters.scala:137:46] wire _homogeneous_T_118 = _homogeneous_T_117 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_120 = _homogeneous_T_119 \| _homogeneous_T_118; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_122 = {1'h0, _homogeneous_T_121}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_123 = _homogeneous_T_122 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_124 = _homogeneous_T_123; // @[Parameters.scala:137:46] wire _homogeneous_T_125 = _homogeneous_T_124 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_126 = _homogeneous_T_125; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_127 = ~_homogeneous_T_126; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_129 = {1'h0, _homogeneous_T_128}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_130 = _homogeneous_T_129 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_131 = _homogeneous_T_130; // @[Parameters.scala:137:46] wire _homogeneous_T_132 = _homogeneous_T_131 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_133 = _homogeneous_T_132; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_134 = ~_homogeneous_T_133; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1; // @[TLB.scala:429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1; // @[TLB.scala:430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1; // @[TLB.scala:434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 \| sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 \| sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 \| sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 \| sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 \| sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 \| sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 \| sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 \| sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 \| _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 \| _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 \| _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 \| _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 \| _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 \| _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 \| _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 \| _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 \| _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 \| _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 \| _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 \| _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 \| _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 \| _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 \| _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 \| _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 \| _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 \| _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 \| _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 \| _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 \| _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 \| _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T \| sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 \| _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [13:0] paa_array_if_cached = paa_array; // @[TLB.scala:541:22, :545:39] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pal_array_if_cached = pal_array; // @[TLB.scala:543:22, :546:39] wire [13:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47] wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5; // @[TLB.scala:588:53, :589:53] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] ae_st_array = _ae_st_array_T_8; // @[TLB.scala:589:53, :590:53] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1; // @[TLB.scala:593:{8,43}] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4; // @[TLB.scala:593:43, :594:43] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] must_alloc_array = _must_alloc_array_T_7; // @[TLB.scala:594:43, :595:46] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 \| lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {\|hi_1, \|hi_2, hi_2[1] \| lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {\|hi_4, hi_4[1] \| lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 \| _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 \| _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 \| multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 \| multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 \| _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 \| multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 \| multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 \| multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 \| multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 \| _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 \| multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 \| multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 \| _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 \| multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 \| multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 \| _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 \| sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 \| sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 \| sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 \| sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = \|r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 \| r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 \| superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T \| superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 \| superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = \|r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 \| r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_32 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_32( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h1)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h8)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 4) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<4>(0h8)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_13 node _source_ok_T_14 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_15 = or(_source_ok_T_14, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_15, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h1)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h8)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_25 = shr(io.in.a.bits.source, 4) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<4>(0h8)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _T_38 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = or(_T_39, _T_44) node _T_46 = and(_T_16, _T_24) node _T_47 = and(_T_46, _T_37) node _T_48 = and(_T_47, _T_45) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_48, UInt<1>(0h1), "") : assert_1 node _T_52 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_52 : node _T_53 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_54 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_55 = and(_T_53, _T_54) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_56 = shr(io.in.a.bits.source, 4) node _T_57 = eq(_T_56, UInt<1>(0h1)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_2) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_2, UInt<4>(0h8)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_63 = shr(io.in.a.bits.source, 4) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = leq(UInt<1>(0h0), uncommonBits_3) node _T_66 = and(_T_64, _T_65) node _T_67 = leq(uncommonBits_3, UInt<4>(0h8)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_70 = or(_T_61, _T_62) node _T_71 = or(_T_70, _T_68) node _T_72 = or(_T_71, _T_69) node _T_73 = and(_T_55, _T_72) node _T_74 = or(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<13>(0h1000))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_82 = cvt(_T_81) node _T_83 = and(_T_82, asSInt(UInt<18>(0h2f000))) node _T_84 = asSInt(_T_83) node _T_85 = eq(_T_84, asSInt(UInt<1>(0h0))) node _T_86 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<13>(0h1000))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = or(_T_80, _T_85) node _T_92 = or(_T_91, _T_90) node _T_93 = and(_T_75, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = and(_T_74, _T_94) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_95, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_99 = shr(io.in.a.bits.source, 4) node _T_100 = eq(_T_99, UInt<1>(0h1)) node _T_101 = leq(UInt<1>(0h0), uncommonBits_4) node _T_102 = and(_T_100, _T_101) node _T_103 = leq(uncommonBits_4, UInt<4>(0h8)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_106 = shr(io.in.a.bits.source, 4) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = leq(UInt<1>(0h0), uncommonBits_5) node _T_109 = and(_T_107, _T_108) node _T_110 = leq(uncommonBits_5, UInt<4>(0h8)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE : UInt<1>[4] connect _WIRE[0], _T_104 connect _WIRE[1], _T_105 connect _WIRE[2], _T_111 connect _WIRE[3], _T_112 node _T_113 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_114 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_115 = mux(_WIRE[0], _T_113, UInt<1>(0h0)) node _T_116 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_117 = mux(_WIRE[2], _T_114, UInt<1>(0h0)) node _T_118 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = or(_T_115, _T_116) node _T_120 = or(_T_119, _T_117) node _T_121 = or(_T_120, _T_118) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<18>(0h2f000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<13>(0h1000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = or(_T_130, _T_135) node _T_142 = or(_T_141, _T_140) node _T_143 = and(_T_125, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = and(_WIRE_1, _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_145, UInt<1>(0h1), "") : assert_3 node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(source_ok, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_152 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_152, UInt<1>(0h1), "") : assert_5 node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(is_aligned, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_159 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_159, UInt<1>(0h1), "") : assert_7 node _T_163 = not(io.in.a.bits.mask) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_164, UInt<1>(0h1), "") : assert_8 node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_168, UInt<1>(0h1), "") : assert_9 node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_172 : node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_176 = shr(io.in.a.bits.source, 4) node _T_177 = eq(_T_176, UInt<1>(0h1)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_6) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_6, UInt<4>(0h8)) node _T_181 = and(_T_179, _T_180) node _T_182 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_183 = shr(io.in.a.bits.source, 4) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = leq(UInt<1>(0h0), uncommonBits_7) node _T_186 = and(_T_184, _T_185) node _T_187 = leq(uncommonBits_7, UInt<4>(0h8)) node _T_188 = and(_T_186, _T_187) node _T_189 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_190 = or(_T_181, _T_182) node _T_191 = or(_T_190, _T_188) node _T_192 = or(_T_191, _T_189) node _T_193 = and(_T_175, _T_192) node _T_194 = or(UInt<1>(0h0), _T_193) node _T_195 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<18>(0h2f000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<13>(0h1000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = or(_T_200, _T_205) node _T_212 = or(_T_211, _T_210) node _T_213 = and(_T_195, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_194, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_215, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_219 = shr(io.in.a.bits.source, 4) node _T_220 = eq(_T_219, UInt<1>(0h1)) node _T_221 = leq(UInt<1>(0h0), uncommonBits_8) node _T_222 = and(_T_220, _T_221) node _T_223 = leq(uncommonBits_8, UInt<4>(0h8)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_226 = shr(io.in.a.bits.source, 4) node _T_227 = eq(_T_226, UInt<1>(0h0)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_9) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_9, UInt<4>(0h8)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], _T_224 connect _WIRE_2[1], _T_225 connect _WIRE_2[2], _T_231 connect _WIRE_2[3], _T_232 node _T_233 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_234 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_235 = mux(_WIRE_2[0], _T_233, UInt<1>(0h0)) node _T_236 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE_2[2], _T_234, UInt<1>(0h0)) node _T_238 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = or(_T_235, _T_236) node _T_240 = or(_T_239, _T_237) node _T_241 = or(_T_240, _T_238) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_241 node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<18>(0h2f000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_250, _T_255) node _T_262 = or(_T_261, _T_260) node _T_263 = and(_T_245, _T_262) node _T_264 = or(UInt<1>(0h0), _T_263) node _T_265 = and(_WIRE_3, _T_264) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_265, UInt<1>(0h1), "") : assert_11 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(source_ok, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_272 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_272, UInt<1>(0h1), "") : assert_13 node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(is_aligned, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_279 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_280 = asUInt(reset) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(_T_279, UInt<1>(0h0)) when _T_282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_279, UInt<1>(0h1), "") : assert_15 node _T_283 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_284 = asUInt(reset) node _T_285 = eq(_T_284, UInt<1>(0h0)) when _T_285 : node _T_286 = eq(_T_283, UInt<1>(0h0)) when _T_286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_283, UInt<1>(0h1), "") : assert_16 node _T_287 = not(io.in.a.bits.mask) node _T_288 = eq(_T_287, UInt<1>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_288, UInt<1>(0h1), "") : assert_17 node _T_292 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_292, UInt<1>(0h1), "") : assert_18 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_300 = shr(io.in.a.bits.source, 4) node _T_301 = eq(_T_300, UInt<1>(0h1)) node _T_302 = leq(UInt<1>(0h0), uncommonBits_10) node _T_303 = and(_T_301, _T_302) node _T_304 = leq(uncommonBits_10, UInt<4>(0h8)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_307 = shr(io.in.a.bits.source, 4) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_11) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_11, UInt<4>(0h8)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_314 = or(_T_305, _T_306) node _T_315 = or(_T_314, _T_312) node _T_316 = or(_T_315, _T_313) node _T_317 = and(_T_299, _T_316) node _T_318 = or(UInt<1>(0h0), _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_318, UInt<1>(0h1), "") : assert_19 node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = and(_T_325, _T_330) node _T_332 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_333 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_334 = and(_T_332, _T_333) node _T_335 = or(UInt<1>(0h0), _T_334) node _T_336 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<18>(0h2f000))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<13>(0h1000))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = or(_T_340, _T_345) node _T_347 = and(_T_335, _T_346) node _T_348 = or(UInt<1>(0h0), _T_331) node _T_349 = or(_T_348, _T_347) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_349, UInt<1>(0h1), "") : assert_20 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(source_ok, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(is_aligned, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_359 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_359, UInt<1>(0h1), "") : assert_23 node _T_363 = eq(io.in.a.bits.mask, mask) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_363, UInt<1>(0h1), "") : assert_24 node _T_367 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_367, UInt<1>(0h1), "") : assert_25 node _T_371 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_371 : node _T_372 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_373 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_374 = and(_T_372, _T_373) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_375 = shr(io.in.a.bits.source, 4) node _T_376 = eq(_T_375, UInt<1>(0h1)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_12) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_12, UInt<4>(0h8)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_382 = shr(io.in.a.bits.source, 4) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_13) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_13, UInt<4>(0h8)) node _T_387 = and(_T_385, _T_386) node _T_388 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_389 = or(_T_380, _T_381) node _T_390 = or(_T_389, _T_387) node _T_391 = or(_T_390, _T_388) node _T_392 = and(_T_374, _T_391) node _T_393 = or(UInt<1>(0h0), _T_392) node _T_394 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_395 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_396 = and(_T_394, _T_395) node _T_397 = or(UInt<1>(0h0), _T_396) node _T_398 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_399 = cvt(_T_398) node _T_400 = and(_T_399, asSInt(UInt<13>(0h1000))) node _T_401 = asSInt(_T_400) node _T_402 = eq(_T_401, asSInt(UInt<1>(0h0))) node _T_403 = and(_T_397, _T_402) node _T_404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_405 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_406 = and(_T_404, _T_405) node _T_407 = or(UInt<1>(0h0), _T_406) node _T_408 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_409 = cvt(_T_408) node _T_410 = and(_T_409, asSInt(UInt<18>(0h2f000))) node _T_411 = asSInt(_T_410) node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0))) node _T_413 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_414 = cvt(_T_413) node _T_415 = and(_T_414, asSInt(UInt<13>(0h1000))) node _T_416 = asSInt(_T_415) node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0))) node _T_418 = or(_T_412, _T_417) node _T_419 = and(_T_407, _T_418) node _T_420 = or(UInt<1>(0h0), _T_403) node _T_421 = or(_T_420, _T_419) node _T_422 = and(_T_393, _T_421) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_422, UInt<1>(0h1), "") : assert_26 node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(source_ok, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(is_aligned, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_432 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_432, UInt<1>(0h1), "") : assert_29 node _T_436 = eq(io.in.a.bits.mask, mask) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_436, UInt<1>(0h1), "") : assert_30 node _T_440 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_440 : node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_444 = shr(io.in.a.bits.source, 4) node _T_445 = eq(_T_444, UInt<1>(0h1)) node _T_446 = leq(UInt<1>(0h0), uncommonBits_14) node _T_447 = and(_T_445, _T_446) node _T_448 = leq(uncommonBits_14, UInt<4>(0h8)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_451 = shr(io.in.a.bits.source, 4) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = leq(UInt<1>(0h0), uncommonBits_15) node _T_454 = and(_T_452, _T_453) node _T_455 = leq(uncommonBits_15, UInt<4>(0h8)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_458 = or(_T_449, _T_450) node _T_459 = or(_T_458, _T_456) node _T_460 = or(_T_459, _T_457) node _T_461 = and(_T_443, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<18>(0h2f000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<13>(0h1000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = or(_T_481, _T_486) node _T_488 = and(_T_476, _T_487) node _T_489 = or(UInt<1>(0h0), _T_472) node _T_490 = or(_T_489, _T_488) node _T_491 = and(_T_462, _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_491, UInt<1>(0h1), "") : assert_31 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(source_ok, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(is_aligned, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_501 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_501, UInt<1>(0h1), "") : assert_34 node _T_505 = not(mask) node _T_506 = and(io.in.a.bits.mask, _T_505) node _T_507 = eq(_T_506, UInt<1>(0h0)) node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_T_507, UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_507, UInt<1>(0h1), "") : assert_35 node _T_511 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_511 : node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_515 = shr(io.in.a.bits.source, 4) node _T_516 = eq(_T_515, UInt<1>(0h1)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_16) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_16, UInt<4>(0h8)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_522 = shr(io.in.a.bits.source, 4) node _T_523 = eq(_T_522, UInt<1>(0h0)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_17) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_17, UInt<4>(0h8)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_529 = or(_T_520, _T_521) node _T_530 = or(_T_529, _T_527) node _T_531 = or(_T_530, _T_528) node _T_532 = and(_T_514, _T_531) node _T_533 = or(UInt<1>(0h0), _T_532) node _T_534 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_535 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_536 = and(_T_534, _T_535) node _T_537 = or(UInt<1>(0h0), _T_536) node _T_538 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_539 = cvt(_T_538) node _T_540 = and(_T_539, asSInt(UInt<13>(0h1000))) node _T_541 = asSInt(_T_540) node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0))) node _T_543 = and(_T_537, _T_542) node _T_544 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_546 = cvt(_T_545) node _T_547 = and(_T_546, asSInt(UInt<18>(0h2f000))) node _T_548 = asSInt(_T_547) node _T_549 = eq(_T_548, asSInt(UInt<1>(0h0))) node _T_550 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_551 = cvt(_T_550) node _T_552 = and(_T_551, asSInt(UInt<13>(0h1000))) node _T_553 = asSInt(_T_552) node _T_554 = eq(_T_553, asSInt(UInt<1>(0h0))) node _T_555 = or(_T_549, _T_554) node _T_556 = and(_T_544, _T_555) node _T_557 = or(UInt<1>(0h0), _T_543) node _T_558 = or(_T_557, _T_556) node _T_559 = and(_T_533, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_559, UInt<1>(0h1), "") : assert_36 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_569 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_569, UInt<1>(0h1), "") : assert_39 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_573, UInt<1>(0h1), "") : assert_40 node _T_577 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_577 : node _T_578 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_579 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 3, 0) node _T_581 = shr(io.in.a.bits.source, 4) node _T_582 = eq(_T_581, UInt<1>(0h1)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_18) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_18, UInt<4>(0h8)) node _T_586 = and(_T_584, _T_585) node _T_587 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 3, 0) node _T_588 = shr(io.in.a.bits.source, 4) node _T_589 = eq(_T_588, UInt<1>(0h0)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_19) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_19, UInt<4>(0h8)) node _T_593 = and(_T_591, _T_592) node _T_594 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_595 = or(_T_586, _T_587) node _T_596 = or(_T_595, _T_593) node _T_597 = or(_T_596, _T_594) node _T_598 = and(_T_580, _T_597) node _T_599 = or(UInt<1>(0h0), _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = and(_T_603, _T_608) node _T_610 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_611 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_612 = cvt(_T_611) node _T_613 = and(_T_612, asSInt(UInt<18>(0h2f000))) node _T_614 = asSInt(_T_613) node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0))) node _T_616 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<13>(0h1000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = or(_T_615, _T_620) node _T_622 = and(_T_610, _T_621) node _T_623 = or(UInt<1>(0h0), _T_609) node _T_624 = or(_T_623, _T_622) node _T_625 = and(_T_599, _T_624) node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(_T_625, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_625, UInt<1>(0h1), "") : assert_41 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(source_ok, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(is_aligned, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_635 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_635, UInt<1>(0h1), "") : assert_44 node _T_639 = eq(io.in.a.bits.mask, mask) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_639, UInt<1>(0h1), "") : assert_45 node _T_643 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_643 : node _T_644 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_645 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_646 = and(_T_644, _T_645) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 3, 0) node _T_647 = shr(io.in.a.bits.source, 4) node _T_648 = eq(_T_647, UInt<1>(0h1)) node _T_649 = leq(UInt<1>(0h0), uncommonBits_20) node _T_650 = and(_T_648, _T_649) node _T_651 = leq(uncommonBits_20, UInt<4>(0h8)) node _T_652 = and(_T_650, _T_651) node _T_653 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 3, 0) node _T_654 = shr(io.in.a.bits.source, 4) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_21) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_21, UInt<4>(0h8)) node _T_659 = and(_T_657, _T_658) node _T_660 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_661 = or(_T_652, _T_653) node _T_662 = or(_T_661, _T_659) node _T_663 = or(_T_662, _T_660) node _T_664 = and(_T_646, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<13>(0h1000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = and(_T_669, _T_674) node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<18>(0h2f000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_683 = cvt(_T_682) node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000))) node _T_685 = asSInt(_T_684) node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0))) node _T_687 = or(_T_681, _T_686) node _T_688 = and(_T_676, _T_687) node _T_689 = or(UInt<1>(0h0), _T_675) node _T_690 = or(_T_689, _T_688) node _T_691 = and(_T_665, _T_690) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_691, UInt<1>(0h1), "") : assert_46 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(source_ok, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(is_aligned, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_701 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_701, UInt<1>(0h1), "") : assert_49 node _T_705 = eq(io.in.a.bits.mask, mask) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_705, UInt<1>(0h1), "") : assert_50 node _T_709 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_709, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_713 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_713, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_16 = shr(io.in.d.bits.source, 4) node _source_ok_T_17 = eq(_source_ok_T_16, UInt<1>(0h1)) node _source_ok_T_18 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = leq(source_ok_uncommonBits_2, UInt<4>(0h8)) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = eq(io.in.d.bits.source, UInt<5>(0h19)) node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0) node _source_ok_T_23 = shr(io.in.d.bits.source, 4) node _source_ok_T_24 = eq(_source_ok_T_23, UInt<1>(0h0)) node _source_ok_T_25 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_26 = and(_source_ok_T_24, _source_ok_T_25) node _source_ok_T_27 = leq(source_ok_uncommonBits_3, UInt<4>(0h8)) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = eq(io.in.d.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_21 connect _source_ok_WIRE_1[1], _source_ok_T_22 connect _source_ok_WIRE_1[2], _source_ok_T_28 connect _source_ok_WIRE_1[3], _source_ok_T_29 node _source_ok_T_30 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_31, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_717 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_717 : node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(source_ok_1, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_721 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_721, UInt<1>(0h1), "") : assert_54 node _T_725 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_725, UInt<1>(0h1), "") : assert_55 node _T_729 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_729, UInt<1>(0h1), "") : assert_56 node _T_733 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_734 = asUInt(reset) node _T_735 = eq(_T_734, UInt<1>(0h0)) when _T_735 : node _T_736 = eq(_T_733, UInt<1>(0h0)) when _T_736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_733, UInt<1>(0h1), "") : assert_57 node _T_737 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_737 : node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(source_ok_1, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(sink_ok, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_744 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_744, UInt<1>(0h1), "") : assert_60 node _T_748 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_748, UInt<1>(0h1), "") : assert_61 node _T_752 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(_T_752, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_752, UInt<1>(0h1), "") : assert_62 node _T_756 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(_T_756, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_756, UInt<1>(0h1), "") : assert_63 node _T_760 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_761 = or(UInt<1>(0h1), _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_761, UInt<1>(0h1), "") : assert_64 node _T_765 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_765 : node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(source_ok_1, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(sink_ok, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_772 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_772, UInt<1>(0h1), "") : assert_67 node _T_776 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(_T_776, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_776, UInt<1>(0h1), "") : assert_68 node _T_780 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_780, UInt<1>(0h1), "") : assert_69 node _T_784 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_785 = or(_T_784, io.in.d.bits.corrupt) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_785, UInt<1>(0h1), "") : assert_70 node _T_789 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_790 = or(UInt<1>(0h1), _T_789) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_790, UInt<1>(0h1), "") : assert_71 node _T_794 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_794 : node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(source_ok_1, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_798 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_798, UInt<1>(0h1), "") : assert_73 node _T_802 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_802, UInt<1>(0h1), "") : assert_74 node _T_806 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_807 = or(UInt<1>(0h1), _T_806) node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(_T_807, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_807, UInt<1>(0h1), "") : assert_75 node _T_811 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_811 : node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(source_ok_1, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_815 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(_T_815, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_815, UInt<1>(0h1), "") : assert_77 node _T_819 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_820 = or(_T_819, io.in.d.bits.corrupt) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_820, UInt<1>(0h1), "") : assert_78 node _T_824 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_825 = or(UInt<1>(0h1), _T_824) node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_T_825, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_825, UInt<1>(0h1), "") : assert_79 node _T_829 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_829 : node _T_830 = asUInt(reset) node _T_831 = eq(_T_830, UInt<1>(0h0)) when _T_831 : node _T_832 = eq(source_ok_1, UInt<1>(0h0)) when _T_832 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_833 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(_T_833, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_833, UInt<1>(0h1), "") : assert_81 node _T_837 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_837, UInt<1>(0h1), "") : assert_82 node _T_841 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_842 = or(UInt<1>(0h1), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_842, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_846 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_846, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_850 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_850, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_854 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_854, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_858 = eq(a_first, UInt<1>(0h0)) node _T_859 = and(io.in.a.valid, _T_858) when _T_859 : node _T_860 = eq(io.in.a.bits.opcode, opcode) node _T_861 = asUInt(reset) node _T_862 = eq(_T_861, UInt<1>(0h0)) when _T_862 : node _T_863 = eq(_T_860, UInt<1>(0h0)) when _T_863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_860, UInt<1>(0h1), "") : assert_87 node _T_864 = eq(io.in.a.bits.param, param) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_864, UInt<1>(0h1), "") : assert_88 node _T_868 = eq(io.in.a.bits.size, size) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_868, UInt<1>(0h1), "") : assert_89 node _T_872 = eq(io.in.a.bits.source, source) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_872, UInt<1>(0h1), "") : assert_90 node _T_876 = eq(io.in.a.bits.address, address) node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(_T_876, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_876, UInt<1>(0h1), "") : assert_91 node _T_880 = and(io.in.a.ready, io.in.a.valid) node _T_881 = and(_T_880, a_first) when _T_881 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_882 = eq(d_first, UInt<1>(0h0)) node _T_883 = and(io.in.d.valid, _T_882) when _T_883 : node _T_884 = eq(io.in.d.bits.opcode, opcode_1) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_884, UInt<1>(0h1), "") : assert_92 node _T_888 = eq(io.in.d.bits.param, param_1) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_888, UInt<1>(0h1), "") : assert_93 node _T_892 = eq(io.in.d.bits.size, size_1) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_892, UInt<1>(0h1), "") : assert_94 node _T_896 = eq(io.in.d.bits.source, source_1) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_896, UInt<1>(0h1), "") : assert_95 node _T_900 = eq(io.in.d.bits.sink, sink) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_900, UInt<1>(0h1), "") : assert_96 node _T_904 = eq(io.in.d.bits.denied, denied) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_904, UInt<1>(0h1), "") : assert_97 node _T_908 = and(io.in.d.ready, io.in.d.valid) node _T_909 = and(_T_908, d_first) when _T_909 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<26>, clock, reset, UInt<26>(0h0) regreset inflight_opcodes : UInt<104>, clock, reset, UInt<104>(0h0) regreset inflight_sizes : UInt<208>, clock, reset, UInt<208>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<26> connect a_set, UInt<26>(0h0) wire a_set_wo_ready : UInt<26> connect a_set_wo_ready, UInt<26>(0h0) wire a_opcodes_set : UInt<104> connect a_opcodes_set, UInt<104>(0h0) wire a_sizes_set : UInt<208> connect a_sizes_set, UInt<208>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_910 = and(io.in.a.valid, a_first_1) node _T_911 = and(_T_910, UInt<1>(0h1)) when _T_911 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_912 = and(io.in.a.ready, io.in.a.valid) node _T_913 = and(_T_912, a_first_1) node _T_914 = and(_T_913, UInt<1>(0h1)) when _T_914 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_915 = dshr(inflight, io.in.a.bits.source) node _T_916 = bits(_T_915, 0, 0) node _T_917 = eq(_T_916, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_917, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<26> connect d_clr, UInt<26>(0h0) wire d_clr_wo_ready : UInt<26> connect d_clr_wo_ready, UInt<26>(0h0) wire d_opcodes_clr : UInt<104> connect d_opcodes_clr, UInt<104>(0h0) wire d_sizes_clr : UInt<208> connect d_sizes_clr, UInt<208>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_921 = and(io.in.d.valid, d_first_1) node _T_922 = and(_T_921, UInt<1>(0h1)) node _T_923 = eq(d_release_ack, UInt<1>(0h0)) node _T_924 = and(_T_922, _T_923) when _T_924 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_925 = and(io.in.d.ready, io.in.d.valid) node _T_926 = and(_T_925, d_first_1) node _T_927 = and(_T_926, UInt<1>(0h1)) node _T_928 = eq(d_release_ack, UInt<1>(0h0)) node _T_929 = and(_T_927, _T_928) when _T_929 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_930 = and(io.in.d.valid, d_first_1) node _T_931 = and(_T_930, UInt<1>(0h1)) node _T_932 = eq(d_release_ack, UInt<1>(0h0)) node _T_933 = and(_T_931, _T_932) when _T_933 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_934 = dshr(inflight, io.in.d.bits.source) node _T_935 = bits(_T_934, 0, 0) node _T_936 = or(_T_935, same_cycle_resp) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_936, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_940 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_941 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_942 = or(_T_940, _T_941) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_942, UInt<1>(0h1), "") : assert_100 node _T_946 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_946, UInt<1>(0h1), "") : assert_101 else : node _T_950 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_951 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_952 = or(_T_950, _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_952, UInt<1>(0h1), "") : assert_102 node _T_956 = eq(io.in.d.bits.size, a_size_lookup) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_956, UInt<1>(0h1), "") : assert_103 node _T_960 = and(io.in.d.valid, d_first_1) node _T_961 = and(_T_960, a_first_1) node _T_962 = and(_T_961, io.in.a.valid) node _T_963 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_964 = and(_T_962, _T_963) node _T_965 = eq(d_release_ack, UInt<1>(0h0)) node _T_966 = and(_T_964, _T_965) when _T_966 : node _T_967 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_968 = or(_T_967, io.in.a.ready) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_968, UInt<1>(0h1), "") : assert_104 node _T_972 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_973 = orr(a_set_wo_ready) node _T_974 = eq(_T_973, UInt<1>(0h0)) node _T_975 = or(_T_972, _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_975, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_979 = orr(inflight) node _T_980 = eq(_T_979, UInt<1>(0h0)) node _T_981 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_982 = or(_T_980, _T_981) node _T_983 = lt(watchdog, plusarg_reader.out) node _T_984 = or(_T_982, _T_983) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_984, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_988 = and(io.in.a.ready, io.in.a.valid) node _T_989 = and(io.in.d.ready, io.in.d.valid) node _T_990 = or(_T_988, _T_989) when _T_990 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<26>, clock, reset, UInt<26>(0h0) regreset inflight_opcodes_1 : UInt<104>, clock, reset, UInt<104>(0h0) regreset inflight_sizes_1 : UInt<208>, clock, reset, UInt<208>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<26> connect c_set, UInt<26>(0h0) wire c_set_wo_ready : UInt<26> connect c_set_wo_ready, UInt<26>(0h0) wire c_opcodes_set : UInt<104> connect c_opcodes_set, UInt<104>(0h0) wire c_sizes_set : UInt<208> connect c_sizes_set, UInt<208>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_991 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_992 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_993 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_994 = and(_T_992, _T_993) node _T_995 = and(_T_991, _T_994) when _T_995 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_996 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_997 = and(_T_996, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_998 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_999 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1000 = and(_T_998, _T_999) node _T_1001 = and(_T_997, _T_1000) when _T_1001 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1002 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1003 = bits(_T_1002, 0, 0) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<26> connect d_clr_1, UInt<26>(0h0) wire d_clr_wo_ready_1 : UInt<26> connect d_clr_wo_ready_1, UInt<26>(0h0) wire d_opcodes_clr_1 : UInt<104> connect d_opcodes_clr_1, UInt<104>(0h0) wire d_sizes_clr_1 : UInt<208> connect d_sizes_clr_1, UInt<208>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1008 = and(io.in.d.valid, d_first_2) node _T_1009 = and(_T_1008, UInt<1>(0h1)) node _T_1010 = and(_T_1009, d_release_ack_1) when _T_1010 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1011 = and(io.in.d.ready, io.in.d.valid) node _T_1012 = and(_T_1011, d_first_2) node _T_1013 = and(_T_1012, UInt<1>(0h1)) node _T_1014 = and(_T_1013, d_release_ack_1) when _T_1014 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1015 = and(io.in.d.valid, d_first_2) node _T_1016 = and(_T_1015, UInt<1>(0h1)) node _T_1017 = and(_T_1016, d_release_ack_1) when _T_1017 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1018 = dshr(inflight_1, io.in.d.bits.source) node _T_1019 = bits(_T_1018, 0, 0) node _T_1020 = or(_T_1019, same_cycle_resp_1) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1024 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_109 else : node _T_1028 = eq(io.in.d.bits.size, c_size_lookup) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_110 node _T_1032 = and(io.in.d.valid, d_first_2) node _T_1033 = and(_T_1032, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1034 = and(_T_1033, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1035 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = and(_T_1036, d_release_ack_1) node _T_1038 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1039 = and(_T_1037, _T_1038) when _T_1039 : node _T_1040 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<5>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1041 = or(_T_1040, _WIRE_27.ready) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_111 node _T_1045 = orr(c_set_wo_ready) when _T_1045 : node _T_1046 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1050 = orr(inflight_1) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) node _T_1052 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1053 = or(_T_1051, _T_1052) node _T_1054 = lt(watchdog_1, plusarg_reader_1.out) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<5>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1059 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1060 = and(io.in.d.ready, io.in.d.valid) node _T_1061 = or(_T_1059, _T_1060) when _T_1061 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_18 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_25 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] c_set = 26'h0; // @[Monitor.scala:738:34] wire [25:0] c_set_wo_ready = 26'h0; // @[Monitor.scala:739:34] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [207:0] c_sizes_set = 208'h0; // @[Monitor.scala:741:34] wire [103:0] c_opcodes_set = 104'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_7 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 5'h19; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = ~_source_ok_T_7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_10 & _source_ok_T_11; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_a_bits_source_0 == 5'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_3 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire _source_ok_T_14 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_15 = _source_ok_T_14 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_15 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_16 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_23 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_19 = _source_ok_T_17; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_20 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_21 = _source_ok_T_19 & _source_ok_T_20; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_21; // @[Parameters.scala:1138:31] wire _source_ok_T_22 = io_in_d_bits_source_0 == 5'h19; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_22; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_24 = ~_source_ok_T_23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_26 = _source_ok_T_24; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_27 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_28 = _source_ok_T_26 & _source_ok_T_27; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_2 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_d_bits_source_0 == 5'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_3 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_31 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_988 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_988; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_988; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_1061 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1061; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1061; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1061; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [25:0] inflight; // @[Monitor.scala:614:27] reg [103:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [207:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [25:0] a_set; // @[Monitor.scala:626:34] wire [25:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [103:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [207:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [103:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [103:0] _a_opcode_lookup_T_6 = {100'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [103:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [207:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [207:0] _a_size_lookup_T_6 = {200'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [207:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[207:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_914 = _T_988 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_914 ? _a_set_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_914 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_914 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_914 ? _a_opcodes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_914 ? _a_sizes_set_T_1[207:0] : 208'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [25:0] d_clr; // @[Monitor.scala:664:34] wire [25:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [103:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [207:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_960 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_960 & ~d_release_ack ? _d_clr_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_929 = _T_1061 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_929 ? _d_clr_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_929 ? _d_opcodes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_929 ? _d_sizes_clr_T_5[207:0] : 208'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [25:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [25:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [25:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [103:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [103:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [103:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [207:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [207:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [207:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [25:0] inflight_1; // @[Monitor.scala:726:35] wire [25:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [103:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [103:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [207:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [207:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [103:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [103:0] _c_opcode_lookup_T_6 = {100'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [103:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [207:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [207:0] _c_size_lookup_T_6 = {200'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [207:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[207:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [25:0] d_clr_1; // @[Monitor.scala:774:34] wire [25:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [103:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [207:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1032 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1032 & d_release_ack_1 ? _d_clr_wo_ready_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_1014 = _T_1061 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1014 ? _d_clr_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1014 ? _d_opcodes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1014 ? _d_sizes_clr_T_11[207:0] : 208'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [25:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [25:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [103:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [103:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [207:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [207:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MSHR_62 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_62( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_57 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_117 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_118 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_13 : input clock : Clock input reset : Reset output io : { req : { flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}}, resp : { `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<13> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 11, 11) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_plaInput, 1, 1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput, 2, 2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_plaInput, 3, 3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 11, 11) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_lo = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_2 = orr(_decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_1 = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 1, 0) node _decoded_T_1 = bits(_decoded_T, 0, 0) node _decoded_T_2 = bits(_decoded_T, 1, 1) node _decoded_T_3 = cat(_decoded_T_1, _decoded_T_2) node _decoded_T_4 = bits(decoded_plaOutput, 3, 2) node _decoded_T_5 = bits(_decoded_T_4, 0, 0) node _decoded_T_6 = bits(_decoded_T_4, 1, 1) node _decoded_T_7 = cat(_decoded_T_5, _decoded_T_6) node decoded = cat(_decoded_T_3, _decoded_T_7) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<13> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<4> node _decoded_orMatrixOutputs_T_3 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 3, 3) node decoded_invMatrixOutputs_lo_1 = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_1 = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_8 = bits(decoded_plaOutput_1, 1, 0) node _decoded_T_9 = bits(_decoded_T_8, 0, 0) node _decoded_T_10 = bits(_decoded_T_8, 1, 1) node _decoded_T_11 = cat(_decoded_T_9, _decoded_T_10) node _decoded_T_12 = bits(decoded_plaOutput_1, 3, 2) node _decoded_T_13 = bits(_decoded_T_12, 0, 0) node _decoded_T_14 = bits(_decoded_T_12, 1, 1) node _decoded_T_15 = cat(_decoded_T_13, _decoded_T_14) node decoded_1 = cat(_decoded_T_11, _decoded_T_15) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_31 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20

module RouteComputer_13( // @[RouteComputer.scala:29:7] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_3 // @[RouteComputer.scala:40:14] ); wire [11:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] assign io_resp_0_vc_sel_0_2 = |{&{decoded_invInputs[0], decoded_invInputs[11]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[0]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_3 = &{decoded_invInputs[0], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_341 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_85 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_341( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_85 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_126 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_140 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_126( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_140 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<4>(0h8)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_141 = shr(io.in.a.bits.source, 2) node _T_142 = eq(_T_141, UInt<4>(0h8)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<4>(0h8)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<27>(0h4000000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<4>(0h8)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<2>(0h2)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<27>(0h4000000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_347 = shr(io.in.a.bits.source, 2) node _T_348 = eq(_T_347, UInt<4>(0h8)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<2>(0h2)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<27>(0h4000000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<4>(0h8)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<2>(0h2)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<27>(0h4000000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<4>(0h8)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<2>(0h2)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_549 = and(_T_547, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<27>(0h4000000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_556) node _T_558 = and(_T_546, _T_557) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_558, UInt<1>(0h1), "") : assert_26 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(source_ok, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(is_aligned, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_568, UInt<1>(0h1), "") : assert_29 node _T_572 = eq(io.in.a.bits.mask, mask) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_572, UInt<1>(0h1), "") : assert_30 node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_576 : node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_35) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<1>(0h1)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_36) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_593 = shr(io.in.a.bits.source, 2) node _T_594 = eq(_T_593, UInt<2>(0h2)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_37) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_598 = and(_T_596, _T_597) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_599 = shr(io.in.a.bits.source, 2) node _T_600 = eq(_T_599, UInt<2>(0h3)) node _T_601 = leq(UInt<1>(0h0), uncommonBits_38) node _T_602 = and(_T_600, _T_601) node _T_603 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_604 = and(_T_602, _T_603) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_605 = shr(io.in.a.bits.source, 2) node _T_606 = eq(_T_605, UInt<4>(0h8)) node _T_607 = leq(UInt<1>(0h0), uncommonBits_39) node _T_608 = and(_T_606, _T_607) node _T_609 = leq(uncommonBits_39, UInt<2>(0h2)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_614 = or(_T_580, _T_586) node _T_615 = or(_T_614, _T_592) node _T_616 = or(_T_615, _T_598) node _T_617 = or(_T_616, _T_604) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_579, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<27>(0h4000000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = and(_T_627, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_635, UInt<1>(0h1), "") : assert_31 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(source_ok, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(is_aligned, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_645, UInt<1>(0h1), "") : assert_34 node _T_649 = not(mask) node _T_650 = and(io.in.a.bits.mask, _T_649) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_651, UInt<1>(0h1), "") : assert_35 node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_655 : node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_40) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h1)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_41) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h2)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_42) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h3)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_43) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_684 = shr(io.in.a.bits.source, 2) node _T_685 = eq(_T_684, UInt<4>(0h8)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_44) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_44, UInt<2>(0h2)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_693 = or(_T_659, _T_665) node _T_694 = or(_T_693, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = and(_T_658, _T_700) node _T_702 = or(UInt<1>(0h0), _T_701) node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_705 = cvt(_T_704) node _T_706 = and(_T_705, asSInt(UInt<27>(0h4000000))) node _T_707 = asSInt(_T_706) node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0))) node _T_709 = and(_T_703, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = and(_T_702, _T_710) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_711, UInt<1>(0h1), "") : assert_36 node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(source_ok, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(is_aligned, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_721, UInt<1>(0h1), "") : assert_39 node _T_725 = eq(io.in.a.bits.mask, mask) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_725, UInt<1>(0h1), "") : assert_40 node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_729 : node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_45) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<1>(0h1)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_46) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<2>(0h2)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_47) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<2>(0h3)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_48) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_757 = and(_T_755, _T_756) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<4>(0h8)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_49) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_49, UInt<2>(0h2)) node _T_763 = and(_T_761, _T_762) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_767 = or(_T_733, _T_739) node _T_768 = or(_T_767, _T_745) node _T_769 = or(_T_768, _T_751) node _T_770 = or(_T_769, _T_757) node _T_771 = or(_T_770, _T_763) node _T_772 = or(_T_771, _T_764) node _T_773 = or(_T_772, _T_765) node _T_774 = or(_T_773, _T_766) node _T_775 = and(_T_732, _T_774) node _T_776 = or(UInt<1>(0h0), _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<27>(0h4000000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_783) node _T_785 = and(_T_776, _T_784) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_785, UInt<1>(0h1), "") : assert_41 node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(source_ok, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(is_aligned, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_795, UInt<1>(0h1), "") : assert_44 node _T_799 = eq(io.in.a.bits.mask, mask) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_799, UInt<1>(0h1), "") : assert_45 node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_803 : node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_806 = and(_T_804, _T_805) node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<1>(0h0)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_50) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<1>(0h1)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_51) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<2>(0h2)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_52) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<2>(0h3)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_53) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<4>(0h8)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_54) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_54, UInt<2>(0h2)) node _T_837 = and(_T_835, _T_836) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_841 = or(_T_807, _T_813) node _T_842 = or(_T_841, _T_819) node _T_843 = or(_T_842, _T_825) node _T_844 = or(_T_843, _T_831) node _T_845 = or(_T_844, _T_837) node _T_846 = or(_T_845, _T_838) node _T_847 = or(_T_846, _T_839) node _T_848 = or(_T_847, _T_840) node _T_849 = and(_T_806, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_852 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_853 = cvt(_T_852) node _T_854 = and(_T_853, asSInt(UInt<27>(0h4000000))) node _T_855 = asSInt(_T_854) node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0))) node _T_857 = and(_T_851, _T_856) node _T_858 = or(UInt<1>(0h0), _T_857) node _T_859 = and(_T_850, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_859, UInt<1>(0h1), "") : assert_46 node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(source_ok, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(is_aligned, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_869, UInt<1>(0h1), "") : assert_49 node _T_873 = eq(io.in.a.bits.mask, mask) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_873, UInt<1>(0h1), "") : assert_50 node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_877, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_881, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 2) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_885 : node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok_1, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_889, UInt<1>(0h1), "") : assert_54 node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_893, UInt<1>(0h1), "") : assert_55 node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_897, UInt<1>(0h1), "") : assert_56 node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_901, UInt<1>(0h1), "") : assert_57 node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_905 : node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok_1, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(sink_ok, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_912, UInt<1>(0h1), "") : assert_60 node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_916, UInt<1>(0h1), "") : assert_61 node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_920, UInt<1>(0h1), "") : assert_62 node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_924, UInt<1>(0h1), "") : assert_63 node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_929 = or(UInt<1>(0h0), _T_928) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_929, UInt<1>(0h1), "") : assert_64 node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_933 : node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(source_ok_1, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(sink_ok, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_940, UInt<1>(0h1), "") : assert_67 node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_944, UInt<1>(0h1), "") : assert_68 node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_948, UInt<1>(0h1), "") : assert_69 node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_953 = or(_T_952, io.in.d.bits.corrupt) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_953, UInt<1>(0h1), "") : assert_70 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = or(UInt<1>(0h0), _T_957) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_958, UInt<1>(0h1), "") : assert_71 node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_962 : node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(source_ok_1, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_966, UInt<1>(0h1), "") : assert_73 node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_970, UInt<1>(0h1), "") : assert_74 node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_975, UInt<1>(0h1), "") : assert_75 node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_979 : node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok_1, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_983, UInt<1>(0h1), "") : assert_77 node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_988 = or(_T_987, io.in.d.bits.corrupt) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_988, UInt<1>(0h1), "") : assert_78 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(UInt<1>(0h0), _T_992) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_993, UInt<1>(0h1), "") : assert_79 node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_997 : node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(source_ok_1, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81 node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82 node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1010 = or(UInt<1>(0h0), _T_1009) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<28>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1026 = eq(a_first, UInt<1>(0h0)) node _T_1027 = and(io.in.a.valid, _T_1026) when _T_1027 : node _T_1028 = eq(io.in.a.bits.opcode, opcode) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87 node _T_1032 = eq(io.in.a.bits.param, param) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88 node _T_1036 = eq(io.in.a.bits.size, size) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89 node _T_1040 = eq(io.in.a.bits.source, source) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90 node _T_1044 = eq(io.in.a.bits.address, address) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91 node _T_1048 = and(io.in.a.ready, io.in.a.valid) node _T_1049 = and(_T_1048, a_first) when _T_1049 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1050 = eq(d_first, UInt<1>(0h0)) node _T_1051 = and(io.in.d.valid, _T_1050) when _T_1051 : node _T_1052 = eq(io.in.d.bits.opcode, opcode_1) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92 node _T_1056 = eq(io.in.d.bits.param, param_1) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93 node _T_1060 = eq(io.in.d.bits.size, size_1) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94 node _T_1064 = eq(io.in.d.bits.source, source_1) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95 node _T_1068 = eq(io.in.d.bits.sink, sink) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96 node _T_1072 = eq(io.in.d.bits.denied, denied) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97 node _T_1076 = and(io.in.d.ready, io.in.d.valid) node _T_1077 = and(_T_1076, d_first) when _T_1077 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1078 = and(io.in.a.valid, a_first_1) node _T_1079 = and(_T_1078, UInt<1>(0h1)) when _T_1079 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1080 = and(io.in.a.ready, io.in.a.valid) node _T_1081 = and(_T_1080, a_first_1) node _T_1082 = and(_T_1081, UInt<1>(0h1)) when _T_1082 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1083 = dshr(inflight, io.in.a.bits.source) node _T_1084 = bits(_T_1083, 0, 0) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(_T_1085, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1089 = and(io.in.d.valid, d_first_1) node _T_1090 = and(_T_1089, UInt<1>(0h1)) node _T_1091 = eq(d_release_ack, UInt<1>(0h0)) node _T_1092 = and(_T_1090, _T_1091) when _T_1092 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1093 = and(io.in.d.ready, io.in.d.valid) node _T_1094 = and(_T_1093, d_first_1) node _T_1095 = and(_T_1094, UInt<1>(0h1)) node _T_1096 = eq(d_release_ack, UInt<1>(0h0)) node _T_1097 = and(_T_1095, _T_1096) when _T_1097 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1098 = and(io.in.d.valid, d_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) node _T_1100 = eq(d_release_ack, UInt<1>(0h0)) node _T_1101 = and(_T_1099, _T_1100) when _T_1101 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1102 = dshr(inflight, io.in.d.bits.source) node _T_1103 = bits(_T_1102, 0, 0) node _T_1104 = or(_T_1103, same_cycle_resp) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1110 = or(_T_1108, _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100 node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101 else : node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1120 = or(_T_1118, _T_1119) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102 node _T_1124 = eq(io.in.d.bits.size, a_size_lookup) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103 node _T_1128 = and(io.in.d.valid, d_first_1) node _T_1129 = and(_T_1128, a_first_1) node _T_1130 = and(_T_1129, io.in.a.valid) node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1132 = and(_T_1130, _T_1131) node _T_1133 = eq(d_release_ack, UInt<1>(0h0)) node _T_1134 = and(_T_1132, _T_1133) when _T_1134 : node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.a.ready) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104 node _T_1140 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1141 = orr(a_set_wo_ready) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) node _T_1143 = or(_T_1140, _T_1142) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_48 node _T_1147 = orr(inflight) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) node _T_1149 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1150 = or(_T_1148, _T_1149) node _T_1151 = lt(watchdog, plusarg_reader.out) node _T_1152 = or(_T_1150, _T_1151) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1156 = and(io.in.a.ready, io.in.a.valid) node _T_1157 = and(io.in.d.ready, io.in.d.valid) node _T_1158 = or(_T_1156, _T_1157) when _T_1158 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1159 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1160 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1161 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = and(_T_1159, _T_1162) when _T_1163 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1164 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1165 = and(_T_1164, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1166 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1167 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = and(_T_1165, _T_1168) when _T_1169 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1170 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1171 = bits(_T_1170, 0, 0) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1176 = and(io.in.d.valid, d_first_2) node _T_1177 = and(_T_1176, UInt<1>(0h1)) node _T_1178 = and(_T_1177, d_release_ack_1) when _T_1178 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1179 = and(io.in.d.ready, io.in.d.valid) node _T_1180 = and(_T_1179, d_first_2) node _T_1181 = and(_T_1180, UInt<1>(0h1)) node _T_1182 = and(_T_1181, d_release_ack_1) when _T_1182 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1183 = and(io.in.d.valid, d_first_2) node _T_1184 = and(_T_1183, UInt<1>(0h1)) node _T_1185 = and(_T_1184, d_release_ack_1) when _T_1185 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1186 = dshr(inflight_1, io.in.d.bits.source) node _T_1187 = bits(_T_1186, 0, 0) node _T_1188 = or(_T_1187, same_cycle_resp_1) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1192 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_109 else : node _T_1196 = eq(io.in.d.bits.size, c_size_lookup) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_110 node _T_1200 = and(io.in.d.valid, d_first_2) node _T_1201 = and(_T_1200, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1202 = and(_T_1201, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1203 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = and(_T_1204, d_release_ack_1) node _T_1206 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : node _T_1208 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<28>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1209 = or(_T_1208, _WIRE_27.ready) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_111 node _T_1213 = orr(c_set_wo_ready) when _T_1213 : node _T_1214 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_49 node _T_1218 = orr(inflight_1) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) node _T_1220 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = lt(watchdog_1, plusarg_reader_1.out) node _T_1223 = or(_T_1221, _T_1222) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<28>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1227 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1228 = and(io.in.d.ready, io.in.d.valid) node _T_1229 = or(_T_1227, _T_1228) when _T_1229 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_24( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1156 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1156; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1156; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1229 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1229; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1229; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1229; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1082 = _T_1156 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1097 = _T_1229 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1200 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1200 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1182 = _T_1229 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1182 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1182 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1182 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PE_306 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_50 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_306( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_50 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_123 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_124 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_194 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_194( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[12]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of ConstellationSystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst tile_prci_domain_1 of TilePRCIDomain_1 inst tile_prci_domain_2 of TilePRCIDomain_2 inst tile_prci_domain_3 of TilePRCIDomain_3 inst tile_prci_domain_4 of TilePRCIDomain_4 inst tile_prci_domain_5 of TilePRCIDomain_5 inst tile_prci_domain_6 of TilePRCIDomain_6 inst tile_prci_domain_7 of TilePRCIDomain_7 inst tile_prci_domain_8 of TilePRCIDomain_8 inst tile_prci_domain_9 of TilePRCIDomain_9 inst tile_prci_domain_10 of TilePRCIDomain_10 inst tile_prci_domain_11 of TilePRCIDomain_11 inst xbar of IntXbar_i12_o1 inst xbar_1 of IntXbar_i12_o1_1 inst xbar_2 of IntXbar_i12_o1_2 inst tileHartIdNexusNode of BundleBridgeNexus_UInt4_12 inst broadcast of BundleBridgeNexus_UInt32_12 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst nexus_2 of BundleBridgeNexus_TraceBundle_1 inst nexus_3 of BundleBridgeNexus_TraceCoreInterface_1 inst nexus_4 of BundleBridgeNexus_TraceBundle_2 inst nexus_5 of BundleBridgeNexus_TraceCoreInterface_2 inst nexus_6 of BundleBridgeNexus_TraceBundle_3 inst nexus_7 of BundleBridgeNexus_TraceCoreInterface_3 inst nexus_8 of BundleBridgeNexus_TraceBundle_4 inst nexus_9 of BundleBridgeNexus_TraceCoreInterface_4 inst nexus_10 of BundleBridgeNexus_TraceBundle_5 inst nexus_11 of BundleBridgeNexus_TraceCoreInterface_5 inst nexus_12 of BundleBridgeNexus_TraceBundle_6 inst nexus_13 of BundleBridgeNexus_TraceCoreInterface_6 inst nexus_14 of BundleBridgeNexus_TraceBundle_7 inst nexus_15 of BundleBridgeNexus_TraceCoreInterface_7 inst nexus_16 of BundleBridgeNexus_TraceBundle_8 inst nexus_17 of BundleBridgeNexus_TraceCoreInterface_8 inst nexus_18 of BundleBridgeNexus_TraceBundle_9 inst nexus_19 of BundleBridgeNexus_TraceCoreInterface_9 inst nexus_20 of BundleBridgeNexus_TraceBundle_10 inst nexus_21 of BundleBridgeNexus_TraceCoreInterface_10 inst nexus_22 of BundleBridgeNexus_TraceBundle_11 inst nexus_23 of BundleBridgeNexus_TraceCoreInterface_11 inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_60 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_1 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_30 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[12] invalidate tileHaltSinkNodeIn[0] invalidate tileHaltSinkNodeIn[1] invalidate tileHaltSinkNodeIn[2] invalidate tileHaltSinkNodeIn[3] invalidate tileHaltSinkNodeIn[4] invalidate tileHaltSinkNodeIn[5] invalidate tileHaltSinkNodeIn[6] invalidate tileHaltSinkNodeIn[7] invalidate tileHaltSinkNodeIn[8] invalidate tileHaltSinkNodeIn[9] invalidate tileHaltSinkNodeIn[10] invalidate tileHaltSinkNodeIn[11] wire tileWFISinkNodeIn : UInt<1>[12] invalidate tileWFISinkNodeIn[0] invalidate tileWFISinkNodeIn[1] invalidate tileWFISinkNodeIn[2] invalidate tileWFISinkNodeIn[3] invalidate tileWFISinkNodeIn[4] invalidate tileWFISinkNodeIn[5] invalidate tileWFISinkNodeIn[6] invalidate tileWFISinkNodeIn[7] invalidate tileWFISinkNodeIn[8] invalidate tileWFISinkNodeIn[9] invalidate tileWFISinkNodeIn[10] invalidate tileWFISinkNodeIn[11] wire tileCeaseSinkNodeIn : UInt<1>[12] invalidate tileCeaseSinkNodeIn[0] invalidate tileCeaseSinkNodeIn[1] invalidate tileCeaseSinkNodeIn[2] invalidate tileCeaseSinkNodeIn[3] invalidate tileCeaseSinkNodeIn[4] invalidate tileCeaseSinkNodeIn[5] invalidate tileCeaseSinkNodeIn[6] invalidate tileCeaseSinkNodeIn[7] invalidate tileCeaseSinkNodeIn[8] invalidate tileCeaseSinkNodeIn[9] invalidate tileCeaseSinkNodeIn[10] invalidate tileCeaseSinkNodeIn[11] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire debugNodesOut_1 : { sync : UInt<1>[1]} invalidate debugNodesOut_1.sync[0] wire debugNodesIn_1 : { sync : UInt<1>[1]} invalidate debugNodesIn_1.sync[0] connect debugNodesOut_1, debugNodesIn_1 wire debugNodesOut_2 : { sync : UInt<1>[1]} invalidate debugNodesOut_2.sync[0] wire debugNodesIn_2 : { sync : UInt<1>[1]} invalidate debugNodesIn_2.sync[0] connect debugNodesOut_2, debugNodesIn_2 wire debugNodesOut_3 : { sync : UInt<1>[1]} invalidate debugNodesOut_3.sync[0] wire debugNodesIn_3 : { sync : UInt<1>[1]} invalidate debugNodesIn_3.sync[0] connect debugNodesOut_3, debugNodesIn_3 wire debugNodesOut_4 : { sync : UInt<1>[1]} invalidate debugNodesOut_4.sync[0] wire debugNodesIn_4 : { sync : UInt<1>[1]} invalidate debugNodesIn_4.sync[0] connect debugNodesOut_4, debugNodesIn_4 wire debugNodesOut_5 : { sync : UInt<1>[1]} invalidate debugNodesOut_5.sync[0] wire debugNodesIn_5 : { sync : UInt<1>[1]} invalidate debugNodesIn_5.sync[0] connect debugNodesOut_5, debugNodesIn_5 wire debugNodesOut_6 : { sync : UInt<1>[1]} invalidate debugNodesOut_6.sync[0] wire debugNodesIn_6 : { sync : UInt<1>[1]} invalidate debugNodesIn_6.sync[0] connect debugNodesOut_6, debugNodesIn_6 wire debugNodesOut_7 : { sync : UInt<1>[1]} invalidate debugNodesOut_7.sync[0] wire debugNodesIn_7 : { sync : UInt<1>[1]} invalidate debugNodesIn_7.sync[0] connect debugNodesOut_7, debugNodesIn_7 wire debugNodesOut_8 : { sync : UInt<1>[1]} invalidate debugNodesOut_8.sync[0] wire debugNodesIn_8 : { sync : UInt<1>[1]} invalidate debugNodesIn_8.sync[0] connect debugNodesOut_8, debugNodesIn_8 wire debugNodesOut_9 : { sync : UInt<1>[1]} invalidate debugNodesOut_9.sync[0] wire debugNodesIn_9 : { sync : UInt<1>[1]} invalidate debugNodesIn_9.sync[0] connect debugNodesOut_9, debugNodesIn_9 wire debugNodesOut_10 : { sync : UInt<1>[1]} invalidate debugNodesOut_10.sync[0] wire debugNodesIn_10 : { sync : UInt<1>[1]} invalidate debugNodesIn_10.sync[0] connect debugNodesOut_10, debugNodesIn_10 wire debugNodesOut_11 : { sync : UInt<1>[1]} invalidate debugNodesOut_11.sync[0] wire debugNodesIn_11 : { sync : UInt<1>[1]} invalidate debugNodesIn_11.sync[0] connect debugNodesOut_11, debugNodesIn_11 wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceCoreNodesIn_1 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_1.cause invalidate traceCoreNodesIn_1.tval invalidate traceCoreNodesIn_1.priv invalidate traceCoreNodesIn_1.group[0].ilastsize invalidate traceCoreNodesIn_1.group[0].itype invalidate traceCoreNodesIn_1.group[0].iaddr invalidate traceCoreNodesIn_1.group[0].iretire wire traceCoreNodesIn_2 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_2.cause invalidate traceCoreNodesIn_2.tval invalidate traceCoreNodesIn_2.priv invalidate traceCoreNodesIn_2.group[0].ilastsize invalidate traceCoreNodesIn_2.group[0].itype invalidate traceCoreNodesIn_2.group[0].iaddr invalidate traceCoreNodesIn_2.group[0].iretire wire traceCoreNodesIn_3 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_3.cause invalidate traceCoreNodesIn_3.tval invalidate traceCoreNodesIn_3.priv invalidate traceCoreNodesIn_3.group[0].ilastsize invalidate traceCoreNodesIn_3.group[0].itype invalidate traceCoreNodesIn_3.group[0].iaddr invalidate traceCoreNodesIn_3.group[0].iretire wire traceCoreNodesIn_4 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_4.cause invalidate traceCoreNodesIn_4.tval invalidate traceCoreNodesIn_4.priv invalidate traceCoreNodesIn_4.group[0].ilastsize invalidate traceCoreNodesIn_4.group[0].itype invalidate traceCoreNodesIn_4.group[0].iaddr invalidate traceCoreNodesIn_4.group[0].iretire wire traceCoreNodesIn_5 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_5.cause invalidate traceCoreNodesIn_5.tval invalidate traceCoreNodesIn_5.priv invalidate traceCoreNodesIn_5.group[0].ilastsize invalidate traceCoreNodesIn_5.group[0].itype invalidate traceCoreNodesIn_5.group[0].iaddr invalidate traceCoreNodesIn_5.group[0].iretire wire traceCoreNodesIn_6 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_6.cause invalidate traceCoreNodesIn_6.tval invalidate traceCoreNodesIn_6.priv invalidate traceCoreNodesIn_6.group[0].ilastsize invalidate traceCoreNodesIn_6.group[0].itype invalidate traceCoreNodesIn_6.group[0].iaddr invalidate traceCoreNodesIn_6.group[0].iretire wire traceCoreNodesIn_7 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_7.cause invalidate traceCoreNodesIn_7.tval invalidate traceCoreNodesIn_7.priv invalidate traceCoreNodesIn_7.group[0].ilastsize invalidate traceCoreNodesIn_7.group[0].itype invalidate traceCoreNodesIn_7.group[0].iaddr invalidate traceCoreNodesIn_7.group[0].iretire wire traceCoreNodesIn_8 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_8.cause invalidate traceCoreNodesIn_8.tval invalidate traceCoreNodesIn_8.priv invalidate traceCoreNodesIn_8.group[0].ilastsize invalidate traceCoreNodesIn_8.group[0].itype invalidate traceCoreNodesIn_8.group[0].iaddr invalidate traceCoreNodesIn_8.group[0].iretire wire traceCoreNodesIn_9 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_9.cause invalidate traceCoreNodesIn_9.tval invalidate traceCoreNodesIn_9.priv invalidate traceCoreNodesIn_9.group[0].ilastsize invalidate traceCoreNodesIn_9.group[0].itype invalidate traceCoreNodesIn_9.group[0].iaddr invalidate traceCoreNodesIn_9.group[0].iretire wire traceCoreNodesIn_10 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_10.cause invalidate traceCoreNodesIn_10.tval invalidate traceCoreNodesIn_10.priv invalidate traceCoreNodesIn_10.group[0].ilastsize invalidate traceCoreNodesIn_10.group[0].itype invalidate traceCoreNodesIn_10.group[0].iaddr invalidate traceCoreNodesIn_10.group[0].iretire wire traceCoreNodesIn_11 : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn_11.cause invalidate traceCoreNodesIn_11.tval invalidate traceCoreNodesIn_11.priv invalidate traceCoreNodesIn_11.group[0].ilastsize invalidate traceCoreNodesIn_11.group[0].itype invalidate traceCoreNodesIn_11.group[0].iaddr invalidate traceCoreNodesIn_11.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid wire traceNodesIn_1 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_1.time invalidate traceNodesIn_1.insns[0].tval invalidate traceNodesIn_1.insns[0].cause invalidate traceNodesIn_1.insns[0].interrupt invalidate traceNodesIn_1.insns[0].exception invalidate traceNodesIn_1.insns[0].priv invalidate traceNodesIn_1.insns[0].insn invalidate traceNodesIn_1.insns[0].iaddr invalidate traceNodesIn_1.insns[0].valid wire traceNodesIn_2 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_2.time invalidate traceNodesIn_2.insns[0].tval invalidate traceNodesIn_2.insns[0].cause invalidate traceNodesIn_2.insns[0].interrupt invalidate traceNodesIn_2.insns[0].exception invalidate traceNodesIn_2.insns[0].priv invalidate traceNodesIn_2.insns[0].insn invalidate traceNodesIn_2.insns[0].iaddr invalidate traceNodesIn_2.insns[0].valid wire traceNodesIn_3 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_3.time invalidate traceNodesIn_3.insns[0].tval invalidate traceNodesIn_3.insns[0].cause invalidate traceNodesIn_3.insns[0].interrupt invalidate traceNodesIn_3.insns[0].exception invalidate traceNodesIn_3.insns[0].priv invalidate traceNodesIn_3.insns[0].insn invalidate traceNodesIn_3.insns[0].iaddr invalidate traceNodesIn_3.insns[0].valid wire traceNodesIn_4 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_4.time invalidate traceNodesIn_4.insns[0].tval invalidate traceNodesIn_4.insns[0].cause invalidate traceNodesIn_4.insns[0].interrupt invalidate traceNodesIn_4.insns[0].exception invalidate traceNodesIn_4.insns[0].priv invalidate traceNodesIn_4.insns[0].insn invalidate traceNodesIn_4.insns[0].iaddr invalidate traceNodesIn_4.insns[0].valid wire traceNodesIn_5 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_5.time invalidate traceNodesIn_5.insns[0].tval invalidate traceNodesIn_5.insns[0].cause invalidate traceNodesIn_5.insns[0].interrupt invalidate traceNodesIn_5.insns[0].exception invalidate traceNodesIn_5.insns[0].priv invalidate traceNodesIn_5.insns[0].insn invalidate traceNodesIn_5.insns[0].iaddr invalidate traceNodesIn_5.insns[0].valid wire traceNodesIn_6 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_6.time invalidate traceNodesIn_6.insns[0].tval invalidate traceNodesIn_6.insns[0].cause invalidate traceNodesIn_6.insns[0].interrupt invalidate traceNodesIn_6.insns[0].exception invalidate traceNodesIn_6.insns[0].priv invalidate traceNodesIn_6.insns[0].insn invalidate traceNodesIn_6.insns[0].iaddr invalidate traceNodesIn_6.insns[0].valid wire traceNodesIn_7 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_7.time invalidate traceNodesIn_7.insns[0].tval invalidate traceNodesIn_7.insns[0].cause invalidate traceNodesIn_7.insns[0].interrupt invalidate traceNodesIn_7.insns[0].exception invalidate traceNodesIn_7.insns[0].priv invalidate traceNodesIn_7.insns[0].insn invalidate traceNodesIn_7.insns[0].iaddr invalidate traceNodesIn_7.insns[0].valid wire traceNodesIn_8 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_8.time invalidate traceNodesIn_8.insns[0].tval invalidate traceNodesIn_8.insns[0].cause invalidate traceNodesIn_8.insns[0].interrupt invalidate traceNodesIn_8.insns[0].exception invalidate traceNodesIn_8.insns[0].priv invalidate traceNodesIn_8.insns[0].insn invalidate traceNodesIn_8.insns[0].iaddr invalidate traceNodesIn_8.insns[0].valid wire traceNodesIn_9 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_9.time invalidate traceNodesIn_9.insns[0].tval invalidate traceNodesIn_9.insns[0].cause invalidate traceNodesIn_9.insns[0].interrupt invalidate traceNodesIn_9.insns[0].exception invalidate traceNodesIn_9.insns[0].priv invalidate traceNodesIn_9.insns[0].insn invalidate traceNodesIn_9.insns[0].iaddr invalidate traceNodesIn_9.insns[0].valid wire traceNodesIn_10 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_10.time invalidate traceNodesIn_10.insns[0].tval invalidate traceNodesIn_10.insns[0].cause invalidate traceNodesIn_10.insns[0].interrupt invalidate traceNodesIn_10.insns[0].exception invalidate traceNodesIn_10.insns[0].priv invalidate traceNodesIn_10.insns[0].insn invalidate traceNodesIn_10.insns[0].iaddr invalidate traceNodesIn_10.insns[0].valid wire traceNodesIn_11 : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn_11.time invalidate traceNodesIn_11.insns[0].tval invalidate traceNodesIn_11.insns[0].cause invalidate traceNodesIn_11.insns[0].interrupt invalidate traceNodesIn_11.insns[0].exception invalidate traceNodesIn_11.insns[0].priv invalidate traceNodesIn_11.insns[0].insn invalidate traceNodesIn_11.insns[0].iaddr invalidate traceNodesIn_11.insns[0].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect tile_prci_domain_1.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_2 connect tile_prci_domain_2.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_3 connect tile_prci_domain_3.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_4 connect tile_prci_domain_4.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_5 connect tile_prci_domain_5.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_6 connect tile_prci_domain_6.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_7 connect tile_prci_domain_7.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_8 connect tile_prci_domain_8.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_9 connect tile_prci_domain_9.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_10 connect tile_prci_domain_10.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_11 connect tile_prci_domain_11.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_12 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_13 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in_0, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_0 connect coh_wrapper.auto.coherent_jbar_anon_in_1, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_1 connect coh_wrapper.auto.coherent_jbar_anon_in_2, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_2 connect coh_wrapper.auto.coherent_jbar_anon_in_3, sbus.auto.coupler_to_bus_named_coh_widget_anon_out_3 connect mbus.auto.bus_xing_in_0, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_0 connect mbus.auto.bus_xing_in_1, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_1 connect mbus.auto.bus_xing_in_2, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_2 connect mbus.auto.bus_xing_in_3, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out_3 connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_2.auto.in, tile_prci_domain_1.auto.element_reset_domain_rockettile_trace_source_out connect nexus_3.auto.in, tile_prci_domain_1.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_4.auto.in, tile_prci_domain_2.auto.element_reset_domain_rockettile_trace_source_out connect nexus_5.auto.in, tile_prci_domain_2.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_6.auto.in, tile_prci_domain_3.auto.element_reset_domain_rockettile_trace_source_out connect nexus_7.auto.in, tile_prci_domain_3.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_8.auto.in, tile_prci_domain_4.auto.element_reset_domain_rockettile_trace_source_out connect nexus_9.auto.in, tile_prci_domain_4.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_10.auto.in, tile_prci_domain_5.auto.element_reset_domain_rockettile_trace_source_out connect nexus_11.auto.in, tile_prci_domain_5.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_12.auto.in, tile_prci_domain_6.auto.element_reset_domain_rockettile_trace_source_out connect nexus_13.auto.in, tile_prci_domain_6.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_14.auto.in, tile_prci_domain_7.auto.element_reset_domain_rockettile_trace_source_out connect nexus_15.auto.in, tile_prci_domain_7.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_16.auto.in, tile_prci_domain_8.auto.element_reset_domain_rockettile_trace_source_out connect nexus_17.auto.in, tile_prci_domain_8.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_18.auto.in, tile_prci_domain_9.auto.element_reset_domain_rockettile_trace_source_out connect nexus_19.auto.in, tile_prci_domain_9.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_20.auto.in, tile_prci_domain_10.auto.element_reset_domain_rockettile_trace_source_out connect nexus_21.auto.in, tile_prci_domain_10.auto.element_reset_domain_rockettile_trace_core_source_out connect nexus_22.auto.in, tile_prci_domain_11.auto.element_reset_domain_rockettile_trace_source_out connect nexus_23.auto.in, tile_prci_domain_11.auto.element_reset_domain_rockettile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_0 connect tile_prci_domain_1.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_1 connect tile_prci_domain_2.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_2 connect tile_prci_domain_3.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_3 connect tile_prci_domain_4.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_4 connect tile_prci_domain_5.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_5 connect tile_prci_domain_6.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_6 connect tile_prci_domain_7.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_7 connect tile_prci_domain_8.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_8 connect tile_prci_domain_9.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_9 connect tile_prci_domain_10.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_10 connect tile_prci_domain_11.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out_11 connect tile_prci_domain.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_0 connect tile_prci_domain_1.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_1 connect tile_prci_domain_2.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_2 connect tile_prci_domain_3.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_3 connect tile_prci_domain_4.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_4 connect tile_prci_domain_5.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_5 connect tile_prci_domain_6.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_6 connect tile_prci_domain_7.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_7 connect tile_prci_domain_8.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_8 connect tile_prci_domain_9.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_9 connect tile_prci_domain_10.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_10 connect tile_prci_domain_11.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out_11 connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out_0 connect debugNodesIn_1, tlDM.auto.dmOuter_int_out_1 connect debugNodesIn_2, tlDM.auto.dmOuter_int_out_2 connect debugNodesIn_3, tlDM.auto.dmOuter_int_out_3 connect debugNodesIn_4, tlDM.auto.dmOuter_int_out_4 connect debugNodesIn_5, tlDM.auto.dmOuter_int_out_5 connect debugNodesIn_6, tlDM.auto.dmOuter_int_out_6 connect debugNodesIn_7, tlDM.auto.dmOuter_int_out_7 connect debugNodesIn_8, tlDM.auto.dmOuter_int_out_8 connect debugNodesIn_9, tlDM.auto.dmOuter_int_out_9 connect debugNodesIn_10, tlDM.auto.dmOuter_int_out_10 connect debugNodesIn_11, tlDM.auto.dmOuter_int_out_11 connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect tile_prci_domain_1.auto.intsink_in.sync[0], debugNodesOut_1.sync[0] connect tile_prci_domain_2.auto.intsink_in.sync[0], debugNodesOut_2.sync[0] connect tile_prci_domain_3.auto.intsink_in.sync[0], debugNodesOut_3.sync[0] connect tile_prci_domain_4.auto.intsink_in.sync[0], debugNodesOut_4.sync[0] connect tile_prci_domain_5.auto.intsink_in.sync[0], debugNodesOut_5.sync[0] connect tile_prci_domain_6.auto.intsink_in.sync[0], debugNodesOut_6.sync[0] connect tile_prci_domain_7.auto.intsink_in.sync[0], debugNodesOut_7.sync[0] connect tile_prci_domain_8.auto.intsink_in.sync[0], debugNodesOut_8.sync[0] connect tile_prci_domain_9.auto.intsink_in.sync[0], debugNodesOut_9.sync[0] connect tile_prci_domain_10.auto.intsink_in.sync[0], debugNodesOut_10.sync[0] connect tile_prci_domain_11.auto.intsink_in.sync[0], debugNodesOut_11.sync[0] connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_0, tile_prci_domain.auto.tl_master_clock_xing_out connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_0.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in_0[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_0[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_0[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_1, tile_prci_domain_1.auto.tl_master_clock_xing_out connect tile_prci_domain_1.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_1.sync[0] connect tile_prci_domain_1.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_1.sync[1] connect tile_prci_domain_1.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_2.sync[0] connect tile_prci_domain_1.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_3.sync[0] connect xbar.auto.anon_in_1[0], tile_prci_domain_1.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_1[0], tile_prci_domain_1.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_1[0], tile_prci_domain_1.auto.intsink_out_2[0] connect traceNodesIn_1, nexus_2.auto.out connect traceCoreNodesIn_1, nexus_3.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_2, tile_prci_domain_2.auto.tl_master_clock_xing_out connect tile_prci_domain_2.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_2.sync[0] connect tile_prci_domain_2.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_2.sync[1] connect tile_prci_domain_2.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_4.sync[0] connect tile_prci_domain_2.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_5.sync[0] connect xbar.auto.anon_in_2[0], tile_prci_domain_2.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_2[0], tile_prci_domain_2.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_2[0], tile_prci_domain_2.auto.intsink_out_2[0] connect traceNodesIn_2, nexus_4.auto.out connect traceCoreNodesIn_2, nexus_5.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_3, tile_prci_domain_3.auto.tl_master_clock_xing_out connect tile_prci_domain_3.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_3.sync[0] connect tile_prci_domain_3.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_3.sync[1] connect tile_prci_domain_3.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_6.sync[0] connect tile_prci_domain_3.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_7.sync[0] connect xbar.auto.anon_in_3[0], tile_prci_domain_3.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_3[0], tile_prci_domain_3.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_3[0], tile_prci_domain_3.auto.intsink_out_2[0] connect traceNodesIn_3, nexus_6.auto.out connect traceCoreNodesIn_3, nexus_7.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_4, tile_prci_domain_4.auto.tl_master_clock_xing_out connect tile_prci_domain_4.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_4.sync[0] connect tile_prci_domain_4.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_4.sync[1] connect tile_prci_domain_4.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_8.sync[0] connect tile_prci_domain_4.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_9.sync[0] connect xbar.auto.anon_in_4[0], tile_prci_domain_4.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_4[0], tile_prci_domain_4.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_4[0], tile_prci_domain_4.auto.intsink_out_2[0] connect traceNodesIn_4, nexus_8.auto.out connect traceCoreNodesIn_4, nexus_9.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_5, tile_prci_domain_5.auto.tl_master_clock_xing_out connect tile_prci_domain_5.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_5.sync[0] connect tile_prci_domain_5.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_5.sync[1] connect tile_prci_domain_5.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_10.sync[0] connect tile_prci_domain_5.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_11.sync[0] connect xbar.auto.anon_in_5[0], tile_prci_domain_5.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_5[0], tile_prci_domain_5.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_5[0], tile_prci_domain_5.auto.intsink_out_2[0] connect traceNodesIn_5, nexus_10.auto.out connect traceCoreNodesIn_5, nexus_11.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_6, tile_prci_domain_6.auto.tl_master_clock_xing_out connect tile_prci_domain_6.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_6.sync[0] connect tile_prci_domain_6.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_6.sync[1] connect tile_prci_domain_6.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_12.sync[0] connect tile_prci_domain_6.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_13.sync[0] connect xbar.auto.anon_in_6[0], tile_prci_domain_6.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_6[0], tile_prci_domain_6.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_6[0], tile_prci_domain_6.auto.intsink_out_2[0] connect traceNodesIn_6, nexus_12.auto.out connect traceCoreNodesIn_6, nexus_13.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_7, tile_prci_domain_7.auto.tl_master_clock_xing_out connect tile_prci_domain_7.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_7.sync[0] connect tile_prci_domain_7.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_7.sync[1] connect tile_prci_domain_7.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_14.sync[0] connect tile_prci_domain_7.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_15.sync[0] connect xbar.auto.anon_in_7[0], tile_prci_domain_7.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_7[0], tile_prci_domain_7.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_7[0], tile_prci_domain_7.auto.intsink_out_2[0] connect traceNodesIn_7, nexus_14.auto.out connect traceCoreNodesIn_7, nexus_15.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_8, tile_prci_domain_8.auto.tl_master_clock_xing_out connect tile_prci_domain_8.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_8.sync[0] connect tile_prci_domain_8.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_8.sync[1] connect tile_prci_domain_8.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_16.sync[0] connect tile_prci_domain_8.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_17.sync[0] connect xbar.auto.anon_in_8[0], tile_prci_domain_8.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_8[0], tile_prci_domain_8.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_8[0], tile_prci_domain_8.auto.intsink_out_2[0] connect traceNodesIn_8, nexus_16.auto.out connect traceCoreNodesIn_8, nexus_17.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_9, tile_prci_domain_9.auto.tl_master_clock_xing_out connect tile_prci_domain_9.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_9.sync[0] connect tile_prci_domain_9.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_9.sync[1] connect tile_prci_domain_9.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_18.sync[0] connect tile_prci_domain_9.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_19.sync[0] connect xbar.auto.anon_in_9[0], tile_prci_domain_9.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_9[0], tile_prci_domain_9.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_9[0], tile_prci_domain_9.auto.intsink_out_2[0] connect traceNodesIn_9, nexus_18.auto.out connect traceCoreNodesIn_9, nexus_19.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_10, tile_prci_domain_10.auto.tl_master_clock_xing_out connect tile_prci_domain_10.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_10.sync[0] connect tile_prci_domain_10.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_10.sync[1] connect tile_prci_domain_10.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_20.sync[0] connect tile_prci_domain_10.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_21.sync[0] connect xbar.auto.anon_in_10[0], tile_prci_domain_10.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_10[0], tile_prci_domain_10.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_10[0], tile_prci_domain_10.auto.intsink_out_2[0] connect traceNodesIn_10, nexus_20.auto.out connect traceCoreNodesIn_10, nexus_21.auto.out connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_11, tile_prci_domain_11.auto.tl_master_clock_xing_out connect tile_prci_domain_11.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out_11.sync[0] connect tile_prci_domain_11.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out_11.sync[1] connect tile_prci_domain_11.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_22.sync[0] connect tile_prci_domain_11.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_23.sync[0] connect xbar.auto.anon_in_11[0], tile_prci_domain_11.auto.intsink_out_0[0] connect xbar_1.auto.anon_in_11[0], tile_prci_domain_11.auto.intsink_out_1[0] connect xbar_2.auto.anon_in_11[0], tile_prci_domain_11.auto.intsink_out_2[0] connect traceNodesIn_11, nexus_22.auto.out connect traceCoreNodesIn_11, nexus_23.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.hartIsInReset[1], resetctrl.hartIsInReset[1] connect tlDM.io.hartIsInReset[2], resetctrl.hartIsInReset[2] connect tlDM.io.hartIsInReset[3], resetctrl.hartIsInReset[3] connect tlDM.io.hartIsInReset[4], resetctrl.hartIsInReset[4] connect tlDM.io.hartIsInReset[5], resetctrl.hartIsInReset[5] connect tlDM.io.hartIsInReset[6], resetctrl.hartIsInReset[6] connect tlDM.io.hartIsInReset[7], resetctrl.hartIsInReset[7] connect tlDM.io.hartIsInReset[8], resetctrl.hartIsInReset[8] connect tlDM.io.hartIsInReset[9], resetctrl.hartIsInReset[9] connect tlDM.io.hartIsInReset[10], resetctrl.hartIsInReset[10] connect tlDM.io.hartIsInReset[11], resetctrl.hartIsInReset[11] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[1], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[2], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[3], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[4], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[5], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[6], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[7], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[8], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[9], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[10], UInt<1>(0h0) connect tlDM.io.ctrl.debugUnavail[11], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell

module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_1, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_2, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_3, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_4, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_5, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_6, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_7, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_8, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_9, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_10, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_11, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [7:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _intsink_auto_out_0; // @[Crossing.scala:109:29] wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [11:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [6:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [11:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_11_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_10_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_9_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_8_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_7_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_6_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_5_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_4_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_3_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_2_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_1_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_0_sync_0; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_23_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_22_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_21_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_20_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_19_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_18_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_17_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_16_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_15_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_14_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_13_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_12_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_11_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_10_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_9_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_8_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_7_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_6_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_5_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_4_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_3_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_2_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_11_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_11_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_10_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_10_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_9_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_9_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_8_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_8_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_7_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_7_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_6_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_6_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_5_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_5_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_4_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_4_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_3_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_3_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_2_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_2_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_1_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_0_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire [3:0] _tileHartIdNexusNode_auto_out_11; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_10; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_9; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_8; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_7; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_6; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_5; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_4; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_3; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_2; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_1; // @[HasTiles.scala:75:39] wire [3:0] _tileHartIdNexusNode_auto_out_0; // @[HasTiles.scala:75:39] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_11_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_11_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_10_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_10_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_9_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_9_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_8_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_8_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [11:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [6:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_3_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_3_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_3_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_3_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_3_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_3_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_2_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_2_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_2_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_2_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_2_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_2_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_1_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_1_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_1_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_1_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_1_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_1_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_0_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_0_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_0_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_0_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_0_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_0_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [5:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [5:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size; // @[LazyScope.scala:98:27] wire [4:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address; // @[LazyScope.scala:98:27] wire [15:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [127:0] _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[LazyScope.scala:98:27] wire [4:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[LazyScope.scala:98:27] wire [5:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [127:0] _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[LazyScope.scala:98:27] wire [28:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _sbus_coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[LazyScope.scala:98:27] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_4_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_3_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_2_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_tilelink_b_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_tilelink_e_valid; // @[Tilelink.scala:455:34] wire [5:0] _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_tilelink_e_bits_sink; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_1_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_valid; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_head; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_tail; // @[Tilelink.scala:455:34] wire [144:0] _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_payload; // @[Tilelink.scala:455:34] wire [3:0] _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_b_bits_egress_id; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_slave_be_io_flits_e_ready; // @[Tilelink.scala:455:34] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_12_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_11_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_10_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_9_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_8_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_7_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_6_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_5_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_4_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_3_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_2_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_valid; // @[Tilelink.scala:435:35] wire [2:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_opcode; // @[Tilelink.scala:435:35] wire [1:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_param; // @[Tilelink.scala:435:35] wire [3:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_size; // @[Tilelink.scala:435:35] wire [6:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_source; // @[Tilelink.scala:435:35] wire [31:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_address; // @[Tilelink.scala:435:35] wire [15:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_mask; // @[Tilelink.scala:435:35] wire [127:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_data; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_b_bits_corrupt; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_tilelink_e_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_1_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_b_ready; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_valid; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_bits_head; // @[Tilelink.scala:435:35] wire [144:0] _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_bits_payload; // @[Tilelink.scala:435:35] wire [4:0] _sbus_system_bus_noc_be_noc_nif_master_be_io_flits_e_bits_egress_id; // @[Tilelink.scala:435:35] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_egress_width_widget_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_ingress_width_widget_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_2_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_2_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_2_flit_bits_tail; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [147:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_egress_width_widget_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_ingress_width_widget_in_2_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_ingress_width_widget_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_ingress_width_widget_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [36:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_4_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_3_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_2_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_address; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_c_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_1_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_valid; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_opcode; // @[Tilelink.scala:386:35] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_param; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_size; // @[Tilelink.scala:386:35] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_source; // @[Tilelink.scala:386:35] wire [31:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_address; // @[Tilelink.scala:386:35] wire [15:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_mask; // @[Tilelink.scala:386:35] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_data; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_a_bits_corrupt; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_tilelink_d_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_a_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_c_ready; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_valid; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_head; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_tail; // @[Tilelink.scala:386:35] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_payload; // @[Tilelink.scala:386:35] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_slave_acd_io_flits_d_bits_egress_id; // @[Tilelink.scala:386:35] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_12_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_11_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_10_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_9_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_8_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_7_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_6_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_5_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_4_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_3_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_2_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_c_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_c_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_1_io_flits_d_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_a_ready; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_valid; // @[Tilelink.scala:363:36] wire [2:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_opcode; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_param; // @[Tilelink.scala:363:36] wire [3:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_size; // @[Tilelink.scala:363:36] wire [6:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_source; // @[Tilelink.scala:363:36] wire [5:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_sink; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_denied; // @[Tilelink.scala:363:36] wire [127:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_data; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_tilelink_d_bits_corrupt; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_head; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_tail; // @[Tilelink.scala:363:36] wire [144:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_payload; // @[Tilelink.scala:363:36] wire [4:0] _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_a_bits_egress_id; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_c_valid; // @[Tilelink.scala:363:36] wire _sbus_system_bus_noc_acd_noc_nif_master_acd_io_flits_d_ready; // @[Tilelink.scala:363:36] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_ingress_nodes_in_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_3_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_egress_nodes_out_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_ingress_nodes_in_1_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_5; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_6; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_5; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_6; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_3_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_3_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_3_flit_bits_tail; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_2_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_1_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_egress_nodes_out_0_flit_bits_payload; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_4_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_3_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_2_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_ingress_nodes_in_0_flit_ready; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40] wire _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40] wire [144:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40] wire [3:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40] wire [1:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40] wire [2:0] _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40] wire _sbus_fixedClockNode_auto_anon_out_13_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_13_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_12_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_12_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_11_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_11_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_10_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_10_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_9_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_9_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_8_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_8_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_7_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_7_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_6_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_6_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_5_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_5_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_4_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_4_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_3_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_3_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_2_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_2_reset; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _sbus_fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27] reg [63:0] sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr; // @[NoC.scala:163:37] reg [63:0] sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:164:37] wire [63:0] sbus_system_bus_noc_acd_noc_noc_debug_any_stall_ctr = sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr + sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50] reg [63:0] sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr; // @[NoC.scala:163:37] reg [63:0] sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:164:37] wire [63:0] sbus_system_bus_noc_be_noc_noc_debug_any_stall_ctr = sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr + sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] always @(posedge _sbus_fixedClockNode_auto_anon_out_0_clock) begin // @[ClockGroup.scala:115:114] if (_sbus_fixedClockNode_auto_anon_out_0_reset) begin // @[ClockGroup.scala:115:114] sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37] sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37] sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37] sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37] end else begin // @[ClockGroup.scala:115:114] sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr <= sbus_system_bus_noc_acd_noc_noc_debug_va_stall_ctr + {62'h0, _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_5 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_6 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_2}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}] sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr <= sbus_system_bus_noc_acd_noc_noc_debug_sa_stall_ctr + {62'h0, _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_5 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_6 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_acd_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_2}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}] sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr <= sbus_system_bus_noc_be_noc_noc_debug_va_stall_ctr + {63'h0, _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_va_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_va_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_va_stall_1}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}] sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr <= sbus_system_bus_noc_be_noc_noc_debug_sa_stall_ctr + {63'h0, _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_1_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_2_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_3_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_5_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_6_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_8_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_9_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_10_auto_routers_debug_out_sa_stall_4 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_11_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_12_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_13_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_1 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_2 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_14_auto_routers_debug_out_sa_stall_3 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_0 + _sbus_system_bus_noc_be_noc_noc_router_sink_domain_15_auto_routers_debug_out_sa_stall_1}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}] end always @(posedge) always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module ScalePipe : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}, out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}} wire out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}} connect out.bits.index, io.in.bits.index connect out.bits.id, io.in.bits.id connect out.bits.scale.bits, io.in.bits.scale.bits connect out.bits.data, io.in.bits.data connect out.valid, io.in.valid wire _out_bits_data_WIRE : { bits : UInt<32>} wire _out_bits_data_WIRE_1 : UInt<32> connect _out_bits_data_WIRE_1, io.in.bits.scale.bits node _out_bits_data_T = bits(_out_bits_data_WIRE_1, 31, 0) connect _out_bits_data_WIRE.bits, _out_bits_data_T node out_bits_data_f_rec_rawIn_sign = bits(_out_bits_data_WIRE.bits, 31, 31) node out_bits_data_f_rec_rawIn_expIn = bits(_out_bits_data_WIRE.bits, 30, 23) node out_bits_data_f_rec_rawIn_fractIn = bits(_out_bits_data_WIRE.bits, 22, 0) node out_bits_data_f_rec_rawIn_isZeroExpIn = eq(out_bits_data_f_rec_rawIn_expIn, UInt<1>(0h0)) node out_bits_data_f_rec_rawIn_isZeroFractIn = eq(out_bits_data_f_rec_rawIn_fractIn, UInt<1>(0h0)) node _out_bits_data_f_rec_rawIn_normDist_T = bits(out_bits_data_f_rec_rawIn_fractIn, 0, 0) node _out_bits_data_f_rec_rawIn_normDist_T_1 = bits(out_bits_data_f_rec_rawIn_fractIn, 1, 1) node _out_bits_data_f_rec_rawIn_normDist_T_2 = bits(out_bits_data_f_rec_rawIn_fractIn, 2, 2) node _out_bits_data_f_rec_rawIn_normDist_T_3 = bits(out_bits_data_f_rec_rawIn_fractIn, 3, 3) node _out_bits_data_f_rec_rawIn_normDist_T_4 = bits(out_bits_data_f_rec_rawIn_fractIn, 4, 4) node _out_bits_data_f_rec_rawIn_normDist_T_5 = bits(out_bits_data_f_rec_rawIn_fractIn, 5, 5) node _out_bits_data_f_rec_rawIn_normDist_T_6 = bits(out_bits_data_f_rec_rawIn_fractIn, 6, 6) node _out_bits_data_f_rec_rawIn_normDist_T_7 = bits(out_bits_data_f_rec_rawIn_fractIn, 7, 7) node _out_bits_data_f_rec_rawIn_normDist_T_8 = bits(out_bits_data_f_rec_rawIn_fractIn, 8, 8) node _out_bits_data_f_rec_rawIn_normDist_T_9 = bits(out_bits_data_f_rec_rawIn_fractIn, 9, 9) node _out_bits_data_f_rec_rawIn_normDist_T_10 = bits(out_bits_data_f_rec_rawIn_fractIn, 10, 10) node _out_bits_data_f_rec_rawIn_normDist_T_11 = bits(out_bits_data_f_rec_rawIn_fractIn, 11, 11) node _out_bits_data_f_rec_rawIn_normDist_T_12 = bits(out_bits_data_f_rec_rawIn_fractIn, 12, 12) node _out_bits_data_f_rec_rawIn_normDist_T_13 = bits(out_bits_data_f_rec_rawIn_fractIn, 13, 13) node _out_bits_data_f_rec_rawIn_normDist_T_14 = bits(out_bits_data_f_rec_rawIn_fractIn, 14, 14) node _out_bits_data_f_rec_rawIn_normDist_T_15 = bits(out_bits_data_f_rec_rawIn_fractIn, 15, 15) node _out_bits_data_f_rec_rawIn_normDist_T_16 = bits(out_bits_data_f_rec_rawIn_fractIn, 16, 16) node _out_bits_data_f_rec_rawIn_normDist_T_17 = bits(out_bits_data_f_rec_rawIn_fractIn, 17, 17) node _out_bits_data_f_rec_rawIn_normDist_T_18 = bits(out_bits_data_f_rec_rawIn_fractIn, 18, 18) node _out_bits_data_f_rec_rawIn_normDist_T_19 = bits(out_bits_data_f_rec_rawIn_fractIn, 19, 19) node _out_bits_data_f_rec_rawIn_normDist_T_20 = bits(out_bits_data_f_rec_rawIn_fractIn, 20, 20) node _out_bits_data_f_rec_rawIn_normDist_T_21 = bits(out_bits_data_f_rec_rawIn_fractIn, 21, 21) node _out_bits_data_f_rec_rawIn_normDist_T_22 = bits(out_bits_data_f_rec_rawIn_fractIn, 22, 22) node _out_bits_data_f_rec_rawIn_normDist_T_23 = mux(_out_bits_data_f_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _out_bits_data_f_rec_rawIn_normDist_T_24 = mux(_out_bits_data_f_rec_rawIn_normDist_T_2, UInt<5>(0h14), _out_bits_data_f_rec_rawIn_normDist_T_23) node _out_bits_data_f_rec_rawIn_normDist_T_25 = mux(_out_bits_data_f_rec_rawIn_normDist_T_3, UInt<5>(0h13), _out_bits_data_f_rec_rawIn_normDist_T_24) node _out_bits_data_f_rec_rawIn_normDist_T_26 = mux(_out_bits_data_f_rec_rawIn_normDist_T_4, UInt<5>(0h12), _out_bits_data_f_rec_rawIn_normDist_T_25) node _out_bits_data_f_rec_rawIn_normDist_T_27 = mux(_out_bits_data_f_rec_rawIn_normDist_T_5, UInt<5>(0h11), _out_bits_data_f_rec_rawIn_normDist_T_26) node _out_bits_data_f_rec_rawIn_normDist_T_28 = mux(_out_bits_data_f_rec_rawIn_normDist_T_6, UInt<5>(0h10), _out_bits_data_f_rec_rawIn_normDist_T_27) node _out_bits_data_f_rec_rawIn_normDist_T_29 = mux(_out_bits_data_f_rec_rawIn_normDist_T_7, UInt<4>(0hf), _out_bits_data_f_rec_rawIn_normDist_T_28) node _out_bits_data_f_rec_rawIn_normDist_T_30 = mux(_out_bits_data_f_rec_rawIn_normDist_T_8, UInt<4>(0he), _out_bits_data_f_rec_rawIn_normDist_T_29) node _out_bits_data_f_rec_rawIn_normDist_T_31 = mux(_out_bits_data_f_rec_rawIn_normDist_T_9, UInt<4>(0hd), _out_bits_data_f_rec_rawIn_normDist_T_30) node _out_bits_data_f_rec_rawIn_normDist_T_32 = mux(_out_bits_data_f_rec_rawIn_normDist_T_10, UInt<4>(0hc), _out_bits_data_f_rec_rawIn_normDist_T_31) node _out_bits_data_f_rec_rawIn_normDist_T_33 = mux(_out_bits_data_f_rec_rawIn_normDist_T_11, UInt<4>(0hb), _out_bits_data_f_rec_rawIn_normDist_T_32) node _out_bits_data_f_rec_rawIn_normDist_T_34 = mux(_out_bits_data_f_rec_rawIn_normDist_T_12, UInt<4>(0ha), _out_bits_data_f_rec_rawIn_normDist_T_33) node _out_bits_data_f_rec_rawIn_normDist_T_35 = mux(_out_bits_data_f_rec_rawIn_normDist_T_13, UInt<4>(0h9), _out_bits_data_f_rec_rawIn_normDist_T_34) node _out_bits_data_f_rec_rawIn_normDist_T_36 = mux(_out_bits_data_f_rec_rawIn_normDist_T_14, UInt<4>(0h8), _out_bits_data_f_rec_rawIn_normDist_T_35) node _out_bits_data_f_rec_rawIn_normDist_T_37 = mux(_out_bits_data_f_rec_rawIn_normDist_T_15, UInt<3>(0h7), _out_bits_data_f_rec_rawIn_normDist_T_36) node _out_bits_data_f_rec_rawIn_normDist_T_38 = mux(_out_bits_data_f_rec_rawIn_normDist_T_16, UInt<3>(0h6), _out_bits_data_f_rec_rawIn_normDist_T_37) node _out_bits_data_f_rec_rawIn_normDist_T_39 = mux(_out_bits_data_f_rec_rawIn_normDist_T_17, UInt<3>(0h5), _out_bits_data_f_rec_rawIn_normDist_T_38) node _out_bits_data_f_rec_rawIn_normDist_T_40 = mux(_out_bits_data_f_rec_rawIn_normDist_T_18, UInt<3>(0h4), _out_bits_data_f_rec_rawIn_normDist_T_39) node _out_bits_data_f_rec_rawIn_normDist_T_41 = mux(_out_bits_data_f_rec_rawIn_normDist_T_19, UInt<2>(0h3), _out_bits_data_f_rec_rawIn_normDist_T_40) node _out_bits_data_f_rec_rawIn_normDist_T_42 = mux(_out_bits_data_f_rec_rawIn_normDist_T_20, UInt<2>(0h2), _out_bits_data_f_rec_rawIn_normDist_T_41) node _out_bits_data_f_rec_rawIn_normDist_T_43 = mux(_out_bits_data_f_rec_rawIn_normDist_T_21, UInt<1>(0h1), _out_bits_data_f_rec_rawIn_normDist_T_42) node out_bits_data_f_rec_rawIn_normDist = mux(_out_bits_data_f_rec_rawIn_normDist_T_22, UInt<1>(0h0), _out_bits_data_f_rec_rawIn_normDist_T_43) node _out_bits_data_f_rec_rawIn_subnormFract_T = dshl(out_bits_data_f_rec_rawIn_fractIn, out_bits_data_f_rec_rawIn_normDist) node _out_bits_data_f_rec_rawIn_subnormFract_T_1 = bits(_out_bits_data_f_rec_rawIn_subnormFract_T, 21, 0) node out_bits_data_f_rec_rawIn_subnormFract = shl(_out_bits_data_f_rec_rawIn_subnormFract_T_1, 1) node _out_bits_data_f_rec_rawIn_adjustedExp_T = xor(out_bits_data_f_rec_rawIn_normDist, UInt<9>(0h1ff)) node _out_bits_data_f_rec_rawIn_adjustedExp_T_1 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, _out_bits_data_f_rec_rawIn_adjustedExp_T, out_bits_data_f_rec_rawIn_expIn) node _out_bits_data_f_rec_rawIn_adjustedExp_T_2 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _out_bits_data_f_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _out_bits_data_f_rec_rawIn_adjustedExp_T_2) node _out_bits_data_f_rec_rawIn_adjustedExp_T_4 = add(_out_bits_data_f_rec_rawIn_adjustedExp_T_1, _out_bits_data_f_rec_rawIn_adjustedExp_T_3) node out_bits_data_f_rec_rawIn_adjustedExp = tail(_out_bits_data_f_rec_rawIn_adjustedExp_T_4, 1) node out_bits_data_f_rec_rawIn_isZero = and(out_bits_data_f_rec_rawIn_isZeroExpIn, out_bits_data_f_rec_rawIn_isZeroFractIn) node _out_bits_data_f_rec_rawIn_isSpecial_T = bits(out_bits_data_f_rec_rawIn_adjustedExp, 8, 7) node out_bits_data_f_rec_rawIn_isSpecial = eq(_out_bits_data_f_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire out_bits_data_f_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_data_f_rec_rawIn_out_isNaN_T = eq(out_bits_data_f_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _out_bits_data_f_rec_rawIn_out_isNaN_T_1 = and(out_bits_data_f_rec_rawIn_isSpecial, _out_bits_data_f_rec_rawIn_out_isNaN_T) connect out_bits_data_f_rec_rawIn.isNaN, _out_bits_data_f_rec_rawIn_out_isNaN_T_1 node _out_bits_data_f_rec_rawIn_out_isInf_T = and(out_bits_data_f_rec_rawIn_isSpecial, out_bits_data_f_rec_rawIn_isZeroFractIn) connect out_bits_data_f_rec_rawIn.isInf, _out_bits_data_f_rec_rawIn_out_isInf_T connect out_bits_data_f_rec_rawIn.isZero, out_bits_data_f_rec_rawIn_isZero connect out_bits_data_f_rec_rawIn.sign, out_bits_data_f_rec_rawIn_sign node _out_bits_data_f_rec_rawIn_out_sExp_T = bits(out_bits_data_f_rec_rawIn_adjustedExp, 8, 0) node _out_bits_data_f_rec_rawIn_out_sExp_T_1 = cvt(_out_bits_data_f_rec_rawIn_out_sExp_T) connect out_bits_data_f_rec_rawIn.sExp, _out_bits_data_f_rec_rawIn_out_sExp_T_1 node _out_bits_data_f_rec_rawIn_out_sig_T = eq(out_bits_data_f_rec_rawIn_isZero, UInt<1>(0h0)) node _out_bits_data_f_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_data_f_rec_rawIn_out_sig_T) node _out_bits_data_f_rec_rawIn_out_sig_T_2 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, out_bits_data_f_rec_rawIn_subnormFract, out_bits_data_f_rec_rawIn_fractIn) node _out_bits_data_f_rec_rawIn_out_sig_T_3 = cat(_out_bits_data_f_rec_rawIn_out_sig_T_1, _out_bits_data_f_rec_rawIn_out_sig_T_2) connect out_bits_data_f_rec_rawIn.sig, _out_bits_data_f_rec_rawIn_out_sig_T_3 node _out_bits_data_f_rec_T = bits(out_bits_data_f_rec_rawIn.sExp, 8, 6) node _out_bits_data_f_rec_T_1 = mux(out_bits_data_f_rec_rawIn.isZero, UInt<3>(0h0), _out_bits_data_f_rec_T) node _out_bits_data_f_rec_T_2 = mux(out_bits_data_f_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _out_bits_data_f_rec_T_3 = or(_out_bits_data_f_rec_T_1, _out_bits_data_f_rec_T_2) node _out_bits_data_f_rec_T_4 = cat(out_bits_data_f_rec_rawIn.sign, _out_bits_data_f_rec_T_3) node _out_bits_data_f_rec_T_5 = bits(out_bits_data_f_rec_rawIn.sExp, 5, 0) node _out_bits_data_f_rec_T_6 = cat(_out_bits_data_f_rec_T_4, _out_bits_data_f_rec_T_5) node _out_bits_data_f_rec_T_7 = bits(out_bits_data_f_rec_rawIn.sig, 22, 0) node out_bits_data_f_rec = cat(_out_bits_data_f_rec_T_6, _out_bits_data_f_rec_T_7) inst out_bits_data_in_to_rec_fn of INToRecFN_i8_e8_s24 connect out_bits_data_in_to_rec_fn.io.signedIn, UInt<1>(0h1) wire _out_bits_data_in_to_rec_fn_io_in_WIRE : UInt<8> node _out_bits_data_in_to_rec_fn_io_in_T = asUInt(io.in.bits.data) connect _out_bits_data_in_to_rec_fn_io_in_WIRE, _out_bits_data_in_to_rec_fn_io_in_T connect out_bits_data_in_to_rec_fn.io.in, _out_bits_data_in_to_rec_fn_io_in_WIRE connect out_bits_data_in_to_rec_fn.io.roundingMode, UInt<3>(0h0) connect out_bits_data_in_to_rec_fn.io.detectTininess, UInt<1>(0h1) inst out_bits_data_muladder of MulAddRecFN_e8_s24 connect out_bits_data_muladder.io.op, UInt<1>(0h0) connect out_bits_data_muladder.io.roundingMode, UInt<3>(0h0) connect out_bits_data_muladder.io.detectTininess, UInt<1>(0h1) connect out_bits_data_muladder.io.a, out_bits_data_in_to_rec_fn.io.out connect out_bits_data_muladder.io.b, out_bits_data_f_rec connect out_bits_data_muladder.io.c, UInt<1>(0h0) inst out_bits_data_rec_fn_to_in of RecFNToIN_e8_s24_i8 connect out_bits_data_rec_fn_to_in.clock, clock connect out_bits_data_rec_fn_to_in.reset, reset connect out_bits_data_rec_fn_to_in.io.in, out_bits_data_muladder.io.out connect out_bits_data_rec_fn_to_in.io.roundingMode, UInt<3>(0h0) connect out_bits_data_rec_fn_to_in.io.signedOut, UInt<1>(0h1) node out_bits_data_overflow = bits(out_bits_data_rec_fn_to_in.io.intExceptionFlags, 1, 1) node out_bits_data_sign_exp = bits(out_bits_data_rec_fn_to_in.io.in, 31, 23) node _out_bits_data_sign_isZero_T = bits(out_bits_data_sign_exp, 8, 6) node out_bits_data_sign_isZero = eq(_out_bits_data_sign_isZero_T, UInt<1>(0h0)) node _out_bits_data_sign_isSpecial_T = bits(out_bits_data_sign_exp, 8, 7) node out_bits_data_sign_isSpecial = eq(_out_bits_data_sign_isSpecial_T, UInt<2>(0h3)) wire out_bits_data_sign_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _out_bits_data_sign_out_isNaN_T = bits(out_bits_data_sign_exp, 6, 6) node _out_bits_data_sign_out_isNaN_T_1 = and(out_bits_data_sign_isSpecial, _out_bits_data_sign_out_isNaN_T) connect out_bits_data_sign_out.isNaN, _out_bits_data_sign_out_isNaN_T_1 node _out_bits_data_sign_out_isInf_T = bits(out_bits_data_sign_exp, 6, 6) node _out_bits_data_sign_out_isInf_T_1 = eq(_out_bits_data_sign_out_isInf_T, UInt<1>(0h0)) node _out_bits_data_sign_out_isInf_T_2 = and(out_bits_data_sign_isSpecial, _out_bits_data_sign_out_isInf_T_1) connect out_bits_data_sign_out.isInf, _out_bits_data_sign_out_isInf_T_2 connect out_bits_data_sign_out.isZero, out_bits_data_sign_isZero node _out_bits_data_sign_out_sign_T = bits(out_bits_data_rec_fn_to_in.io.in, 32, 32) connect out_bits_data_sign_out.sign, _out_bits_data_sign_out_sign_T node _out_bits_data_sign_out_sExp_T = cvt(out_bits_data_sign_exp) connect out_bits_data_sign_out.sExp, _out_bits_data_sign_out_sExp_T node _out_bits_data_sign_out_sig_T = eq(out_bits_data_sign_isZero, UInt<1>(0h0)) node _out_bits_data_sign_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_data_sign_out_sig_T) node _out_bits_data_sign_out_sig_T_2 = bits(out_bits_data_rec_fn_to_in.io.in, 22, 0) node _out_bits_data_sign_out_sig_T_3 = cat(_out_bits_data_sign_out_sig_T_1, _out_bits_data_sign_out_sig_T_2) connect out_bits_data_sign_out.sig, _out_bits_data_sign_out_sig_T_3 node out_bits_data_sat = mux(out_bits_data_sign_out.sign, asSInt(UInt<8>(0h80)), asSInt(UInt<8>(0h7f))) wire _out_bits_data_WIRE_2 : SInt<8> node _out_bits_data_T_1 = asSInt(out_bits_data_rec_fn_to_in.io.out) connect _out_bits_data_WIRE_2, _out_bits_data_T_1 node _out_bits_data_T_2 = mux(out_bits_data_overflow, out_bits_data_sat, _out_bits_data_WIRE_2) connect out.bits.data, _out_bits_data_T_2 regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_v, out.valid reg io_out_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when out.valid : connect io_out_pipe_b, out.bits regreset io_out_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_pipe_v, io_out_pipe_v reg io_out_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when io_out_pipe_v : connect io_out_pipe_pipe_b, io_out_pipe_b regreset io_out_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_pipe_pipe_v, io_out_pipe_pipe_v reg io_out_pipe_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when io_out_pipe_pipe_v : connect io_out_pipe_pipe_pipe_b, io_out_pipe_pipe_b regreset io_out_pipe_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_pipe_pipe_pipe_v, io_out_pipe_pipe_pipe_v reg io_out_pipe_pipe_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock when io_out_pipe_pipe_pipe_v : connect io_out_pipe_pipe_pipe_pipe_b, io_out_pipe_pipe_pipe_b wire io_out_pipe_pipe_pipe_pipe_out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}} connect io_out_pipe_pipe_pipe_pipe_out.valid, io_out_pipe_pipe_pipe_pipe_v connect io_out_pipe_pipe_pipe_pipe_out.bits, io_out_pipe_pipe_pipe_pipe_b connect io.out, io_out_pipe_pipe_pipe_pipe_out

module ScalePipe( // @[VectorScalarMultiplier.scala:33:7] input clock, // @[VectorScalarMultiplier.scala:33:7] input reset, // @[VectorScalarMultiplier.scala:33:7] input io_in_valid, // @[VectorScalarMultiplier.scala:35:14] input [7:0] io_in_bits_data, // @[VectorScalarMultiplier.scala:35:14] input [31:0] io_in_bits_scale_bits, // @[VectorScalarMultiplier.scala:35:14] input [1:0] io_in_bits_id, // @[VectorScalarMultiplier.scala:35:14] input [3:0] io_in_bits_index, // @[VectorScalarMultiplier.scala:35:14] output io_out_valid, // @[VectorScalarMultiplier.scala:35:14] output [7:0] io_out_bits_data, // @[VectorScalarMultiplier.scala:35:14] output [1:0] io_out_bits_id, // @[VectorScalarMultiplier.scala:35:14] output [3:0] io_out_bits_index // @[VectorScalarMultiplier.scala:35:14] ); wire out_bits_data_f_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [2:0] _out_bits_data_rec_fn_to_in_io_intExceptionFlags; // @[Configs.scala:93:34] wire [32:0] _out_bits_data_muladder_io_out; // @[Configs.scala:84:30] wire [32:0] _out_bits_data_in_to_rec_fn_io_out; // @[Configs.scala:76:34] wire io_in_valid_0 = io_in_valid; // @[VectorScalarMultiplier.scala:33:7] wire [7:0] io_in_bits_data_0 = io_in_bits_data; // @[VectorScalarMultiplier.scala:33:7] wire [31:0] io_in_bits_scale_bits_0 = io_in_bits_scale_bits; // @[VectorScalarMultiplier.scala:33:7] wire [1:0] io_in_bits_id_0 = io_in_bits_id; // @[VectorScalarMultiplier.scala:33:7] wire [3:0] io_in_bits_index_0 = io_in_bits_index; // @[VectorScalarMultiplier.scala:33:7] wire out_valid = io_in_valid_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire [7:0] _out_bits_data_in_to_rec_fn_io_in_T = io_in_bits_data_0; // @[VectorScalarMultiplier.scala:33:7] wire [31:0] out_bits_scale_bits = io_in_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire [31:0] _out_bits_data_WIRE_1 = io_in_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:33:7, :41:89] wire [1:0] out_bits_id = io_in_bits_id_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire [3:0] out_bits_index = io_in_bits_index_0; // @[VectorScalarMultiplier.scala:33:7, :40:21] wire io_out_pipe_pipe_pipe_pipe_out_valid; // @[Valid.scala:135:21] wire [7:0] io_out_pipe_pipe_pipe_pipe_out_bits_data; // @[Valid.scala:135:21] wire [31:0] io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits; // @[Valid.scala:135:21] wire [1:0] io_out_pipe_pipe_pipe_pipe_out_bits_id; // @[Valid.scala:135:21] wire [3:0] io_out_pipe_pipe_pipe_pipe_out_bits_index; // @[Valid.scala:135:21] wire [31:0] io_out_bits_scale_bits; // @[VectorScalarMultiplier.scala:33:7] wire [7:0] io_out_bits_data_0; // @[VectorScalarMultiplier.scala:33:7] wire [1:0] io_out_bits_id_0; // @[VectorScalarMultiplier.scala:33:7] wire [3:0] io_out_bits_index_0; // @[VectorScalarMultiplier.scala:33:7] wire io_out_valid_0; // @[VectorScalarMultiplier.scala:33:7] wire [7:0] _out_bits_data_T_2; // @[Configs.scala:104:12] wire [7:0] out_bits_data; // @[VectorScalarMultiplier.scala:40:21] wire [31:0] _out_bits_data_T; // @[VectorScalarMultiplier.scala:41:89] assign _out_bits_data_T = _out_bits_data_WIRE_1; // @[VectorScalarMultiplier.scala:41:89] wire [31:0] _out_bits_data_WIRE_bits = _out_bits_data_T; // @[VectorScalarMultiplier.scala:41:89] wire out_bits_data_f_rec_rawIn_sign = _out_bits_data_WIRE_bits[31]; // @[rawFloatFromFN.scala:44:18] wire out_bits_data_f_rec_rawIn_sign_0 = out_bits_data_f_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] out_bits_data_f_rec_rawIn_expIn = _out_bits_data_WIRE_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] out_bits_data_f_rec_rawIn_fractIn = _out_bits_data_WIRE_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire out_bits_data_f_rec_rawIn_isZeroExpIn = out_bits_data_f_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire out_bits_data_f_rec_rawIn_isZeroFractIn = out_bits_data_f_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _out_bits_data_f_rec_rawIn_normDist_T = out_bits_data_f_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_1 = out_bits_data_f_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_2 = out_bits_data_f_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_3 = out_bits_data_f_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_4 = out_bits_data_f_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_5 = out_bits_data_f_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_6 = out_bits_data_f_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_7 = out_bits_data_f_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_8 = out_bits_data_f_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_9 = out_bits_data_f_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_10 = out_bits_data_f_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_11 = out_bits_data_f_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_12 = out_bits_data_f_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_13 = out_bits_data_f_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_14 = out_bits_data_f_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_15 = out_bits_data_f_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_16 = out_bits_data_f_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_17 = out_bits_data_f_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_18 = out_bits_data_f_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_19 = out_bits_data_f_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_20 = out_bits_data_f_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_21 = out_bits_data_f_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _out_bits_data_f_rec_rawIn_normDist_T_22 = out_bits_data_f_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_23 = _out_bits_data_f_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_24 = _out_bits_data_f_rec_rawIn_normDist_T_2 ? 5'h14 : _out_bits_data_f_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_25 = _out_bits_data_f_rec_rawIn_normDist_T_3 ? 5'h13 : _out_bits_data_f_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_26 = _out_bits_data_f_rec_rawIn_normDist_T_4 ? 5'h12 : _out_bits_data_f_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_27 = _out_bits_data_f_rec_rawIn_normDist_T_5 ? 5'h11 : _out_bits_data_f_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_28 = _out_bits_data_f_rec_rawIn_normDist_T_6 ? 5'h10 : _out_bits_data_f_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_29 = _out_bits_data_f_rec_rawIn_normDist_T_7 ? 5'hF : _out_bits_data_f_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_30 = _out_bits_data_f_rec_rawIn_normDist_T_8 ? 5'hE : _out_bits_data_f_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_31 = _out_bits_data_f_rec_rawIn_normDist_T_9 ? 5'hD : _out_bits_data_f_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_32 = _out_bits_data_f_rec_rawIn_normDist_T_10 ? 5'hC : _out_bits_data_f_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_33 = _out_bits_data_f_rec_rawIn_normDist_T_11 ? 5'hB : _out_bits_data_f_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_34 = _out_bits_data_f_rec_rawIn_normDist_T_12 ? 5'hA : _out_bits_data_f_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_35 = _out_bits_data_f_rec_rawIn_normDist_T_13 ? 5'h9 : _out_bits_data_f_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_36 = _out_bits_data_f_rec_rawIn_normDist_T_14 ? 5'h8 : _out_bits_data_f_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_37 = _out_bits_data_f_rec_rawIn_normDist_T_15 ? 5'h7 : _out_bits_data_f_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_38 = _out_bits_data_f_rec_rawIn_normDist_T_16 ? 5'h6 : _out_bits_data_f_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_39 = _out_bits_data_f_rec_rawIn_normDist_T_17 ? 5'h5 : _out_bits_data_f_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_40 = _out_bits_data_f_rec_rawIn_normDist_T_18 ? 5'h4 : _out_bits_data_f_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_41 = _out_bits_data_f_rec_rawIn_normDist_T_19 ? 5'h3 : _out_bits_data_f_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_42 = _out_bits_data_f_rec_rawIn_normDist_T_20 ? 5'h2 : _out_bits_data_f_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_43 = _out_bits_data_f_rec_rawIn_normDist_T_21 ? 5'h1 : _out_bits_data_f_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] out_bits_data_f_rec_rawIn_normDist = _out_bits_data_f_rec_rawIn_normDist_T_22 ? 5'h0 : _out_bits_data_f_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _out_bits_data_f_rec_rawIn_subnormFract_T = {31'h0, out_bits_data_f_rec_rawIn_fractIn} << out_bits_data_f_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _out_bits_data_f_rec_rawIn_subnormFract_T_1 = _out_bits_data_f_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] out_bits_data_f_rec_rawIn_subnormFract = {_out_bits_data_f_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _out_bits_data_f_rec_rawIn_adjustedExp_T = {4'hF, ~out_bits_data_f_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_1 = out_bits_data_f_rec_rawIn_isZeroExpIn ? _out_bits_data_f_rec_rawIn_adjustedExp_T : {1'h0, out_bits_data_f_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_2 = out_bits_data_f_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_3 = {6'h20, _out_bits_data_f_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_4 = {1'h0, _out_bits_data_f_rec_rawIn_adjustedExp_T_1} + {2'h0, _out_bits_data_f_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] out_bits_data_f_rec_rawIn_adjustedExp = _out_bits_data_f_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _out_bits_data_f_rec_rawIn_out_sExp_T = out_bits_data_f_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire out_bits_data_f_rec_rawIn_isZero = out_bits_data_f_rec_rawIn_isZeroExpIn & out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire out_bits_data_f_rec_rawIn_isZero_0 = out_bits_data_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _out_bits_data_f_rec_rawIn_isSpecial_T = out_bits_data_f_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire out_bits_data_f_rec_rawIn_isSpecial = &_out_bits_data_f_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _out_bits_data_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _out_bits_data_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _out_bits_data_f_rec_T_2 = out_bits_data_f_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _out_bits_data_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _out_bits_data_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire out_bits_data_f_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] out_bits_data_f_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] out_bits_data_f_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _out_bits_data_f_rec_rawIn_out_isNaN_T = ~out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _out_bits_data_f_rec_rawIn_out_isNaN_T_1 = out_bits_data_f_rec_rawIn_isSpecial & _out_bits_data_f_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign out_bits_data_f_rec_rawIn_isNaN = _out_bits_data_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _out_bits_data_f_rec_rawIn_out_isInf_T = out_bits_data_f_rec_rawIn_isSpecial & out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign out_bits_data_f_rec_rawIn_isInf = _out_bits_data_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _out_bits_data_f_rec_rawIn_out_sExp_T_1 = {1'h0, _out_bits_data_f_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign out_bits_data_f_rec_rawIn_sExp = _out_bits_data_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _out_bits_data_f_rec_rawIn_out_sig_T = ~out_bits_data_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _out_bits_data_f_rec_rawIn_out_sig_T_1 = {1'h0, _out_bits_data_f_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _out_bits_data_f_rec_rawIn_out_sig_T_2 = out_bits_data_f_rec_rawIn_isZeroExpIn ? out_bits_data_f_rec_rawIn_subnormFract : out_bits_data_f_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _out_bits_data_f_rec_rawIn_out_sig_T_3 = {_out_bits_data_f_rec_rawIn_out_sig_T_1, _out_bits_data_f_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign out_bits_data_f_rec_rawIn_sig = _out_bits_data_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _out_bits_data_f_rec_T = out_bits_data_f_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _out_bits_data_f_rec_T_1 = out_bits_data_f_rec_rawIn_isZero_0 ? 3'h0 : _out_bits_data_f_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _out_bits_data_f_rec_T_3 = {_out_bits_data_f_rec_T_1[2:1], _out_bits_data_f_rec_T_1[0] | _out_bits_data_f_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _out_bits_data_f_rec_T_4 = {out_bits_data_f_rec_rawIn_sign_0, _out_bits_data_f_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _out_bits_data_f_rec_T_5 = out_bits_data_f_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _out_bits_data_f_rec_T_6 = {_out_bits_data_f_rec_T_4, _out_bits_data_f_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _out_bits_data_f_rec_T_7 = out_bits_data_f_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] out_bits_data_f_rec = {_out_bits_data_f_rec_T_6, _out_bits_data_f_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] _out_bits_data_in_to_rec_fn_io_in_WIRE = _out_bits_data_in_to_rec_fn_io_in_T; // @[Configs.scala:78:41] wire out_bits_data_overflow = _out_bits_data_rec_fn_to_in_io_intExceptionFlags[1]; // @[Configs.scala:93:34, :98:57] wire [8:0] out_bits_data_sign_exp = _out_bits_data_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _out_bits_data_sign_isZero_T = out_bits_data_sign_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire out_bits_data_sign_isZero = _out_bits_data_sign_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire out_bits_data_sign_out_isZero = out_bits_data_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _out_bits_data_sign_isSpecial_T = out_bits_data_sign_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire out_bits_data_sign_isSpecial = &_out_bits_data_sign_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _out_bits_data_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _out_bits_data_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _out_bits_data_sign_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _out_bits_data_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _out_bits_data_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire out_bits_data_sign_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_data_sign_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire out_bits_data_sign_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] out_bits_data_sign_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] out_bits_data_sign_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _out_bits_data_sign_out_isNaN_T = out_bits_data_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _out_bits_data_sign_out_isInf_T = out_bits_data_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _out_bits_data_sign_out_isNaN_T_1 = out_bits_data_sign_isSpecial & _out_bits_data_sign_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign out_bits_data_sign_out_isNaN = _out_bits_data_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _out_bits_data_sign_out_isInf_T_1 = ~_out_bits_data_sign_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _out_bits_data_sign_out_isInf_T_2 = out_bits_data_sign_isSpecial & _out_bits_data_sign_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign out_bits_data_sign_out_isInf = _out_bits_data_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _out_bits_data_sign_out_sign_T = _out_bits_data_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign out_bits_data_sign_out_sign = _out_bits_data_sign_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _out_bits_data_sign_out_sExp_T = {1'h0, out_bits_data_sign_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign out_bits_data_sign_out_sExp = _out_bits_data_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _out_bits_data_sign_out_sig_T = ~out_bits_data_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _out_bits_data_sign_out_sig_T_1 = {1'h0, _out_bits_data_sign_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _out_bits_data_sign_out_sig_T_2 = _out_bits_data_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _out_bits_data_sign_out_sig_T_3 = {_out_bits_data_sign_out_sig_T_1, _out_bits_data_sign_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign out_bits_data_sign_out_sig = _out_bits_data_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [7:0] out_bits_data_sat = out_bits_data_sign_out_sign ? 8'h80 : 8'h7F; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _out_bits_data_T_1; // @[Configs.scala:104:56] wire [7:0] _out_bits_data_WIRE_2 = _out_bits_data_T_1; // @[Configs.scala:104:56] assign _out_bits_data_T_2 = out_bits_data_overflow ? out_bits_data_sat : _out_bits_data_WIRE_2; // @[Configs.scala:98:57, :102:22, :104:{12,56}] assign out_bits_data = _out_bits_data_T_2; // @[VectorScalarMultiplier.scala:40:21] reg io_out_pipe_v; // @[Valid.scala:141:24] reg [7:0] io_out_pipe_b_data; // @[Valid.scala:142:26] reg [31:0] io_out_pipe_b_scale_bits; // @[Valid.scala:142:26] reg [1:0] io_out_pipe_b_id; // @[Valid.scala:142:26] reg [3:0] io_out_pipe_b_index; // @[Valid.scala:142:26] reg io_out_pipe_pipe_v; // @[Valid.scala:141:24] reg [7:0] io_out_pipe_pipe_b_data; // @[Valid.scala:142:26] reg [31:0] io_out_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] reg [1:0] io_out_pipe_pipe_b_id; // @[Valid.scala:142:26] reg [3:0] io_out_pipe_pipe_b_index; // @[Valid.scala:142:26] reg io_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24] reg [7:0] io_out_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26] reg [31:0] io_out_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] reg [1:0] io_out_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26] reg [3:0] io_out_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26] reg io_out_pipe_pipe_pipe_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_pipe_pipe_pipe_out_valid = io_out_pipe_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg [7:0] io_out_pipe_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_data = io_out_pipe_pipe_pipe_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [31:0] io_out_pipe_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits = io_out_pipe_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:135:21, :142:26] reg [1:0] io_out_pipe_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_id = io_out_pipe_pipe_pipe_pipe_b_id; // @[Valid.scala:135:21, :142:26] reg [3:0] io_out_pipe_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26] assign io_out_pipe_pipe_pipe_pipe_out_bits_index = io_out_pipe_pipe_pipe_pipe_b_index; // @[Valid.scala:135:21, :142:26] assign io_out_valid_0 = io_out_pipe_pipe_pipe_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_pipe_pipe_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_scale_bits = io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits; // @[Valid.scala:135:21] assign io_out_bits_id_0 = io_out_pipe_pipe_pipe_pipe_out_bits_id; // @[Valid.scala:135:21] assign io_out_bits_index_0 = io_out_pipe_pipe_pipe_pipe_out_bits_index; // @[Valid.scala:135:21] always @(posedge clock) begin // @[VectorScalarMultiplier.scala:33:7] if (reset) begin // @[VectorScalarMultiplier.scala:33:7] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[VectorScalarMultiplier.scala:33:7] io_out_pipe_v <= out_valid; // @[Valid.scala:141:24] io_out_pipe_pipe_v <= io_out_pipe_v; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_v <= io_out_pipe_pipe_v; // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_pipe_v <= io_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24] end if (out_valid) begin // @[VectorScalarMultiplier.scala:40:21] io_out_pipe_b_data <= out_bits_data; // @[Valid.scala:142:26] io_out_pipe_b_scale_bits <= out_bits_scale_bits; // @[Valid.scala:142:26] io_out_pipe_b_id <= out_bits_id; // @[Valid.scala:142:26] io_out_pipe_b_index <= out_bits_index; // @[Valid.scala:142:26] end if (io_out_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_pipe_b_data <= io_out_pipe_b_data; // @[Valid.scala:142:26] io_out_pipe_pipe_b_scale_bits <= io_out_pipe_b_scale_bits; // @[Valid.scala:142:26] io_out_pipe_pipe_b_id <= io_out_pipe_b_id; // @[Valid.scala:142:26] io_out_pipe_pipe_b_index <= io_out_pipe_b_index; // @[Valid.scala:142:26] end if (io_out_pipe_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_b_data; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_b_scale_bits <= io_out_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_b_id <= io_out_pipe_pipe_b_id; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_b_index <= io_out_pipe_pipe_b_index; // @[Valid.scala:142:26] end if (io_out_pipe_pipe_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_pipe_b_scale_bits <= io_out_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_pipe_b_id <= io_out_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26] io_out_pipe_pipe_pipe_pipe_b_index <= io_out_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26] end always @(posedge) INToRecFN_i8_e8_s24 out_bits_data_in_to_rec_fn ( // @[Configs.scala:76:34] .io_in (_out_bits_data_in_to_rec_fn_io_in_WIRE), // @[Configs.scala:78:41] .io_out (_out_bits_data_in_to_rec_fn_io_out) ); // @[Configs.scala:76:34] MulAddRecFN_e8_s24 out_bits_data_muladder ( // @[Configs.scala:84:30] .io_a (_out_bits_data_in_to_rec_fn_io_out), // @[Configs.scala:76:34] .io_b (out_bits_data_f_rec), // @[recFNFromFN.scala:50:41] .io_out (_out_bits_data_muladder_io_out) ); // @[Configs.scala:84:30] RecFNToIN_e8_s24_i8 out_bits_data_rec_fn_to_in ( // @[Configs.scala:93:34] .clock (clock), .reset (reset), .io_in (_out_bits_data_muladder_io_out), // @[Configs.scala:84:30] .io_out (_out_bits_data_T_1), .io_intExceptionFlags (_out_bits_data_rec_fn_to_in_io_intExceptionFlags) ); // @[Configs.scala:93:34] assign io_out_valid = io_out_valid_0; // @[VectorScalarMultiplier.scala:33:7] assign io_out_bits_data = io_out_bits_data_0; // @[VectorScalarMultiplier.scala:33:7] assign io_out_bits_id = io_out_bits_id_0; // @[VectorScalarMultiplier.scala:33:7] assign io_out_bits_index = io_out_bits_index_0; // @[VectorScalarMultiplier.scala:33:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_2 : input clock : Clock input reset : Reset output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<4>(0hf)) when _T : connect doing_reset, UInt<1>(0h0) reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0)) node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0) wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect f2_entry, entries[_f2_entry_T_1] node _T_1 = eq(io.update_idx, io.f2_req_idx) node _T_2 = and(io.update_repair, _T_1) when _T_2 : connect f2_entry.s_cnt, io.update_meta.s_cnt else : node _T_3 = eq(io.update_idx, io.f2_req_idx) node _T_4 = and(io.update_mispredict, _T_3) when _T_4 : connect f2_entry.s_cnt, UInt<1>(0h0) reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f3_entry, f2_entry reg f3_scnt_REG : UInt, clock connect f3_scnt_REG, io.f2_req_idx node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) node _f3_tag_T = bits(io.f2_req_idx, 13, 4) reg f3_tag : UInt, clock connect f3_tag, _f3_tag_T connect io.f3_pred, io.f3_pred_in connect io.f3_meta.s_cnt, f3_scnt node _T_5 = eq(f3_entry.tag, f3_tag) when _T_5 : node _T_6 = eq(f3_scnt, f3_entry.p_cnt) node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) connect io.f3_pred, _io_f3_pred_T reg f4_fire : UInt<1>, clock connect f4_fire, io.f3_req_fire reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f4_entry, f3_entry reg f4_tag : UInt, clock connect f4_tag, f3_tag reg f4_scnt : UInt, clock connect f4_scnt, f3_scnt reg f4_idx_REG : UInt, clock connect f4_idx_REG, io.f2_req_idx reg f4_idx : UInt, clock connect f4_idx, f4_idx_REG when f4_fire : node _T_9 = eq(f4_entry.tag, f4_tag) when _T_9 : node _T_10 = eq(f4_scnt, f4_entry.p_cnt) node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _T_13 = or(f4_idx, UInt<4>(0h0)) node _T_14 = bits(_T_13, 3, 0) connect entries[_T_14].age, UInt<3>(0h7) node _T_15 = or(f4_idx, UInt<4>(0h0)) node _T_16 = bits(_T_15, 3, 0) connect entries[_T_16].s_cnt, UInt<1>(0h0) else : node _T_17 = or(f4_idx, UInt<4>(0h0)) node _T_18 = bits(_T_17, 3, 0) node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 node _T_19 = or(f4_idx, UInt<4>(0h0)) node _T_20 = bits(_T_19, 3, 0) node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) node _entries_age_T_2 = tail(_entries_age_T_1, 1) node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) connect entries[_T_20].age, _entries_age_T_3 node _entry_T = or(io.update_idx, UInt<4>(0h0)) node _entry_T_1 = bits(_entry_T, 3, 0) node tag = bits(io.update_idx, 13, 4) node tag_match = eq(entries[_entry_T_1].tag, tag) node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect wentry, entries[_entry_T_1] node _T_21 = eq(doing_reset, UInt<1>(0h0)) node _T_22 = and(io.update_mispredict, _T_21) when _T_22 : node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_24 = and(_T_23, tag_match) when _T_24 : connect wentry.s_cnt, UInt<1>(0h0) connect wentry.conf, UInt<1>(0h0) else : node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_26 = eq(tag_match, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : skip else : node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_29 = and(_T_28, tag_match) node _T_30 = and(_T_29, ctr_match) when _T_30 : node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) connect wentry.conf, _wentry_conf_T_1 connect wentry.s_cnt, UInt<1>(0h0) else : node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_32 = and(_T_31, tag_match) node _T_33 = eq(ctr_match, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) when _T_34 : connect wentry.conf, UInt<1>(0h0) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_36 = eq(tag_match, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_41 = eq(tag_match, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) when _T_44 : node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) node _wentry_age_T_1 = tail(_wentry_age_T, 1) connect wentry.age, _wentry_age_T_1 else : node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_46 = and(_T_45, tag_match) node _T_47 = and(_T_46, ctr_match) when _T_47 : connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_49 = and(_T_48, tag_match) node _T_50 = eq(ctr_match, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect wentry.p_cnt, io.update_meta.s_cnt connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_53 = eq(tag_match, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt node _T_55 = or(io.update_idx, UInt<4>(0h0)) node _T_56 = bits(_T_55, 3, 0) connect entries[_T_56], wentry else : node _T_57 = eq(doing_reset, UInt<1>(0h0)) node _T_58 = and(io.update_repair, _T_57) when _T_58 : node _T_59 = eq(io.update_idx, f4_idx) node _T_60 = and(f4_fire, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(tag_match, _T_61) when _T_62 : connect wentry.s_cnt, io.update_meta.s_cnt node _T_63 = or(io.update_idx, UInt<4>(0h0)) node _T_64 = bits(_T_63, 3, 0) connect entries[_T_64], wentry when doing_reset : wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect _entries_WIRE.s_cnt, UInt<10>(0h0) connect _entries_WIRE.p_cnt, UInt<10>(0h0) connect _entries_WIRE.age, UInt<3>(0h0) connect _entries_WIRE.conf, UInt<3>(0h0) connect _entries_WIRE.tag, UInt<10>(0h0) connect entries[reset_idx], _entries_WIRE

module LoopBranchPredictorColumn_2( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [36:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [36:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [36:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [36:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [36:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [36:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [36:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [36:0] f4_idx_REG; // @[loop.scala:92:35] reg [36:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_1 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_1 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T

module IntSyncCrossingSource_n1x1_1( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_1 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_77 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} inst input_buffer of InputBuffer_77 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) inst route_arbiter of Arbiter2_RouteComputerReq_31 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2] wire vcalloc_vals : UInt<1>[2] node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0)) node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11) node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_18 = and(io.router_req.ready, io.router_req.valid) when _T_18 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1]) when _T_19 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = bits(vcalloc_sel, 0, 0) node _mask_T_6 = bits(vcalloc_sel, 1, 1) node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_7, _mask_T_8) wire _mask_WIRE : UInt<2> connect _mask_WIRE, _mask_T_9 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2] node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10 connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2] node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1] node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_14 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_15 : UInt<2> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_14.egress_node_id, _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_16 : UInt<4> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_14.egress_node, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_34 connect _io_vcalloc_req_bits_WIRE_14.ingress_node_id, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_18 : UInt<4> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_14.ingress_node, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_14.vnet_id, _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_14 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_20 = bits(vcalloc_sel, 1, 1) node _T_21 = and(vcalloc_vals[1], _T_20) node _T_22 = and(_T_21, io.vcalloc_req.ready) when _T_22 : connect states[1].g, UInt<3>(0h3) node _T_23 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_23 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready) node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1) connect io.debug.va_stall, _io_debug_va_stall_T_3 node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_24 : node _T_25 = bits(vcalloc_sel, 0, 0) when _T_25 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_26 = bits(vcalloc_sel, 1, 1) when _T_26 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_190 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] node _credit_available_T = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node _credit_available_T_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node _credit_available_T_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi = cat(states[1].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi, credit_available_lo) node _credit_available_T_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _credit_available_T_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node _credit_available_T_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_1 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_27 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_28 = and(_T_27, input_buffer.io.deq[1].bits.tail) when _T_28 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_5 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5 node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_7 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1) connect salloc_outs[0].vid, _salloc_outs_0_vid_T node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _vc_sel_WIRE : UInt<1>[2] node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_4 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_7 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_3 : UInt<1>[2] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_10 connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4 node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_13 connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5 connect vc_sel.`1`, _vc_sel_WIRE_3 wire _vc_sel_WIRE_6 : UInt<1>[2] node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_16 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_19 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 connect vc_sel.`2`, _vc_sel_WIRE_6 wire _vc_sel_WIRE_9 : UInt<1>[1] node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_22 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 connect vc_sel.`3`, _vc_sel_WIRE_9 node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1) node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0)) node _virt_channel_T_7 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0)) node _virt_channel_T_8 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = or(_virt_channel_T_6, _virt_channel_T_7) node _virt_channel_T_11 = or(_virt_channel_T_10, _virt_channel_T_8) node _virt_channel_T_12 = or(_virt_channel_T_11, _virt_channel_T_9) wire virt_channel : UInt<1> connect virt_channel, _virt_channel_T_12 node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_29 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3) wire _salloc_outs_0_flit_payload_WIRE : UInt<37> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`3`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) node _T_30 = asUInt(reset) when _T_30 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0)

module InputUnit_77( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_2_1; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire _GEN_1 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_62 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_62( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_434 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_178 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_434( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_178 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_34 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_68 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_34 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0he) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0he)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_18 = eq(UInt<5>(0h10), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(UInt<5>(0h11), io.in.bits.egress_id) when _T_19 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_21 = and(route_q.io.enq.valid, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_22, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_69 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_34 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_27 = and(vcalloc_q.io.enq.valid, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_34( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h1E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h1B; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_12 = {1'h0, {1'h0, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T}}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h5 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hA : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'h9 : 4'h0); // @[Mux.scala:30:73] wire [2:0] _GEN_0 = _route_buffer_io_enq_bits_flow_egress_node_T_12[2:0] | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h6 : 3'h0); // @[Mux.scala:30:73] wire [3:0] _GEN_1 = {_route_buffer_io_enq_bits_flow_egress_node_T_12[3], _GEN_0}; // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_1 == 4'hE; // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_1 != 4'hE; // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 connect _source_ok_WIRE[9], _source_ok_T_44 node _source_ok_T_45 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[2]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[3]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[4]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[5]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[6]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[7]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_52, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h3)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<2>(0h2)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<4>(0h8)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_112 = eq(_T_111, UInt<1>(0h0)) node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_114 = cvt(_T_113) node _T_115 = and(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = asSInt(_T_115) node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0))) node _T_118 = or(_T_112, _T_117) node _T_119 = and(_T_11, _T_24) node _T_120 = and(_T_119, _T_37) node _T_121 = and(_T_120, _T_50) node _T_122 = and(_T_121, _T_63) node _T_123 = and(_T_122, _T_76) node _T_124 = and(_T_123, _T_89) node _T_125 = and(_T_124, _T_102) node _T_126 = and(_T_125, _T_110) node _T_127 = and(_T_126, _T_118) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_127, UInt<1>(0h1), "") : assert_1 node _T_131 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_131 : node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_136 = shr(io.in.a.bits.source, 2) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = leq(UInt<1>(0h0), uncommonBits_7) node _T_139 = and(_T_137, _T_138) node _T_140 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_141 = and(_T_139, _T_140) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_142 = shr(io.in.a.bits.source, 2) node _T_143 = eq(_T_142, UInt<1>(0h1)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_8) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_147 = and(_T_145, _T_146) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_148 = shr(io.in.a.bits.source, 2) node _T_149 = eq(_T_148, UInt<2>(0h2)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_9) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_154 = shr(io.in.a.bits.source, 2) node _T_155 = eq(_T_154, UInt<2>(0h3)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_10) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_159 = and(_T_157, _T_158) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_160 = shr(io.in.a.bits.source, 3) node _T_161 = eq(_T_160, UInt<2>(0h3)) node _T_162 = leq(UInt<1>(0h0), uncommonBits_11) node _T_163 = and(_T_161, _T_162) node _T_164 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_165 = and(_T_163, _T_164) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_166 = shr(io.in.a.bits.source, 3) node _T_167 = eq(_T_166, UInt<2>(0h2)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_12) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_172 = shr(io.in.a.bits.source, 3) node _T_173 = eq(_T_172, UInt<4>(0h8)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_13) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_179 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_180 = or(_T_135, _T_141) node _T_181 = or(_T_180, _T_147) node _T_182 = or(_T_181, _T_153) node _T_183 = or(_T_182, _T_159) node _T_184 = or(_T_183, _T_165) node _T_185 = or(_T_184, _T_171) node _T_186 = or(_T_185, _T_177) node _T_187 = or(_T_186, _T_178) node _T_188 = or(_T_187, _T_179) node _T_189 = and(_T_134, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_192 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<14>(0h2000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<13>(0h1000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<17>(0h10000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<18>(0h2f000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<17>(0h10000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<13>(0h1000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<27>(0h4000000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<13>(0h1000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_196, _T_201) node _T_238 = or(_T_237, _T_206) node _T_239 = or(_T_238, _T_211) node _T_240 = or(_T_239, _T_216) node _T_241 = or(_T_240, _T_221) node _T_242 = or(_T_241, _T_226) node _T_243 = or(_T_242, _T_231) node _T_244 = or(_T_243, _T_236) node _T_245 = and(_T_191, _T_244) node _T_246 = or(UInt<1>(0h0), _T_245) node _T_247 = and(_T_190, _T_246) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_247, UInt<1>(0h1), "") : assert_2 node _T_251 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_14) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_15) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_16) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_17) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_276 = shr(io.in.a.bits.source, 3) node _T_277 = eq(_T_276, UInt<2>(0h3)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_18) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_281 = and(_T_279, _T_280) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_282 = shr(io.in.a.bits.source, 3) node _T_283 = eq(_T_282, UInt<2>(0h2)) node _T_284 = leq(UInt<1>(0h0), uncommonBits_19) node _T_285 = and(_T_283, _T_284) node _T_286 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_287 = and(_T_285, _T_286) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_288 = shr(io.in.a.bits.source, 3) node _T_289 = eq(_T_288, UInt<4>(0h8)) node _T_290 = leq(UInt<1>(0h0), uncommonBits_20) node _T_291 = and(_T_289, _T_290) node _T_292 = leq(uncommonBits_20, UInt<3>(0h4)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_295 = eq(io.in.a.bits.source, UInt<7>(0h48)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_251 connect _WIRE[1], _T_257 connect _WIRE[2], _T_263 connect _WIRE[3], _T_269 connect _WIRE[4], _T_275 connect _WIRE[5], _T_281 connect _WIRE[6], _T_287 connect _WIRE[7], _T_293 connect _WIRE[8], _T_294 connect _WIRE[9], _T_295 node _T_296 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_297 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_298 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_299 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_302 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_304 = mux(_WIRE[7], _T_296, UInt<1>(0h0)) node _T_305 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_306 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_307 = or(_T_297, _T_298) node _T_308 = or(_T_307, _T_299) node _T_309 = or(_T_308, _T_300) node _T_310 = or(_T_309, _T_301) node _T_311 = or(_T_310, _T_302) node _T_312 = or(_T_311, _T_303) node _T_313 = or(_T_312, _T_304) node _T_314 = or(_T_313, _T_305) node _T_315 = or(_T_314, _T_306) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_315 node _T_316 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_317 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_318 = and(_T_316, _T_317) node _T_319 = or(UInt<1>(0h0), _T_318) node _T_320 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<14>(0h2000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<13>(0h1000))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_324, _T_329) node _T_366 = or(_T_365, _T_334) node _T_367 = or(_T_366, _T_339) node _T_368 = or(_T_367, _T_344) node _T_369 = or(_T_368, _T_349) node _T_370 = or(_T_369, _T_354) node _T_371 = or(_T_370, _T_359) node _T_372 = or(_T_371, _T_364) node _T_373 = and(_T_319, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_WIRE_1, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_375, UInt<1>(0h1), "") : assert_3 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(source_ok, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_382 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_382, UInt<1>(0h1), "") : assert_5 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(is_aligned, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_389 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_389, UInt<1>(0h1), "") : assert_7 node _T_393 = not(io.in.a.bits.mask) node _T_394 = eq(_T_393, UInt<1>(0h0)) node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_T_394, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_394, UInt<1>(0h1), "") : assert_8 node _T_398 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_398, UInt<1>(0h1), "") : assert_9 node _T_402 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_402 : node _T_403 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_404 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_21) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<1>(0h1)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_22) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_419 = shr(io.in.a.bits.source, 2) node _T_420 = eq(_T_419, UInt<2>(0h2)) node _T_421 = leq(UInt<1>(0h0), uncommonBits_23) node _T_422 = and(_T_420, _T_421) node _T_423 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_424 = and(_T_422, _T_423) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_425 = shr(io.in.a.bits.source, 2) node _T_426 = eq(_T_425, UInt<2>(0h3)) node _T_427 = leq(UInt<1>(0h0), uncommonBits_24) node _T_428 = and(_T_426, _T_427) node _T_429 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_430 = and(_T_428, _T_429) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_431 = shr(io.in.a.bits.source, 3) node _T_432 = eq(_T_431, UInt<2>(0h3)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_25) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_436 = and(_T_434, _T_435) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_437 = shr(io.in.a.bits.source, 3) node _T_438 = eq(_T_437, UInt<2>(0h2)) node _T_439 = leq(UInt<1>(0h0), uncommonBits_26) node _T_440 = and(_T_438, _T_439) node _T_441 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_442 = and(_T_440, _T_441) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_443 = shr(io.in.a.bits.source, 3) node _T_444 = eq(_T_443, UInt<4>(0h8)) node _T_445 = leq(UInt<1>(0h0), uncommonBits_27) node _T_446 = and(_T_444, _T_445) node _T_447 = leq(uncommonBits_27, UInt<3>(0h4)) node _T_448 = and(_T_446, _T_447) node _T_449 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_450 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_451 = or(_T_406, _T_412) node _T_452 = or(_T_451, _T_418) node _T_453 = or(_T_452, _T_424) node _T_454 = or(_T_453, _T_430) node _T_455 = or(_T_454, _T_436) node _T_456 = or(_T_455, _T_442) node _T_457 = or(_T_456, _T_448) node _T_458 = or(_T_457, _T_449) node _T_459 = or(_T_458, _T_450) node _T_460 = and(_T_405, _T_459) node _T_461 = or(UInt<1>(0h0), _T_460) node _T_462 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_464 = cvt(_T_463) node _T_465 = and(_T_464, asSInt(UInt<14>(0h2000))) node _T_466 = asSInt(_T_465) node _T_467 = eq(_T_466, asSInt(UInt<1>(0h0))) node _T_468 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_469 = cvt(_T_468) node _T_470 = and(_T_469, asSInt(UInt<13>(0h1000))) node _T_471 = asSInt(_T_470) node _T_472 = eq(_T_471, asSInt(UInt<1>(0h0))) node _T_473 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_474 = cvt(_T_473) node _T_475 = and(_T_474, asSInt(UInt<17>(0h10000))) node _T_476 = asSInt(_T_475) node _T_477 = eq(_T_476, asSInt(UInt<1>(0h0))) node _T_478 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_479 = cvt(_T_478) node _T_480 = and(_T_479, asSInt(UInt<18>(0h2f000))) node _T_481 = asSInt(_T_480) node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0))) node _T_483 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_484 = cvt(_T_483) node _T_485 = and(_T_484, asSInt(UInt<17>(0h10000))) node _T_486 = asSInt(_T_485) node _T_487 = eq(_T_486, asSInt(UInt<1>(0h0))) node _T_488 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_489 = cvt(_T_488) node _T_490 = and(_T_489, asSInt(UInt<13>(0h1000))) node _T_491 = asSInt(_T_490) node _T_492 = eq(_T_491, asSInt(UInt<1>(0h0))) node _T_493 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_494 = cvt(_T_493) node _T_495 = and(_T_494, asSInt(UInt<27>(0h4000000))) node _T_496 = asSInt(_T_495) node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0))) node _T_498 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_499 = cvt(_T_498) node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000))) node _T_501 = asSInt(_T_500) node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0))) node _T_503 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<13>(0h1000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = or(_T_467, _T_472) node _T_509 = or(_T_508, _T_477) node _T_510 = or(_T_509, _T_482) node _T_511 = or(_T_510, _T_487) node _T_512 = or(_T_511, _T_492) node _T_513 = or(_T_512, _T_497) node _T_514 = or(_T_513, _T_502) node _T_515 = or(_T_514, _T_507) node _T_516 = and(_T_462, _T_515) node _T_517 = or(UInt<1>(0h0), _T_516) node _T_518 = and(_T_461, _T_517) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_518, UInt<1>(0h1), "") : assert_10 node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_523 = shr(io.in.a.bits.source, 2) node _T_524 = eq(_T_523, UInt<1>(0h0)) node _T_525 = leq(UInt<1>(0h0), uncommonBits_28) node _T_526 = and(_T_524, _T_525) node _T_527 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_528 = and(_T_526, _T_527) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_529 = shr(io.in.a.bits.source, 2) node _T_530 = eq(_T_529, UInt<1>(0h1)) node _T_531 = leq(UInt<1>(0h0), uncommonBits_29) node _T_532 = and(_T_530, _T_531) node _T_533 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_534 = and(_T_532, _T_533) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_535 = shr(io.in.a.bits.source, 2) node _T_536 = eq(_T_535, UInt<2>(0h2)) node _T_537 = leq(UInt<1>(0h0), uncommonBits_30) node _T_538 = and(_T_536, _T_537) node _T_539 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_540 = and(_T_538, _T_539) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_541 = shr(io.in.a.bits.source, 2) node _T_542 = eq(_T_541, UInt<2>(0h3)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_31) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_547 = shr(io.in.a.bits.source, 3) node _T_548 = eq(_T_547, UInt<2>(0h3)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_32) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_553 = shr(io.in.a.bits.source, 3) node _T_554 = eq(_T_553, UInt<2>(0h2)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_33) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_559 = shr(io.in.a.bits.source, 3) node _T_560 = eq(_T_559, UInt<4>(0h8)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_34) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_564 = and(_T_562, _T_563) node _T_565 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_566 = eq(io.in.a.bits.source, UInt<7>(0h48)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_522 connect _WIRE_2[1], _T_528 connect _WIRE_2[2], _T_534 connect _WIRE_2[3], _T_540 connect _WIRE_2[4], _T_546 connect _WIRE_2[5], _T_552 connect _WIRE_2[6], _T_558 connect _WIRE_2[7], _T_564 connect _WIRE_2[8], _T_565 connect _WIRE_2[9], _T_566 node _T_567 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_568 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_569 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_570 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_572 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_573 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_574 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_575 = mux(_WIRE_2[7], _T_567, UInt<1>(0h0)) node _T_576 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_577 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = or(_T_568, _T_569) node _T_579 = or(_T_578, _T_570) node _T_580 = or(_T_579, _T_571) node _T_581 = or(_T_580, _T_572) node _T_582 = or(_T_581, _T_573) node _T_583 = or(_T_582, _T_574) node _T_584 = or(_T_583, _T_575) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_577) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_586 node _T_587 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_588 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_589 = and(_T_587, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<14>(0h2000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<13>(0h1000))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_602 = cvt(_T_601) node _T_603 = and(_T_602, asSInt(UInt<17>(0h10000))) node _T_604 = asSInt(_T_603) node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0))) node _T_606 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_607 = cvt(_T_606) node _T_608 = and(_T_607, asSInt(UInt<18>(0h2f000))) node _T_609 = asSInt(_T_608) node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0))) node _T_611 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_612 = cvt(_T_611) node _T_613 = and(_T_612, asSInt(UInt<17>(0h10000))) node _T_614 = asSInt(_T_613) node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0))) node _T_616 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<13>(0h1000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_622 = cvt(_T_621) node _T_623 = and(_T_622, asSInt(UInt<27>(0h4000000))) node _T_624 = asSInt(_T_623) node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0))) node _T_626 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_627 = cvt(_T_626) node _T_628 = and(_T_627, asSInt(UInt<13>(0h1000))) node _T_629 = asSInt(_T_628) node _T_630 = eq(_T_629, asSInt(UInt<1>(0h0))) node _T_631 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_632 = cvt(_T_631) node _T_633 = and(_T_632, asSInt(UInt<13>(0h1000))) node _T_634 = asSInt(_T_633) node _T_635 = eq(_T_634, asSInt(UInt<1>(0h0))) node _T_636 = or(_T_595, _T_600) node _T_637 = or(_T_636, _T_605) node _T_638 = or(_T_637, _T_610) node _T_639 = or(_T_638, _T_615) node _T_640 = or(_T_639, _T_620) node _T_641 = or(_T_640, _T_625) node _T_642 = or(_T_641, _T_630) node _T_643 = or(_T_642, _T_635) node _T_644 = and(_T_590, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = and(_WIRE_3, _T_645) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_646, UInt<1>(0h1), "") : assert_11 node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(source_ok, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_653 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_653, UInt<1>(0h1), "") : assert_13 node _T_657 = asUInt(reset) node _T_658 = eq(_T_657, UInt<1>(0h0)) when _T_658 : node _T_659 = eq(is_aligned, UInt<1>(0h0)) when _T_659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_660 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_660, UInt<1>(0h1), "") : assert_15 node _T_664 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(_T_664, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_664, UInt<1>(0h1), "") : assert_16 node _T_668 = not(io.in.a.bits.mask) node _T_669 = eq(_T_668, UInt<1>(0h0)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_669, UInt<1>(0h1), "") : assert_17 node _T_673 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_673, UInt<1>(0h1), "") : assert_18 node _T_677 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_677 : node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<1>(0h0)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_35) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_688 = shr(io.in.a.bits.source, 2) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_36) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_694 = shr(io.in.a.bits.source, 2) node _T_695 = eq(_T_694, UInt<2>(0h2)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_37) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_699 = and(_T_697, _T_698) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_700 = shr(io.in.a.bits.source, 2) node _T_701 = eq(_T_700, UInt<2>(0h3)) node _T_702 = leq(UInt<1>(0h0), uncommonBits_38) node _T_703 = and(_T_701, _T_702) node _T_704 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_706 = shr(io.in.a.bits.source, 3) node _T_707 = eq(_T_706, UInt<2>(0h3)) node _T_708 = leq(UInt<1>(0h0), uncommonBits_39) node _T_709 = and(_T_707, _T_708) node _T_710 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_711 = and(_T_709, _T_710) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_712 = shr(io.in.a.bits.source, 3) node _T_713 = eq(_T_712, UInt<2>(0h2)) node _T_714 = leq(UInt<1>(0h0), uncommonBits_40) node _T_715 = and(_T_713, _T_714) node _T_716 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_717 = and(_T_715, _T_716) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_718 = shr(io.in.a.bits.source, 3) node _T_719 = eq(_T_718, UInt<4>(0h8)) node _T_720 = leq(UInt<1>(0h0), uncommonBits_41) node _T_721 = and(_T_719, _T_720) node _T_722 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_726 = or(_T_681, _T_687) node _T_727 = or(_T_726, _T_693) node _T_728 = or(_T_727, _T_699) node _T_729 = or(_T_728, _T_705) node _T_730 = or(_T_729, _T_711) node _T_731 = or(_T_730, _T_717) node _T_732 = or(_T_731, _T_723) node _T_733 = or(_T_732, _T_724) node _T_734 = or(_T_733, _T_725) node _T_735 = and(_T_680, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_736, UInt<1>(0h1), "") : assert_19 node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_742 = and(_T_740, _T_741) node _T_743 = or(UInt<1>(0h0), _T_742) node _T_744 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_745 = cvt(_T_744) node _T_746 = and(_T_745, asSInt(UInt<13>(0h1000))) node _T_747 = asSInt(_T_746) node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0))) node _T_749 = and(_T_743, _T_748) node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_752 = and(_T_750, _T_751) node _T_753 = or(UInt<1>(0h0), _T_752) node _T_754 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<14>(0h2000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<18>(0h2f000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<17>(0h10000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<13>(0h1000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_780 = cvt(_T_779) node _T_781 = and(_T_780, asSInt(UInt<27>(0h4000000))) node _T_782 = asSInt(_T_781) node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0))) node _T_784 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_785 = cvt(_T_784) node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000))) node _T_787 = asSInt(_T_786) node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0))) node _T_789 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_790 = cvt(_T_789) node _T_791 = and(_T_790, asSInt(UInt<13>(0h1000))) node _T_792 = asSInt(_T_791) node _T_793 = eq(_T_792, asSInt(UInt<1>(0h0))) node _T_794 = or(_T_758, _T_763) node _T_795 = or(_T_794, _T_768) node _T_796 = or(_T_795, _T_773) node _T_797 = or(_T_796, _T_778) node _T_798 = or(_T_797, _T_783) node _T_799 = or(_T_798, _T_788) node _T_800 = or(_T_799, _T_793) node _T_801 = and(_T_753, _T_800) node _T_802 = or(UInt<1>(0h0), _T_749) node _T_803 = or(_T_802, _T_801) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_803, UInt<1>(0h1), "") : assert_20 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(source_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(is_aligned, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_813 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_813, UInt<1>(0h1), "") : assert_23 node _T_817 = eq(io.in.a.bits.mask, mask) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_817, UInt<1>(0h1), "") : assert_24 node _T_821 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_821, UInt<1>(0h1), "") : assert_25 node _T_825 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_825 : node _T_826 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_827 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_828 = and(_T_826, _T_827) node _T_829 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_830 = shr(io.in.a.bits.source, 2) node _T_831 = eq(_T_830, UInt<1>(0h0)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_42) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_835 = and(_T_833, _T_834) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_836 = shr(io.in.a.bits.source, 2) node _T_837 = eq(_T_836, UInt<1>(0h1)) node _T_838 = leq(UInt<1>(0h0), uncommonBits_43) node _T_839 = and(_T_837, _T_838) node _T_840 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_841 = and(_T_839, _T_840) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<2>(0h2)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_44) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<2>(0h3)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_45) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_854 = shr(io.in.a.bits.source, 3) node _T_855 = eq(_T_854, UInt<2>(0h3)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_46) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_860 = shr(io.in.a.bits.source, 3) node _T_861 = eq(_T_860, UInt<2>(0h2)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_47) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_865 = and(_T_863, _T_864) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_866 = shr(io.in.a.bits.source, 3) node _T_867 = eq(_T_866, UInt<4>(0h8)) node _T_868 = leq(UInt<1>(0h0), uncommonBits_48) node _T_869 = and(_T_867, _T_868) node _T_870 = leq(uncommonBits_48, UInt<3>(0h4)) node _T_871 = and(_T_869, _T_870) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_874 = or(_T_829, _T_835) node _T_875 = or(_T_874, _T_841) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_853) node _T_878 = or(_T_877, _T_859) node _T_879 = or(_T_878, _T_865) node _T_880 = or(_T_879, _T_871) node _T_881 = or(_T_880, _T_872) node _T_882 = or(_T_881, _T_873) node _T_883 = and(_T_828, _T_882) node _T_884 = or(UInt<1>(0h0), _T_883) node _T_885 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_886 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_887 = and(_T_885, _T_886) node _T_888 = or(UInt<1>(0h0), _T_887) node _T_889 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = and(_T_888, _T_893) node _T_895 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_896 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_897 = and(_T_895, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<18>(0h2f000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<17>(0h10000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<13>(0h1000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<27>(0h4000000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<13>(0h1000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_942 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<17>(0h10000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = and(_T_941, _T_946) node _T_948 = or(UInt<1>(0h0), _T_894) node _T_949 = or(_T_948, _T_940) node _T_950 = or(_T_949, _T_947) node _T_951 = and(_T_884, _T_950) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_951, UInt<1>(0h1), "") : assert_26 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(source_ok, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(is_aligned, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_961 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_961, UInt<1>(0h1), "") : assert_29 node _T_965 = eq(io.in.a.bits.mask, mask) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_965, UInt<1>(0h1), "") : assert_30 node _T_969 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_969 : node _T_970 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_971 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_972 = and(_T_970, _T_971) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_974 = shr(io.in.a.bits.source, 2) node _T_975 = eq(_T_974, UInt<1>(0h0)) node _T_976 = leq(UInt<1>(0h0), uncommonBits_49) node _T_977 = and(_T_975, _T_976) node _T_978 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_979 = and(_T_977, _T_978) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_980 = shr(io.in.a.bits.source, 2) node _T_981 = eq(_T_980, UInt<1>(0h1)) node _T_982 = leq(UInt<1>(0h0), uncommonBits_50) node _T_983 = and(_T_981, _T_982) node _T_984 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_985 = and(_T_983, _T_984) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_986 = shr(io.in.a.bits.source, 2) node _T_987 = eq(_T_986, UInt<2>(0h2)) node _T_988 = leq(UInt<1>(0h0), uncommonBits_51) node _T_989 = and(_T_987, _T_988) node _T_990 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_991 = and(_T_989, _T_990) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_992 = shr(io.in.a.bits.source, 2) node _T_993 = eq(_T_992, UInt<2>(0h3)) node _T_994 = leq(UInt<1>(0h0), uncommonBits_52) node _T_995 = and(_T_993, _T_994) node _T_996 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_997 = and(_T_995, _T_996) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_998 = shr(io.in.a.bits.source, 3) node _T_999 = eq(_T_998, UInt<2>(0h3)) node _T_1000 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_1003 = and(_T_1001, _T_1002) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_1004 = shr(io.in.a.bits.source, 3) node _T_1005 = eq(_T_1004, UInt<2>(0h2)) node _T_1006 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1007 = and(_T_1005, _T_1006) node _T_1008 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_1009 = and(_T_1007, _T_1008) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_1010 = shr(io.in.a.bits.source, 3) node _T_1011 = eq(_T_1010, UInt<4>(0h8)) node _T_1012 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1013 = and(_T_1011, _T_1012) node _T_1014 = leq(uncommonBits_55, UInt<3>(0h4)) node _T_1015 = and(_T_1013, _T_1014) node _T_1016 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1017 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1018 = or(_T_973, _T_979) node _T_1019 = or(_T_1018, _T_985) node _T_1020 = or(_T_1019, _T_991) node _T_1021 = or(_T_1020, _T_997) node _T_1022 = or(_T_1021, _T_1003) node _T_1023 = or(_T_1022, _T_1009) node _T_1024 = or(_T_1023, _T_1015) node _T_1025 = or(_T_1024, _T_1016) node _T_1026 = or(_T_1025, _T_1017) node _T_1027 = and(_T_972, _T_1026) node _T_1028 = or(UInt<1>(0h0), _T_1027) node _T_1029 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1030 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1034 = cvt(_T_1033) node _T_1035 = and(_T_1034, asSInt(UInt<13>(0h1000))) node _T_1036 = asSInt(_T_1035) node _T_1037 = eq(_T_1036, asSInt(UInt<1>(0h0))) node _T_1038 = and(_T_1032, _T_1037) node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1040 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = or(UInt<1>(0h0), _T_1041) node _T_1043 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1044 = cvt(_T_1043) node _T_1045 = and(_T_1044, asSInt(UInt<14>(0h2000))) node _T_1046 = asSInt(_T_1045) node _T_1047 = eq(_T_1046, asSInt(UInt<1>(0h0))) node _T_1048 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1049 = cvt(_T_1048) node _T_1050 = and(_T_1049, asSInt(UInt<18>(0h2f000))) node _T_1051 = asSInt(_T_1050) node _T_1052 = eq(_T_1051, asSInt(UInt<1>(0h0))) node _T_1053 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1054 = cvt(_T_1053) node _T_1055 = and(_T_1054, asSInt(UInt<17>(0h10000))) node _T_1056 = asSInt(_T_1055) node _T_1057 = eq(_T_1056, asSInt(UInt<1>(0h0))) node _T_1058 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1059 = cvt(_T_1058) node _T_1060 = and(_T_1059, asSInt(UInt<13>(0h1000))) node _T_1061 = asSInt(_T_1060) node _T_1062 = eq(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<27>(0h4000000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1069 = cvt(_T_1068) node _T_1070 = and(_T_1069, asSInt(UInt<13>(0h1000))) node _T_1071 = asSInt(_T_1070) node _T_1072 = eq(_T_1071, asSInt(UInt<1>(0h0))) node _T_1073 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<13>(0h1000))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = or(_T_1047, _T_1052) node _T_1079 = or(_T_1078, _T_1057) node _T_1080 = or(_T_1079, _T_1062) node _T_1081 = or(_T_1080, _T_1067) node _T_1082 = or(_T_1081, _T_1072) node _T_1083 = or(_T_1082, _T_1077) node _T_1084 = and(_T_1042, _T_1083) node _T_1085 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1086 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<17>(0h10000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = and(_T_1085, _T_1090) node _T_1092 = or(UInt<1>(0h0), _T_1038) node _T_1093 = or(_T_1092, _T_1084) node _T_1094 = or(_T_1093, _T_1091) node _T_1095 = and(_T_1028, _T_1094) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_31 node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(source_ok, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(is_aligned, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1105 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_34 node _T_1109 = not(mask) node _T_1110 = and(io.in.a.bits.mask, _T_1109) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_35 node _T_1115 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1115 : node _T_1116 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1117 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1120 = shr(io.in.a.bits.source, 2) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) node _T_1122 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1125 = and(_T_1123, _T_1124) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1126 = shr(io.in.a.bits.source, 2) node _T_1127 = eq(_T_1126, UInt<1>(0h1)) node _T_1128 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1131 = and(_T_1129, _T_1130) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1132 = shr(io.in.a.bits.source, 2) node _T_1133 = eq(_T_1132, UInt<2>(0h2)) node _T_1134 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1135 = and(_T_1133, _T_1134) node _T_1136 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1137 = and(_T_1135, _T_1136) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1138 = shr(io.in.a.bits.source, 2) node _T_1139 = eq(_T_1138, UInt<2>(0h3)) node _T_1140 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1141 = and(_T_1139, _T_1140) node _T_1142 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1143 = and(_T_1141, _T_1142) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_1144 = shr(io.in.a.bits.source, 3) node _T_1145 = eq(_T_1144, UInt<2>(0h3)) node _T_1146 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1147 = and(_T_1145, _T_1146) node _T_1148 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_1149 = and(_T_1147, _T_1148) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_1150 = shr(io.in.a.bits.source, 3) node _T_1151 = eq(_T_1150, UInt<2>(0h2)) node _T_1152 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_1155 = and(_T_1153, _T_1154) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_1156 = shr(io.in.a.bits.source, 3) node _T_1157 = eq(_T_1156, UInt<4>(0h8)) node _T_1158 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1159 = and(_T_1157, _T_1158) node _T_1160 = leq(uncommonBits_62, UInt<3>(0h4)) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1163 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1164 = or(_T_1119, _T_1125) node _T_1165 = or(_T_1164, _T_1131) node _T_1166 = or(_T_1165, _T_1137) node _T_1167 = or(_T_1166, _T_1143) node _T_1168 = or(_T_1167, _T_1149) node _T_1169 = or(_T_1168, _T_1155) node _T_1170 = or(_T_1169, _T_1161) node _T_1171 = or(_T_1170, _T_1162) node _T_1172 = or(_T_1171, _T_1163) node _T_1173 = and(_T_1118, _T_1172) node _T_1174 = or(UInt<1>(0h0), _T_1173) node _T_1175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1176 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _T_1178 = or(UInt<1>(0h0), _T_1177) node _T_1179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1180 = cvt(_T_1179) node _T_1181 = and(_T_1180, asSInt(UInt<14>(0h2000))) node _T_1182 = asSInt(_T_1181) node _T_1183 = eq(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1185 = cvt(_T_1184) node _T_1186 = and(_T_1185, asSInt(UInt<13>(0h1000))) node _T_1187 = asSInt(_T_1186) node _T_1188 = eq(_T_1187, asSInt(UInt<1>(0h0))) node _T_1189 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1190 = cvt(_T_1189) node _T_1191 = and(_T_1190, asSInt(UInt<18>(0h2f000))) node _T_1192 = asSInt(_T_1191) node _T_1193 = eq(_T_1192, asSInt(UInt<1>(0h0))) node _T_1194 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1195 = cvt(_T_1194) node _T_1196 = and(_T_1195, asSInt(UInt<17>(0h10000))) node _T_1197 = asSInt(_T_1196) node _T_1198 = eq(_T_1197, asSInt(UInt<1>(0h0))) node _T_1199 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1200 = cvt(_T_1199) node _T_1201 = and(_T_1200, asSInt(UInt<13>(0h1000))) node _T_1202 = asSInt(_T_1201) node _T_1203 = eq(_T_1202, asSInt(UInt<1>(0h0))) node _T_1204 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1205 = cvt(_T_1204) node _T_1206 = and(_T_1205, asSInt(UInt<27>(0h4000000))) node _T_1207 = asSInt(_T_1206) node _T_1208 = eq(_T_1207, asSInt(UInt<1>(0h0))) node _T_1209 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1210 = cvt(_T_1209) node _T_1211 = and(_T_1210, asSInt(UInt<13>(0h1000))) node _T_1212 = asSInt(_T_1211) node _T_1213 = eq(_T_1212, asSInt(UInt<1>(0h0))) node _T_1214 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<13>(0h1000))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = or(_T_1183, _T_1188) node _T_1220 = or(_T_1219, _T_1193) node _T_1221 = or(_T_1220, _T_1198) node _T_1222 = or(_T_1221, _T_1203) node _T_1223 = or(_T_1222, _T_1208) node _T_1224 = or(_T_1223, _T_1213) node _T_1225 = or(_T_1224, _T_1218) node _T_1226 = and(_T_1178, _T_1225) node _T_1227 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1228 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1229 = cvt(_T_1228) node _T_1230 = and(_T_1229, asSInt(UInt<17>(0h10000))) node _T_1231 = asSInt(_T_1230) node _T_1232 = eq(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = and(_T_1227, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1226) node _T_1235 = or(_T_1234, _T_1233) node _T_1236 = and(_T_1174, _T_1235) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_36 node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(source_ok, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(is_aligned, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1246 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_39 node _T_1250 = eq(io.in.a.bits.mask, mask) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_40 node _T_1254 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1254 : node _T_1255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1256 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1259 = shr(io.in.a.bits.source, 2) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) node _T_1261 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1264 = and(_T_1262, _T_1263) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_1265 = shr(io.in.a.bits.source, 2) node _T_1266 = eq(_T_1265, UInt<1>(0h1)) node _T_1267 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1268 = and(_T_1266, _T_1267) node _T_1269 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_1270 = and(_T_1268, _T_1269) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1271 = shr(io.in.a.bits.source, 2) node _T_1272 = eq(_T_1271, UInt<2>(0h2)) node _T_1273 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1276 = and(_T_1274, _T_1275) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1277 = shr(io.in.a.bits.source, 2) node _T_1278 = eq(_T_1277, UInt<2>(0h3)) node _T_1279 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1280 = and(_T_1278, _T_1279) node _T_1281 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1282 = and(_T_1280, _T_1281) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_1283 = shr(io.in.a.bits.source, 3) node _T_1284 = eq(_T_1283, UInt<2>(0h3)) node _T_1285 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1286 = and(_T_1284, _T_1285) node _T_1287 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_1288 = and(_T_1286, _T_1287) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_1289 = shr(io.in.a.bits.source, 3) node _T_1290 = eq(_T_1289, UInt<2>(0h2)) node _T_1291 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1292 = and(_T_1290, _T_1291) node _T_1293 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_1294 = and(_T_1292, _T_1293) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1295 = shr(io.in.a.bits.source, 3) node _T_1296 = eq(_T_1295, UInt<4>(0h8)) node _T_1297 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1298 = and(_T_1296, _T_1297) node _T_1299 = leq(uncommonBits_69, UInt<3>(0h4)) node _T_1300 = and(_T_1298, _T_1299) node _T_1301 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1302 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1303 = or(_T_1258, _T_1264) node _T_1304 = or(_T_1303, _T_1270) node _T_1305 = or(_T_1304, _T_1276) node _T_1306 = or(_T_1305, _T_1282) node _T_1307 = or(_T_1306, _T_1288) node _T_1308 = or(_T_1307, _T_1294) node _T_1309 = or(_T_1308, _T_1300) node _T_1310 = or(_T_1309, _T_1301) node _T_1311 = or(_T_1310, _T_1302) node _T_1312 = and(_T_1257, _T_1311) node _T_1313 = or(UInt<1>(0h0), _T_1312) node _T_1314 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1315 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1316 = and(_T_1314, _T_1315) node _T_1317 = or(UInt<1>(0h0), _T_1316) node _T_1318 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<14>(0h2000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<13>(0h1000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<18>(0h2f000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<17>(0h10000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<13>(0h1000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<27>(0h4000000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<13>(0h1000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1354 = cvt(_T_1353) node _T_1355 = and(_T_1354, asSInt(UInt<13>(0h1000))) node _T_1356 = asSInt(_T_1355) node _T_1357 = eq(_T_1356, asSInt(UInt<1>(0h0))) node _T_1358 = or(_T_1322, _T_1327) node _T_1359 = or(_T_1358, _T_1332) node _T_1360 = or(_T_1359, _T_1337) node _T_1361 = or(_T_1360, _T_1342) node _T_1362 = or(_T_1361, _T_1347) node _T_1363 = or(_T_1362, _T_1352) node _T_1364 = or(_T_1363, _T_1357) node _T_1365 = and(_T_1317, _T_1364) node _T_1366 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1367 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<17>(0h10000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = and(_T_1366, _T_1371) node _T_1373 = or(UInt<1>(0h0), _T_1365) node _T_1374 = or(_T_1373, _T_1372) node _T_1375 = and(_T_1313, _T_1374) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_41 node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(source_ok, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(is_aligned, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1385 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_44 node _T_1389 = eq(io.in.a.bits.mask, mask) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_45 node _T_1393 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1393 : node _T_1394 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1395 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1398 = shr(io.in.a.bits.source, 2) node _T_1399 = eq(_T_1398, UInt<1>(0h0)) node _T_1400 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1401 = and(_T_1399, _T_1400) node _T_1402 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1403 = and(_T_1401, _T_1402) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1404 = shr(io.in.a.bits.source, 2) node _T_1405 = eq(_T_1404, UInt<1>(0h1)) node _T_1406 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1409 = and(_T_1407, _T_1408) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1410 = shr(io.in.a.bits.source, 2) node _T_1411 = eq(_T_1410, UInt<2>(0h2)) node _T_1412 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1413 = and(_T_1411, _T_1412) node _T_1414 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1415 = and(_T_1413, _T_1414) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1416 = shr(io.in.a.bits.source, 2) node _T_1417 = eq(_T_1416, UInt<2>(0h3)) node _T_1418 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1421 = and(_T_1419, _T_1420) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1422 = shr(io.in.a.bits.source, 3) node _T_1423 = eq(_T_1422, UInt<2>(0h3)) node _T_1424 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1425 = and(_T_1423, _T_1424) node _T_1426 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1427 = and(_T_1425, _T_1426) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_1428 = shr(io.in.a.bits.source, 3) node _T_1429 = eq(_T_1428, UInt<2>(0h2)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1433 = and(_T_1431, _T_1432) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1434 = shr(io.in.a.bits.source, 3) node _T_1435 = eq(_T_1434, UInt<4>(0h8)) node _T_1436 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1437 = and(_T_1435, _T_1436) node _T_1438 = leq(uncommonBits_76, UInt<3>(0h4)) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1441 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1442 = or(_T_1397, _T_1403) node _T_1443 = or(_T_1442, _T_1409) node _T_1444 = or(_T_1443, _T_1415) node _T_1445 = or(_T_1444, _T_1421) node _T_1446 = or(_T_1445, _T_1427) node _T_1447 = or(_T_1446, _T_1433) node _T_1448 = or(_T_1447, _T_1439) node _T_1449 = or(_T_1448, _T_1440) node _T_1450 = or(_T_1449, _T_1441) node _T_1451 = and(_T_1396, _T_1450) node _T_1452 = or(UInt<1>(0h0), _T_1451) node _T_1453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = or(UInt<1>(0h0), _T_1455) node _T_1457 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = and(_T_1456, _T_1461) node _T_1463 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1464 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<14>(0h2000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<17>(0h10000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<18>(0h2f000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<17>(0h10000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<13>(0h1000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<13>(0h1000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1468, _T_1473) node _T_1505 = or(_T_1504, _T_1478) node _T_1506 = or(_T_1505, _T_1483) node _T_1507 = or(_T_1506, _T_1488) node _T_1508 = or(_T_1507, _T_1493) node _T_1509 = or(_T_1508, _T_1498) node _T_1510 = or(_T_1509, _T_1503) node _T_1511 = and(_T_1463, _T_1510) node _T_1512 = or(UInt<1>(0h0), _T_1462) node _T_1513 = or(_T_1512, _T_1511) node _T_1514 = and(_T_1452, _T_1513) node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(_T_1514, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1514, UInt<1>(0h1), "") : assert_46 node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(source_ok, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(is_aligned, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1524 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_49 node _T_1528 = eq(io.in.a.bits.mask, mask) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_50 node _T_1532 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1536 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1537 = asUInt(reset) node _T_1538 = eq(_T_1537, UInt<1>(0h0)) when _T_1538 : node _T_1539 = eq(_T_1536, UInt<1>(0h0)) when _T_1539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1536, UInt<1>(0h1), "") : assert_52 node _source_ok_T_53 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<1>(0h0)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<1>(0h1)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 2) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<2>(0h2)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 2) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<2>(0h3)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 3) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<2>(0h3)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 3) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<2>(0h2)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 3) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<4>(0h8)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_13, UInt<3>(0h4)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h48)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_53 connect _source_ok_WIRE_1[1], _source_ok_T_59 connect _source_ok_WIRE_1[2], _source_ok_T_65 connect _source_ok_WIRE_1[3], _source_ok_T_71 connect _source_ok_WIRE_1[4], _source_ok_T_77 connect _source_ok_WIRE_1[5], _source_ok_T_83 connect _source_ok_WIRE_1[6], _source_ok_T_89 connect _source_ok_WIRE_1[7], _source_ok_T_95 connect _source_ok_WIRE_1[8], _source_ok_T_96 connect _source_ok_WIRE_1[9], _source_ok_T_97 node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_105, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1540 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1540 : node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(source_ok_1, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1544 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_54 node _T_1548 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_55 node _T_1552 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_56 node _T_1556 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_57 node _T_1560 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1560 : node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(source_ok_1, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(sink_ok, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1567 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_60 node _T_1571 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_61 node _T_1575 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_62 node _T_1579 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_63 node _T_1583 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1584 = or(UInt<1>(0h1), _T_1583) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_64 node _T_1588 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1588 : node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(source_ok_1, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(sink_ok, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1595 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_67 node _T_1599 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_68 node _T_1603 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_69 node _T_1607 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1608 = or(_T_1607, io.in.d.bits.corrupt) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_70 node _T_1612 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1613 = or(UInt<1>(0h1), _T_1612) node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(_T_1613, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1613, UInt<1>(0h1), "") : assert_71 node _T_1617 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1617 : node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(source_ok_1, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1621 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_73 node _T_1625 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1626 = asUInt(reset) node _T_1627 = eq(_T_1626, UInt<1>(0h0)) when _T_1627 : node _T_1628 = eq(_T_1625, UInt<1>(0h0)) when _T_1628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1625, UInt<1>(0h1), "") : assert_74 node _T_1629 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1630 = or(UInt<1>(0h1), _T_1629) node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(_T_1630, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1630, UInt<1>(0h1), "") : assert_75 node _T_1634 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1634 : node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(source_ok_1, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1638 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1639 = asUInt(reset) node _T_1640 = eq(_T_1639, UInt<1>(0h0)) when _T_1640 : node _T_1641 = eq(_T_1638, UInt<1>(0h0)) when _T_1641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1638, UInt<1>(0h1), "") : assert_77 node _T_1642 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1643 = or(_T_1642, io.in.d.bits.corrupt) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_78 node _T_1647 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1648 = or(UInt<1>(0h1), _T_1647) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_79 node _T_1652 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1652 : node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(source_ok_1, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1656 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_81 node _T_1660 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_82 node _T_1664 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1665 = or(UInt<1>(0h1), _T_1664) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.mask, UInt<16>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1669 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1673 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1677 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1678 = asUInt(reset) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) when _T_1679 : node _T_1680 = eq(_T_1677, UInt<1>(0h0)) when _T_1680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1677, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1681 = eq(a_first, UInt<1>(0h0)) node _T_1682 = and(io.in.a.valid, _T_1681) when _T_1682 : node _T_1683 = eq(io.in.a.bits.opcode, opcode) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_87 node _T_1687 = eq(io.in.a.bits.param, param) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_88 node _T_1691 = eq(io.in.a.bits.size, size) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_89 node _T_1695 = eq(io.in.a.bits.source, source) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_90 node _T_1699 = eq(io.in.a.bits.address, address) node _T_1700 = asUInt(reset) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) when _T_1701 : node _T_1702 = eq(_T_1699, UInt<1>(0h0)) when _T_1702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1699, UInt<1>(0h1), "") : assert_91 node _T_1703 = and(io.in.a.ready, io.in.a.valid) node _T_1704 = and(_T_1703, a_first) when _T_1704 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1705 = eq(d_first, UInt<1>(0h0)) node _T_1706 = and(io.in.d.valid, _T_1705) when _T_1706 : node _T_1707 = eq(io.in.d.bits.opcode, opcode_1) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_92 node _T_1711 = eq(io.in.d.bits.param, param_1) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_93 node _T_1715 = eq(io.in.d.bits.size, size_1) node _T_1716 = asUInt(reset) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) when _T_1717 : node _T_1718 = eq(_T_1715, UInt<1>(0h0)) when _T_1718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1715, UInt<1>(0h1), "") : assert_94 node _T_1719 = eq(io.in.d.bits.source, source_1) node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(_T_1719, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1719, UInt<1>(0h1), "") : assert_95 node _T_1723 = eq(io.in.d.bits.sink, sink) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_96 node _T_1727 = eq(io.in.d.bits.denied, denied) node _T_1728 = asUInt(reset) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) when _T_1729 : node _T_1730 = eq(_T_1727, UInt<1>(0h0)) when _T_1730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1727, UInt<1>(0h1), "") : assert_97 node _T_1731 = and(io.in.d.ready, io.in.d.valid) node _T_1732 = and(_T_1731, d_first) when _T_1732 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<73>, clock, reset, UInt<73>(0h0) regreset inflight_opcodes : UInt<292>, clock, reset, UInt<292>(0h0) regreset inflight_sizes : UInt<584>, clock, reset, UInt<584>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<73> connect a_set, UInt<73>(0h0) wire a_set_wo_ready : UInt<73> connect a_set_wo_ready, UInt<73>(0h0) wire a_opcodes_set : UInt<292> connect a_opcodes_set, UInt<292>(0h0) wire a_sizes_set : UInt<584> connect a_sizes_set, UInt<584>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1733 = and(io.in.a.valid, a_first_1) node _T_1734 = and(_T_1733, UInt<1>(0h1)) when _T_1734 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1735 = and(io.in.a.ready, io.in.a.valid) node _T_1736 = and(_T_1735, a_first_1) node _T_1737 = and(_T_1736, UInt<1>(0h1)) when _T_1737 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1738 = dshr(inflight, io.in.a.bits.source) node _T_1739 = bits(_T_1738, 0, 0) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) node _T_1741 = asUInt(reset) node _T_1742 = eq(_T_1741, UInt<1>(0h0)) when _T_1742 : node _T_1743 = eq(_T_1740, UInt<1>(0h0)) when _T_1743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1740, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<73> connect d_clr, UInt<73>(0h0) wire d_clr_wo_ready : UInt<73> connect d_clr_wo_ready, UInt<73>(0h0) wire d_opcodes_clr : UInt<292> connect d_opcodes_clr, UInt<292>(0h0) wire d_sizes_clr : UInt<584> connect d_sizes_clr, UInt<584>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1744 = and(io.in.d.valid, d_first_1) node _T_1745 = and(_T_1744, UInt<1>(0h1)) node _T_1746 = eq(d_release_ack, UInt<1>(0h0)) node _T_1747 = and(_T_1745, _T_1746) when _T_1747 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1748 = and(io.in.d.ready, io.in.d.valid) node _T_1749 = and(_T_1748, d_first_1) node _T_1750 = and(_T_1749, UInt<1>(0h1)) node _T_1751 = eq(d_release_ack, UInt<1>(0h0)) node _T_1752 = and(_T_1750, _T_1751) when _T_1752 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1753 = and(io.in.d.valid, d_first_1) node _T_1754 = and(_T_1753, UInt<1>(0h1)) node _T_1755 = eq(d_release_ack, UInt<1>(0h0)) node _T_1756 = and(_T_1754, _T_1755) when _T_1756 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1757 = dshr(inflight, io.in.d.bits.source) node _T_1758 = bits(_T_1757, 0, 0) node _T_1759 = or(_T_1758, same_cycle_resp) node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(_T_1759, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1759, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1763 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1764 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1765 = or(_T_1763, _T_1764) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_100 node _T_1769 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_101 else : node _T_1773 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1774 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1775 = or(_T_1773, _T_1774) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_102 node _T_1779 = eq(io.in.d.bits.size, a_size_lookup) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_103 node _T_1783 = and(io.in.d.valid, d_first_1) node _T_1784 = and(_T_1783, a_first_1) node _T_1785 = and(_T_1784, io.in.a.valid) node _T_1786 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = eq(d_release_ack, UInt<1>(0h0)) node _T_1789 = and(_T_1787, _T_1788) when _T_1789 : node _T_1790 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1791 = or(_T_1790, io.in.a.ready) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_104 node _T_1795 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1796 = orr(a_set_wo_ready) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) node _T_1798 = or(_T_1795, _T_1797) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_1802 = orr(inflight) node _T_1803 = eq(_T_1802, UInt<1>(0h0)) node _T_1804 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1805 = or(_T_1803, _T_1804) node _T_1806 = lt(watchdog, plusarg_reader.out) node _T_1807 = or(_T_1805, _T_1806) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1811 = and(io.in.a.ready, io.in.a.valid) node _T_1812 = and(io.in.d.ready, io.in.d.valid) node _T_1813 = or(_T_1811, _T_1812) when _T_1813 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<73>, clock, reset, UInt<73>(0h0) regreset inflight_opcodes_1 : UInt<292>, clock, reset, UInt<292>(0h0) regreset inflight_sizes_1 : UInt<584>, clock, reset, UInt<584>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<73> connect c_set, UInt<73>(0h0) wire c_set_wo_ready : UInt<73> connect c_set_wo_ready, UInt<73>(0h0) wire c_opcodes_set : UInt<292> connect c_opcodes_set, UInt<292>(0h0) wire c_sizes_set : UInt<584> connect c_sizes_set, UInt<584>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1814 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1815 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1816 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = and(_T_1814, _T_1817) when _T_1818 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1819 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1820 = and(_T_1819, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1821 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1822 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = and(_T_1820, _T_1823) when _T_1824 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1825 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1826 = bits(_T_1825, 0, 0) node _T_1827 = eq(_T_1826, UInt<1>(0h0)) node _T_1828 = asUInt(reset) node _T_1829 = eq(_T_1828, UInt<1>(0h0)) when _T_1829 : node _T_1830 = eq(_T_1827, UInt<1>(0h0)) when _T_1830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1827, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<73> connect d_clr_1, UInt<73>(0h0) wire d_clr_wo_ready_1 : UInt<73> connect d_clr_wo_ready_1, UInt<73>(0h0) wire d_opcodes_clr_1 : UInt<292> connect d_opcodes_clr_1, UInt<292>(0h0) wire d_sizes_clr_1 : UInt<584> connect d_sizes_clr_1, UInt<584>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1831 = and(io.in.d.valid, d_first_2) node _T_1832 = and(_T_1831, UInt<1>(0h1)) node _T_1833 = and(_T_1832, d_release_ack_1) when _T_1833 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1834 = and(io.in.d.ready, io.in.d.valid) node _T_1835 = and(_T_1834, d_first_2) node _T_1836 = and(_T_1835, UInt<1>(0h1)) node _T_1837 = and(_T_1836, d_release_ack_1) when _T_1837 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1838 = and(io.in.d.valid, d_first_2) node _T_1839 = and(_T_1838, UInt<1>(0h1)) node _T_1840 = and(_T_1839, d_release_ack_1) when _T_1840 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1841 = dshr(inflight_1, io.in.d.bits.source) node _T_1842 = bits(_T_1841, 0, 0) node _T_1843 = or(_T_1842, same_cycle_resp_1) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1847 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1848 = asUInt(reset) node _T_1849 = eq(_T_1848, UInt<1>(0h0)) when _T_1849 : node _T_1850 = eq(_T_1847, UInt<1>(0h0)) when _T_1850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1847, UInt<1>(0h1), "") : assert_109 else : node _T_1851 = eq(io.in.d.bits.size, c_size_lookup) node _T_1852 = asUInt(reset) node _T_1853 = eq(_T_1852, UInt<1>(0h0)) when _T_1853 : node _T_1854 = eq(_T_1851, UInt<1>(0h0)) when _T_1854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1851, UInt<1>(0h1), "") : assert_110 node _T_1855 = and(io.in.d.valid, d_first_2) node _T_1856 = and(_T_1855, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1857 = and(_T_1856, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1858 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = and(_T_1859, d_release_ack_1) node _T_1861 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1862 = and(_T_1860, _T_1861) when _T_1862 : node _T_1863 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<128>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1864 = or(_T_1863, _WIRE_27.ready) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_111 node _T_1868 = orr(c_set_wo_ready) when _T_1868 : node _T_1869 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1870 = asUInt(reset) node _T_1871 = eq(_T_1870, UInt<1>(0h0)) when _T_1871 : node _T_1872 = eq(_T_1869, UInt<1>(0h0)) when _T_1872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1869, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1873 = orr(inflight_1) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) node _T_1875 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1876 = or(_T_1874, _T_1875) node _T_1877 = lt(watchdog_1, plusarg_reader_1.out) node _T_1878 = or(_T_1876, _T_1877) node _T_1879 = asUInt(reset) node _T_1880 = eq(_T_1879, UInt<1>(0h0)) when _T_1880 : node _T_1881 = eq(_T_1878, UInt<1>(0h0)) when _T_1881 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1878, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<128>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1882 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1883 = and(io.in.d.ready, io.in.d.valid) node _T_1884 = or(_T_1882, _T_1883) when _T_1884 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [583:0] c_sizes_set = 584'h0; // @[Monitor.scala:741:34] wire [291:0] c_opcodes_set = 292'h0; // @[Monitor.scala:740:34] wire [72:0] c_set = 73'h0; // @[Monitor.scala:738:34] wire [72:0] c_set_wo_ready = 73'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_52 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_72 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_55 = _source_ok_T_54 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_73 = _source_ok_T_72 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_78 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_84 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_90 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_79 = _source_ok_T_78 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_85 = _source_ok_T_84 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_91 = _source_ok_T_90 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_94 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_105 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1811 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1811; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1811; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1884 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1884; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1884; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1884; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [72:0] inflight; // @[Monitor.scala:614:27] reg [291:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [583:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [72:0] a_set; // @[Monitor.scala:626:34] wire [72:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [291:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [583:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [291:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [291:0] _a_opcode_lookup_T_6 = {288'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [291:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [583:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [583:0] _a_size_lookup_T_6 = {576'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [583:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[583:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire _T_1737 = _T_1811 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1737 ? _a_set_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1737 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1737 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1737 ? _a_opcodes_set_T_1[291:0] : 292'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1737 ? _a_sizes_set_T_1[583:0] : 584'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [72:0] d_clr; // @[Monitor.scala:664:34] wire [72:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [291:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [583:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1783 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1783 & ~d_release_ack ? _d_clr_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire _T_1752 = _T_1884 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1752 ? _d_clr_T[72:0] : 73'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1752 ? _d_opcodes_clr_T_5[291:0] : 292'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1752 ? _d_sizes_clr_T_5[583:0] : 584'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [72:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [72:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [72:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [291:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [291:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [291:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [583:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [583:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [583:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [72:0] inflight_1; // @[Monitor.scala:726:35] wire [72:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [291:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [291:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [583:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [583:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [291:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [291:0] _c_opcode_lookup_T_6 = {288'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [291:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [583:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [583:0] _c_size_lookup_T_6 = {576'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [583:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[583:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [72:0] d_clr_1; // @[Monitor.scala:774:34] wire [72:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [291:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [583:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1855 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1855 & d_release_ack_1 ? _d_clr_wo_ready_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35] wire _T_1837 = _T_1884 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1837 ? _d_clr_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1837 ? _d_opcodes_clr_T_11[291:0] : 292'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1837 ? _d_sizes_clr_T_11[583:0] : 584'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [72:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [72:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [291:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [291:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [583:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [583:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.user.amba_prot.fetch invalidate anonIn.a.bits.user.amba_prot.secure invalidate anonIn.a.bits.user.amba_prot.privileged invalidate anonIn.a.bits.user.amba_prot.writealloc invalidate anonIn.a.bits.user.amba_prot.readalloc invalidate anonIn.a.bits.user.amba_prot.modifiable invalidate anonIn.a.bits.user.amba_prot.bufferable invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.user.amba_prot.fetch invalidate anonIn_1.a.bits.user.amba_prot.secure invalidate anonIn_1.a.bits.user.amba_prot.privileged invalidate anonIn_1.a.bits.user.amba_prot.writealloc invalidate anonIn_1.a.bits.user.amba_prot.readalloc invalidate anonIn_1.a.bits.user.amba_prot.modifiable invalidate anonIn_1.a.bits.user.amba_prot.bufferable invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_35 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_36 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch connect monitor_1.io.in.a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure connect monitor_1.io.in.a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged connect monitor_1.io.in.a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc connect monitor_1.io.in.a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc connect monitor_1.io.in.a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable connect monitor_1.io.in.a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.user.amba_prot.fetch invalidate anonOut.a.bits.user.amba_prot.secure invalidate anonOut.a.bits.user.amba_prot.privileged invalidate anonOut.a.bits.user.amba_prot.writealloc invalidate anonOut.a.bits.user.amba_prot.readalloc invalidate anonOut.a.bits.user.amba_prot.modifiable invalidate anonOut.a.bits.user.amba_prot.bufferable invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] invalidate in[0].a.bits.user.amba_prot.fetch invalidate in[0].a.bits.user.amba_prot.secure invalidate in[0].a.bits.user.amba_prot.privileged invalidate in[0].a.bits.user.amba_prot.writealloc invalidate in[0].a.bits.user.amba_prot.readalloc invalidate in[0].a.bits.user.amba_prot.modifiable invalidate in[0].a.bits.user.amba_prot.bufferable connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h1)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<1>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.user.amba_prot.fetch invalidate _WIRE_9.bits.user.amba_prot.secure invalidate _WIRE_9.bits.user.amba_prot.privileged invalidate _WIRE_9.bits.user.amba_prot.writealloc invalidate _WIRE_9.bits.user.amba_prot.readalloc invalidate _WIRE_9.bits.user.amba_prot.modifiable invalidate _WIRE_9.bits.user.amba_prot.bufferable invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.user.amba_prot.fetch invalidate _WIRE_11.bits.user.amba_prot.secure invalidate _WIRE_11.bits.user.amba_prot.privileged invalidate _WIRE_11.bits.user.amba_prot.writealloc invalidate _WIRE_11.bits.user.amba_prot.readalloc invalidate _WIRE_11.bits.user.amba_prot.modifiable invalidate _WIRE_11.bits.user.amba_prot.bufferable invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready connect anonIn.d.bits.source, UInt<1>(0h0) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) invalidate in[1].a.bits.user.amba_prot.fetch invalidate in[1].a.bits.user.amba_prot.secure invalidate in[1].a.bits.user.amba_prot.privileged invalidate in[1].a.bits.user.amba_prot.writealloc invalidate in[1].a.bits.user.amba_prot.readalloc invalidate in[1].a.bits.user.amba_prot.modifiable invalidate in[1].a.bits.user.amba_prot.bufferable connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch connect in[1].a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure connect in[1].a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged connect in[1].a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc connect in[1].a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc connect in[1].a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable connect in[1].a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0)) connect in[1].a.bits.source, _in_1_a_bits_source_T wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<1>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.valid, UInt<1>(0h0) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.user.amba_prot.fetch invalidate _WIRE_33.bits.user.amba_prot.secure invalidate _WIRE_33.bits.user.amba_prot.privileged invalidate _WIRE_33.bits.user.amba_prot.writealloc invalidate _WIRE_33.bits.user.amba_prot.readalloc invalidate _WIRE_33.bits.user.amba_prot.modifiable invalidate _WIRE_33.bits.user.amba_prot.bufferable invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<1>(0h0) connect _WIRE_34.bits.size, UInt<4>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.user.amba_prot.fetch invalidate _WIRE_35.bits.user.amba_prot.secure invalidate _WIRE_35.bits.user.amba_prot.privileged invalidate _WIRE_35.bits.user.amba_prot.writealloc invalidate _WIRE_35.bits.user.amba_prot.readalloc invalidate _WIRE_35.bits.user.amba_prot.modifiable invalidate _WIRE_35.bits.user.amba_prot.bufferable invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<1>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.valid, UInt<1>(0h0) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<1>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready connect anonIn_1.d.bits.source, UInt<1>(0h0) wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.valid, UInt<1>(0h0) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] invalidate out[0].a.bits.user.amba_prot.fetch invalidate out[0].a.bits.user.amba_prot.secure invalidate out[0].a.bits.user.amba_prot.privileged invalidate out[0].a.bits.user.amba_prot.writealloc invalidate out[0].a.bits.user.amba_prot.readalloc invalidate out[0].a.bits.user.amba_prot.modifiable invalidate out[0].a.bits.user.amba_prot.bufferable connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<1>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<32>(0h0) connect _WIRE_50.bits.source, UInt<1>(0h0) connect _WIRE_50.bits.size, UInt<4>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<1>(0h0) connect _WIRE_52.bits.size, UInt<4>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<32>(0h0) connect _WIRE_54.bits.source, UInt<1>(0h0) connect _WIRE_54.bits.size, UInt<4>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<1>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.user.amba_prot.fetch invalidate _WIRE_57.bits.user.amba_prot.secure invalidate _WIRE_57.bits.user.amba_prot.privileged invalidate _WIRE_57.bits.user.amba_prot.writealloc invalidate _WIRE_57.bits.user.amba_prot.readalloc invalidate _WIRE_57.bits.user.amba_prot.modifiable invalidate _WIRE_57.bits.user.amba_prot.bufferable invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_58.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_58.bits.address, UInt<32>(0h0) connect _WIRE_58.bits.source, UInt<1>(0h0) connect _WIRE_58.bits.size, UInt<4>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.user.amba_prot.fetch invalidate _WIRE_59.bits.user.amba_prot.secure invalidate _WIRE_59.bits.user.amba_prot.privileged invalidate _WIRE_59.bits.user.amba_prot.writealloc invalidate _WIRE_59.bits.user.amba_prot.readalloc invalidate _WIRE_59.bits.user.amba_prot.modifiable invalidate _WIRE_59.bits.user.amba_prot.bufferable invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<1>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_62.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_62.bits.address, UInt<32>(0h0) connect _WIRE_62.bits.source, UInt<1>(0h0) connect _WIRE_62.bits.size, UInt<4>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<1>(0h0) connect _addressC_WIRE.bits.size, UInt<4>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE_2.bits.data, UInt<64>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _addressC_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) connect _addressC_WIRE_2.bits.source, UInt<1>(0h0) connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE_2.valid, UInt<1>(0h0) connect _addressC_WIRE_2.ready, UInt<1>(0h0) wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<1>(0h0) connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<1>(0h1)) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<1>(0h0)) node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<1>(0h1)) node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<1>(0h0)) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<1>(0h0) connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<1>(0h0) connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.source, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect in[0].a.ready, portsAOI_filtered[0].ready wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect in[1].a.ready, portsAOI_filtered_1[0].ready wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<1>(0h0) connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) wire _portsBIO_WIRE_2 : UInt<1> connect _portsBIO_WIRE_2, _portsBIO_T_2 connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<1>(0h0) connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE_2.bits.source, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_7 : UInt<1> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_8 : UInt<1> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_9 : UInt<1> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_10 : UInt<1> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_11 : UInt<1> connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11 node _out_0_a_bits_T_24 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_0_a_bits_T_25 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_25) wire _out_0_a_bits_WIRE_12 : UInt<1> connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_26 connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12 node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28) wire _out_0_a_bits_WIRE_13 : UInt<1> connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_29 connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13 connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6 connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31) wire _out_0_a_bits_WIRE_14 : UInt<32> connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_32 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14 node _out_0_a_bits_T_33 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_34 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_34) wire _out_0_a_bits_WIRE_15 : UInt<1> connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_35 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15 node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37) wire _out_0_a_bits_WIRE_16 : UInt<4> connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_38 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16 node _out_0_a_bits_T_39 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_40 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_40) wire _out_0_a_bits_WIRE_17 : UInt<3> connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_41 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17 node _out_0_a_bits_T_42 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_43 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_43) wire _out_0_a_bits_WIRE_18 : UInt<3> connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_44 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_72.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<1>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.user.amba_prot.fetch invalidate _WIRE_73.bits.user.amba_prot.secure invalidate _WIRE_73.bits.user.amba_prot.privileged invalidate _WIRE_73.bits.user.amba_prot.writealloc invalidate _WIRE_73.bits.user.amba_prot.readalloc invalidate _WIRE_73.bits.user.amba_prot.modifiable invalidate _WIRE_73.bits.user.amba_prot.bufferable invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.mask, UInt<8>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<1>(0h0) connect _WIRE_76.bits.size, UInt<4>(0h0) connect _WIRE_76.bits.param, UInt<2>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.mask invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode connect in[0].d, portsDIO_filtered[0] connect portsBIO_filtered[0].ready, UInt<1>(0h0) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<64>(0h0) connect _WIRE_78.bits.mask, UInt<8>(0h0) connect _WIRE_78.bits.address, UInt<32>(0h0) connect _WIRE_78.bits.source, UInt<1>(0h0) connect _WIRE_78.bits.size, UInt<4>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.corrupt invalidate _WIRE_79.bits.data invalidate _WIRE_79.bits.mask invalidate _WIRE_79.bits.address invalidate _WIRE_79.bits.source invalidate _WIRE_79.bits.size invalidate _WIRE_79.bits.param invalidate _WIRE_79.bits.opcode connect in[1].d, portsDIO_filtered[1] connect portsBIO_filtered[1].ready, UInt<1>(0h0)

module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_0_d_bits_sink; // @[Xbar.scala:216:19] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_privileged_0 = auto_anon_in_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire auto_anon_in_1_a_bits_user_amba_prot_bufferable = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_modifiable = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_user_amba_prot_fetch = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_secure = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_bufferable = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_modifiable = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_privileged = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_secure = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_user_amba_prot_fetch = 1'h1; // @[MixedNode.scala:551:17] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_0_a_bits_source = 1'h1; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_bufferable = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_modifiable = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_fetch = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _in_0_a_bits_source_T = 1'h1; // @[Xbar.scala:166:55] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire requestBOI_0_1 = 1'h1; // @[Parameters.scala:46:9] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire portsAOI_filtered_0_bits_source = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:352:24] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire portsAOI_filtered_1_0_bits_user_amba_prot_bufferable = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_modifiable = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_fetch = 1'h1; // @[Xbar.scala:352:24] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_40 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_user_amba_prot_fetch = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_source = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire _in_1_a_bits_source_T = 1'h0; // @[Xbar.scala:166:55] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:46:9] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsAOI_filtered_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_source = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_34 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [63:0] auto_anon_in_1_a_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] in_1_a_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _out_0_a_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [8:0] beatsAI_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_user_amba_prot_readalloc = auto_anon_in_1_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_user_amba_prot_writealloc = auto_anon_in_1_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_bufferable = auto_anon_in_0_a_bits_user_amba_prot_bufferable_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_modifiable = auto_anon_in_0_a_bits_user_amba_prot_modifiable_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_readalloc = auto_anon_in_0_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_writealloc = auto_anon_in_0_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_user_amba_prot_privileged = auto_anon_in_0_a_bits_user_amba_prot_privileged_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17] wire anonOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_bufferable_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_modifiable_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_privileged_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_secure_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_user_amba_prot_fetch_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_bufferable = anonIn_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_modifiable = anonIn_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_readalloc = anonIn_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_writealloc = anonIn_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18] wire in_0_a_bits_user_amba_prot_privileged = anonIn_a_bits_user_amba_prot_privileged; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_readalloc = anonIn_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18] wire in_1_a_bits_user_amba_prot_writealloc = anonIn_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_bufferable_0 = anonOut_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_modifiable_0 = anonOut_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_readalloc_0 = anonOut_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_writealloc_0 = anonOut_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_privileged_0 = anonOut_a_bits_user_amba_prot_privileged; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_secure; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_secure_0 = anonOut_a_bits_user_amba_prot_secure; // @[Xbar.scala:74:9] wire out_0_a_bits_user_amba_prot_fetch; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_user_amba_prot_fetch_0 = anonOut_a_bits_user_amba_prot_fetch; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_bufferable = in_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_modifiable = in_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_readalloc = in_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_writealloc = in_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_user_amba_prot_privileged = in_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_readalloc = in_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_user_amba_prot_writealloc = in_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_bits_source; // @[Xbar.scala:159:18] wire in_1_d_bits_source; // @[Xbar.scala:159:18] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_bufferable; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_bufferable = out_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_modifiable; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_modifiable = out_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_readalloc; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_readalloc = out_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_writealloc; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_writealloc = out_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_privileged; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_privileged = out_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_secure; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_secure = out_0_a_bits_user_amba_prot_secure; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_user_amba_prot_fetch; // @[Mux.scala:30:73] assign anonOut_a_bits_user_amba_prot_fetch = out_0_a_bits_user_amba_prot_fetch; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire requestDOI_0_0 = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = ~out_0_d_bits_source; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to this FIRRTL code module Tile_53 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_309 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_53( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_309 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IDPool : input clock : Clock input reset : Reset output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}} regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff) regreset select : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid : UInt<1>, clock, reset, UInt<1>(0h1) connect io.alloc.valid, valid connect io.alloc.bits, select node taken_shiftAmount = bits(io.alloc.bits, 2, 0) node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount) node _taken_T_1 = bits(_taken_T, 7, 0) node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0)) node allocated_shiftAmount = bits(io.free.bits, 2, 0) node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount) node _allocated_T_1 = bits(_allocated_T, 7, 0) node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0)) node _bitmap1_T = not(taken) node _bitmap1_T_1 = and(bitmap, _bitmap1_T) node bitmap1 = or(_bitmap1_T_1, allocated) node _select1_T = bits(bitmap1, 0, 0) node _select1_T_1 = bits(bitmap1, 1, 1) node _select1_T_2 = bits(bitmap1, 2, 2) node _select1_T_3 = bits(bitmap1, 3, 3) node _select1_T_4 = bits(bitmap1, 4, 4) node _select1_T_5 = bits(bitmap1, 5, 5) node _select1_T_6 = bits(bitmap1, 6, 6) node _select1_T_7 = bits(bitmap1, 7, 7) node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8) node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9) node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10) node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11) node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12) node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13) node _valid1_T = orr(bitmap) node _valid1_T_1 = bits(bitmap, 0, 0) node _valid1_T_2 = bits(bitmap, 1, 1) node _valid1_T_3 = bits(bitmap, 2, 2) node _valid1_T_4 = bits(bitmap, 3, 3) node _valid1_T_5 = bits(bitmap, 4, 4) node _valid1_T_6 = bits(bitmap, 5, 5) node _valid1_T_7 = bits(bitmap, 6, 6) node _valid1_T_8 = bits(bitmap, 7, 7) node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2) node _valid1_T_10 = bits(_valid1_T_9, 1, 0) node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4) node _valid1_T_12 = bits(_valid1_T_11, 1, 0) node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12) node _valid1_T_14 = bits(_valid1_T_13, 2, 0) node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6) node _valid1_T_16 = bits(_valid1_T_15, 1, 0) node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8) node _valid1_T_18 = bits(_valid1_T_17, 1, 0) node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18) node _valid1_T_20 = bits(_valid1_T_19, 2, 0) node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20) node _valid1_T_22 = bits(_valid1_T_21, 3, 0) node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1)) node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready) node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0)) node _valid1_T_26 = and(_valid1_T, _valid1_T_25) node valid1 = or(_valid1_T_26, io.free.valid) node _T = or(io.alloc.ready, io.free.valid) when _T : connect bitmap, bitmap1 connect valid, valid1 node _T_1 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_2 = and(_T_1, io.free.valid) node _T_3 = or(io.alloc.ready, _T_2) when _T_3 : connect select, select1 node _T_4 = eq(io.free.valid, UInt<1>(0h0)) node _T_5 = not(taken) node _T_6 = and(bitmap, _T_5) node _T_7 = dshr(_T_6, io.free.bits) node _T_8 = bits(_T_7, 0, 0) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_4, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = orr(bitmap) node _T_15 = eq(valid, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node _T_19 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_20 = and(_T_19, io.free.valid) node _T_21 = or(io.alloc.ready, _T_20) reg REG : UInt<1>, clock connect REG, _T_21 node _T_22 = and(io.alloc.valid, REG) when _T_22 : node _T_23 = bits(bitmap, 0, 0) node _T_24 = bits(bitmap, 1, 1) node _T_25 = bits(bitmap, 2, 2) node _T_26 = bits(bitmap, 3, 3) node _T_27 = bits(bitmap, 4, 4) node _T_28 = bits(bitmap, 5, 5) node _T_29 = bits(bitmap, 6, 6) node _T_30 = bits(bitmap, 7, 7) node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7)) node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31) node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32) node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33) node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34) node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35) node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36) node _T_38 = eq(select, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2 assert(clock, _T_38, UInt<1>(0h1), "") : assert_2

module IDPool( // @[IDPool.scala:8:7] input clock, // @[IDPool.scala:8:7] input reset, // @[IDPool.scala:8:7] input io_free_valid, // @[IDPool.scala:12:14] input [2:0] io_free_bits, // @[IDPool.scala:12:14] input io_alloc_ready, // @[IDPool.scala:12:14] output io_alloc_valid, // @[IDPool.scala:12:14] output [2:0] io_alloc_bits // @[IDPool.scala:12:14] ); wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7] wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7] wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7] wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7] wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49] wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49] wire io_alloc_valid_0; // @[IDPool.scala:8:7] reg [7:0] bitmap; // @[IDPool.scala:18:23] reg [2:0] select; // @[IDPool.scala:19:23] assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23] reg valid; // @[IDPool.scala:20:23] assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23] wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}] wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}] wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27] wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}] wire [7:0] bitmap1 = _bitmap1_T_1 | allocated; // @[IDPool.scala:26:22, :27:{25,35}] wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45] wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45] wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45] wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45] wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45] wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45] wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45] wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45] wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45] wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45] wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45] wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45] wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45] wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45] wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45] wire _valid1_T = |bitmap; // @[IDPool.scala:18:23, :29:28] wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46] wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46] wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}] wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}] wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}] wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}] wire valid1 = _valid1_T_26 | io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17] reg REG; // @[IDPool.scala:51:36]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h13)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h13)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_86 = shr(io.in.a.bits.source, 5) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<5>(0h13)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<5>(0h13)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_199 = shr(io.in.a.bits.source, 5) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<5>(0h13)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_240 = shr(io.in.a.bits.source, 5) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<5>(0h13)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_283 = shr(io.in.a.bits.source, 5) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<5>(0h13)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_321 = shr(io.in.a.bits.source, 5) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<5>(0h13)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_359 = shr(io.in.a.bits.source, 5) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<5>(0h13)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<20> connect a_set, UInt<20>(0h0) wire a_set_wo_ready : UInt<20> connect a_set_wo_ready, UInt<20>(0h0) wire a_opcodes_set : UInt<80> connect a_opcodes_set, UInt<80>(0h0) wire a_sizes_set : UInt<80> connect a_sizes_set, UInt<80>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<20> connect d_clr, UInt<20>(0h0) wire d_clr_wo_ready : UInt<20> connect d_clr_wo_ready, UInt<20>(0h0) wire d_opcodes_clr : UInt<80> connect d_opcodes_clr, UInt<80>(0h0) wire d_sizes_clr : UInt<80> connect d_sizes_clr, UInt<80>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_110 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<20> connect c_set, UInt<20>(0h0) wire c_set_wo_ready : UInt<20> connect c_set_wo_ready, UInt<20>(0h0) wire c_opcodes_set : UInt<80> connect c_opcodes_set, UInt<80>(0h0) wire c_sizes_set : UInt<80> connect c_sizes_set, UInt<80>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<20> connect d_clr_1, UInt<20>(0h0) wire d_clr_wo_ready_1 : UInt<20> connect d_clr_wo_ready_1, UInt<20>(0h0) wire d_opcodes_clr_1 : UInt<80> connect d_opcodes_clr_1, UInt<80>(0h0) wire d_sizes_clr_1 : UInt<80> connect d_sizes_clr_1, UInt<80>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_111 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_14 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_148 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_149 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_150 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_14( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_148 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_149 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_150 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_48 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_99 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_100 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = |flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_48 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorBank_1 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid inst columns_0 of LoopBranchPredictorColumn_4 connect columns_0.clock, clock connect columns_0.reset, reset inst columns_1 of LoopBranchPredictorColumn_5 connect columns_1.clock, clock connect columns_1.reset, reset inst columns_2 of LoopBranchPredictorColumn_6 connect columns_2.clock, clock connect columns_2.reset, reset inst columns_3 of LoopBranchPredictorColumn_7 connect columns_3.clock, clock connect columns_3.reset, reset wire f3_meta : { s_cnt : UInt<10>}[4] node lo = cat(f3_meta[1].s_cnt, f3_meta[0].s_cnt) node hi = cat(f3_meta[3].s_cnt, f3_meta[2].s_cnt) node _T = cat(hi, lo) wire update_meta : { s_cnt : UInt<10>}[4] wire _update_meta_WIRE : UInt<40> connect _update_meta_WIRE, s1_update.bits.meta node _update_meta_T = bits(_update_meta_WIRE, 9, 0) connect update_meta[0].s_cnt, _update_meta_T node _update_meta_T_1 = bits(_update_meta_WIRE, 19, 10) connect update_meta[1].s_cnt, _update_meta_T_1 node _update_meta_T_2 = bits(_update_meta_WIRE, 29, 20) connect update_meta[2].s_cnt, _update_meta_T_2 node _update_meta_T_3 = bits(_update_meta_WIRE, 39, 30) connect update_meta[3].s_cnt, _update_meta_T_3 connect columns_0.io.f2_req_valid, s2_valid connect columns_0.io.f2_req_idx, s2_idx node _columns_0_io_f3_req_fire_T = bits(s3_mask, 0, 0) node _columns_0_io_f3_req_fire_T_1 = and(s3_valid, _columns_0_io_f3_req_fire_T) node _columns_0_io_f3_req_fire_T_2 = and(_columns_0_io_f3_req_fire_T_1, io.f3_fire) node _columns_0_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].is_br) reg columns_0_io_f3_req_fire_REG : UInt<1>, clock connect columns_0_io_f3_req_fire_REG, _columns_0_io_f3_req_fire_T_3 node _columns_0_io_f3_req_fire_T_4 = and(_columns_0_io_f3_req_fire_T_2, columns_0_io_f3_req_fire_REG) connect columns_0.io.f3_req_fire, _columns_0_io_f3_req_fire_T_4 connect columns_0.io.f3_pred_in, io.resp_in[0].f3[0].taken connect io.resp.f3[0].taken, columns_0.io.f3_pred node _columns_0_io_update_mispredict_T = bits(s1_update.bits.br_mask, 0, 0) node _columns_0_io_update_mispredict_T_1 = and(s1_update.valid, _columns_0_io_update_mispredict_T) node _columns_0_io_update_mispredict_T_2 = and(_columns_0_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_0_io_update_mispredict_T_3 = and(_columns_0_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_0.io.update_mispredict, _columns_0_io_update_mispredict_T_3 node _columns_0_io_update_repair_T = bits(s1_update.bits.br_mask, 0, 0) node _columns_0_io_update_repair_T_1 = and(s1_update.valid, _columns_0_io_update_repair_T) node _columns_0_io_update_repair_T_2 = and(_columns_0_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_0.io.update_repair, _columns_0_io_update_repair_T_2 connect columns_0.io.update_idx, s1_update_idx connect columns_0.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_0.io.update_meta.s_cnt, update_meta[0].s_cnt connect f3_meta[0], columns_0.io.f3_meta connect columns_1.io.f2_req_valid, s2_valid connect columns_1.io.f2_req_idx, s2_idx node _columns_1_io_f3_req_fire_T = bits(s3_mask, 1, 1) node _columns_1_io_f3_req_fire_T_1 = and(s3_valid, _columns_1_io_f3_req_fire_T) node _columns_1_io_f3_req_fire_T_2 = and(_columns_1_io_f3_req_fire_T_1, io.f3_fire) node _columns_1_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].is_br) reg columns_1_io_f3_req_fire_REG : UInt<1>, clock connect columns_1_io_f3_req_fire_REG, _columns_1_io_f3_req_fire_T_3 node _columns_1_io_f3_req_fire_T_4 = and(_columns_1_io_f3_req_fire_T_2, columns_1_io_f3_req_fire_REG) connect columns_1.io.f3_req_fire, _columns_1_io_f3_req_fire_T_4 connect columns_1.io.f3_pred_in, io.resp_in[0].f3[1].taken connect io.resp.f3[1].taken, columns_1.io.f3_pred node _columns_1_io_update_mispredict_T = bits(s1_update.bits.br_mask, 1, 1) node _columns_1_io_update_mispredict_T_1 = and(s1_update.valid, _columns_1_io_update_mispredict_T) node _columns_1_io_update_mispredict_T_2 = and(_columns_1_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_1_io_update_mispredict_T_3 = and(_columns_1_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_1.io.update_mispredict, _columns_1_io_update_mispredict_T_3 node _columns_1_io_update_repair_T = bits(s1_update.bits.br_mask, 1, 1) node _columns_1_io_update_repair_T_1 = and(s1_update.valid, _columns_1_io_update_repair_T) node _columns_1_io_update_repair_T_2 = and(_columns_1_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_1.io.update_repair, _columns_1_io_update_repair_T_2 connect columns_1.io.update_idx, s1_update_idx connect columns_1.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_1.io.update_meta.s_cnt, update_meta[1].s_cnt connect f3_meta[1], columns_1.io.f3_meta connect columns_2.io.f2_req_valid, s2_valid connect columns_2.io.f2_req_idx, s2_idx node _columns_2_io_f3_req_fire_T = bits(s3_mask, 2, 2) node _columns_2_io_f3_req_fire_T_1 = and(s3_valid, _columns_2_io_f3_req_fire_T) node _columns_2_io_f3_req_fire_T_2 = and(_columns_2_io_f3_req_fire_T_1, io.f3_fire) node _columns_2_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].is_br) reg columns_2_io_f3_req_fire_REG : UInt<1>, clock connect columns_2_io_f3_req_fire_REG, _columns_2_io_f3_req_fire_T_3 node _columns_2_io_f3_req_fire_T_4 = and(_columns_2_io_f3_req_fire_T_2, columns_2_io_f3_req_fire_REG) connect columns_2.io.f3_req_fire, _columns_2_io_f3_req_fire_T_4 connect columns_2.io.f3_pred_in, io.resp_in[0].f3[2].taken connect io.resp.f3[2].taken, columns_2.io.f3_pred node _columns_2_io_update_mispredict_T = bits(s1_update.bits.br_mask, 2, 2) node _columns_2_io_update_mispredict_T_1 = and(s1_update.valid, _columns_2_io_update_mispredict_T) node _columns_2_io_update_mispredict_T_2 = and(_columns_2_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_2_io_update_mispredict_T_3 = and(_columns_2_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_2.io.update_mispredict, _columns_2_io_update_mispredict_T_3 node _columns_2_io_update_repair_T = bits(s1_update.bits.br_mask, 2, 2) node _columns_2_io_update_repair_T_1 = and(s1_update.valid, _columns_2_io_update_repair_T) node _columns_2_io_update_repair_T_2 = and(_columns_2_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_2.io.update_repair, _columns_2_io_update_repair_T_2 connect columns_2.io.update_idx, s1_update_idx connect columns_2.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_2.io.update_meta.s_cnt, update_meta[2].s_cnt connect f3_meta[2], columns_2.io.f3_meta connect columns_3.io.f2_req_valid, s2_valid connect columns_3.io.f2_req_idx, s2_idx node _columns_3_io_f3_req_fire_T = bits(s3_mask, 3, 3) node _columns_3_io_f3_req_fire_T_1 = and(s3_valid, _columns_3_io_f3_req_fire_T) node _columns_3_io_f3_req_fire_T_2 = and(_columns_3_io_f3_req_fire_T_1, io.f3_fire) node _columns_3_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].is_br) reg columns_3_io_f3_req_fire_REG : UInt<1>, clock connect columns_3_io_f3_req_fire_REG, _columns_3_io_f3_req_fire_T_3 node _columns_3_io_f3_req_fire_T_4 = and(_columns_3_io_f3_req_fire_T_2, columns_3_io_f3_req_fire_REG) connect columns_3.io.f3_req_fire, _columns_3_io_f3_req_fire_T_4 connect columns_3.io.f3_pred_in, io.resp_in[0].f3[3].taken connect io.resp.f3[3].taken, columns_3.io.f3_pred node _columns_3_io_update_mispredict_T = bits(s1_update.bits.br_mask, 3, 3) node _columns_3_io_update_mispredict_T_1 = and(s1_update.valid, _columns_3_io_update_mispredict_T) node _columns_3_io_update_mispredict_T_2 = and(_columns_3_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update) node _columns_3_io_update_mispredict_T_3 = and(_columns_3_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted) connect columns_3.io.update_mispredict, _columns_3_io_update_mispredict_T_3 node _columns_3_io_update_repair_T = bits(s1_update.bits.br_mask, 3, 3) node _columns_3_io_update_repair_T_1 = and(s1_update.valid, _columns_3_io_update_repair_T) node _columns_3_io_update_repair_T_2 = and(_columns_3_io_update_repair_T_1, s1_update.bits.is_repair_update) connect columns_3.io.update_repair, _columns_3_io_update_repair_T_2 connect columns_3.io.update_idx, s1_update_idx connect columns_3.io.update_resolve_dir, s1_update.bits.cfi_taken connect columns_3.io.update_meta.s_cnt, update_meta[3].s_cnt connect f3_meta[3], columns_3.io.f3_meta node io_f3_meta_lo = cat(f3_meta[1].s_cnt, f3_meta[0].s_cnt) node io_f3_meta_hi = cat(f3_meta[3].s_cnt, f3_meta[2].s_cnt) node _io_f3_meta_T = cat(io_f3_meta_hi, io_f3_meta_lo) connect io.f3_meta, _io_f3_meta_T

module LoopBranchPredictorBank_1( // @[loop.scala:20:7] input clock, // @[loop.scala:20:7] input reset, // @[loop.scala:20:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire io_f0_valid_0 = io_f0_valid; // @[loop.scala:20:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[loop.scala:20:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[loop.scala:20:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[loop.scala:20:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[loop.scala:20:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[loop.scala:20:7] wire io_f3_fire_0 = io_f3_fire; // @[loop.scala:20:7] wire io_update_valid_0 = io_update_valid; // @[loop.scala:20:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[loop.scala:20:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[loop.scala:20:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[loop.scala:20:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[loop.scala:20:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[loop.scala:20:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[loop.scala:20:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[loop.scala:20:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[loop.scala:20:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[loop.scala:20:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[loop.scala:20:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[loop.scala:20:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[loop.scala:20:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[loop.scala:20:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[loop.scala:20:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[loop.scala:20:7] wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[loop.scala:20:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[loop.scala:20:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] wire io_resp_f3_0_taken_0; // @[loop.scala:20:7] wire io_resp_f3_1_taken_0; // @[loop.scala:20:7] wire io_resp_f3_2_taken_0; // @[loop.scala:20:7] wire io_resp_f3_3_taken_0; // @[loop.scala:20:7] wire [119:0] io_f3_meta_0; // @[loop.scala:20:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [36:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire [9:0] f3_meta_0_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_1_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_2_s_cnt; // @[loop.scala:184:21] wire [9:0] f3_meta_3_s_cnt; // @[loop.scala:184:21] wire [19:0] _GEN = {f3_meta_1_s_cnt, f3_meta_0_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] lo; // @[loop.scala:185:33] assign lo = _GEN; // @[loop.scala:185:33] wire [19:0] io_f3_meta_lo; // @[loop.scala:212:25] assign io_f3_meta_lo = _GEN; // @[loop.scala:185:33, :212:25] wire [19:0] _GEN_0 = {f3_meta_3_s_cnt, f3_meta_2_s_cnt}; // @[loop.scala:184:21, :185:33] wire [19:0] hi; // @[loop.scala:185:33] assign hi = _GEN_0; // @[loop.scala:185:33] wire [19:0] io_f3_meta_hi; // @[loop.scala:212:25] assign io_f3_meta_hi = _GEN_0; // @[loop.scala:185:33, :212:25] wire [9:0] _update_meta_T; // @[loop.scala:187:49] wire [9:0] _update_meta_T_1; // @[loop.scala:187:49] wire [9:0] _update_meta_T_2; // @[loop.scala:187:49] wire [9:0] _update_meta_T_3; // @[loop.scala:187:49] wire [9:0] update_meta_0_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_1_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_2_s_cnt; // @[loop.scala:187:49] wire [9:0] update_meta_3_s_cnt; // @[loop.scala:187:49] wire [39:0] _update_meta_WIRE = s1_update_bits_meta[39:0]; // @[predictor.scala:184:30] assign _update_meta_T = _update_meta_WIRE[9:0]; // @[loop.scala:187:49] assign update_meta_0_s_cnt = _update_meta_T; // @[loop.scala:187:49] assign _update_meta_T_1 = _update_meta_WIRE[19:10]; // @[loop.scala:187:49] assign update_meta_1_s_cnt = _update_meta_T_1; // @[loop.scala:187:49] assign _update_meta_T_2 = _update_meta_WIRE[29:20]; // @[loop.scala:187:49] assign update_meta_2_s_cnt = _update_meta_T_2; // @[loop.scala:187:49] assign _update_meta_T_3 = _update_meta_WIRE[39:30]; // @[loop.scala:187:49] assign update_meta_3_s_cnt = _update_meta_T_3; // @[loop.scala:187:49] wire _columns_0_io_f3_req_fire_T = s3_mask[0]; // @[predictor.scala:175:24] wire _columns_0_io_f3_req_fire_T_1 = s3_valid & _columns_0_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_0_io_f3_req_fire_T_2 = _columns_0_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_0_io_f3_req_fire_T_3 = io_resp_in_0_f2_0_predicted_pc_valid_0 & io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_0_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_0_io_f3_req_fire_T_4 = _columns_0_io_f3_req_fire_T_2 & columns_0_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_0_io_update_mispredict_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_1 = s1_update_valid & _columns_0_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_2 = _columns_0_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_0_io_update_mispredict_T_3 = _columns_0_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_1 = s1_update_valid & _columns_0_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_0_io_update_repair_T_2 = _columns_0_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_1_io_f3_req_fire_T = s3_mask[1]; // @[predictor.scala:175:24] wire _columns_1_io_f3_req_fire_T_1 = s3_valid & _columns_1_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_1_io_f3_req_fire_T_2 = _columns_1_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_1_io_f3_req_fire_T_3 = io_resp_in_0_f2_1_predicted_pc_valid_0 & io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_1_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_1_io_f3_req_fire_T_4 = _columns_1_io_f3_req_fire_T_2 & columns_1_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_1_io_update_mispredict_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_1 = s1_update_valid & _columns_1_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_2 = _columns_1_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_1_io_update_mispredict_T_3 = _columns_1_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_1 = s1_update_valid & _columns_1_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_1_io_update_repair_T_2 = _columns_1_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_2_io_f3_req_fire_T = s3_mask[2]; // @[predictor.scala:175:24] wire _columns_2_io_f3_req_fire_T_1 = s3_valid & _columns_2_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_2_io_f3_req_fire_T_2 = _columns_2_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_2_io_f3_req_fire_T_3 = io_resp_in_0_f2_2_predicted_pc_valid_0 & io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_2_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_2_io_f3_req_fire_T_4 = _columns_2_io_f3_req_fire_T_2 & columns_2_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_2_io_update_mispredict_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_1 = s1_update_valid & _columns_2_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_2 = _columns_2_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_2_io_update_mispredict_T_3 = _columns_2_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_1 = s1_update_valid & _columns_2_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_2_io_update_repair_T_2 = _columns_2_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire _columns_3_io_f3_req_fire_T = s3_mask[3]; // @[predictor.scala:175:24] wire _columns_3_io_f3_req_fire_T_1 = s3_valid & _columns_3_io_f3_req_fire_T; // @[predictor.scala:170:25] wire _columns_3_io_f3_req_fire_T_2 = _columns_3_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}] wire _columns_3_io_f3_req_fire_T_3 = io_resp_in_0_f2_3_predicted_pc_valid_0 & io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7, :193:54] reg columns_3_io_f3_req_fire_REG; // @[loop.scala:193:14] wire _columns_3_io_f3_req_fire_T_4 = _columns_3_io_f3_req_fire_T_2 & columns_3_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14] wire _columns_3_io_update_mispredict_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_1 = s1_update_valid & _columns_3_io_update_mispredict_T; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_2 = _columns_3_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] wire _columns_3_io_update_mispredict_T_3 = _columns_3_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_1 = s1_update_valid & _columns_3_io_update_repair_T; // @[predictor.scala:184:30] wire _columns_3_io_update_repair_T_2 = _columns_3_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30] wire [39:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[loop.scala:212:25] assign io_f3_meta_0 = {80'h0, _io_f3_meta_T}; // @[loop.scala:20:7, :212:{14,25}] always @(posedge clock) begin // @[loop.scala:20:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] columns_0_io_f3_req_fire_REG <= _columns_0_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_1_io_f3_req_fire_REG <= _columns_1_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_2_io_f3_req_fire_REG <= _columns_2_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] columns_3_io_f3_req_fire_REG <= _columns_3_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}] always @(posedge) LoopBranchPredictorColumn_4 columns_0 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_0_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_0_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_0_taken_0), .io_f3_meta_s_cnt (f3_meta_0_s_cnt), .io_update_mispredict (_columns_0_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_0_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_0_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_5 columns_1 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_1_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_1_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_1_taken_0), .io_f3_meta_s_cnt (f3_meta_1_s_cnt), .io_update_mispredict (_columns_1_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_1_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_1_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_6 columns_2 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_2_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_2_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_2_taken_0), .io_f3_meta_s_cnt (f3_meta_2_s_cnt), .io_update_mispredict (_columns_2_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_2_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_2_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] LoopBranchPredictorColumn_7 columns_3 ( // @[loop.scala:182:45] .clock (clock), .reset (reset), .io_f2_req_valid (s2_valid), // @[predictor.scala:169:25] .io_f2_req_idx (s2_idx), // @[predictor.scala:164:29] .io_f3_req_fire (_columns_3_io_f3_req_fire_T_4), // @[loop.scala:192:72] .io_f3_pred_in (io_resp_in_0_f3_3_taken_0), // @[loop.scala:20:7] .io_f3_pred (io_resp_f3_3_taken_0), .io_f3_meta_s_cnt (f3_meta_3_s_cnt), .io_update_mispredict (_columns_3_io_update_mispredict_T_3), // @[loop.scala:200:82] .io_update_repair (_columns_3_io_update_repair_T_2), // @[loop.scala:203:72] .io_update_idx (s1_update_idx), // @[predictor.scala:185:30] .io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30] .io_update_meta_s_cnt (update_meta_3_s_cnt) // @[loop.scala:187:49] ); // @[loop.scala:182:45] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[loop.scala:20:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7] assign io_f3_meta = io_f3_meta_0; // @[loop.scala:20:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_22 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_22 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i1_e8_s24_22(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_22 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module FPUUnit_1 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip fcsr_rm : UInt<3>} connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.sfence.bits.hg invalidate io.resp.bits.sfence.bits.hv invalidate io.resp.bits.sfence.bits.asid invalidate io.resp.bits.sfence.bits.addr invalidate io.resp.bits.sfence.bits.rs2 invalidate io.resp.bits.sfence.bits.rs1 invalidate io.resp.bits.sfence.valid invalidate io.resp.bits.mxcpt.bits invalidate io.resp.bits.mxcpt.valid invalidate io.resp.bits.addr invalidate io.resp.bits.fflags.bits.flags invalidate io.resp.bits.fflags.bits.uop.debug_tsrc invalidate io.resp.bits.fflags.bits.uop.debug_fsrc invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.resp.bits.fflags.bits.uop.bp_debug_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.resp.bits.fflags.bits.uop.fp_single invalidate io.resp.bits.fflags.bits.uop.fp_val invalidate io.resp.bits.fflags.bits.uop.frs3_en invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate io.resp.bits.fflags.bits.uop.dst_rtype invalidate io.resp.bits.fflags.bits.uop.ldst_val invalidate io.resp.bits.fflags.bits.uop.lrs3 invalidate io.resp.bits.fflags.bits.uop.lrs2 invalidate io.resp.bits.fflags.bits.uop.lrs1 invalidate io.resp.bits.fflags.bits.uop.ldst invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.resp.bits.fflags.bits.uop.flush_on_commit invalidate io.resp.bits.fflags.bits.uop.is_unique invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.resp.bits.fflags.bits.uop.uses_stq invalidate io.resp.bits.fflags.bits.uop.uses_ldq invalidate io.resp.bits.fflags.bits.uop.is_amo invalidate io.resp.bits.fflags.bits.uop.is_fencei invalidate io.resp.bits.fflags.bits.uop.is_fence invalidate io.resp.bits.fflags.bits.uop.mem_signed invalidate io.resp.bits.fflags.bits.uop.mem_size invalidate io.resp.bits.fflags.bits.uop.mem_cmd invalidate io.resp.bits.fflags.bits.uop.bypassable invalidate io.resp.bits.fflags.bits.uop.exc_cause invalidate io.resp.bits.fflags.bits.uop.exception invalidate io.resp.bits.fflags.bits.uop.stale_pdst invalidate io.resp.bits.fflags.bits.uop.ppred_busy invalidate io.resp.bits.fflags.bits.uop.prs3_busy invalidate io.resp.bits.fflags.bits.uop.prs2_busy invalidate io.resp.bits.fflags.bits.uop.prs1_busy invalidate io.resp.bits.fflags.bits.uop.ppred invalidate io.resp.bits.fflags.bits.uop.prs3 invalidate io.resp.bits.fflags.bits.uop.prs2 invalidate io.resp.bits.fflags.bits.uop.prs1 invalidate io.resp.bits.fflags.bits.uop.pdst invalidate io.resp.bits.fflags.bits.uop.rxq_idx invalidate io.resp.bits.fflags.bits.uop.stq_idx invalidate io.resp.bits.fflags.bits.uop.ldq_idx invalidate io.resp.bits.fflags.bits.uop.rob_idx invalidate io.resp.bits.fflags.bits.uop.csr_addr invalidate io.resp.bits.fflags.bits.uop.imm_packed invalidate io.resp.bits.fflags.bits.uop.taken invalidate io.resp.bits.fflags.bits.uop.pc_lob invalidate io.resp.bits.fflags.bits.uop.edge_inst invalidate io.resp.bits.fflags.bits.uop.ftq_idx invalidate io.resp.bits.fflags.bits.uop.br_tag invalidate io.resp.bits.fflags.bits.uop.br_mask invalidate io.resp.bits.fflags.bits.uop.is_sfb invalidate io.resp.bits.fflags.bits.uop.is_jal invalidate io.resp.bits.fflags.bits.uop.is_jalr invalidate io.resp.bits.fflags.bits.uop.is_br invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_state invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate io.resp.bits.fflags.bits.uop.fu_code invalidate io.resp.bits.fflags.bits.uop.iq_type invalidate io.resp.bits.fflags.bits.uop.debug_pc invalidate io.resp.bits.fflags.bits.uop.is_rvc invalidate io.resp.bits.fflags.bits.uop.debug_inst invalidate io.resp.bits.fflags.bits.uop.inst invalidate io.resp.bits.fflags.bits.uop.uopc invalidate io.resp.bits.fflags.valid invalidate io.resp.bits.data invalidate io.resp.bits.predicated invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.req.ready, UInt<1>(0h1) wire _r_valids_WIRE : UInt<1>[4] connect _r_valids_WIRE[0], UInt<1>(0h0) connect _r_valids_WIRE[1], UInt<1>(0h0) connect _r_valids_WIRE[2], UInt<1>(0h0) connect _r_valids_WIRE[3], UInt<1>(0h0) regreset r_valids : UInt<1>[4], clock, reset, _r_valids_WIRE reg r_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[4], clock node _r_valids_0_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _r_valids_0_T_1 = neq(_r_valids_0_T, UInt<1>(0h0)) node _r_valids_0_T_2 = eq(_r_valids_0_T_1, UInt<1>(0h0)) node _r_valids_0_T_3 = and(io.req.valid, _r_valids_0_T_2) node _r_valids_0_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_0_T_5 = and(_r_valids_0_T_3, _r_valids_0_T_4) connect r_valids[0], _r_valids_0_T_5 connect r_uops[0], io.req.bits.uop node _r_uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_0_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uops_0_br_mask_T) connect r_uops[0].br_mask, _r_uops_0_br_mask_T_1 node _r_valids_1_T = and(io.brupdate.b1.mispredict_mask, r_uops[0].br_mask) node _r_valids_1_T_1 = neq(_r_valids_1_T, UInt<1>(0h0)) node _r_valids_1_T_2 = eq(_r_valids_1_T_1, UInt<1>(0h0)) node _r_valids_1_T_3 = and(r_valids[0], _r_valids_1_T_2) node _r_valids_1_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_1_T_5 = and(_r_valids_1_T_3, _r_valids_1_T_4) connect r_valids[1], _r_valids_1_T_5 connect r_uops[1], r_uops[0] node _r_uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_1_br_mask_T_1 = and(r_uops[0].br_mask, _r_uops_1_br_mask_T) connect r_uops[1].br_mask, _r_uops_1_br_mask_T_1 node _r_valids_2_T = and(io.brupdate.b1.mispredict_mask, r_uops[1].br_mask) node _r_valids_2_T_1 = neq(_r_valids_2_T, UInt<1>(0h0)) node _r_valids_2_T_2 = eq(_r_valids_2_T_1, UInt<1>(0h0)) node _r_valids_2_T_3 = and(r_valids[1], _r_valids_2_T_2) node _r_valids_2_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_2_T_5 = and(_r_valids_2_T_3, _r_valids_2_T_4) connect r_valids[2], _r_valids_2_T_5 connect r_uops[2], r_uops[1] node _r_uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_2_br_mask_T_1 = and(r_uops[1].br_mask, _r_uops_2_br_mask_T) connect r_uops[2].br_mask, _r_uops_2_br_mask_T_1 node _r_valids_3_T = and(io.brupdate.b1.mispredict_mask, r_uops[2].br_mask) node _r_valids_3_T_1 = neq(_r_valids_3_T, UInt<1>(0h0)) node _r_valids_3_T_2 = eq(_r_valids_3_T_1, UInt<1>(0h0)) node _r_valids_3_T_3 = and(r_valids[2], _r_valids_3_T_2) node _r_valids_3_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_3_T_5 = and(_r_valids_3_T_3, _r_valids_3_T_4) connect r_valids[3], _r_valids_3_T_5 connect r_uops[3], r_uops[2] node _r_uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_3_br_mask_T_1 = and(r_uops[2].br_mask, _r_uops_3_br_mask_T) connect r_uops[3].br_mask, _r_uops_3_br_mask_T_1 node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_uops[3].br_mask) node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0)) node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0)) node _io_resp_valid_T_3 = and(r_valids[3], _io_resp_valid_T_2) connect io.resp.valid, _io_resp_valid_T_3 connect io.resp.bits.predicated, UInt<1>(0h0) connect io.resp.bits.uop, r_uops[3] node _io_resp_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_resp_bits_uop_br_mask_T_1 = and(r_uops[3].br_mask, _io_resp_bits_uop_br_mask_T) connect io.resp.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T_1 inst fpu of FPU_3 connect fpu.clock, clock connect fpu.reset, reset connect fpu.io.req.valid, io.req.valid connect fpu.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect fpu.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect fpu.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect fpu.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect fpu.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect fpu.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect fpu.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect fpu.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect fpu.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect fpu.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect fpu.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect fpu.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect fpu.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect fpu.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect fpu.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect fpu.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect fpu.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect fpu.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect fpu.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect fpu.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect fpu.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect fpu.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect fpu.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect fpu.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect fpu.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect fpu.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect fpu.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect fpu.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect fpu.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect fpu.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect fpu.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect fpu.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect fpu.io.req.bits.uop.exception, io.req.bits.uop.exception connect fpu.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect fpu.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect fpu.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect fpu.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect fpu.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect fpu.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect fpu.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect fpu.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect fpu.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect fpu.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect fpu.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect fpu.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect fpu.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect fpu.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect fpu.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect fpu.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect fpu.io.req.bits.uop.taken, io.req.bits.uop.taken connect fpu.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect fpu.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect fpu.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect fpu.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect fpu.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect fpu.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect fpu.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect fpu.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect fpu.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect fpu.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect fpu.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect fpu.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect fpu.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect fpu.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect fpu.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect fpu.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect fpu.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect fpu.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect fpu.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect fpu.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect fpu.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect fpu.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect fpu.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect fpu.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect fpu.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect fpu.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect fpu.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect fpu.io.req.bits.uop.inst, io.req.bits.uop.inst connect fpu.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect fpu.io.req.bits.rs1_data, io.req.bits.rs1_data connect fpu.io.req.bits.rs2_data, io.req.bits.rs2_data connect fpu.io.req.bits.rs3_data, io.req.bits.rs3_data connect fpu.io.req.bits.fcsr_rm, io.fcsr_rm connect io.resp.bits.data, fpu.io.resp.bits.data connect io.resp.bits.fflags.valid, fpu.io.resp.bits.fflags.valid connect io.resp.bits.fflags.bits.uop.debug_tsrc, io.resp.bits.uop.debug_tsrc connect io.resp.bits.fflags.bits.uop.debug_fsrc, io.resp.bits.uop.debug_fsrc connect io.resp.bits.fflags.bits.uop.bp_xcpt_if, io.resp.bits.uop.bp_xcpt_if connect io.resp.bits.fflags.bits.uop.bp_debug_if, io.resp.bits.uop.bp_debug_if connect io.resp.bits.fflags.bits.uop.xcpt_ma_if, io.resp.bits.uop.xcpt_ma_if connect io.resp.bits.fflags.bits.uop.xcpt_ae_if, io.resp.bits.uop.xcpt_ae_if connect io.resp.bits.fflags.bits.uop.xcpt_pf_if, io.resp.bits.uop.xcpt_pf_if connect io.resp.bits.fflags.bits.uop.fp_single, io.resp.bits.uop.fp_single connect io.resp.bits.fflags.bits.uop.fp_val, io.resp.bits.uop.fp_val connect io.resp.bits.fflags.bits.uop.frs3_en, io.resp.bits.uop.frs3_en connect io.resp.bits.fflags.bits.uop.lrs2_rtype, io.resp.bits.uop.lrs2_rtype connect io.resp.bits.fflags.bits.uop.lrs1_rtype, io.resp.bits.uop.lrs1_rtype connect io.resp.bits.fflags.bits.uop.dst_rtype, io.resp.bits.uop.dst_rtype connect io.resp.bits.fflags.bits.uop.ldst_val, io.resp.bits.uop.ldst_val connect io.resp.bits.fflags.bits.uop.lrs3, io.resp.bits.uop.lrs3 connect io.resp.bits.fflags.bits.uop.lrs2, io.resp.bits.uop.lrs2 connect io.resp.bits.fflags.bits.uop.lrs1, io.resp.bits.uop.lrs1 connect io.resp.bits.fflags.bits.uop.ldst, io.resp.bits.uop.ldst connect io.resp.bits.fflags.bits.uop.ldst_is_rs1, io.resp.bits.uop.ldst_is_rs1 connect io.resp.bits.fflags.bits.uop.flush_on_commit, io.resp.bits.uop.flush_on_commit connect io.resp.bits.fflags.bits.uop.is_unique, io.resp.bits.uop.is_unique connect io.resp.bits.fflags.bits.uop.is_sys_pc2epc, io.resp.bits.uop.is_sys_pc2epc connect io.resp.bits.fflags.bits.uop.uses_stq, io.resp.bits.uop.uses_stq connect io.resp.bits.fflags.bits.uop.uses_ldq, io.resp.bits.uop.uses_ldq connect io.resp.bits.fflags.bits.uop.is_amo, io.resp.bits.uop.is_amo connect io.resp.bits.fflags.bits.uop.is_fencei, io.resp.bits.uop.is_fencei connect io.resp.bits.fflags.bits.uop.is_fence, io.resp.bits.uop.is_fence connect io.resp.bits.fflags.bits.uop.mem_signed, io.resp.bits.uop.mem_signed connect io.resp.bits.fflags.bits.uop.mem_size, io.resp.bits.uop.mem_size connect io.resp.bits.fflags.bits.uop.mem_cmd, io.resp.bits.uop.mem_cmd connect io.resp.bits.fflags.bits.uop.bypassable, io.resp.bits.uop.bypassable connect io.resp.bits.fflags.bits.uop.exc_cause, io.resp.bits.uop.exc_cause connect io.resp.bits.fflags.bits.uop.exception, io.resp.bits.uop.exception connect io.resp.bits.fflags.bits.uop.stale_pdst, io.resp.bits.uop.stale_pdst connect io.resp.bits.fflags.bits.uop.ppred_busy, io.resp.bits.uop.ppred_busy connect io.resp.bits.fflags.bits.uop.prs3_busy, io.resp.bits.uop.prs3_busy connect io.resp.bits.fflags.bits.uop.prs2_busy, io.resp.bits.uop.prs2_busy connect io.resp.bits.fflags.bits.uop.prs1_busy, io.resp.bits.uop.prs1_busy connect io.resp.bits.fflags.bits.uop.ppred, io.resp.bits.uop.ppred connect io.resp.bits.fflags.bits.uop.prs3, io.resp.bits.uop.prs3 connect io.resp.bits.fflags.bits.uop.prs2, io.resp.bits.uop.prs2 connect io.resp.bits.fflags.bits.uop.prs1, io.resp.bits.uop.prs1 connect io.resp.bits.fflags.bits.uop.pdst, io.resp.bits.uop.pdst connect io.resp.bits.fflags.bits.uop.rxq_idx, io.resp.bits.uop.rxq_idx connect io.resp.bits.fflags.bits.uop.stq_idx, io.resp.bits.uop.stq_idx connect io.resp.bits.fflags.bits.uop.ldq_idx, io.resp.bits.uop.ldq_idx connect io.resp.bits.fflags.bits.uop.rob_idx, io.resp.bits.uop.rob_idx connect io.resp.bits.fflags.bits.uop.csr_addr, io.resp.bits.uop.csr_addr connect io.resp.bits.fflags.bits.uop.imm_packed, io.resp.bits.uop.imm_packed connect io.resp.bits.fflags.bits.uop.taken, io.resp.bits.uop.taken connect io.resp.bits.fflags.bits.uop.pc_lob, io.resp.bits.uop.pc_lob connect io.resp.bits.fflags.bits.uop.edge_inst, io.resp.bits.uop.edge_inst connect io.resp.bits.fflags.bits.uop.ftq_idx, io.resp.bits.uop.ftq_idx connect io.resp.bits.fflags.bits.uop.br_tag, io.resp.bits.uop.br_tag connect io.resp.bits.fflags.bits.uop.br_mask, io.resp.bits.uop.br_mask connect io.resp.bits.fflags.bits.uop.is_sfb, io.resp.bits.uop.is_sfb connect io.resp.bits.fflags.bits.uop.is_jal, io.resp.bits.uop.is_jal connect io.resp.bits.fflags.bits.uop.is_jalr, io.resp.bits.uop.is_jalr connect io.resp.bits.fflags.bits.uop.is_br, io.resp.bits.uop.is_br connect io.resp.bits.fflags.bits.uop.iw_p2_poisoned, io.resp.bits.uop.iw_p2_poisoned connect io.resp.bits.fflags.bits.uop.iw_p1_poisoned, io.resp.bits.uop.iw_p1_poisoned connect io.resp.bits.fflags.bits.uop.iw_state, io.resp.bits.uop.iw_state connect io.resp.bits.fflags.bits.uop.ctrl.is_std, io.resp.bits.uop.ctrl.is_std connect io.resp.bits.fflags.bits.uop.ctrl.is_sta, io.resp.bits.uop.ctrl.is_sta connect io.resp.bits.fflags.bits.uop.ctrl.is_load, io.resp.bits.uop.ctrl.is_load connect io.resp.bits.fflags.bits.uop.ctrl.csr_cmd, io.resp.bits.uop.ctrl.csr_cmd connect io.resp.bits.fflags.bits.uop.ctrl.fcn_dw, io.resp.bits.uop.ctrl.fcn_dw connect io.resp.bits.fflags.bits.uop.ctrl.op_fcn, io.resp.bits.uop.ctrl.op_fcn connect io.resp.bits.fflags.bits.uop.ctrl.imm_sel, io.resp.bits.uop.ctrl.imm_sel connect io.resp.bits.fflags.bits.uop.ctrl.op2_sel, io.resp.bits.uop.ctrl.op2_sel connect io.resp.bits.fflags.bits.uop.ctrl.op1_sel, io.resp.bits.uop.ctrl.op1_sel connect io.resp.bits.fflags.bits.uop.ctrl.br_type, io.resp.bits.uop.ctrl.br_type connect io.resp.bits.fflags.bits.uop.fu_code, io.resp.bits.uop.fu_code connect io.resp.bits.fflags.bits.uop.iq_type, io.resp.bits.uop.iq_type connect io.resp.bits.fflags.bits.uop.debug_pc, io.resp.bits.uop.debug_pc connect io.resp.bits.fflags.bits.uop.is_rvc, io.resp.bits.uop.is_rvc connect io.resp.bits.fflags.bits.uop.debug_inst, io.resp.bits.uop.debug_inst connect io.resp.bits.fflags.bits.uop.inst, io.resp.bits.uop.inst connect io.resp.bits.fflags.bits.uop.uopc, io.resp.bits.uop.uopc connect io.resp.bits.fflags.bits.flags, fpu.io.resp.bits.fflags.bits.flags

module FPUUnit_1( // @[functional-unit.scala:564:7] input clock, // @[functional-unit.scala:564:7] input reset, // @[functional-unit.scala:564:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs3_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:564:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:564:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:564:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:564:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:564:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:564:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:564:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:564:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:564:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:564:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:564:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:564:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:564:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:564:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:564:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:564:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:564:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:564:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:564:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:564:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:564:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:564:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:564:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:564:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:564:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:564:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:564:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:564:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:564:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:564:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:564:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:564:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:564:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:564:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:564:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:564:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:564:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:564:7] wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[functional-unit.scala:564:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:564:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:564:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:564:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:564:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:564:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:564:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:564:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:564:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:564:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:564:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:564:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:564:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:564:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:564:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:564:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:564:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:564:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:564:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:564:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:564:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:564:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:564:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:564:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:564:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:564:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:564:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:564:7] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:564:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:564:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:564:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_2 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_3 = 1'h0; // @[functional-unit.scala:236:35] wire io_req_ready = 1'h1; // @[functional-unit.scala:564:7] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] wire [15:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:564:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:564:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:564:7] wire io_resp_valid_0; // @[functional-unit.scala:564:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg r_valids_2; // @[functional-unit.scala:236:27] reg r_valids_3; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_1_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_1_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_2_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_2_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_2_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_2_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_2_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_iw_state; // @[functional-unit.scala:237:23] reg r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_2_is_br; // @[functional-unit.scala:237:23] reg r_uops_2_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_2_is_jal; // @[functional-unit.scala:237:23] reg r_uops_2_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_2_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_2_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_2_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_2_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_2_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_2_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_ppred; // @[functional-unit.scala:237:23] reg r_uops_2_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_2_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_2_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_2_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_2_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_2_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_2_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_2_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_2_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_mem_size; // @[functional-unit.scala:237:23] reg r_uops_2_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_2_is_fence; // @[functional-unit.scala:237:23] reg r_uops_2_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_2_is_amo; // @[functional-unit.scala:237:23] reg r_uops_2_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_2_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_2_is_unique; // @[functional-unit.scala:237:23] reg r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_2_lrs3; // @[functional-unit.scala:237:23] reg r_uops_2_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_2_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_2_fp_val; // @[functional-unit.scala:237:23] reg r_uops_2_fp_single; // @[functional-unit.scala:237:23] reg r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_3_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_3_uopc; // @[functional-unit.scala:237:23, :564:7] reg [31:0] r_uops_3_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_3_inst; // @[functional-unit.scala:237:23, :564:7] reg [31:0] r_uops_3_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_3_debug_inst; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_3_is_rvc; // @[functional-unit.scala:237:23, :564:7] reg [39:0] r_uops_3_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_3_debug_pc; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_3_iq_type; // @[functional-unit.scala:237:23, :564:7] reg [9:0] r_uops_3_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_3_fu_code; // @[functional-unit.scala:237:23, :564:7] reg [3:0] r_uops_3_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_3_ctrl_br_type; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_3_ctrl_op1_sel; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_3_ctrl_op2_sel; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_3_ctrl_imm_sel; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_3_ctrl_op_fcn; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_3_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :564:7] reg [2:0] r_uops_3_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_3_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_3_ctrl_is_load; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_3_ctrl_is_sta; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_3_ctrl_is_std; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_3_iw_state; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_3_iw_p1_poisoned; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_3_iw_p2_poisoned; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_3_is_br; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_3_is_jalr; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_3_is_jal; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_3_is_sfb; // @[functional-unit.scala:237:23, :564:7] reg [15:0] r_uops_3_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_3_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_3_br_tag; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_3_ftq_idx; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_3_edge_inst; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_3_pc_lob; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_3_taken; // @[functional-unit.scala:237:23, :564:7] reg [19:0] r_uops_3_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_3_imm_packed; // @[functional-unit.scala:237:23, :564:7] reg [11:0] r_uops_3_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_3_csr_addr; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_3_rob_idx; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_3_ldq_idx; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_3_stq_idx; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_3_rxq_idx; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_3_pdst; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_3_prs1; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_3_prs2; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_3_prs3; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_3_ppred; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_3_prs1_busy; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_3_prs2_busy; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_3_prs3_busy; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_3_ppred_busy; // @[functional-unit.scala:237:23, :564:7] reg [6:0] r_uops_3_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_3_stale_pdst; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_3_exception; // @[functional-unit.scala:237:23, :564:7] reg [63:0] r_uops_3_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_3_exc_cause; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_3_bypassable; // @[functional-unit.scala:237:23, :564:7] reg [4:0] r_uops_3_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_3_mem_cmd; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_3_mem_size; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_3_mem_signed; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_3_is_fence; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_3_is_fencei; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_3_is_amo; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_3_uses_ldq; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_3_uses_stq; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_3_is_sys_pc2epc; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_3_is_unique; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_3_flush_on_commit; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_3_ldst_is_rs1; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_3_ldst; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_3_lrs1; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_3_lrs2; // @[functional-unit.scala:237:23, :564:7] reg [5:0] r_uops_3_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_3_lrs3; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_3_ldst_val; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_3_dst_rtype; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_3_lrs1_rtype; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_3_lrs2_rtype; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_3_frs3_en; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_3_fp_val; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_3_fp_single; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_3_xcpt_pf_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_3_xcpt_ae_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_3_xcpt_ma_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_3_bp_debug_if; // @[functional-unit.scala:237:23, :564:7] reg r_uops_3_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_3_bp_xcpt_if; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_3_debug_fsrc; // @[functional-unit.scala:237:23, :564:7] reg [1:0] r_uops_3_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_3_debug_tsrc; // @[functional-unit.scala:237:23, :564:7] wire [15:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :564:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :564:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [15:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_2_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _r_valids_2_T_1 = |_r_valids_2_T; // @[util.scala:118:{51,59}] wire _r_valids_2_T_2 = ~_r_valids_2_T_1; // @[util.scala:118:59] wire _r_valids_2_T_3 = r_valids_1 & _r_valids_2_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_2_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7] wire _r_valids_2_T_5 = _r_valids_2_T_3 & _r_valids_2_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_2_br_mask_T_1 = r_uops_1_br_mask & _r_uops_2_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_3_T = io_brupdate_b1_mispredict_mask_0 & r_uops_2_br_mask; // @[util.scala:118:51] wire _r_valids_3_T_1 = |_r_valids_3_T; // @[util.scala:118:{51,59}] wire _r_valids_3_T_2 = ~_r_valids_3_T_1; // @[util.scala:118:59] wire _r_valids_3_T_3 = r_valids_2 & _r_valids_3_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_3_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7] wire _r_valids_3_T_5 = _r_valids_3_T_3 & _r_valids_3_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_3_br_mask_T_1 = r_uops_2_br_mask & _r_uops_3_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_3_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_3 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :564:7] wire [15:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_3_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] always @(posedge clock) begin // @[functional-unit.scala:564:7] if (reset) begin // @[functional-unit.scala:564:7] r_valids_0 <= 1'h0; // @[functional-unit.scala:236:27] r_valids_1 <= 1'h0; // @[functional-unit.scala:236:27] r_valids_2 <= 1'h0; // @[functional-unit.scala:236:27] r_valids_3 <= 1'h0; // @[functional-unit.scala:236:27] end else begin // @[functional-unit.scala:564:7] r_valids_0 <= _r_valids_0_T_5; // @[functional-unit.scala:236:27, :240:84] r_valids_1 <= _r_valids_1_T_5; // @[functional-unit.scala:236:27, :246:83] r_valids_2 <= _r_valids_2_T_5; // @[functional-unit.scala:236:27, :246:83] r_valids_3 <= _r_valids_3_T_5; // @[functional-unit.scala:236:27, :246:83] end r_uops_0_uopc <= io_req_bits_uop_uopc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_inst <= io_req_bits_uop_inst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_inst <= io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_rvc <= io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_pc <= io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iq_type <= io_req_bits_uop_iq_type_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_fu_code <= io_req_bits_uop_fu_code_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_br_type <= io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_is_load <= io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ctrl_is_std <= io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iw_state <= io_req_bits_uop_iw_state_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_br <= io_req_bits_uop_is_br_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_jalr <= io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_jal <= io_req_bits_uop_is_jal_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_sfb <= io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_br_mask <= _r_uops_0_br_mask_T_1; // @[util.scala:85:25] r_uops_0_br_tag <= io_req_bits_uop_br_tag_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ftq_idx <= io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_edge_inst <= io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_pc_lob <= io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_taken <= io_req_bits_uop_taken_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_imm_packed <= io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_csr_addr <= io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_rob_idx <= io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldq_idx <= io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_stq_idx <= io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_rxq_idx <= io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_pdst <= io_req_bits_uop_pdst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs1 <= io_req_bits_uop_prs1_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs2 <= io_req_bits_uop_prs2_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs3 <= io_req_bits_uop_prs3_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ppred <= io_req_bits_uop_ppred_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs1_busy <= io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs2_busy <= io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_prs3_busy <= io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ppred_busy <= io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_stale_pdst <= io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_exception <= io_req_bits_uop_exception_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_exc_cause <= io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_bypassable <= io_req_bits_uop_bypassable_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_mem_cmd <= io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_mem_size <= io_req_bits_uop_mem_size_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_mem_signed <= io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_fence <= io_req_bits_uop_is_fence_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_fencei <= io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_amo <= io_req_bits_uop_is_amo_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_uses_ldq <= io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_uses_stq <= io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_is_unique <= io_req_bits_uop_is_unique_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_flush_on_commit <= io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldst <= io_req_bits_uop_ldst_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs1 <= io_req_bits_uop_lrs1_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs2 <= io_req_bits_uop_lrs2_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs3 <= io_req_bits_uop_lrs3_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_ldst_val <= io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_dst_rtype <= io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs1_rtype <= io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_lrs2_rtype <= io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_frs3_en <= io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_fp_val <= io_req_bits_uop_fp_val_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_fp_single <= io_req_bits_uop_fp_single_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_bp_debug_if <= io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_fsrc <= io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_0_debug_tsrc <= io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:237:23, :564:7] r_uops_1_uopc <= r_uops_0_uopc; // @[functional-unit.scala:237:23] r_uops_1_inst <= r_uops_0_inst; // @[functional-unit.scala:237:23] r_uops_1_debug_inst <= r_uops_0_debug_inst; // @[functional-unit.scala:237:23] r_uops_1_is_rvc <= r_uops_0_is_rvc; // @[functional-unit.scala:237:23] r_uops_1_debug_pc <= r_uops_0_debug_pc; // @[functional-unit.scala:237:23] r_uops_1_iq_type <= r_uops_0_iq_type; // @[functional-unit.scala:237:23] r_uops_1_fu_code <= r_uops_0_fu_code; // @[functional-unit.scala:237:23] r_uops_1_ctrl_br_type <= r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] r_uops_1_ctrl_op1_sel <= r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] r_uops_1_ctrl_op2_sel <= r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] r_uops_1_ctrl_imm_sel <= r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] r_uops_1_ctrl_op_fcn <= r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] r_uops_1_ctrl_fcn_dw <= r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] r_uops_1_ctrl_csr_cmd <= r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] r_uops_1_ctrl_is_load <= r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] r_uops_1_ctrl_is_sta <= r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] r_uops_1_ctrl_is_std <= r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] r_uops_1_iw_state <= r_uops_0_iw_state; // @[functional-unit.scala:237:23] r_uops_1_iw_p1_poisoned <= r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] r_uops_1_iw_p2_poisoned <= r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] r_uops_1_is_br <= r_uops_0_is_br; // @[functional-unit.scala:237:23] r_uops_1_is_jalr <= r_uops_0_is_jalr; // @[functional-unit.scala:237:23] r_uops_1_is_jal <= r_uops_0_is_jal; // @[functional-unit.scala:237:23] r_uops_1_is_sfb <= r_uops_0_is_sfb; // @[functional-unit.scala:237:23] r_uops_1_br_mask <= _r_uops_1_br_mask_T_1; // @[util.scala:85:25] r_uops_1_br_tag <= r_uops_0_br_tag; // @[functional-unit.scala:237:23] r_uops_1_ftq_idx <= r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] r_uops_1_edge_inst <= r_uops_0_edge_inst; // @[functional-unit.scala:237:23] r_uops_1_pc_lob <= r_uops_0_pc_lob; // @[functional-unit.scala:237:23] r_uops_1_taken <= r_uops_0_taken; // @[functional-unit.scala:237:23] r_uops_1_imm_packed <= r_uops_0_imm_packed; // @[functional-unit.scala:237:23] r_uops_1_csr_addr <= r_uops_0_csr_addr; // @[functional-unit.scala:237:23] r_uops_1_rob_idx <= r_uops_0_rob_idx; // @[functional-unit.scala:237:23] r_uops_1_ldq_idx <= r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] r_uops_1_stq_idx <= r_uops_0_stq_idx; // @[functional-unit.scala:237:23] r_uops_1_rxq_idx <= r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] r_uops_1_pdst <= r_uops_0_pdst; // @[functional-unit.scala:237:23] r_uops_1_prs1 <= r_uops_0_prs1; // @[functional-unit.scala:237:23] r_uops_1_prs2 <= r_uops_0_prs2; // @[functional-unit.scala:237:23] r_uops_1_prs3 <= r_uops_0_prs3; // @[functional-unit.scala:237:23] r_uops_1_ppred <= r_uops_0_ppred; // @[functional-unit.scala:237:23] r_uops_1_prs1_busy <= r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] r_uops_1_prs2_busy <= r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] r_uops_1_prs3_busy <= r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] r_uops_1_ppred_busy <= r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] r_uops_1_stale_pdst <= r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] r_uops_1_exception <= r_uops_0_exception; // @[functional-unit.scala:237:23] r_uops_1_exc_cause <= r_uops_0_exc_cause; // @[functional-unit.scala:237:23] r_uops_1_bypassable <= r_uops_0_bypassable; // @[functional-unit.scala:237:23] r_uops_1_mem_cmd <= r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] r_uops_1_mem_size <= r_uops_0_mem_size; // @[functional-unit.scala:237:23] r_uops_1_mem_signed <= r_uops_0_mem_signed; // @[functional-unit.scala:237:23] r_uops_1_is_fence <= r_uops_0_is_fence; // @[functional-unit.scala:237:23] r_uops_1_is_fencei <= r_uops_0_is_fencei; // @[functional-unit.scala:237:23] r_uops_1_is_amo <= r_uops_0_is_amo; // @[functional-unit.scala:237:23] r_uops_1_uses_ldq <= r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] r_uops_1_uses_stq <= r_uops_0_uses_stq; // @[functional-unit.scala:237:23] r_uops_1_is_sys_pc2epc <= r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] r_uops_1_is_unique <= r_uops_0_is_unique; // @[functional-unit.scala:237:23] r_uops_1_flush_on_commit <= r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] r_uops_1_ldst_is_rs1 <= r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] r_uops_1_ldst <= r_uops_0_ldst; // @[functional-unit.scala:237:23] r_uops_1_lrs1 <= r_uops_0_lrs1; // @[functional-unit.scala:237:23] r_uops_1_lrs2 <= r_uops_0_lrs2; // @[functional-unit.scala:237:23] r_uops_1_lrs3 <= r_uops_0_lrs3; // @[functional-unit.scala:237:23] r_uops_1_ldst_val <= r_uops_0_ldst_val; // @[functional-unit.scala:237:23] r_uops_1_dst_rtype <= r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] r_uops_1_lrs1_rtype <= r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] r_uops_1_lrs2_rtype <= r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] r_uops_1_frs3_en <= r_uops_0_frs3_en; // @[functional-unit.scala:237:23] r_uops_1_fp_val <= r_uops_0_fp_val; // @[functional-unit.scala:237:23] r_uops_1_fp_single <= r_uops_0_fp_single; // @[functional-unit.scala:237:23] r_uops_1_xcpt_pf_if <= r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] r_uops_1_xcpt_ae_if <= r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] r_uops_1_xcpt_ma_if <= r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] r_uops_1_bp_debug_if <= r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] r_uops_1_bp_xcpt_if <= r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] r_uops_1_debug_fsrc <= r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] r_uops_1_debug_tsrc <= r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] r_uops_2_uopc <= r_uops_1_uopc; // @[functional-unit.scala:237:23] r_uops_2_inst <= r_uops_1_inst; // @[functional-unit.scala:237:23] r_uops_2_debug_inst <= r_uops_1_debug_inst; // @[functional-unit.scala:237:23] r_uops_2_is_rvc <= r_uops_1_is_rvc; // @[functional-unit.scala:237:23] r_uops_2_debug_pc <= r_uops_1_debug_pc; // @[functional-unit.scala:237:23] r_uops_2_iq_type <= r_uops_1_iq_type; // @[functional-unit.scala:237:23] r_uops_2_fu_code <= r_uops_1_fu_code; // @[functional-unit.scala:237:23] r_uops_2_ctrl_br_type <= r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] r_uops_2_ctrl_op1_sel <= r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] r_uops_2_ctrl_op2_sel <= r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] r_uops_2_ctrl_imm_sel <= r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] r_uops_2_ctrl_op_fcn <= r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] r_uops_2_ctrl_fcn_dw <= r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] r_uops_2_ctrl_csr_cmd <= r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] r_uops_2_ctrl_is_load <= r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] r_uops_2_ctrl_is_sta <= r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] r_uops_2_ctrl_is_std <= r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] r_uops_2_iw_state <= r_uops_1_iw_state; // @[functional-unit.scala:237:23] r_uops_2_iw_p1_poisoned <= r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] r_uops_2_iw_p2_poisoned <= r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] r_uops_2_is_br <= r_uops_1_is_br; // @[functional-unit.scala:237:23] r_uops_2_is_jalr <= r_uops_1_is_jalr; // @[functional-unit.scala:237:23] r_uops_2_is_jal <= r_uops_1_is_jal; // @[functional-unit.scala:237:23] r_uops_2_is_sfb <= r_uops_1_is_sfb; // @[functional-unit.scala:237:23] r_uops_2_br_mask <= _r_uops_2_br_mask_T_1; // @[util.scala:85:25] r_uops_2_br_tag <= r_uops_1_br_tag; // @[functional-unit.scala:237:23] r_uops_2_ftq_idx <= r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] r_uops_2_edge_inst <= r_uops_1_edge_inst; // @[functional-unit.scala:237:23] r_uops_2_pc_lob <= r_uops_1_pc_lob; // @[functional-unit.scala:237:23] r_uops_2_taken <= r_uops_1_taken; // @[functional-unit.scala:237:23] r_uops_2_imm_packed <= r_uops_1_imm_packed; // @[functional-unit.scala:237:23] r_uops_2_csr_addr <= r_uops_1_csr_addr; // @[functional-unit.scala:237:23] r_uops_2_rob_idx <= r_uops_1_rob_idx; // @[functional-unit.scala:237:23] r_uops_2_ldq_idx <= r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] r_uops_2_stq_idx <= r_uops_1_stq_idx; // @[functional-unit.scala:237:23] r_uops_2_rxq_idx <= r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] r_uops_2_pdst <= r_uops_1_pdst; // @[functional-unit.scala:237:23] r_uops_2_prs1 <= r_uops_1_prs1; // @[functional-unit.scala:237:23] r_uops_2_prs2 <= r_uops_1_prs2; // @[functional-unit.scala:237:23] r_uops_2_prs3 <= r_uops_1_prs3; // @[functional-unit.scala:237:23] r_uops_2_ppred <= r_uops_1_ppred; // @[functional-unit.scala:237:23] r_uops_2_prs1_busy <= r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] r_uops_2_prs2_busy <= r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] r_uops_2_prs3_busy <= r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] r_uops_2_ppred_busy <= r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] r_uops_2_stale_pdst <= r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] r_uops_2_exception <= r_uops_1_exception; // @[functional-unit.scala:237:23] r_uops_2_exc_cause <= r_uops_1_exc_cause; // @[functional-unit.scala:237:23] r_uops_2_bypassable <= r_uops_1_bypassable; // @[functional-unit.scala:237:23] r_uops_2_mem_cmd <= r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] r_uops_2_mem_size <= r_uops_1_mem_size; // @[functional-unit.scala:237:23] r_uops_2_mem_signed <= r_uops_1_mem_signed; // @[functional-unit.scala:237:23] r_uops_2_is_fence <= r_uops_1_is_fence; // @[functional-unit.scala:237:23] r_uops_2_is_fencei <= r_uops_1_is_fencei; // @[functional-unit.scala:237:23] r_uops_2_is_amo <= r_uops_1_is_amo; // @[functional-unit.scala:237:23] r_uops_2_uses_ldq <= r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] r_uops_2_uses_stq <= r_uops_1_uses_stq; // @[functional-unit.scala:237:23] r_uops_2_is_sys_pc2epc <= r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] r_uops_2_is_unique <= r_uops_1_is_unique; // @[functional-unit.scala:237:23] r_uops_2_flush_on_commit <= r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] r_uops_2_ldst_is_rs1 <= r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] r_uops_2_ldst <= r_uops_1_ldst; // @[functional-unit.scala:237:23] r_uops_2_lrs1 <= r_uops_1_lrs1; // @[functional-unit.scala:237:23] r_uops_2_lrs2 <= r_uops_1_lrs2; // @[functional-unit.scala:237:23] r_uops_2_lrs3 <= r_uops_1_lrs3; // @[functional-unit.scala:237:23] r_uops_2_ldst_val <= r_uops_1_ldst_val; // @[functional-unit.scala:237:23] r_uops_2_dst_rtype <= r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] r_uops_2_lrs1_rtype <= r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] r_uops_2_lrs2_rtype <= r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] r_uops_2_frs3_en <= r_uops_1_frs3_en; // @[functional-unit.scala:237:23] r_uops_2_fp_val <= r_uops_1_fp_val; // @[functional-unit.scala:237:23] r_uops_2_fp_single <= r_uops_1_fp_single; // @[functional-unit.scala:237:23] r_uops_2_xcpt_pf_if <= r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] r_uops_2_xcpt_ae_if <= r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] r_uops_2_xcpt_ma_if <= r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] r_uops_2_bp_debug_if <= r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] r_uops_2_bp_xcpt_if <= r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] r_uops_2_debug_fsrc <= r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] r_uops_2_debug_tsrc <= r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] r_uops_3_uopc <= r_uops_2_uopc; // @[functional-unit.scala:237:23] r_uops_3_inst <= r_uops_2_inst; // @[functional-unit.scala:237:23] r_uops_3_debug_inst <= r_uops_2_debug_inst; // @[functional-unit.scala:237:23] r_uops_3_is_rvc <= r_uops_2_is_rvc; // @[functional-unit.scala:237:23] r_uops_3_debug_pc <= r_uops_2_debug_pc; // @[functional-unit.scala:237:23] r_uops_3_iq_type <= r_uops_2_iq_type; // @[functional-unit.scala:237:23] r_uops_3_fu_code <= r_uops_2_fu_code; // @[functional-unit.scala:237:23] r_uops_3_ctrl_br_type <= r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23] r_uops_3_ctrl_op1_sel <= r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23] r_uops_3_ctrl_op2_sel <= r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23] r_uops_3_ctrl_imm_sel <= r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23] r_uops_3_ctrl_op_fcn <= r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23] r_uops_3_ctrl_fcn_dw <= r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23] r_uops_3_ctrl_csr_cmd <= r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23] r_uops_3_ctrl_is_load <= r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23] r_uops_3_ctrl_is_sta <= r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23] r_uops_3_ctrl_is_std <= r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23] r_uops_3_iw_state <= r_uops_2_iw_state; // @[functional-unit.scala:237:23] r_uops_3_iw_p1_poisoned <= r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23] r_uops_3_iw_p2_poisoned <= r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23] r_uops_3_is_br <= r_uops_2_is_br; // @[functional-unit.scala:237:23] r_uops_3_is_jalr <= r_uops_2_is_jalr; // @[functional-unit.scala:237:23] r_uops_3_is_jal <= r_uops_2_is_jal; // @[functional-unit.scala:237:23] r_uops_3_is_sfb <= r_uops_2_is_sfb; // @[functional-unit.scala:237:23] r_uops_3_br_mask <= _r_uops_3_br_mask_T_1; // @[util.scala:85:25] r_uops_3_br_tag <= r_uops_2_br_tag; // @[functional-unit.scala:237:23] r_uops_3_ftq_idx <= r_uops_2_ftq_idx; // @[functional-unit.scala:237:23] r_uops_3_edge_inst <= r_uops_2_edge_inst; // @[functional-unit.scala:237:23] r_uops_3_pc_lob <= r_uops_2_pc_lob; // @[functional-unit.scala:237:23] r_uops_3_taken <= r_uops_2_taken; // @[functional-unit.scala:237:23] r_uops_3_imm_packed <= r_uops_2_imm_packed; // @[functional-unit.scala:237:23] r_uops_3_csr_addr <= r_uops_2_csr_addr; // @[functional-unit.scala:237:23] r_uops_3_rob_idx <= r_uops_2_rob_idx; // @[functional-unit.scala:237:23] r_uops_3_ldq_idx <= r_uops_2_ldq_idx; // @[functional-unit.scala:237:23] r_uops_3_stq_idx <= r_uops_2_stq_idx; // @[functional-unit.scala:237:23] r_uops_3_rxq_idx <= r_uops_2_rxq_idx; // @[functional-unit.scala:237:23] r_uops_3_pdst <= r_uops_2_pdst; // @[functional-unit.scala:237:23] r_uops_3_prs1 <= r_uops_2_prs1; // @[functional-unit.scala:237:23] r_uops_3_prs2 <= r_uops_2_prs2; // @[functional-unit.scala:237:23] r_uops_3_prs3 <= r_uops_2_prs3; // @[functional-unit.scala:237:23] r_uops_3_ppred <= r_uops_2_ppred; // @[functional-unit.scala:237:23] r_uops_3_prs1_busy <= r_uops_2_prs1_busy; // @[functional-unit.scala:237:23] r_uops_3_prs2_busy <= r_uops_2_prs2_busy; // @[functional-unit.scala:237:23] r_uops_3_prs3_busy <= r_uops_2_prs3_busy; // @[functional-unit.scala:237:23] r_uops_3_ppred_busy <= r_uops_2_ppred_busy; // @[functional-unit.scala:237:23] r_uops_3_stale_pdst <= r_uops_2_stale_pdst; // @[functional-unit.scala:237:23] r_uops_3_exception <= r_uops_2_exception; // @[functional-unit.scala:237:23] r_uops_3_exc_cause <= r_uops_2_exc_cause; // @[functional-unit.scala:237:23] r_uops_3_bypassable <= r_uops_2_bypassable; // @[functional-unit.scala:237:23] r_uops_3_mem_cmd <= r_uops_2_mem_cmd; // @[functional-unit.scala:237:23] r_uops_3_mem_size <= r_uops_2_mem_size; // @[functional-unit.scala:237:23] r_uops_3_mem_signed <= r_uops_2_mem_signed; // @[functional-unit.scala:237:23] r_uops_3_is_fence <= r_uops_2_is_fence; // @[functional-unit.scala:237:23] r_uops_3_is_fencei <= r_uops_2_is_fencei; // @[functional-unit.scala:237:23] r_uops_3_is_amo <= r_uops_2_is_amo; // @[functional-unit.scala:237:23] r_uops_3_uses_ldq <= r_uops_2_uses_ldq; // @[functional-unit.scala:237:23] r_uops_3_uses_stq <= r_uops_2_uses_stq; // @[functional-unit.scala:237:23] r_uops_3_is_sys_pc2epc <= r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23] r_uops_3_is_unique <= r_uops_2_is_unique; // @[functional-unit.scala:237:23] r_uops_3_flush_on_commit <= r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23] r_uops_3_ldst_is_rs1 <= r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23] r_uops_3_ldst <= r_uops_2_ldst; // @[functional-unit.scala:237:23] r_uops_3_lrs1 <= r_uops_2_lrs1; // @[functional-unit.scala:237:23] r_uops_3_lrs2 <= r_uops_2_lrs2; // @[functional-unit.scala:237:23] r_uops_3_lrs3 <= r_uops_2_lrs3; // @[functional-unit.scala:237:23] r_uops_3_ldst_val <= r_uops_2_ldst_val; // @[functional-unit.scala:237:23] r_uops_3_dst_rtype <= r_uops_2_dst_rtype; // @[functional-unit.scala:237:23] r_uops_3_lrs1_rtype <= r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23] r_uops_3_lrs2_rtype <= r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23] r_uops_3_frs3_en <= r_uops_2_frs3_en; // @[functional-unit.scala:237:23] r_uops_3_fp_val <= r_uops_2_fp_val; // @[functional-unit.scala:237:23] r_uops_3_fp_single <= r_uops_2_fp_single; // @[functional-unit.scala:237:23] r_uops_3_xcpt_pf_if <= r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23] r_uops_3_xcpt_ae_if <= r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23] r_uops_3_xcpt_ma_if <= r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23] r_uops_3_bp_debug_if <= r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23] r_uops_3_bp_xcpt_if <= r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23] r_uops_3_debug_fsrc <= r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23] r_uops_3_debug_tsrc <= r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23] always @(posedge) FPU_3 fpu ( // @[functional-unit.scala:572:19] .clock (clock), .reset (reset), .io_req_valid (io_req_valid_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_uopc (io_req_bits_uop_uopc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_inst (io_req_bits_uop_inst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iq_type (io_req_bits_uop_iq_type_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_fu_code (io_req_bits_uop_fu_code_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iw_state (io_req_bits_uop_iw_state_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_br (io_req_bits_uop_is_br_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_jal (io_req_bits_uop_is_jal_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_taken (io_req_bits_uop_taken_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_pdst (io_req_bits_uop_pdst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs1 (io_req_bits_uop_prs1_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs2 (io_req_bits_uop_prs2_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs3 (io_req_bits_uop_prs3_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ppred (io_req_bits_uop_ppred_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_exception (io_req_bits_uop_exception_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_mem_size (io_req_bits_uop_mem_size_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_fence (io_req_bits_uop_is_fence_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_is_unique (io_req_bits_uop_is_unique_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldst (io_req_bits_uop_ldst_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_fp_single (io_req_bits_uop_fp_single_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc_0), // @[functional-unit.scala:564:7] .io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc_0), // @[functional-unit.scala:564:7] .io_req_bits_rs1_data (io_req_bits_rs1_data_0), // @[functional-unit.scala:564:7] .io_req_bits_rs2_data (io_req_bits_rs2_data_0), // @[functional-unit.scala:564:7] .io_req_bits_rs3_data (io_req_bits_rs3_data_0), // @[functional-unit.scala:564:7] .io_req_bits_fcsr_rm (io_fcsr_rm_0), // @[functional-unit.scala:564:7] .io_resp_bits_data (io_resp_bits_data_0), .io_resp_bits_fflags_valid (io_resp_bits_fflags_valid_0), .io_resp_bits_fflags_bits_flags (io_resp_bits_fflags_bits_flags_0) ); // @[functional-unit.scala:572:19] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_uopc = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iq_type = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_fu_code = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_br_type = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_op1_sel = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_op2_sel = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_imm_sel = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_op_fcn = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_fcn_dw = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_csr_cmd = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_is_load = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_is_sta = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ctrl_is_std = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iw_state = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iw_p1_poisoned = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_iw_p2_poisoned = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_br = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_jalr = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_jal = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_csr_addr = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_bypassable = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_ldst_val = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_fp_single = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_valid = io_resp_bits_fflags_valid_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_uopc = io_resp_bits_fflags_bits_uop_uopc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_inst = io_resp_bits_fflags_bits_uop_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_inst = io_resp_bits_fflags_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_rvc = io_resp_bits_fflags_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_pc = io_resp_bits_fflags_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iq_type = io_resp_bits_fflags_bits_uop_iq_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_fu_code = io_resp_bits_fflags_bits_uop_fu_code_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_br_type = io_resp_bits_fflags_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel = io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel = io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel = io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn = io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_is_load = io_resp_bits_fflags_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_is_sta = io_resp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ctrl_is_std = io_resp_bits_fflags_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iw_state = io_resp_bits_fflags_bits_uop_iw_state_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned = io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned = io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_br = io_resp_bits_fflags_bits_uop_is_br_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_jalr = io_resp_bits_fflags_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_jal = io_resp_bits_fflags_bits_uop_is_jal_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_sfb = io_resp_bits_fflags_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_br_mask = io_resp_bits_fflags_bits_uop_br_mask_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_br_tag = io_resp_bits_fflags_bits_uop_br_tag_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ftq_idx = io_resp_bits_fflags_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_edge_inst = io_resp_bits_fflags_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_pc_lob = io_resp_bits_fflags_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_taken = io_resp_bits_fflags_bits_uop_taken_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_imm_packed = io_resp_bits_fflags_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_csr_addr = io_resp_bits_fflags_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_rob_idx = io_resp_bits_fflags_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldq_idx = io_resp_bits_fflags_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_stq_idx = io_resp_bits_fflags_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_rxq_idx = io_resp_bits_fflags_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_pdst = io_resp_bits_fflags_bits_uop_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs1 = io_resp_bits_fflags_bits_uop_prs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs2 = io_resp_bits_fflags_bits_uop_prs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs3 = io_resp_bits_fflags_bits_uop_prs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ppred = io_resp_bits_fflags_bits_uop_ppred_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs1_busy = io_resp_bits_fflags_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs2_busy = io_resp_bits_fflags_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_prs3_busy = io_resp_bits_fflags_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ppred_busy = io_resp_bits_fflags_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_stale_pdst = io_resp_bits_fflags_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_exception = io_resp_bits_fflags_bits_uop_exception_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_exc_cause = io_resp_bits_fflags_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_bypassable = io_resp_bits_fflags_bits_uop_bypassable_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_mem_cmd = io_resp_bits_fflags_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_mem_size = io_resp_bits_fflags_bits_uop_mem_size_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_mem_signed = io_resp_bits_fflags_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_fence = io_resp_bits_fflags_bits_uop_is_fence_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_fencei = io_resp_bits_fflags_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_amo = io_resp_bits_fflags_bits_uop_is_amo_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_uses_ldq = io_resp_bits_fflags_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_uses_stq = io_resp_bits_fflags_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc = io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_is_unique = io_resp_bits_fflags_bits_uop_is_unique_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_flush_on_commit = io_resp_bits_fflags_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldst_is_rs1 = io_resp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldst = io_resp_bits_fflags_bits_uop_ldst_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs1 = io_resp_bits_fflags_bits_uop_lrs1_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs2 = io_resp_bits_fflags_bits_uop_lrs2_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs3 = io_resp_bits_fflags_bits_uop_lrs3_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_ldst_val = io_resp_bits_fflags_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_dst_rtype = io_resp_bits_fflags_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs1_rtype = io_resp_bits_fflags_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_lrs2_rtype = io_resp_bits_fflags_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_frs3_en = io_resp_bits_fflags_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_fp_val = io_resp_bits_fflags_bits_uop_fp_val_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_fp_single = io_resp_bits_fflags_bits_uop_fp_single_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_xcpt_pf_if = io_resp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_xcpt_ae_if = io_resp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_xcpt_ma_if = io_resp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_bp_debug_if = io_resp_bits_fflags_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_bp_xcpt_if = io_resp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_fsrc = io_resp_bits_fflags_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_uop_debug_tsrc = io_resp_bits_fflags_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7] assign io_resp_bits_fflags_bits_flags = io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:564:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_14 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_14( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_104 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_104( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_87 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_87( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_3 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_3( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_4 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleC_a32d128s7k6z4c_4 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40)) node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0)) node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<7>(0h40)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T

module TLCToNoC_4( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_56 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_56 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_56( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_56 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NonSyncResetSynchronizerPrimitiveShiftReg_d3_6 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} reg sync_0 : UInt<1>, clock reg sync_1 : UInt<1>, clock reg sync_2 : UInt<1>, clock node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module NonSyncResetSynchronizerPrimitiveShiftReg_d3_6( // @[SynchronizerReg.scala:37:15] input clock, // @[SynchronizerReg.scala:37:15] input reset, // @[SynchronizerReg.scala:37:15] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:37:15] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:37:15, :54:22] wire io_q_0; // @[SynchronizerReg.scala:37:15] reg sync_0; // @[SynchronizerReg.scala:51:66] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:37:15, :51:66] reg sync_1; // @[SynchronizerReg.scala:51:66] reg sync_2; // @[SynchronizerReg.scala:51:66] always @(posedge clock) begin // @[SynchronizerReg.scala:37:15] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:66] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:66] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:66, :54:22] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:37:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_322 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_66 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_322( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_66 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_119 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_120 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PE_449 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_193 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_449( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_193 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Router_60 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_127 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_128 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_129 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_5 of InputUnit_127 connect input_unit_0_from_5.clock, clock connect input_unit_0_from_5.reset, reset inst input_unit_1_from_12 of InputUnit_128 connect input_unit_1_from_12.clock, clock connect input_unit_1_from_12.reset, reset inst input_unit_2_from_14 of InputUnit_129 connect input_unit_2_from_14.clock, clock connect input_unit_2_from_14.reset, reset inst output_unit_0_to_5 of OutputUnit_127 connect output_unit_0_to_5.clock, clock connect output_unit_0_to_5.reset, reset inst output_unit_1_to_12 of OutputUnit_128 connect output_unit_1_to_12.clock, clock connect output_unit_1_to_12.reset, reset inst output_unit_2_to_14 of OutputUnit_129 connect output_unit_2_to_14.clock, clock connect output_unit_2_to_14.reset, reset inst switch of Switch_60 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_60 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_60 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_60 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_6 connect input_unit_0_from_5.io.in, destNodesIn connect input_unit_1_from_12.io.in, destNodesIn_1 connect input_unit_2_from_14.io.in, destNodesIn_2 connect output_unit_0_to_5.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_5.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_5.io.out.flit connect output_unit_1_to_12.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_12.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_12.io.out.flit connect output_unit_2_to_14.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_14.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_14.io.out.flit connect route_computer.io.req.`0`, input_unit_0_from_5.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_12.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_14.io.router_req connect input_unit_0_from_5.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_12.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_14.io.router_resp, route_computer.io.resp.`2` connect vc_allocator.io.req.`0`, input_unit_0_from_5.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_12.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_14.io.vcalloc_req connect input_unit_0_from_5.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_12.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_14.io.vcalloc_resp, vc_allocator.io.resp.`2` connect output_unit_0_to_5.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_12.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_14.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_5.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_5.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_5.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_5.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_5.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_5.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_5.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_5.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_5.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_5.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_5.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_5.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_5.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_5.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_5.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_5.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_5.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_5.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_5.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_5.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_5.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_5.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_5.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_5.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_5.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_5.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_5.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_5.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_5.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_5.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_5.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_5.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_5.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_5.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_5.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_5.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_5.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_5.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_5.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_5.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`0`[8].flow.egress_node_id, output_unit_0_to_5.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[8].flow.egress_node, output_unit_0_to_5.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node, output_unit_0_to_5.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`0`[8].flow.vnet_id, output_unit_0_to_5.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`0`[8].occupied, output_unit_0_to_5.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`0`[9].flow.egress_node_id, output_unit_0_to_5.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[9].flow.egress_node, output_unit_0_to_5.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node, output_unit_0_to_5.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`0`[9].flow.vnet_id, output_unit_0_to_5.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`0`[9].occupied, output_unit_0_to_5.io.channel_status[9].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_12.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_12.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_12.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_12.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_12.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_12.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_12.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_12.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_12.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_12.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_12.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_12.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_12.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_12.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_12.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_12.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_12.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_12.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_12.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_12.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_12.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[5].flow.egress_node_id, output_unit_1_to_12.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.egress_node, output_unit_1_to_12.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node, output_unit_1_to_12.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`1`[5].flow.vnet_id, output_unit_1_to_12.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`1`[5].occupied, output_unit_1_to_12.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`1`[6].flow.egress_node_id, output_unit_1_to_12.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.egress_node, output_unit_1_to_12.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node, output_unit_1_to_12.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`1`[6].flow.vnet_id, output_unit_1_to_12.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`1`[6].occupied, output_unit_1_to_12.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`1`[7].flow.egress_node_id, output_unit_1_to_12.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.egress_node, output_unit_1_to_12.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node, output_unit_1_to_12.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`1`[7].flow.vnet_id, output_unit_1_to_12.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`1`[7].occupied, output_unit_1_to_12.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[8].flow.egress_node_id, output_unit_1_to_12.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[8].flow.egress_node, output_unit_1_to_12.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`1`[8].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[8].flow.ingress_node, output_unit_1_to_12.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`1`[8].flow.vnet_id, output_unit_1_to_12.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`1`[8].occupied, output_unit_1_to_12.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`1`[9].flow.egress_node_id, output_unit_1_to_12.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[9].flow.egress_node, output_unit_1_to_12.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`1`[9].flow.ingress_node_id, output_unit_1_to_12.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[9].flow.ingress_node, output_unit_1_to_12.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`1`[9].flow.vnet_id, output_unit_1_to_12.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`1`[9].occupied, output_unit_1_to_12.io.channel_status[9].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_14.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_14.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_14.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_14.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_14.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_14.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_14.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_14.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_14.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_14.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_14.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_14.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_14.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_14.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_14.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_14.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_14.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_14.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_14.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_14.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_14.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_14.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_14.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_14.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_14.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`2`[5].flow.egress_node_id, output_unit_2_to_14.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[5].flow.egress_node, output_unit_2_to_14.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node, output_unit_2_to_14.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`2`[5].flow.vnet_id, output_unit_2_to_14.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`2`[5].occupied, output_unit_2_to_14.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`2`[6].flow.egress_node_id, output_unit_2_to_14.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[6].flow.egress_node, output_unit_2_to_14.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node, output_unit_2_to_14.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`2`[6].flow.vnet_id, output_unit_2_to_14.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`2`[6].occupied, output_unit_2_to_14.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`2`[7].flow.egress_node_id, output_unit_2_to_14.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[7].flow.egress_node, output_unit_2_to_14.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node, output_unit_2_to_14.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`2`[7].flow.vnet_id, output_unit_2_to_14.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`2`[7].occupied, output_unit_2_to_14.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`2`[8].flow.egress_node_id, output_unit_2_to_14.io.channel_status[8].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[8].flow.egress_node, output_unit_2_to_14.io.channel_status[8].flow.egress_node connect vc_allocator.io.channel_status.`2`[8].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[8].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[8].flow.ingress_node, output_unit_2_to_14.io.channel_status[8].flow.ingress_node connect vc_allocator.io.channel_status.`2`[8].flow.vnet_id, output_unit_2_to_14.io.channel_status[8].flow.vnet_id connect vc_allocator.io.channel_status.`2`[8].occupied, output_unit_2_to_14.io.channel_status[8].occupied connect vc_allocator.io.channel_status.`2`[9].flow.egress_node_id, output_unit_2_to_14.io.channel_status[9].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[9].flow.egress_node, output_unit_2_to_14.io.channel_status[9].flow.egress_node connect vc_allocator.io.channel_status.`2`[9].flow.ingress_node_id, output_unit_2_to_14.io.channel_status[9].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[9].flow.ingress_node, output_unit_2_to_14.io.channel_status[9].flow.ingress_node connect vc_allocator.io.channel_status.`2`[9].flow.vnet_id, output_unit_2_to_14.io.channel_status[9].flow.vnet_id connect vc_allocator.io.channel_status.`2`[9].occupied, output_unit_2_to_14.io.channel_status[9].occupied connect input_unit_0_from_5.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`0`[8], output_unit_0_to_5.io.credit_available[8] connect input_unit_0_from_5.io.out_credit_available.`0`[9], output_unit_0_to_5.io.credit_available[9] connect input_unit_0_from_5.io.out_credit_available.`1`[0], output_unit_1_to_12.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`1`[1], output_unit_1_to_12.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`1`[2], output_unit_1_to_12.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`1`[3], output_unit_1_to_12.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`1`[4], output_unit_1_to_12.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`1`[5], output_unit_1_to_12.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`1`[6], output_unit_1_to_12.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`1`[7], output_unit_1_to_12.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`1`[8], output_unit_1_to_12.io.credit_available[8] connect input_unit_0_from_5.io.out_credit_available.`1`[9], output_unit_1_to_12.io.credit_available[9] connect input_unit_0_from_5.io.out_credit_available.`2`[0], output_unit_2_to_14.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`2`[1], output_unit_2_to_14.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`2`[2], output_unit_2_to_14.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`2`[3], output_unit_2_to_14.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`2`[4], output_unit_2_to_14.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`2`[5], output_unit_2_to_14.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`2`[6], output_unit_2_to_14.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`2`[7], output_unit_2_to_14.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`2`[8], output_unit_2_to_14.io.credit_available[8] connect input_unit_0_from_5.io.out_credit_available.`2`[9], output_unit_2_to_14.io.credit_available[9] connect input_unit_1_from_12.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_1_from_12.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_1_from_12.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_1_from_12.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_1_from_12.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_1_from_12.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_1_from_12.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_1_from_12.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_1_from_12.io.out_credit_available.`0`[8], output_unit_0_to_5.io.credit_available[8] connect input_unit_1_from_12.io.out_credit_available.`0`[9], output_unit_0_to_5.io.credit_available[9] connect input_unit_1_from_12.io.out_credit_available.`1`[0], output_unit_1_to_12.io.credit_available[0] connect input_unit_1_from_12.io.out_credit_available.`1`[1], output_unit_1_to_12.io.credit_available[1] connect input_unit_1_from_12.io.out_credit_available.`1`[2], output_unit_1_to_12.io.credit_available[2] connect input_unit_1_from_12.io.out_credit_available.`1`[3], output_unit_1_to_12.io.credit_available[3] connect input_unit_1_from_12.io.out_credit_available.`1`[4], output_unit_1_to_12.io.credit_available[4] connect input_unit_1_from_12.io.out_credit_available.`1`[5], output_unit_1_to_12.io.credit_available[5] connect input_unit_1_from_12.io.out_credit_available.`1`[6], output_unit_1_to_12.io.credit_available[6] connect input_unit_1_from_12.io.out_credit_available.`1`[7], output_unit_1_to_12.io.credit_available[7] connect input_unit_1_from_12.io.out_credit_available.`1`[8], output_unit_1_to_12.io.credit_available[8] connect input_unit_1_from_12.io.out_credit_available.`1`[9], output_unit_1_to_12.io.credit_available[9] connect input_unit_1_from_12.io.out_credit_available.`2`[0], output_unit_2_to_14.io.credit_available[0] connect input_unit_1_from_12.io.out_credit_available.`2`[1], output_unit_2_to_14.io.credit_available[1] connect input_unit_1_from_12.io.out_credit_available.`2`[2], output_unit_2_to_14.io.credit_available[2] connect input_unit_1_from_12.io.out_credit_available.`2`[3], output_unit_2_to_14.io.credit_available[3] connect input_unit_1_from_12.io.out_credit_available.`2`[4], output_unit_2_to_14.io.credit_available[4] connect input_unit_1_from_12.io.out_credit_available.`2`[5], output_unit_2_to_14.io.credit_available[5] connect input_unit_1_from_12.io.out_credit_available.`2`[6], output_unit_2_to_14.io.credit_available[6] connect input_unit_1_from_12.io.out_credit_available.`2`[7], output_unit_2_to_14.io.credit_available[7] connect input_unit_1_from_12.io.out_credit_available.`2`[8], output_unit_2_to_14.io.credit_available[8] connect input_unit_1_from_12.io.out_credit_available.`2`[9], output_unit_2_to_14.io.credit_available[9] connect input_unit_2_from_14.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_2_from_14.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_2_from_14.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_2_from_14.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_2_from_14.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_2_from_14.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_2_from_14.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_2_from_14.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_2_from_14.io.out_credit_available.`0`[8], output_unit_0_to_5.io.credit_available[8] connect input_unit_2_from_14.io.out_credit_available.`0`[9], output_unit_0_to_5.io.credit_available[9] connect input_unit_2_from_14.io.out_credit_available.`1`[0], output_unit_1_to_12.io.credit_available[0] connect input_unit_2_from_14.io.out_credit_available.`1`[1], output_unit_1_to_12.io.credit_available[1] connect input_unit_2_from_14.io.out_credit_available.`1`[2], output_unit_1_to_12.io.credit_available[2] connect input_unit_2_from_14.io.out_credit_available.`1`[3], output_unit_1_to_12.io.credit_available[3] connect input_unit_2_from_14.io.out_credit_available.`1`[4], output_unit_1_to_12.io.credit_available[4] connect input_unit_2_from_14.io.out_credit_available.`1`[5], output_unit_1_to_12.io.credit_available[5] connect input_unit_2_from_14.io.out_credit_available.`1`[6], output_unit_1_to_12.io.credit_available[6] connect input_unit_2_from_14.io.out_credit_available.`1`[7], output_unit_1_to_12.io.credit_available[7] connect input_unit_2_from_14.io.out_credit_available.`1`[8], output_unit_1_to_12.io.credit_available[8] connect input_unit_2_from_14.io.out_credit_available.`1`[9], output_unit_1_to_12.io.credit_available[9] connect input_unit_2_from_14.io.out_credit_available.`2`[0], output_unit_2_to_14.io.credit_available[0] connect input_unit_2_from_14.io.out_credit_available.`2`[1], output_unit_2_to_14.io.credit_available[1] connect input_unit_2_from_14.io.out_credit_available.`2`[2], output_unit_2_to_14.io.credit_available[2] connect input_unit_2_from_14.io.out_credit_available.`2`[3], output_unit_2_to_14.io.credit_available[3] connect input_unit_2_from_14.io.out_credit_available.`2`[4], output_unit_2_to_14.io.credit_available[4] connect input_unit_2_from_14.io.out_credit_available.`2`[5], output_unit_2_to_14.io.credit_available[5] connect input_unit_2_from_14.io.out_credit_available.`2`[6], output_unit_2_to_14.io.credit_available[6] connect input_unit_2_from_14.io.out_credit_available.`2`[7], output_unit_2_to_14.io.credit_available[7] connect input_unit_2_from_14.io.out_credit_available.`2`[8], output_unit_2_to_14.io.credit_available[8] connect input_unit_2_from_14.io.out_credit_available.`2`[9], output_unit_2_to_14.io.credit_available[9] connect switch_allocator.io.req.`0`[0], input_unit_0_from_5.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_12.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_14.io.salloc_req[0] connect output_unit_0_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_5.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_5.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_5.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_5.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_5.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_5.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_5.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_5.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_5.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_5.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_5.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_5.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_5.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_5.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect output_unit_0_to_5.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`0`[8].tail connect output_unit_0_to_5.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`0`[8].alloc connect output_unit_0_to_5.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`0`[9].tail connect output_unit_0_to_5.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`0`[9].alloc connect output_unit_1_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_1_to_12.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail connect output_unit_1_to_12.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc connect output_unit_1_to_12.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail connect output_unit_1_to_12.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc connect output_unit_1_to_12.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`1`[5].tail connect output_unit_1_to_12.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`1`[5].alloc connect output_unit_1_to_12.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`1`[6].tail connect output_unit_1_to_12.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`1`[6].alloc connect output_unit_1_to_12.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`1`[7].tail connect output_unit_1_to_12.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`1`[7].alloc connect output_unit_1_to_12.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`1`[8].tail connect output_unit_1_to_12.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`1`[8].alloc connect output_unit_1_to_12.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`1`[9].tail connect output_unit_1_to_12.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`1`[9].alloc connect output_unit_2_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_14.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_14.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_14.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_14.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect output_unit_2_to_14.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail connect output_unit_2_to_14.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc connect output_unit_2_to_14.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail connect output_unit_2_to_14.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc connect output_unit_2_to_14.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`2`[5].tail connect output_unit_2_to_14.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`2`[5].alloc connect output_unit_2_to_14.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`2`[6].tail connect output_unit_2_to_14.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`2`[6].alloc connect output_unit_2_to_14.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`2`[7].tail connect output_unit_2_to_14.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`2`[7].alloc connect output_unit_2_to_14.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`2`[8].tail connect output_unit_2_to_14.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`2`[8].alloc connect output_unit_2_to_14.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`2`[9].tail connect output_unit_2_to_14.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`2`[9].alloc connect switch.io.in.`0`[0], input_unit_0_from_5.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_12.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_14.io.out[0] connect output_unit_0_to_5.io.in, switch.io.out.`0` connect output_unit_1_to_12.io.in, switch.io.out.`1` connect output_unit_2_to_14.io.in, switch.io.out.`2` reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect input_unit_0_from_5.io.block, UInt<1>(0h0) connect input_unit_1_from_12.io.block, UInt<1>(0h0) connect input_unit_2_from_14.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_5.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_12.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_14.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_5.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_12.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_14.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_138 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 5 13 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 12 13 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 14 13 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid

module Router_60( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [3:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_9; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_9; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_14_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_2_to_14_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_12_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_1_to_12_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_9_occupied; // @[Router.scala:122:13] wire [3:0] _input_unit_2_from_14_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_14_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_14_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_14_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_8; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_14_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_15 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = or(_T_518, _T_523) node _T_525 = and(_T_513, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = and(_T_512, _T_526) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_527, UInt<1>(0h1), "") : assert_2 node _T_531 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h0)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_8) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<1>(0h1)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_9) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h2)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_10) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_550 = shr(io.in.a.bits.source, 2) node _T_551 = eq(_T_550, UInt<2>(0h3)) node _T_552 = leq(UInt<1>(0h0), uncommonBits_11) node _T_553 = and(_T_551, _T_552) node _T_554 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_562 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_563 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_564 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_565 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_566 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_567 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_592 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_531 connect _WIRE[1], _T_537 connect _WIRE[2], _T_543 connect _WIRE[3], _T_549 connect _WIRE[4], _T_555 connect _WIRE[5], _T_556 connect _WIRE[6], _T_557 connect _WIRE[7], _T_558 connect _WIRE[8], _T_559 connect _WIRE[9], _T_560 connect _WIRE[10], _T_561 connect _WIRE[11], _T_562 connect _WIRE[12], _T_563 connect _WIRE[13], _T_564 connect _WIRE[14], _T_565 connect _WIRE[15], _T_566 connect _WIRE[16], _T_567 connect _WIRE[17], _T_568 connect _WIRE[18], _T_569 connect _WIRE[19], _T_570 connect _WIRE[20], _T_571 connect _WIRE[21], _T_572 connect _WIRE[22], _T_573 connect _WIRE[23], _T_574 connect _WIRE[24], _T_575 connect _WIRE[25], _T_576 connect _WIRE[26], _T_577 connect _WIRE[27], _T_578 connect _WIRE[28], _T_579 connect _WIRE[29], _T_580 connect _WIRE[30], _T_581 connect _WIRE[31], _T_582 connect _WIRE[32], _T_583 connect _WIRE[33], _T_584 connect _WIRE[34], _T_585 connect _WIRE[35], _T_586 connect _WIRE[36], _T_587 connect _WIRE[37], _T_588 connect _WIRE[38], _T_589 connect _WIRE[39], _T_590 connect _WIRE[40], _T_591 connect _WIRE[41], _T_592 node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_600 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_601 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_602 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_603 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_604 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_605 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_608 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[5], _T_593, UInt<1>(0h0)) node _T_611 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[8], _T_594, UInt<1>(0h0)) node _T_614 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[11], _T_595, UInt<1>(0h0)) node _T_617 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[14], _T_596, UInt<1>(0h0)) node _T_620 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[17], _T_597, UInt<1>(0h0)) node _T_623 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[20], _T_598, UInt<1>(0h0)) node _T_626 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[23], _T_599, UInt<1>(0h0)) node _T_629 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[26], _T_600, UInt<1>(0h0)) node _T_632 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[29], _T_601, UInt<1>(0h0)) node _T_635 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[32], _T_602, UInt<1>(0h0)) node _T_638 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[35], _T_603, UInt<1>(0h0)) node _T_641 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_642 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_643 = mux(_WIRE[38], _T_604, UInt<1>(0h0)) node _T_644 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_645 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_646 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_647 = or(_T_605, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) node _T_682 = or(_T_681, _T_641) node _T_683 = or(_T_682, _T_642) node _T_684 = or(_T_683, _T_643) node _T_685 = or(_T_684, _T_644) node _T_686 = or(_T_685, _T_645) node _T_687 = or(_T_686, _T_646) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_687 node _T_688 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_689 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_690 = and(_T_688, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<13>(0h1000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<13>(0h1000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = or(_T_696, _T_701) node _T_703 = and(_T_691, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = and(_WIRE_1, _T_704) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_705, UInt<1>(0h1), "") : assert_3 node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(source_ok, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_712 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_712, UInt<1>(0h1), "") : assert_5 node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(is_aligned, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_719 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_719, UInt<1>(0h1), "") : assert_7 node _T_723 = not(io.in.a.bits.mask) node _T_724 = eq(_T_723, UInt<1>(0h0)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_724, UInt<1>(0h1), "") : assert_8 node _T_728 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_728, UInt<1>(0h1), "") : assert_9 node _T_732 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_732 : node _T_733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<1>(0h0)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_12) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<1>(0h1)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_13) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_749 = shr(io.in.a.bits.source, 2) node _T_750 = eq(_T_749, UInt<2>(0h2)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_14) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_755 = shr(io.in.a.bits.source, 2) node _T_756 = eq(_T_755, UInt<2>(0h3)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_15) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_760 = and(_T_758, _T_759) node _T_761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_798 = or(_T_736, _T_742) node _T_799 = or(_T_798, _T_748) node _T_800 = or(_T_799, _T_754) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = or(_T_826, _T_786) node _T_828 = or(_T_827, _T_787) node _T_829 = or(_T_828, _T_788) node _T_830 = or(_T_829, _T_789) node _T_831 = or(_T_830, _T_790) node _T_832 = or(_T_831, _T_791) node _T_833 = or(_T_832, _T_792) node _T_834 = or(_T_833, _T_793) node _T_835 = or(_T_834, _T_794) node _T_836 = or(_T_835, _T_795) node _T_837 = or(_T_836, _T_796) node _T_838 = or(_T_837, _T_797) node _T_839 = and(_T_735, _T_838) node _T_840 = or(UInt<1>(0h0), _T_839) node _T_841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_842 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_843 = cvt(_T_842) node _T_844 = and(_T_843, asSInt(UInt<13>(0h1000))) node _T_845 = asSInt(_T_844) node _T_846 = eq(_T_845, asSInt(UInt<1>(0h0))) node _T_847 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = or(_T_846, _T_851) node _T_853 = and(_T_841, _T_852) node _T_854 = or(UInt<1>(0h0), _T_853) node _T_855 = and(_T_840, _T_854) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_855, UInt<1>(0h1), "") : assert_10 node _T_859 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<1>(0h0)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_16) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_866 = shr(io.in.a.bits.source, 2) node _T_867 = eq(_T_866, UInt<1>(0h1)) node _T_868 = leq(UInt<1>(0h0), uncommonBits_17) node _T_869 = and(_T_867, _T_868) node _T_870 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_871 = and(_T_869, _T_870) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_872 = shr(io.in.a.bits.source, 2) node _T_873 = eq(_T_872, UInt<2>(0h2)) node _T_874 = leq(UInt<1>(0h0), uncommonBits_18) node _T_875 = and(_T_873, _T_874) node _T_876 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_877 = and(_T_875, _T_876) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_878 = shr(io.in.a.bits.source, 2) node _T_879 = eq(_T_878, UInt<2>(0h3)) node _T_880 = leq(UInt<1>(0h0), uncommonBits_19) node _T_881 = and(_T_879, _T_880) node _T_882 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_883 = and(_T_881, _T_882) node _T_884 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_885 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_886 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_887 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_888 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_889 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_890 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_891 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_892 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_893 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_894 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_895 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_902 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_903 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_904 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_911 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_912 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_913 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_914 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_915 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_916 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_917 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_918 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_919 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_920 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_859 connect _WIRE_2[1], _T_865 connect _WIRE_2[2], _T_871 connect _WIRE_2[3], _T_877 connect _WIRE_2[4], _T_883 connect _WIRE_2[5], _T_884 connect _WIRE_2[6], _T_885 connect _WIRE_2[7], _T_886 connect _WIRE_2[8], _T_887 connect _WIRE_2[9], _T_888 connect _WIRE_2[10], _T_889 connect _WIRE_2[11], _T_890 connect _WIRE_2[12], _T_891 connect _WIRE_2[13], _T_892 connect _WIRE_2[14], _T_893 connect _WIRE_2[15], _T_894 connect _WIRE_2[16], _T_895 connect _WIRE_2[17], _T_896 connect _WIRE_2[18], _T_897 connect _WIRE_2[19], _T_898 connect _WIRE_2[20], _T_899 connect _WIRE_2[21], _T_900 connect _WIRE_2[22], _T_901 connect _WIRE_2[23], _T_902 connect _WIRE_2[24], _T_903 connect _WIRE_2[25], _T_904 connect _WIRE_2[26], _T_905 connect _WIRE_2[27], _T_906 connect _WIRE_2[28], _T_907 connect _WIRE_2[29], _T_908 connect _WIRE_2[30], _T_909 connect _WIRE_2[31], _T_910 connect _WIRE_2[32], _T_911 connect _WIRE_2[33], _T_912 connect _WIRE_2[34], _T_913 connect _WIRE_2[35], _T_914 connect _WIRE_2[36], _T_915 connect _WIRE_2[37], _T_916 connect _WIRE_2[38], _T_917 connect _WIRE_2[39], _T_918 connect _WIRE_2[40], _T_919 connect _WIRE_2[41], _T_920 node _T_921 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_922 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_923 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_924 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_925 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_926 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_927 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_928 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_929 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_930 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_931 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_932 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_933 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[5], _T_921, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[8], _T_922, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[11], _T_923, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[14], _T_924, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[17], _T_925, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[20], _T_926, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[23], _T_927, UInt<1>(0h0)) node _T_957 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_958 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_959 = mux(_WIRE_2[26], _T_928, UInt<1>(0h0)) node _T_960 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_961 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_962 = mux(_WIRE_2[29], _T_929, UInt<1>(0h0)) node _T_963 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_964 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_965 = mux(_WIRE_2[32], _T_930, UInt<1>(0h0)) node _T_966 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_967 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_968 = mux(_WIRE_2[35], _T_931, UInt<1>(0h0)) node _T_969 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_970 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_971 = mux(_WIRE_2[38], _T_932, UInt<1>(0h0)) node _T_972 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_973 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_974 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_975 = or(_T_933, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) node _T_998 = or(_T_997, _T_957) node _T_999 = or(_T_998, _T_958) node _T_1000 = or(_T_999, _T_959) node _T_1001 = or(_T_1000, _T_960) node _T_1002 = or(_T_1001, _T_961) node _T_1003 = or(_T_1002, _T_962) node _T_1004 = or(_T_1003, _T_963) node _T_1005 = or(_T_1004, _T_964) node _T_1006 = or(_T_1005, _T_965) node _T_1007 = or(_T_1006, _T_966) node _T_1008 = or(_T_1007, _T_967) node _T_1009 = or(_T_1008, _T_968) node _T_1010 = or(_T_1009, _T_969) node _T_1011 = or(_T_1010, _T_970) node _T_1012 = or(_T_1011, _T_971) node _T_1013 = or(_T_1012, _T_972) node _T_1014 = or(_T_1013, _T_973) node _T_1015 = or(_T_1014, _T_974) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1015 node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1017 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<13>(0h1000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<13>(0h1000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = or(_T_1024, _T_1029) node _T_1031 = and(_T_1019, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = and(_WIRE_3, _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_11 node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(source_ok, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1040 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_13 node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(is_aligned, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1047 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_15 node _T_1051 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_16 node _T_1055 = not(io.in.a.bits.mask) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_17 node _T_1060 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_18 node _T_1064 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1064 : node _T_1065 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1066 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1067 = and(_T_1065, _T_1066) node _T_1068 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1069 = shr(io.in.a.bits.source, 2) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) node _T_1071 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1074 = and(_T_1072, _T_1073) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1075 = shr(io.in.a.bits.source, 2) node _T_1076 = eq(_T_1075, UInt<1>(0h1)) node _T_1077 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1080 = and(_T_1078, _T_1079) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1081 = shr(io.in.a.bits.source, 2) node _T_1082 = eq(_T_1081, UInt<2>(0h2)) node _T_1083 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1086 = and(_T_1084, _T_1085) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<2>(0h3)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1094 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1095 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1096 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1097 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1098 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1099 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1100 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1101 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1102 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1103 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1104 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1125 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1126 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1128 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1129 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1130 = or(_T_1068, _T_1074) node _T_1131 = or(_T_1130, _T_1080) node _T_1132 = or(_T_1131, _T_1086) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = or(_T_1146, _T_1106) node _T_1148 = or(_T_1147, _T_1107) node _T_1149 = or(_T_1148, _T_1108) node _T_1150 = or(_T_1149, _T_1109) node _T_1151 = or(_T_1150, _T_1110) node _T_1152 = or(_T_1151, _T_1111) node _T_1153 = or(_T_1152, _T_1112) node _T_1154 = or(_T_1153, _T_1113) node _T_1155 = or(_T_1154, _T_1114) node _T_1156 = or(_T_1155, _T_1115) node _T_1157 = or(_T_1156, _T_1116) node _T_1158 = or(_T_1157, _T_1117) node _T_1159 = or(_T_1158, _T_1118) node _T_1160 = or(_T_1159, _T_1119) node _T_1161 = or(_T_1160, _T_1120) node _T_1162 = or(_T_1161, _T_1121) node _T_1163 = or(_T_1162, _T_1122) node _T_1164 = or(_T_1163, _T_1123) node _T_1165 = or(_T_1164, _T_1124) node _T_1166 = or(_T_1165, _T_1125) node _T_1167 = or(_T_1166, _T_1126) node _T_1168 = or(_T_1167, _T_1127) node _T_1169 = or(_T_1168, _T_1128) node _T_1170 = or(_T_1169, _T_1129) node _T_1171 = and(_T_1067, _T_1170) node _T_1172 = or(UInt<1>(0h0), _T_1171) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_19 node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1177 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1178 = and(_T_1176, _T_1177) node _T_1179 = or(UInt<1>(0h0), _T_1178) node _T_1180 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1181 = cvt(_T_1180) node _T_1182 = and(_T_1181, asSInt(UInt<13>(0h1000))) node _T_1183 = asSInt(_T_1182) node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0))) node _T_1185 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<13>(0h1000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = or(_T_1184, _T_1189) node _T_1191 = and(_T_1179, _T_1190) node _T_1192 = or(UInt<1>(0h0), _T_1191) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_20 node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(source_ok, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(is_aligned, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1202 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_23 node _T_1206 = eq(io.in.a.bits.mask, mask) node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(_T_1206, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1206, UInt<1>(0h1), "") : assert_24 node _T_1210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_25 node _T_1214 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1214 : node _T_1215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1217 = and(_T_1215, _T_1216) node _T_1218 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1219 = shr(io.in.a.bits.source, 2) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) node _T_1221 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1224 = and(_T_1222, _T_1223) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1225 = shr(io.in.a.bits.source, 2) node _T_1226 = eq(_T_1225, UInt<1>(0h1)) node _T_1227 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1230 = and(_T_1228, _T_1229) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1231 = shr(io.in.a.bits.source, 2) node _T_1232 = eq(_T_1231, UInt<2>(0h2)) node _T_1233 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1236 = and(_T_1234, _T_1235) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1237 = shr(io.in.a.bits.source, 2) node _T_1238 = eq(_T_1237, UInt<2>(0h3)) node _T_1239 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1240 = and(_T_1238, _T_1239) node _T_1241 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1242 = and(_T_1240, _T_1241) node _T_1243 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1244 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1245 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1246 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1247 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1248 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1249 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1250 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1251 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1252 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1253 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1254 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1255 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1256 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1257 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1258 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1259 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1260 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1261 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1262 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1263 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1264 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1265 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1266 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1267 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1268 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1269 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1270 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1271 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1272 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1273 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1274 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1275 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1279 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1280 = or(_T_1218, _T_1224) node _T_1281 = or(_T_1280, _T_1230) node _T_1282 = or(_T_1281, _T_1236) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = or(_T_1290, _T_1250) node _T_1292 = or(_T_1291, _T_1251) node _T_1293 = or(_T_1292, _T_1252) node _T_1294 = or(_T_1293, _T_1253) node _T_1295 = or(_T_1294, _T_1254) node _T_1296 = or(_T_1295, _T_1255) node _T_1297 = or(_T_1296, _T_1256) node _T_1298 = or(_T_1297, _T_1257) node _T_1299 = or(_T_1298, _T_1258) node _T_1300 = or(_T_1299, _T_1259) node _T_1301 = or(_T_1300, _T_1260) node _T_1302 = or(_T_1301, _T_1261) node _T_1303 = or(_T_1302, _T_1262) node _T_1304 = or(_T_1303, _T_1263) node _T_1305 = or(_T_1304, _T_1264) node _T_1306 = or(_T_1305, _T_1265) node _T_1307 = or(_T_1306, _T_1266) node _T_1308 = or(_T_1307, _T_1267) node _T_1309 = or(_T_1308, _T_1268) node _T_1310 = or(_T_1309, _T_1269) node _T_1311 = or(_T_1310, _T_1270) node _T_1312 = or(_T_1311, _T_1271) node _T_1313 = or(_T_1312, _T_1272) node _T_1314 = or(_T_1313, _T_1273) node _T_1315 = or(_T_1314, _T_1274) node _T_1316 = or(_T_1315, _T_1275) node _T_1317 = or(_T_1316, _T_1276) node _T_1318 = or(_T_1317, _T_1277) node _T_1319 = or(_T_1318, _T_1278) node _T_1320 = or(_T_1319, _T_1279) node _T_1321 = and(_T_1217, _T_1320) node _T_1322 = or(UInt<1>(0h0), _T_1321) node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = or(UInt<1>(0h0), _T_1325) node _T_1327 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<13>(0h1000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = or(_T_1331, _T_1336) node _T_1338 = and(_T_1326, _T_1337) node _T_1339 = or(UInt<1>(0h0), _T_1338) node _T_1340 = and(_T_1322, _T_1339) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_26 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(source_ok, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1350 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_29 node _T_1354 = eq(io.in.a.bits.mask, mask) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_30 node _T_1358 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1358 : node _T_1359 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1360 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1361 = and(_T_1359, _T_1360) node _T_1362 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1363 = shr(io.in.a.bits.source, 2) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) node _T_1365 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1366 = and(_T_1364, _T_1365) node _T_1367 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1368 = and(_T_1366, _T_1367) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1369 = shr(io.in.a.bits.source, 2) node _T_1370 = eq(_T_1369, UInt<1>(0h1)) node _T_1371 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1372 = and(_T_1370, _T_1371) node _T_1373 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1374 = and(_T_1372, _T_1373) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1375 = shr(io.in.a.bits.source, 2) node _T_1376 = eq(_T_1375, UInt<2>(0h2)) node _T_1377 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1380 = and(_T_1378, _T_1379) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1381 = shr(io.in.a.bits.source, 2) node _T_1382 = eq(_T_1381, UInt<2>(0h3)) node _T_1383 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1388 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1389 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1390 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1391 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1392 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1393 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1394 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1395 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1396 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1397 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1398 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1399 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1400 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1401 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1402 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1403 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1404 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1405 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1406 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1407 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1408 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1409 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1410 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1423 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1424 = or(_T_1362, _T_1368) node _T_1425 = or(_T_1424, _T_1374) node _T_1426 = or(_T_1425, _T_1380) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = or(_T_1428, _T_1388) node _T_1430 = or(_T_1429, _T_1389) node _T_1431 = or(_T_1430, _T_1390) node _T_1432 = or(_T_1431, _T_1391) node _T_1433 = or(_T_1432, _T_1392) node _T_1434 = or(_T_1433, _T_1393) node _T_1435 = or(_T_1434, _T_1394) node _T_1436 = or(_T_1435, _T_1395) node _T_1437 = or(_T_1436, _T_1396) node _T_1438 = or(_T_1437, _T_1397) node _T_1439 = or(_T_1438, _T_1398) node _T_1440 = or(_T_1439, _T_1399) node _T_1441 = or(_T_1440, _T_1400) node _T_1442 = or(_T_1441, _T_1401) node _T_1443 = or(_T_1442, _T_1402) node _T_1444 = or(_T_1443, _T_1403) node _T_1445 = or(_T_1444, _T_1404) node _T_1446 = or(_T_1445, _T_1405) node _T_1447 = or(_T_1446, _T_1406) node _T_1448 = or(_T_1447, _T_1407) node _T_1449 = or(_T_1448, _T_1408) node _T_1450 = or(_T_1449, _T_1409) node _T_1451 = or(_T_1450, _T_1410) node _T_1452 = or(_T_1451, _T_1411) node _T_1453 = or(_T_1452, _T_1412) node _T_1454 = or(_T_1453, _T_1413) node _T_1455 = or(_T_1454, _T_1414) node _T_1456 = or(_T_1455, _T_1415) node _T_1457 = or(_T_1456, _T_1416) node _T_1458 = or(_T_1457, _T_1417) node _T_1459 = or(_T_1458, _T_1418) node _T_1460 = or(_T_1459, _T_1419) node _T_1461 = or(_T_1460, _T_1420) node _T_1462 = or(_T_1461, _T_1421) node _T_1463 = or(_T_1462, _T_1422) node _T_1464 = or(_T_1463, _T_1423) node _T_1465 = and(_T_1361, _T_1464) node _T_1466 = or(UInt<1>(0h0), _T_1465) node _T_1467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = or(UInt<1>(0h0), _T_1469) node _T_1471 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<13>(0h1000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = or(_T_1475, _T_1480) node _T_1482 = and(_T_1470, _T_1481) node _T_1483 = or(UInt<1>(0h0), _T_1482) node _T_1484 = and(_T_1466, _T_1483) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_31 node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(source_ok, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(is_aligned, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1494 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_34 node _T_1498 = not(mask) node _T_1499 = and(io.in.a.bits.mask, _T_1498) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_35 node _T_1504 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1504 : node _T_1505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1507 = and(_T_1505, _T_1506) node _T_1508 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1509 = shr(io.in.a.bits.source, 2) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) node _T_1511 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1512 = and(_T_1510, _T_1511) node _T_1513 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1514 = and(_T_1512, _T_1513) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1515 = shr(io.in.a.bits.source, 2) node _T_1516 = eq(_T_1515, UInt<1>(0h1)) node _T_1517 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1518 = and(_T_1516, _T_1517) node _T_1519 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1520 = and(_T_1518, _T_1519) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1521 = shr(io.in.a.bits.source, 2) node _T_1522 = eq(_T_1521, UInt<2>(0h2)) node _T_1523 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1524 = and(_T_1522, _T_1523) node _T_1525 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1526 = and(_T_1524, _T_1525) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1527 = shr(io.in.a.bits.source, 2) node _T_1528 = eq(_T_1527, UInt<2>(0h3)) node _T_1529 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1532 = and(_T_1530, _T_1531) node _T_1533 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1534 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1535 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1536 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1537 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1538 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1539 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1540 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1541 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1542 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1543 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1544 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1545 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1546 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1547 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1548 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1549 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1550 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1551 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1552 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1553 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1554 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1555 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1556 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1557 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1558 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1559 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1560 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1561 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1562 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1563 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1565 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1566 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1567 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1568 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1569 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1570 = or(_T_1508, _T_1514) node _T_1571 = or(_T_1570, _T_1520) node _T_1572 = or(_T_1571, _T_1526) node _T_1573 = or(_T_1572, _T_1532) node _T_1574 = or(_T_1573, _T_1533) node _T_1575 = or(_T_1574, _T_1534) node _T_1576 = or(_T_1575, _T_1535) node _T_1577 = or(_T_1576, _T_1536) node _T_1578 = or(_T_1577, _T_1537) node _T_1579 = or(_T_1578, _T_1538) node _T_1580 = or(_T_1579, _T_1539) node _T_1581 = or(_T_1580, _T_1540) node _T_1582 = or(_T_1581, _T_1541) node _T_1583 = or(_T_1582, _T_1542) node _T_1584 = or(_T_1583, _T_1543) node _T_1585 = or(_T_1584, _T_1544) node _T_1586 = or(_T_1585, _T_1545) node _T_1587 = or(_T_1586, _T_1546) node _T_1588 = or(_T_1587, _T_1547) node _T_1589 = or(_T_1588, _T_1548) node _T_1590 = or(_T_1589, _T_1549) node _T_1591 = or(_T_1590, _T_1550) node _T_1592 = or(_T_1591, _T_1551) node _T_1593 = or(_T_1592, _T_1552) node _T_1594 = or(_T_1593, _T_1553) node _T_1595 = or(_T_1594, _T_1554) node _T_1596 = or(_T_1595, _T_1555) node _T_1597 = or(_T_1596, _T_1556) node _T_1598 = or(_T_1597, _T_1557) node _T_1599 = or(_T_1598, _T_1558) node _T_1600 = or(_T_1599, _T_1559) node _T_1601 = or(_T_1600, _T_1560) node _T_1602 = or(_T_1601, _T_1561) node _T_1603 = or(_T_1602, _T_1562) node _T_1604 = or(_T_1603, _T_1563) node _T_1605 = or(_T_1604, _T_1564) node _T_1606 = or(_T_1605, _T_1565) node _T_1607 = or(_T_1606, _T_1566) node _T_1608 = or(_T_1607, _T_1567) node _T_1609 = or(_T_1608, _T_1568) node _T_1610 = or(_T_1609, _T_1569) node _T_1611 = and(_T_1507, _T_1610) node _T_1612 = or(UInt<1>(0h0), _T_1611) node _T_1613 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1614 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1615 = cvt(_T_1614) node _T_1616 = and(_T_1615, asSInt(UInt<13>(0h1000))) node _T_1617 = asSInt(_T_1616) node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) node _T_1619 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1620 = cvt(_T_1619) node _T_1621 = and(_T_1620, asSInt(UInt<13>(0h1000))) node _T_1622 = asSInt(_T_1621) node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) node _T_1624 = or(_T_1618, _T_1623) node _T_1625 = and(_T_1613, _T_1624) node _T_1626 = or(UInt<1>(0h0), _T_1625) node _T_1627 = and(_T_1612, _T_1626) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_36 node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(source_ok, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(is_aligned, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1637 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_39 node _T_1641 = eq(io.in.a.bits.mask, mask) node _T_1642 = asUInt(reset) node _T_1643 = eq(_T_1642, UInt<1>(0h0)) when _T_1643 : node _T_1644 = eq(_T_1641, UInt<1>(0h0)) when _T_1644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1641, UInt<1>(0h1), "") : assert_40 node _T_1645 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1645 : node _T_1646 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1647 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1648 = and(_T_1646, _T_1647) node _T_1649 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1650 = shr(io.in.a.bits.source, 2) node _T_1651 = eq(_T_1650, UInt<1>(0h0)) node _T_1652 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1653 = and(_T_1651, _T_1652) node _T_1654 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1655 = and(_T_1653, _T_1654) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1656 = shr(io.in.a.bits.source, 2) node _T_1657 = eq(_T_1656, UInt<1>(0h1)) node _T_1658 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1661 = and(_T_1659, _T_1660) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1662 = shr(io.in.a.bits.source, 2) node _T_1663 = eq(_T_1662, UInt<2>(0h2)) node _T_1664 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1667 = and(_T_1665, _T_1666) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1668 = shr(io.in.a.bits.source, 2) node _T_1669 = eq(_T_1668, UInt<2>(0h3)) node _T_1670 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1673 = and(_T_1671, _T_1672) node _T_1674 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1675 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1676 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1677 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1678 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1679 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1680 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1681 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1682 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1683 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1684 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1685 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1686 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1687 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1688 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1689 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1690 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1691 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1692 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1693 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1694 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1695 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1696 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1697 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1698 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1699 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1700 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1701 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1702 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1703 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1704 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1705 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1706 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1707 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1708 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1709 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1710 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1711 = or(_T_1649, _T_1655) node _T_1712 = or(_T_1711, _T_1661) node _T_1713 = or(_T_1712, _T_1667) node _T_1714 = or(_T_1713, _T_1673) node _T_1715 = or(_T_1714, _T_1674) node _T_1716 = or(_T_1715, _T_1675) node _T_1717 = or(_T_1716, _T_1676) node _T_1718 = or(_T_1717, _T_1677) node _T_1719 = or(_T_1718, _T_1678) node _T_1720 = or(_T_1719, _T_1679) node _T_1721 = or(_T_1720, _T_1680) node _T_1722 = or(_T_1721, _T_1681) node _T_1723 = or(_T_1722, _T_1682) node _T_1724 = or(_T_1723, _T_1683) node _T_1725 = or(_T_1724, _T_1684) node _T_1726 = or(_T_1725, _T_1685) node _T_1727 = or(_T_1726, _T_1686) node _T_1728 = or(_T_1727, _T_1687) node _T_1729 = or(_T_1728, _T_1688) node _T_1730 = or(_T_1729, _T_1689) node _T_1731 = or(_T_1730, _T_1690) node _T_1732 = or(_T_1731, _T_1691) node _T_1733 = or(_T_1732, _T_1692) node _T_1734 = or(_T_1733, _T_1693) node _T_1735 = or(_T_1734, _T_1694) node _T_1736 = or(_T_1735, _T_1695) node _T_1737 = or(_T_1736, _T_1696) node _T_1738 = or(_T_1737, _T_1697) node _T_1739 = or(_T_1738, _T_1698) node _T_1740 = or(_T_1739, _T_1699) node _T_1741 = or(_T_1740, _T_1700) node _T_1742 = or(_T_1741, _T_1701) node _T_1743 = or(_T_1742, _T_1702) node _T_1744 = or(_T_1743, _T_1703) node _T_1745 = or(_T_1744, _T_1704) node _T_1746 = or(_T_1745, _T_1705) node _T_1747 = or(_T_1746, _T_1706) node _T_1748 = or(_T_1747, _T_1707) node _T_1749 = or(_T_1748, _T_1708) node _T_1750 = or(_T_1749, _T_1709) node _T_1751 = or(_T_1750, _T_1710) node _T_1752 = and(_T_1648, _T_1751) node _T_1753 = or(UInt<1>(0h0), _T_1752) node _T_1754 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1755 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1756 = cvt(_T_1755) node _T_1757 = and(_T_1756, asSInt(UInt<13>(0h1000))) node _T_1758 = asSInt(_T_1757) node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0))) node _T_1760 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1761 = cvt(_T_1760) node _T_1762 = and(_T_1761, asSInt(UInt<13>(0h1000))) node _T_1763 = asSInt(_T_1762) node _T_1764 = eq(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = or(_T_1759, _T_1764) node _T_1766 = and(_T_1754, _T_1765) node _T_1767 = or(UInt<1>(0h0), _T_1766) node _T_1768 = and(_T_1753, _T_1767) node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(_T_1768, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1768, UInt<1>(0h1), "") : assert_41 node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(source_ok, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1775 = asUInt(reset) node _T_1776 = eq(_T_1775, UInt<1>(0h0)) when _T_1776 : node _T_1777 = eq(is_aligned, UInt<1>(0h0)) when _T_1777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1778 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_44 node _T_1782 = eq(io.in.a.bits.mask, mask) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_45 node _T_1786 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1786 : node _T_1787 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1788 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1789 = and(_T_1787, _T_1788) node _T_1790 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1791 = shr(io.in.a.bits.source, 2) node _T_1792 = eq(_T_1791, UInt<1>(0h0)) node _T_1793 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1794 = and(_T_1792, _T_1793) node _T_1795 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1796 = and(_T_1794, _T_1795) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1797 = shr(io.in.a.bits.source, 2) node _T_1798 = eq(_T_1797, UInt<1>(0h1)) node _T_1799 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1800 = and(_T_1798, _T_1799) node _T_1801 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1802 = and(_T_1800, _T_1801) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1803 = shr(io.in.a.bits.source, 2) node _T_1804 = eq(_T_1803, UInt<2>(0h2)) node _T_1805 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1806 = and(_T_1804, _T_1805) node _T_1807 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1808 = and(_T_1806, _T_1807) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1809 = shr(io.in.a.bits.source, 2) node _T_1810 = eq(_T_1809, UInt<2>(0h3)) node _T_1811 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1812 = and(_T_1810, _T_1811) node _T_1813 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1814 = and(_T_1812, _T_1813) node _T_1815 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1816 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1817 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1818 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1819 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1820 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1821 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1822 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1823 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1824 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1825 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1826 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1827 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1828 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1829 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1830 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1831 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1832 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1833 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1834 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1835 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1836 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1837 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1838 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1839 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1840 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1841 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1842 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1843 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1844 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1845 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1846 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1847 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1848 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1849 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1850 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1851 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1852 = or(_T_1790, _T_1796) node _T_1853 = or(_T_1852, _T_1802) node _T_1854 = or(_T_1853, _T_1808) node _T_1855 = or(_T_1854, _T_1814) node _T_1856 = or(_T_1855, _T_1815) node _T_1857 = or(_T_1856, _T_1816) node _T_1858 = or(_T_1857, _T_1817) node _T_1859 = or(_T_1858, _T_1818) node _T_1860 = or(_T_1859, _T_1819) node _T_1861 = or(_T_1860, _T_1820) node _T_1862 = or(_T_1861, _T_1821) node _T_1863 = or(_T_1862, _T_1822) node _T_1864 = or(_T_1863, _T_1823) node _T_1865 = or(_T_1864, _T_1824) node _T_1866 = or(_T_1865, _T_1825) node _T_1867 = or(_T_1866, _T_1826) node _T_1868 = or(_T_1867, _T_1827) node _T_1869 = or(_T_1868, _T_1828) node _T_1870 = or(_T_1869, _T_1829) node _T_1871 = or(_T_1870, _T_1830) node _T_1872 = or(_T_1871, _T_1831) node _T_1873 = or(_T_1872, _T_1832) node _T_1874 = or(_T_1873, _T_1833) node _T_1875 = or(_T_1874, _T_1834) node _T_1876 = or(_T_1875, _T_1835) node _T_1877 = or(_T_1876, _T_1836) node _T_1878 = or(_T_1877, _T_1837) node _T_1879 = or(_T_1878, _T_1838) node _T_1880 = or(_T_1879, _T_1839) node _T_1881 = or(_T_1880, _T_1840) node _T_1882 = or(_T_1881, _T_1841) node _T_1883 = or(_T_1882, _T_1842) node _T_1884 = or(_T_1883, _T_1843) node _T_1885 = or(_T_1884, _T_1844) node _T_1886 = or(_T_1885, _T_1845) node _T_1887 = or(_T_1886, _T_1846) node _T_1888 = or(_T_1887, _T_1847) node _T_1889 = or(_T_1888, _T_1848) node _T_1890 = or(_T_1889, _T_1849) node _T_1891 = or(_T_1890, _T_1850) node _T_1892 = or(_T_1891, _T_1851) node _T_1893 = and(_T_1789, _T_1892) node _T_1894 = or(UInt<1>(0h0), _T_1893) node _T_1895 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1896 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1897 = cvt(_T_1896) node _T_1898 = and(_T_1897, asSInt(UInt<13>(0h1000))) node _T_1899 = asSInt(_T_1898) node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = or(_T_1900, _T_1905) node _T_1907 = and(_T_1895, _T_1906) node _T_1908 = or(UInt<1>(0h0), _T_1907) node _T_1909 = and(_T_1894, _T_1908) node _T_1910 = asUInt(reset) node _T_1911 = eq(_T_1910, UInt<1>(0h0)) when _T_1911 : node _T_1912 = eq(_T_1909, UInt<1>(0h0)) when _T_1912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1909, UInt<1>(0h1), "") : assert_46 node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(source_ok, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(is_aligned, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1919 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_49 node _T_1923 = eq(io.in.a.bits.mask, mask) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_50 node _T_1927 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1928 = asUInt(reset) node _T_1929 = eq(_T_1928, UInt<1>(0h0)) when _T_1929 : node _T_1930 = eq(_T_1927, UInt<1>(0h0)) when _T_1930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1927, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1931 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1932 = asUInt(reset) node _T_1933 = eq(_T_1932, UInt<1>(0h0)) when _T_1933 : node _T_1934 = eq(_T_1931, UInt<1>(0h0)) when _T_1934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1931, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1935 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1935 : node _T_1936 = asUInt(reset) node _T_1937 = eq(_T_1936, UInt<1>(0h0)) when _T_1937 : node _T_1938 = eq(source_ok_1, UInt<1>(0h0)) when _T_1938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1939 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_54 node _T_1943 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_55 node _T_1947 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1948 = asUInt(reset) node _T_1949 = eq(_T_1948, UInt<1>(0h0)) when _T_1949 : node _T_1950 = eq(_T_1947, UInt<1>(0h0)) when _T_1950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1947, UInt<1>(0h1), "") : assert_56 node _T_1951 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1952 = asUInt(reset) node _T_1953 = eq(_T_1952, UInt<1>(0h0)) when _T_1953 : node _T_1954 = eq(_T_1951, UInt<1>(0h0)) when _T_1954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1951, UInt<1>(0h1), "") : assert_57 node _T_1955 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1955 : node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(source_ok_1, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(sink_ok, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1962 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_60 node _T_1966 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(_T_1966, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1966, UInt<1>(0h1), "") : assert_61 node _T_1970 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1971 = asUInt(reset) node _T_1972 = eq(_T_1971, UInt<1>(0h0)) when _T_1972 : node _T_1973 = eq(_T_1970, UInt<1>(0h0)) when _T_1973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1970, UInt<1>(0h1), "") : assert_62 node _T_1974 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1975 = asUInt(reset) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : node _T_1977 = eq(_T_1974, UInt<1>(0h0)) when _T_1977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1974, UInt<1>(0h1), "") : assert_63 node _T_1978 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1979 = or(UInt<1>(0h0), _T_1978) node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(_T_1979, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1979, UInt<1>(0h1), "") : assert_64 node _T_1983 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1983 : node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(source_ok_1, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1987 = asUInt(reset) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) when _T_1988 : node _T_1989 = eq(sink_ok, UInt<1>(0h0)) when _T_1989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(_T_1990, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1990, UInt<1>(0h1), "") : assert_67 node _T_1994 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_68 node _T_1998 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_69 node _T_2002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2003 = or(_T_2002, io.in.d.bits.corrupt) node _T_2004 = asUInt(reset) node _T_2005 = eq(_T_2004, UInt<1>(0h0)) when _T_2005 : node _T_2006 = eq(_T_2003, UInt<1>(0h0)) when _T_2006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2003, UInt<1>(0h1), "") : assert_70 node _T_2007 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2008 = or(UInt<1>(0h0), _T_2007) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_71 node _T_2012 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2012 : node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(source_ok_1, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2016 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_73 node _T_2020 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_74 node _T_2024 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = asUInt(reset) node _T_2027 = eq(_T_2026, UInt<1>(0h0)) when _T_2027 : node _T_2028 = eq(_T_2025, UInt<1>(0h0)) when _T_2028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2025, UInt<1>(0h1), "") : assert_75 node _T_2029 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2029 : node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_1, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2033 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_77 node _T_2037 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2038 = or(_T_2037, io.in.d.bits.corrupt) node _T_2039 = asUInt(reset) node _T_2040 = eq(_T_2039, UInt<1>(0h0)) when _T_2040 : node _T_2041 = eq(_T_2038, UInt<1>(0h0)) when _T_2041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2038, UInt<1>(0h1), "") : assert_78 node _T_2042 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2043 = or(UInt<1>(0h0), _T_2042) node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(_T_2043, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2043, UInt<1>(0h1), "") : assert_79 node _T_2047 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2047 : node _T_2048 = asUInt(reset) node _T_2049 = eq(_T_2048, UInt<1>(0h0)) when _T_2049 : node _T_2050 = eq(source_ok_1, UInt<1>(0h0)) when _T_2050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2051 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2052 = asUInt(reset) node _T_2053 = eq(_T_2052, UInt<1>(0h0)) when _T_2053 : node _T_2054 = eq(_T_2051, UInt<1>(0h0)) when _T_2054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2051, UInt<1>(0h1), "") : assert_81 node _T_2055 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2056 = asUInt(reset) node _T_2057 = eq(_T_2056, UInt<1>(0h0)) when _T_2057 : node _T_2058 = eq(_T_2055, UInt<1>(0h0)) when _T_2058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2055, UInt<1>(0h1), "") : assert_82 node _T_2059 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2060 = or(UInt<1>(0h0), _T_2059) node _T_2061 = asUInt(reset) node _T_2062 = eq(_T_2061, UInt<1>(0h0)) when _T_2062 : node _T_2063 = eq(_T_2060, UInt<1>(0h0)) when _T_2063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2060, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2064 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2065 = asUInt(reset) node _T_2066 = eq(_T_2065, UInt<1>(0h0)) when _T_2066 : node _T_2067 = eq(_T_2064, UInt<1>(0h0)) when _T_2067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2064, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2068 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2069 = asUInt(reset) node _T_2070 = eq(_T_2069, UInt<1>(0h0)) when _T_2070 : node _T_2071 = eq(_T_2068, UInt<1>(0h0)) when _T_2071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2068, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2072 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2073 = asUInt(reset) node _T_2074 = eq(_T_2073, UInt<1>(0h0)) when _T_2074 : node _T_2075 = eq(_T_2072, UInt<1>(0h0)) when _T_2075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2072, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2076 = eq(a_first, UInt<1>(0h0)) node _T_2077 = and(io.in.a.valid, _T_2076) when _T_2077 : node _T_2078 = eq(io.in.a.bits.opcode, opcode) node _T_2079 = asUInt(reset) node _T_2080 = eq(_T_2079, UInt<1>(0h0)) when _T_2080 : node _T_2081 = eq(_T_2078, UInt<1>(0h0)) when _T_2081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2078, UInt<1>(0h1), "") : assert_87 node _T_2082 = eq(io.in.a.bits.param, param) node _T_2083 = asUInt(reset) node _T_2084 = eq(_T_2083, UInt<1>(0h0)) when _T_2084 : node _T_2085 = eq(_T_2082, UInt<1>(0h0)) when _T_2085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2082, UInt<1>(0h1), "") : assert_88 node _T_2086 = eq(io.in.a.bits.size, size) node _T_2087 = asUInt(reset) node _T_2088 = eq(_T_2087, UInt<1>(0h0)) when _T_2088 : node _T_2089 = eq(_T_2086, UInt<1>(0h0)) when _T_2089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2086, UInt<1>(0h1), "") : assert_89 node _T_2090 = eq(io.in.a.bits.source, source) node _T_2091 = asUInt(reset) node _T_2092 = eq(_T_2091, UInt<1>(0h0)) when _T_2092 : node _T_2093 = eq(_T_2090, UInt<1>(0h0)) when _T_2093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2090, UInt<1>(0h1), "") : assert_90 node _T_2094 = eq(io.in.a.bits.address, address) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_91 node _T_2098 = and(io.in.a.ready, io.in.a.valid) node _T_2099 = and(_T_2098, a_first) when _T_2099 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2100 = eq(d_first, UInt<1>(0h0)) node _T_2101 = and(io.in.d.valid, _T_2100) when _T_2101 : node _T_2102 = eq(io.in.d.bits.opcode, opcode_1) node _T_2103 = asUInt(reset) node _T_2104 = eq(_T_2103, UInt<1>(0h0)) when _T_2104 : node _T_2105 = eq(_T_2102, UInt<1>(0h0)) when _T_2105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2102, UInt<1>(0h1), "") : assert_92 node _T_2106 = eq(io.in.d.bits.param, param_1) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_93 node _T_2110 = eq(io.in.d.bits.size, size_1) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_94 node _T_2114 = eq(io.in.d.bits.source, source_1) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_95 node _T_2118 = eq(io.in.d.bits.sink, sink) node _T_2119 = asUInt(reset) node _T_2120 = eq(_T_2119, UInt<1>(0h0)) when _T_2120 : node _T_2121 = eq(_T_2118, UInt<1>(0h0)) when _T_2121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2118, UInt<1>(0h1), "") : assert_96 node _T_2122 = eq(io.in.d.bits.denied, denied) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_97 node _T_2126 = and(io.in.d.ready, io.in.d.valid) node _T_2127 = and(_T_2126, d_first) when _T_2127 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2128 = and(io.in.a.valid, a_first_1) node _T_2129 = and(_T_2128, UInt<1>(0h1)) when _T_2129 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2130 = and(io.in.a.ready, io.in.a.valid) node _T_2131 = and(_T_2130, a_first_1) node _T_2132 = and(_T_2131, UInt<1>(0h1)) when _T_2132 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2133 = dshr(inflight, io.in.a.bits.source) node _T_2134 = bits(_T_2133, 0, 0) node _T_2135 = eq(_T_2134, UInt<1>(0h0)) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2139 = and(io.in.d.valid, d_first_1) node _T_2140 = and(_T_2139, UInt<1>(0h1)) node _T_2141 = eq(d_release_ack, UInt<1>(0h0)) node _T_2142 = and(_T_2140, _T_2141) when _T_2142 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2143 = and(io.in.d.ready, io.in.d.valid) node _T_2144 = and(_T_2143, d_first_1) node _T_2145 = and(_T_2144, UInt<1>(0h1)) node _T_2146 = eq(d_release_ack, UInt<1>(0h0)) node _T_2147 = and(_T_2145, _T_2146) when _T_2147 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2148 = and(io.in.d.valid, d_first_1) node _T_2149 = and(_T_2148, UInt<1>(0h1)) node _T_2150 = eq(d_release_ack, UInt<1>(0h0)) node _T_2151 = and(_T_2149, _T_2150) when _T_2151 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2152 = dshr(inflight, io.in.d.bits.source) node _T_2153 = bits(_T_2152, 0, 0) node _T_2154 = or(_T_2153, same_cycle_resp) node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(_T_2154, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2154, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2158 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2159 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2160 = or(_T_2158, _T_2159) node _T_2161 = asUInt(reset) node _T_2162 = eq(_T_2161, UInt<1>(0h0)) when _T_2162 : node _T_2163 = eq(_T_2160, UInt<1>(0h0)) when _T_2163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2160, UInt<1>(0h1), "") : assert_100 node _T_2164 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(_T_2164, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2164, UInt<1>(0h1), "") : assert_101 else : node _T_2168 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2169 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2170 = or(_T_2168, _T_2169) node _T_2171 = asUInt(reset) node _T_2172 = eq(_T_2171, UInt<1>(0h0)) when _T_2172 : node _T_2173 = eq(_T_2170, UInt<1>(0h0)) when _T_2173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2170, UInt<1>(0h1), "") : assert_102 node _T_2174 = eq(io.in.d.bits.size, a_size_lookup) node _T_2175 = asUInt(reset) node _T_2176 = eq(_T_2175, UInt<1>(0h0)) when _T_2176 : node _T_2177 = eq(_T_2174, UInt<1>(0h0)) when _T_2177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2174, UInt<1>(0h1), "") : assert_103 node _T_2178 = and(io.in.d.valid, d_first_1) node _T_2179 = and(_T_2178, a_first_1) node _T_2180 = and(_T_2179, io.in.a.valid) node _T_2181 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2182 = and(_T_2180, _T_2181) node _T_2183 = eq(d_release_ack, UInt<1>(0h0)) node _T_2184 = and(_T_2182, _T_2183) when _T_2184 : node _T_2185 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2186 = or(_T_2185, io.in.a.ready) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_62 node _T_2190 = orr(inflight) node _T_2191 = eq(_T_2190, UInt<1>(0h0)) node _T_2192 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2193 = or(_T_2191, _T_2192) node _T_2194 = lt(watchdog, plusarg_reader.out) node _T_2195 = or(_T_2193, _T_2194) node _T_2196 = asUInt(reset) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) when _T_2197 : node _T_2198 = eq(_T_2195, UInt<1>(0h0)) when _T_2198 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2195, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2199 = and(io.in.a.ready, io.in.a.valid) node _T_2200 = and(io.in.d.ready, io.in.d.valid) node _T_2201 = or(_T_2199, _T_2200) when _T_2201 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2202 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2203 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2204 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2205 = and(_T_2203, _T_2204) node _T_2206 = and(_T_2202, _T_2205) when _T_2206 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2207 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2208 = and(_T_2207, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2209 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2210 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2211 = and(_T_2209, _T_2210) node _T_2212 = and(_T_2208, _T_2211) when _T_2212 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2213 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2214 = bits(_T_2213, 0, 0) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2219 = and(io.in.d.valid, d_first_2) node _T_2220 = and(_T_2219, UInt<1>(0h1)) node _T_2221 = and(_T_2220, d_release_ack_1) when _T_2221 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2222 = and(io.in.d.ready, io.in.d.valid) node _T_2223 = and(_T_2222, d_first_2) node _T_2224 = and(_T_2223, UInt<1>(0h1)) node _T_2225 = and(_T_2224, d_release_ack_1) when _T_2225 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2226 = and(io.in.d.valid, d_first_2) node _T_2227 = and(_T_2226, UInt<1>(0h1)) node _T_2228 = and(_T_2227, d_release_ack_1) when _T_2228 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2229 = dshr(inflight_1, io.in.d.bits.source) node _T_2230 = bits(_T_2229, 0, 0) node _T_2231 = or(_T_2230, same_cycle_resp_1) node _T_2232 = asUInt(reset) node _T_2233 = eq(_T_2232, UInt<1>(0h0)) when _T_2233 : node _T_2234 = eq(_T_2231, UInt<1>(0h0)) when _T_2234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2231, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2235 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2236 = asUInt(reset) node _T_2237 = eq(_T_2236, UInt<1>(0h0)) when _T_2237 : node _T_2238 = eq(_T_2235, UInt<1>(0h0)) when _T_2238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2235, UInt<1>(0h1), "") : assert_108 else : node _T_2239 = eq(io.in.d.bits.size, c_size_lookup) node _T_2240 = asUInt(reset) node _T_2241 = eq(_T_2240, UInt<1>(0h0)) when _T_2241 : node _T_2242 = eq(_T_2239, UInt<1>(0h0)) when _T_2242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2239, UInt<1>(0h1), "") : assert_109 node _T_2243 = and(io.in.d.valid, d_first_2) node _T_2244 = and(_T_2243, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2245 = and(_T_2244, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2246 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2247 = and(_T_2245, _T_2246) node _T_2248 = and(_T_2247, d_release_ack_1) node _T_2249 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2250 = and(_T_2248, _T_2249) when _T_2250 : node _T_2251 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2252 = or(_T_2251, _WIRE_27.ready) node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(_T_2252, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2252, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_63 node _T_2256 = orr(inflight_1) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) node _T_2258 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2259 = or(_T_2257, _T_2258) node _T_2260 = lt(watchdog_1, plusarg_reader_1.out) node _T_2261 = or(_T_2259, _T_2260) node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : node _T_2264 = eq(_T_2261, UInt<1>(0h0)) when _T_2264 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2261, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2265 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2266 = and(io.in.d.ready, io.in.d.valid) node _T_2267 = or(_T_2265, _T_2266) when _T_2267 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module LoopMatmulStC : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { max_k : UInt<16>, max_j : UInt<16>, max_i : UInt<16>, pad_j : UInt<2>, pad_i : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, full_c : UInt<1>, act : UInt<3>, addr_start : UInt<12>, loop_id : UInt<1>, is_resadd : UInt<1>}}, cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, flip ex_k : UInt<16>, flip ex_j : UInt<16>, flip ex_i : UInt<16>, flip ex_completed : UInt<1>, j : UInt<16>, i : UInt<16>, idle : UInt<1>, flip rob_overloaded : UInt<1>, loop_id : UInt<1>} regreset state : UInt<2>, clock, reset, UInt<1>(0h0) reg req : { max_k : UInt<16>, max_j : UInt<16>, max_i : UInt<16>, pad_j : UInt<2>, pad_i : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, full_c : UInt<1>, act : UInt<3>, addr_start : UInt<12>, loop_id : UInt<1>, is_resadd : UInt<1>}, clock node _max_blocks_T = leq(req.max_j, UInt<3>(0h4)) node _max_blocks_T_1 = mux(_max_blocks_T, req.max_j, UInt<3>(0h4)) node max_blocks = mux(req.full_c, UInt<1>(0h1), _max_blocks_T_1) reg j : UInt<16>, clock reg i : UInt<16>, clock node _dram_offset_T = mul(i, req.dram_stride) node _dram_offset_T_1 = add(_dram_offset_T, j) node _dram_offset_T_2 = tail(_dram_offset_T_1, 1) node _dram_offset_T_3 = mul(_dram_offset_T_2, UInt<3>(0h4)) node _dram_offset_T_4 = mul(_dram_offset_T_3, UInt<3>(0h4)) node _dram_offset_T_5 = mul(i, req.dram_stride) node _dram_offset_T_6 = add(_dram_offset_T_5, j) node _dram_offset_T_7 = tail(_dram_offset_T_6, 1) node _dram_offset_T_8 = mul(_dram_offset_T_7, UInt<3>(0h4)) node _dram_offset_T_9 = mul(_dram_offset_T_8, UInt<3>(0h4)) node dram_offset = mux(req.full_c, _dram_offset_T_4, _dram_offset_T_9) node _dram_addr_T = and(dram_offset, UInt<32>(0hffffffff)) node _dram_addr_T_1 = add(req.dram_addr, _dram_addr_T) node dram_addr = tail(_dram_addr_T_1, 1) node _sp_addr_T = mul(i, req.max_j) node _sp_addr_T_1 = add(_sp_addr_T, j) node _sp_addr_T_2 = tail(_sp_addr_T_1, 1) node _sp_addr_T_3 = mul(_sp_addr_T_2, UInt<3>(0h4)) node _sp_addr_T_4 = add(req.addr_start, _sp_addr_T_3) node sp_addr = tail(_sp_addr_T_4, 1) node _blocks_T = add(j, max_blocks) node _blocks_T_1 = tail(_blocks_T, 1) node _blocks_T_2 = leq(_blocks_T_1, req.max_j) node _blocks_T_3 = sub(req.max_j, j) node _blocks_T_4 = tail(_blocks_T_3, 1) node blocks = mux(_blocks_T_2, max_blocks, _blocks_T_4) node _cols_T = mul(blocks, UInt<3>(0h4)) node _cols_T_1 = add(j, blocks) node _cols_T_2 = tail(_cols_T_1, 1) node _cols_T_3 = geq(_cols_T_2, req.max_j) node _cols_T_4 = mux(_cols_T_3, req.pad_j, UInt<1>(0h0)) node _cols_T_5 = sub(_cols_T, _cols_T_4) node cols = tail(_cols_T_5, 1) node _rows_T = sub(req.max_i, UInt<1>(0h1)) node _rows_T_1 = tail(_rows_T, 1) node _rows_T_2 = eq(i, _rows_T_1) node _rows_T_3 = mux(_rows_T_2, req.pad_i, UInt<1>(0h0)) node _rows_T_4 = sub(UInt<3>(0h4), _rows_T_3) node rows = tail(_rows_T_4, 1) wire mvout_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate mvout_cmd.status.uie invalidate mvout_cmd.status.sie invalidate mvout_cmd.status.hie invalidate mvout_cmd.status.mie invalidate mvout_cmd.status.upie invalidate mvout_cmd.status.spie invalidate mvout_cmd.status.ube invalidate mvout_cmd.status.mpie invalidate mvout_cmd.status.spp invalidate mvout_cmd.status.vs invalidate mvout_cmd.status.mpp invalidate mvout_cmd.status.fs invalidate mvout_cmd.status.xs invalidate mvout_cmd.status.mprv invalidate mvout_cmd.status.sum invalidate mvout_cmd.status.mxr invalidate mvout_cmd.status.tvm invalidate mvout_cmd.status.tw invalidate mvout_cmd.status.tsr invalidate mvout_cmd.status.zero1 invalidate mvout_cmd.status.sd_rv32 invalidate mvout_cmd.status.uxl invalidate mvout_cmd.status.sxl invalidate mvout_cmd.status.sbe invalidate mvout_cmd.status.mbe invalidate mvout_cmd.status.gva invalidate mvout_cmd.status.mpv invalidate mvout_cmd.status.zero2 invalidate mvout_cmd.status.sd invalidate mvout_cmd.status.v invalidate mvout_cmd.status.prv invalidate mvout_cmd.status.dv invalidate mvout_cmd.status.dprv invalidate mvout_cmd.status.isa invalidate mvout_cmd.status.wfi invalidate mvout_cmd.status.cease invalidate mvout_cmd.status.debug invalidate mvout_cmd.rs2 invalidate mvout_cmd.rs1 invalidate mvout_cmd.inst.opcode invalidate mvout_cmd.inst.rd invalidate mvout_cmd.inst.xs2 invalidate mvout_cmd.inst.xs1 invalidate mvout_cmd.inst.xd invalidate mvout_cmd.inst.rs1 invalidate mvout_cmd.inst.rs2 invalidate mvout_cmd.inst.funct connect mvout_cmd.inst.funct, UInt<2>(0h3) connect mvout_cmd.rs1, dram_addr wire mvout_cmd_rs2 : { _spacer2 : UInt<13>, num_rows : UInt<3>, _spacer1 : UInt<11>, num_cols : UInt<5>, _spacer0 : UInt<0>, local_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}} invalidate mvout_cmd_rs2.local_addr.data invalidate mvout_cmd_rs2.local_addr.garbage_bit invalidate mvout_cmd_rs2.local_addr.garbage invalidate mvout_cmd_rs2.local_addr.norm_cmd invalidate mvout_cmd_rs2.local_addr.read_full_acc_row invalidate mvout_cmd_rs2.local_addr.accumulate invalidate mvout_cmd_rs2.local_addr.is_acc_addr invalidate mvout_cmd_rs2._spacer0 invalidate mvout_cmd_rs2.num_cols invalidate mvout_cmd_rs2._spacer1 invalidate mvout_cmd_rs2.num_rows invalidate mvout_cmd_rs2._spacer2 connect mvout_cmd_rs2.num_rows, rows connect mvout_cmd_rs2.num_cols, cols wire _mvout_cmd_rs2_local_addr_result_result_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _mvout_cmd_rs2_local_addr_result_result_WIRE_1 : UInt<32> connect _mvout_cmd_rs2_local_addr_result_result_WIRE_1, sp_addr node _mvout_cmd_rs2_local_addr_result_result_T = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 13, 0) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.data, _mvout_cmd_rs2_local_addr_result_result_T node _mvout_cmd_rs2_local_addr_result_result_T_1 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 14, 14) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.garbage_bit, _mvout_cmd_rs2_local_addr_result_result_T_1 node _mvout_cmd_rs2_local_addr_result_result_T_2 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 25, 15) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.garbage, _mvout_cmd_rs2_local_addr_result_result_T_2 node _mvout_cmd_rs2_local_addr_result_result_T_3 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 28, 26) wire _mvout_cmd_rs2_local_addr_result_result_WIRE_2 : UInt<3> connect _mvout_cmd_rs2_local_addr_result_result_WIRE_2, _mvout_cmd_rs2_local_addr_result_result_T_3 wire _mvout_cmd_rs2_local_addr_result_result_WIRE_3 : UInt<3> connect _mvout_cmd_rs2_local_addr_result_result_WIRE_3, _mvout_cmd_rs2_local_addr_result_result_WIRE_2 connect _mvout_cmd_rs2_local_addr_result_result_WIRE.norm_cmd, _mvout_cmd_rs2_local_addr_result_result_WIRE_3 node _mvout_cmd_rs2_local_addr_result_result_T_4 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 29, 29) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.read_full_acc_row, _mvout_cmd_rs2_local_addr_result_result_T_4 node _mvout_cmd_rs2_local_addr_result_result_T_5 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 30, 30) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.accumulate, _mvout_cmd_rs2_local_addr_result_result_T_5 node _mvout_cmd_rs2_local_addr_result_result_T_6 = bits(_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 31, 31) connect _mvout_cmd_rs2_local_addr_result_result_WIRE.is_acc_addr, _mvout_cmd_rs2_local_addr_result_result_T_6 wire mvout_cmd_rs2_local_addr_result_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvout_cmd_rs2_local_addr_result_result, _mvout_cmd_rs2_local_addr_result_result_WIRE connect mvout_cmd_rs2_local_addr_result_result.garbage, UInt<1>(0h0) wire mvout_cmd_rs2_local_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvout_cmd_rs2_local_addr_result, mvout_cmd_rs2_local_addr_result_result connect mvout_cmd_rs2_local_addr_result.is_acc_addr, UInt<1>(0h1) connect mvout_cmd_rs2_local_addr_result.accumulate, UInt<1>(0h0) connect mvout_cmd_rs2_local_addr_result.read_full_acc_row, req.full_c connect mvout_cmd_rs2.local_addr, mvout_cmd_rs2_local_addr_result node _mvout_cmd_rs2_T = asUInt(mvout_cmd_rs2.local_addr.norm_cmd) node mvout_cmd_rs2_lo_hi = cat(mvout_cmd_rs2.local_addr.garbage, mvout_cmd_rs2.local_addr.garbage_bit) node mvout_cmd_rs2_lo = cat(mvout_cmd_rs2_lo_hi, mvout_cmd_rs2.local_addr.data) node mvout_cmd_rs2_hi_lo = cat(mvout_cmd_rs2.local_addr.read_full_acc_row, _mvout_cmd_rs2_T) node mvout_cmd_rs2_hi_hi = cat(mvout_cmd_rs2.local_addr.is_acc_addr, mvout_cmd_rs2.local_addr.accumulate) node mvout_cmd_rs2_hi = cat(mvout_cmd_rs2_hi_hi, mvout_cmd_rs2_hi_lo) node _mvout_cmd_rs2_T_1 = cat(mvout_cmd_rs2_hi, mvout_cmd_rs2_lo) node mvout_cmd_rs2_lo_hi_1 = cat(mvout_cmd_rs2.num_cols, mvout_cmd_rs2._spacer0) node mvout_cmd_rs2_lo_1 = cat(mvout_cmd_rs2_lo_hi_1, _mvout_cmd_rs2_T_1) node mvout_cmd_rs2_hi_hi_1 = cat(mvout_cmd_rs2._spacer2, mvout_cmd_rs2.num_rows) node mvout_cmd_rs2_hi_1 = cat(mvout_cmd_rs2_hi_hi_1, mvout_cmd_rs2._spacer1) node _mvout_cmd_rs2_T_2 = cat(mvout_cmd_rs2_hi_1, mvout_cmd_rs2_lo_1) connect mvout_cmd.rs2, _mvout_cmd_rs2_T_2 reg ln_row : UInt<16>, clock reg ln_cmd : UInt<16>, clock reg ln_stat_id : UInt<16>, clock wire _ln_norm_cmds_WIRE : UInt<3>[2] connect _ln_norm_cmds_WIRE[0], UInt<1>(0h1) connect _ln_norm_cmds_WIRE[1], UInt<2>(0h2) wire _ln_norm_cmds_WIRE_1 : UInt<3>[2] connect _ln_norm_cmds_WIRE_1[0], UInt<2>(0h3) connect _ln_norm_cmds_WIRE_1[1], UInt<3>(0h4) wire _ln_norm_cmds_WIRE_2 : UInt<3>[2] connect _ln_norm_cmds_WIRE_2[0], UInt<1>(0h0) connect _ln_norm_cmds_WIRE_2[1], UInt<1>(0h0) wire ln_norm_cmds : UInt<3>[2][3] connect ln_norm_cmds[0], _ln_norm_cmds_WIRE connect ln_norm_cmds[1], _ln_norm_cmds_WIRE_1 connect ln_norm_cmds[2], _ln_norm_cmds_WIRE_2 wire _sm_norm_cmds_WIRE : UInt<3>[2] connect _sm_norm_cmds_WIRE[0], UInt<3>(0h5) connect _sm_norm_cmds_WIRE[1], UInt<3>(0h5) wire _sm_norm_cmds_WIRE_1 : UInt<3>[2] connect _sm_norm_cmds_WIRE_1[0], UInt<3>(0h6) connect _sm_norm_cmds_WIRE_1[1], UInt<3>(0h7) wire _sm_norm_cmds_WIRE_2 : UInt<3>[2] connect _sm_norm_cmds_WIRE_2[0], UInt<1>(0h0) connect _sm_norm_cmds_WIRE_2[1], UInt<1>(0h0) wire sm_norm_cmds : UInt<3>[2][3] connect sm_norm_cmds[0], _sm_norm_cmds_WIRE connect sm_norm_cmds[1], _sm_norm_cmds_WIRE_1 connect sm_norm_cmds[2], _sm_norm_cmds_WIRE_2 node _ln_stat_ids_T = sub(rows, ln_row) node _ln_stat_ids_T_1 = asUInt(_ln_stat_ids_T) node _ln_stat_ids_T_2 = gt(_ln_stat_ids_T_1, UInt<2>(0h2)) node _ln_stat_ids_T_3 = sub(rows, ln_row) node _ln_stat_ids_T_4 = asUInt(_ln_stat_ids_T_3) node ln_stat_ids = mux(_ln_stat_ids_T_2, UInt<2>(0h2), _ln_stat_ids_T_4) node ln_r = add(ln_row, ln_stat_id) node _ln_sp_addr_T = mul(i, req.max_j) node _ln_sp_addr_T_1 = add(_ln_sp_addr_T, j) node _ln_sp_addr_T_2 = mul(_ln_sp_addr_T_1, UInt<3>(0h4)) node _ln_sp_addr_T_3 = add(req.addr_start, _ln_sp_addr_T_2) node ln_sp_addr = add(_ln_sp_addr_T_3, ln_r) node _ln_norm_cmd_T = add(j, max_blocks) node _ln_norm_cmd_T_1 = geq(_ln_norm_cmd_T, req.max_j) node _ln_norm_cmd_T_2 = eq(req.act, UInt<2>(0h2)) node _ln_norm_cmd_T_3 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_4 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_5 = mux(_ln_norm_cmd_T_2, ln_norm_cmds[_ln_norm_cmd_T_3][1], sm_norm_cmds[_ln_norm_cmd_T_4][1]) node _ln_norm_cmd_T_6 = eq(req.act, UInt<2>(0h2)) node _ln_norm_cmd_T_7 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_8 = bits(ln_cmd, 1, 0) node _ln_norm_cmd_T_9 = mux(_ln_norm_cmd_T_6, ln_norm_cmds[_ln_norm_cmd_T_7][0], sm_norm_cmds[_ln_norm_cmd_T_8][0]) node ln_norm_cmd = mux(_ln_norm_cmd_T_1, _ln_norm_cmd_T_5, _ln_norm_cmd_T_9) node _ln_dram_offset_T = mul(i, req.dram_stride) node _ln_dram_offset_T_1 = add(_ln_dram_offset_T, j) node _ln_dram_offset_T_2 = mul(_ln_dram_offset_T_1, UInt<3>(0h4)) node _ln_dram_offset_T_3 = mul(ln_r, req.dram_stride) node _ln_dram_offset_T_4 = add(_ln_dram_offset_T_2, _ln_dram_offset_T_3) node ln_dram_offset = mul(_ln_dram_offset_T_4, UInt<3>(0h4)) node _ln_dram_addr_T = and(ln_dram_offset, UInt<32>(0hffffffff)) node _ln_dram_addr_T_1 = add(req.dram_addr, _ln_dram_addr_T) node ln_dram_addr = tail(_ln_dram_addr_T_1, 1) wire ln_config_norm_rs1 : { q_const : UInt<32>, _spacer1 : UInt<13>, q_const_type : UInt<1>, set_stats_id_only : UInt<1>, act_msb : UInt<1>, norm_stats_id : UInt<8>, _spacer0 : UInt<6>, cmd_type : UInt<2>} invalidate ln_config_norm_rs1.cmd_type invalidate ln_config_norm_rs1._spacer0 invalidate ln_config_norm_rs1.norm_stats_id invalidate ln_config_norm_rs1.act_msb invalidate ln_config_norm_rs1.set_stats_id_only invalidate ln_config_norm_rs1.q_const_type invalidate ln_config_norm_rs1._spacer1 invalidate ln_config_norm_rs1.q_const connect ln_config_norm_rs1.set_stats_id_only, UInt<1>(0h1) connect ln_config_norm_rs1.cmd_type, UInt<2>(0h3) connect ln_config_norm_rs1.norm_stats_id, ln_stat_id wire ln_config_norm : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate ln_config_norm.status.uie invalidate ln_config_norm.status.sie invalidate ln_config_norm.status.hie invalidate ln_config_norm.status.mie invalidate ln_config_norm.status.upie invalidate ln_config_norm.status.spie invalidate ln_config_norm.status.ube invalidate ln_config_norm.status.mpie invalidate ln_config_norm.status.spp invalidate ln_config_norm.status.vs invalidate ln_config_norm.status.mpp invalidate ln_config_norm.status.fs invalidate ln_config_norm.status.xs invalidate ln_config_norm.status.mprv invalidate ln_config_norm.status.sum invalidate ln_config_norm.status.mxr invalidate ln_config_norm.status.tvm invalidate ln_config_norm.status.tw invalidate ln_config_norm.status.tsr invalidate ln_config_norm.status.zero1 invalidate ln_config_norm.status.sd_rv32 invalidate ln_config_norm.status.uxl invalidate ln_config_norm.status.sxl invalidate ln_config_norm.status.sbe invalidate ln_config_norm.status.mbe invalidate ln_config_norm.status.gva invalidate ln_config_norm.status.mpv invalidate ln_config_norm.status.zero2 invalidate ln_config_norm.status.sd invalidate ln_config_norm.status.v invalidate ln_config_norm.status.prv invalidate ln_config_norm.status.dv invalidate ln_config_norm.status.dprv invalidate ln_config_norm.status.isa invalidate ln_config_norm.status.wfi invalidate ln_config_norm.status.cease invalidate ln_config_norm.status.debug invalidate ln_config_norm.rs2 invalidate ln_config_norm.rs1 invalidate ln_config_norm.inst.opcode invalidate ln_config_norm.inst.rd invalidate ln_config_norm.inst.xs2 invalidate ln_config_norm.inst.xs1 invalidate ln_config_norm.inst.xd invalidate ln_config_norm.inst.rs1 invalidate ln_config_norm.inst.rs2 invalidate ln_config_norm.inst.funct connect ln_config_norm.inst.funct, UInt<1>(0h0) node ln_config_norm_rs1_lo_lo = cat(ln_config_norm_rs1._spacer0, ln_config_norm_rs1.cmd_type) node ln_config_norm_rs1_lo_hi = cat(ln_config_norm_rs1.act_msb, ln_config_norm_rs1.norm_stats_id) node ln_config_norm_rs1_lo = cat(ln_config_norm_rs1_lo_hi, ln_config_norm_rs1_lo_lo) node ln_config_norm_rs1_hi_lo = cat(ln_config_norm_rs1.q_const_type, ln_config_norm_rs1.set_stats_id_only) node ln_config_norm_rs1_hi_hi = cat(ln_config_norm_rs1.q_const, ln_config_norm_rs1._spacer1) node ln_config_norm_rs1_hi = cat(ln_config_norm_rs1_hi_hi, ln_config_norm_rs1_hi_lo) node _ln_config_norm_rs1_T = cat(ln_config_norm_rs1_hi, ln_config_norm_rs1_lo) connect ln_config_norm.rs1, _ln_config_norm_rs1_T invalidate ln_config_norm.rs2 wire ln_mvout_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate ln_mvout_cmd.status.uie invalidate ln_mvout_cmd.status.sie invalidate ln_mvout_cmd.status.hie invalidate ln_mvout_cmd.status.mie invalidate ln_mvout_cmd.status.upie invalidate ln_mvout_cmd.status.spie invalidate ln_mvout_cmd.status.ube invalidate ln_mvout_cmd.status.mpie invalidate ln_mvout_cmd.status.spp invalidate ln_mvout_cmd.status.vs invalidate ln_mvout_cmd.status.mpp invalidate ln_mvout_cmd.status.fs invalidate ln_mvout_cmd.status.xs invalidate ln_mvout_cmd.status.mprv invalidate ln_mvout_cmd.status.sum invalidate ln_mvout_cmd.status.mxr invalidate ln_mvout_cmd.status.tvm invalidate ln_mvout_cmd.status.tw invalidate ln_mvout_cmd.status.tsr invalidate ln_mvout_cmd.status.zero1 invalidate ln_mvout_cmd.status.sd_rv32 invalidate ln_mvout_cmd.status.uxl invalidate ln_mvout_cmd.status.sxl invalidate ln_mvout_cmd.status.sbe invalidate ln_mvout_cmd.status.mbe invalidate ln_mvout_cmd.status.gva invalidate ln_mvout_cmd.status.mpv invalidate ln_mvout_cmd.status.zero2 invalidate ln_mvout_cmd.status.sd invalidate ln_mvout_cmd.status.v invalidate ln_mvout_cmd.status.prv invalidate ln_mvout_cmd.status.dv invalidate ln_mvout_cmd.status.dprv invalidate ln_mvout_cmd.status.isa invalidate ln_mvout_cmd.status.wfi invalidate ln_mvout_cmd.status.cease invalidate ln_mvout_cmd.status.debug invalidate ln_mvout_cmd.rs2 invalidate ln_mvout_cmd.rs1 invalidate ln_mvout_cmd.inst.opcode invalidate ln_mvout_cmd.inst.rd invalidate ln_mvout_cmd.inst.xs2 invalidate ln_mvout_cmd.inst.xs1 invalidate ln_mvout_cmd.inst.xd invalidate ln_mvout_cmd.inst.rs1 invalidate ln_mvout_cmd.inst.rs2 invalidate ln_mvout_cmd.inst.funct connect ln_mvout_cmd.inst.funct, UInt<2>(0h3) connect ln_mvout_cmd.rs1, ln_dram_addr wire ln_mvout_cmd_rs2 : { _spacer2 : UInt<13>, num_rows : UInt<3>, _spacer1 : UInt<11>, num_cols : UInt<5>, _spacer0 : UInt<0>, local_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}} invalidate ln_mvout_cmd_rs2.local_addr.data invalidate ln_mvout_cmd_rs2.local_addr.garbage_bit invalidate ln_mvout_cmd_rs2.local_addr.garbage invalidate ln_mvout_cmd_rs2.local_addr.norm_cmd invalidate ln_mvout_cmd_rs2.local_addr.read_full_acc_row invalidate ln_mvout_cmd_rs2.local_addr.accumulate invalidate ln_mvout_cmd_rs2.local_addr.is_acc_addr invalidate ln_mvout_cmd_rs2._spacer0 invalidate ln_mvout_cmd_rs2.num_cols invalidate ln_mvout_cmd_rs2._spacer1 invalidate ln_mvout_cmd_rs2.num_rows invalidate ln_mvout_cmd_rs2._spacer2 connect ln_mvout_cmd_rs2.num_rows, UInt<1>(0h1) connect ln_mvout_cmd_rs2.num_cols, cols wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1 : UInt<32> connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, ln_sp_addr node _ln_mvout_cmd_rs2_local_addr_result_result_T = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 13, 0) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.data, _ln_mvout_cmd_rs2_local_addr_result_result_T node _ln_mvout_cmd_rs2_local_addr_result_result_T_1 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 14, 14) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.garbage_bit, _ln_mvout_cmd_rs2_local_addr_result_result_T_1 node _ln_mvout_cmd_rs2_local_addr_result_result_T_2 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 25, 15) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.garbage, _ln_mvout_cmd_rs2_local_addr_result_result_T_2 node _ln_mvout_cmd_rs2_local_addr_result_result_T_3 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 28, 26) wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2 : UInt<3> connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2, _ln_mvout_cmd_rs2_local_addr_result_result_T_3 wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3 : UInt<3> connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3, _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2 connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.norm_cmd, _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3 node _ln_mvout_cmd_rs2_local_addr_result_result_T_4 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 29, 29) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.read_full_acc_row, _ln_mvout_cmd_rs2_local_addr_result_result_T_4 node _ln_mvout_cmd_rs2_local_addr_result_result_T_5 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 30, 30) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.accumulate, _ln_mvout_cmd_rs2_local_addr_result_result_T_5 node _ln_mvout_cmd_rs2_local_addr_result_result_T_6 = bits(_ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1, 31, 31) connect _ln_mvout_cmd_rs2_local_addr_result_result_WIRE.is_acc_addr, _ln_mvout_cmd_rs2_local_addr_result_result_T_6 wire ln_mvout_cmd_rs2_local_addr_result_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect ln_mvout_cmd_rs2_local_addr_result_result, _ln_mvout_cmd_rs2_local_addr_result_result_WIRE connect ln_mvout_cmd_rs2_local_addr_result_result.garbage, UInt<1>(0h0) wire ln_mvout_cmd_rs2_local_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect ln_mvout_cmd_rs2_local_addr_result, ln_mvout_cmd_rs2_local_addr_result_result connect ln_mvout_cmd_rs2_local_addr_result.is_acc_addr, UInt<1>(0h1) connect ln_mvout_cmd_rs2_local_addr_result.accumulate, UInt<1>(0h0) connect ln_mvout_cmd_rs2_local_addr_result.read_full_acc_row, req.full_c connect ln_mvout_cmd_rs2.local_addr, ln_mvout_cmd_rs2_local_addr_result connect ln_mvout_cmd_rs2.local_addr.norm_cmd, ln_norm_cmd node _ln_mvout_cmd_rs2_T = asUInt(ln_mvout_cmd_rs2.local_addr.norm_cmd) node ln_mvout_cmd_rs2_lo_hi = cat(ln_mvout_cmd_rs2.local_addr.garbage, ln_mvout_cmd_rs2.local_addr.garbage_bit) node ln_mvout_cmd_rs2_lo = cat(ln_mvout_cmd_rs2_lo_hi, ln_mvout_cmd_rs2.local_addr.data) node ln_mvout_cmd_rs2_hi_lo = cat(ln_mvout_cmd_rs2.local_addr.read_full_acc_row, _ln_mvout_cmd_rs2_T) node ln_mvout_cmd_rs2_hi_hi = cat(ln_mvout_cmd_rs2.local_addr.is_acc_addr, ln_mvout_cmd_rs2.local_addr.accumulate) node ln_mvout_cmd_rs2_hi = cat(ln_mvout_cmd_rs2_hi_hi, ln_mvout_cmd_rs2_hi_lo) node _ln_mvout_cmd_rs2_T_1 = cat(ln_mvout_cmd_rs2_hi, ln_mvout_cmd_rs2_lo) node ln_mvout_cmd_rs2_lo_hi_1 = cat(ln_mvout_cmd_rs2.num_cols, ln_mvout_cmd_rs2._spacer0) node ln_mvout_cmd_rs2_lo_1 = cat(ln_mvout_cmd_rs2_lo_hi_1, _ln_mvout_cmd_rs2_T_1) node ln_mvout_cmd_rs2_hi_hi_1 = cat(ln_mvout_cmd_rs2._spacer2, ln_mvout_cmd_rs2.num_rows) node ln_mvout_cmd_rs2_hi_1 = cat(ln_mvout_cmd_rs2_hi_hi_1, ln_mvout_cmd_rs2._spacer1) node _ln_mvout_cmd_rs2_T_2 = cat(ln_mvout_cmd_rs2_hi_1, ln_mvout_cmd_rs2_lo_1) connect ln_mvout_cmd.rs2, _ln_mvout_cmd_rs2_T_2 node _io_req_ready_T = eq(state, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T connect io.j, j connect io.i, i node _io_idle_T = eq(state, UInt<1>(0h0)) connect io.idle, _io_idle_T node _ex_ahead_T = neq(req.act, UInt<2>(0h2)) node _ex_ahead_T_1 = neq(req.act, UInt<3>(0h4)) node _ex_ahead_T_2 = and(_ex_ahead_T, _ex_ahead_T_1) node _ex_ahead_T_3 = sub(req.max_k, UInt<1>(0h1)) node _ex_ahead_T_4 = tail(_ex_ahead_T_3, 1) node _ex_ahead_T_5 = eq(io.ex_k, _ex_ahead_T_4) node _ex_ahead_T_6 = add(j, blocks) node _ex_ahead_T_7 = tail(_ex_ahead_T_6, 1) node _ex_ahead_T_8 = geq(io.ex_j, _ex_ahead_T_7) node _ex_ahead_T_9 = add(j, blocks) node _ex_ahead_T_10 = tail(_ex_ahead_T_9, 1) node _ex_ahead_T_11 = sub(_ex_ahead_T_10, UInt<1>(0h1)) node _ex_ahead_T_12 = tail(_ex_ahead_T_11, 1) node _ex_ahead_T_13 = eq(io.ex_j, _ex_ahead_T_12) node _ex_ahead_T_14 = gt(io.ex_i, i) node _ex_ahead_T_15 = and(_ex_ahead_T_13, _ex_ahead_T_14) node _ex_ahead_T_16 = or(_ex_ahead_T_8, _ex_ahead_T_15) node _ex_ahead_T_17 = and(_ex_ahead_T_5, _ex_ahead_T_16) node _ex_ahead_T_18 = and(_ex_ahead_T_2, _ex_ahead_T_17) node _ex_ahead_T_19 = or(io.ex_completed, _ex_ahead_T_18) wire ex_ahead : UInt<1> connect ex_ahead, _ex_ahead_T_19 when req.is_resadd : node _ex_ahead_T_20 = gt(io.ex_i, i) node _ex_ahead_T_21 = eq(io.ex_i, i) node _ex_ahead_T_22 = add(j, blocks) node _ex_ahead_T_23 = tail(_ex_ahead_T_22, 1) node _ex_ahead_T_24 = geq(io.ex_j, _ex_ahead_T_23) node _ex_ahead_T_25 = and(_ex_ahead_T_21, _ex_ahead_T_24) node _ex_ahead_T_26 = or(_ex_ahead_T_20, _ex_ahead_T_25) node _ex_ahead_T_27 = or(io.ex_completed, _ex_ahead_T_26) connect ex_ahead, _ex_ahead_T_27 node _io_cmd_valid_T = neq(state, UInt<1>(0h0)) node _io_cmd_valid_T_1 = eq(io.rob_overloaded, UInt<1>(0h0)) node _io_cmd_valid_T_2 = and(_io_cmd_valid_T, _io_cmd_valid_T_1) node _io_cmd_valid_T_3 = and(_io_cmd_valid_T_2, ex_ahead) node _io_cmd_valid_T_4 = neq(req.dram_addr, UInt<1>(0h0)) node _io_cmd_valid_T_5 = and(_io_cmd_valid_T_3, _io_cmd_valid_T_4) connect io.cmd.valid, _io_cmd_valid_T_5 node _io_cmd_bits_T = eq(state, UInt<2>(0h2)) node _io_cmd_bits_T_1 = eq(state, UInt<2>(0h3)) node _io_cmd_bits_T_2 = mux(_io_cmd_bits_T_1, ln_mvout_cmd, mvout_cmd) node _io_cmd_bits_T_3 = mux(_io_cmd_bits_T, ln_config_norm, _io_cmd_bits_T_2) connect io.cmd.bits, _io_cmd_bits_T_3 connect io.loop_id, req.loop_id node _T = eq(req.dram_addr, UInt<1>(0h0)) when _T : connect state, UInt<1>(0h0) else : node _T_1 = and(io.cmd.ready, io.cmd.valid) node _T_2 = eq(state, UInt<1>(0h1)) node _T_3 = and(_T_1, _T_2) when _T_3 : node _next_i_max_T = sub(req.max_i, UInt<1>(0h1)) node next_i_max = tail(_next_i_max_T, 1) node _next_i_T = add(i, UInt<1>(0h1)) node _next_i_T_1 = tail(_next_i_T, 1) node _next_i_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _next_i_T_3 = add(i, UInt<1>(0h1)) node _next_i_T_4 = gt(_next_i_T_3, next_i_max) node _next_i_T_5 = mux(_next_i_T_4, UInt<1>(0h0), _next_i_T_1) node next_i = mux(_next_i_T_2, i, _next_i_T_5) node _next_j_T = eq(next_i, UInt<1>(0h0)) node _next_j_max_T = sub(req.max_j, UInt<1>(0h1)) node next_j_max = tail(_next_j_max_T, 1) node _next_j_T_1 = add(j, max_blocks) node _next_j_T_2 = tail(_next_j_T_1, 1) node _next_j_T_3 = eq(_next_j_T, UInt<1>(0h0)) node _next_j_T_4 = add(j, max_blocks) node _next_j_T_5 = gt(_next_j_T_4, next_j_max) node _next_j_T_6 = mux(_next_j_T_5, UInt<1>(0h0), _next_j_T_2) node next_j = mux(_next_j_T_3, j, _next_j_T_6) connect i, next_i connect j, next_j node _T_4 = eq(next_i, UInt<1>(0h0)) node _T_5 = eq(next_j, UInt<1>(0h0)) node _T_6 = and(_T_4, _T_5) when _T_6 : connect state, UInt<1>(0h0) else : node _T_7 = and(io.cmd.ready, io.cmd.valid) node _T_8 = eq(state, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) when _T_9 : connect state, UInt<2>(0h3) else : node _T_10 = and(io.cmd.ready, io.cmd.valid) node _T_11 = eq(state, UInt<2>(0h3)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _next_j_max_T_1 = sub(req.max_j, UInt<1>(0h1)) node next_j_max_1 = tail(_next_j_max_T_1, 1) node _next_j_T_7 = add(j, max_blocks) node _next_j_T_8 = tail(_next_j_T_7, 1) node _next_j_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _next_j_T_10 = add(j, max_blocks) node _next_j_T_11 = gt(_next_j_T_10, next_j_max_1) node _next_j_T_12 = mux(_next_j_T_11, UInt<1>(0h0), _next_j_T_8) node next_j_1 = mux(_next_j_T_9, j, _next_j_T_12) node _next_stat_id_T = eq(next_j_1, UInt<1>(0h0)) node _next_stat_id_max_T = sub(ln_stat_ids, UInt<1>(0h1)) node next_stat_id_max = tail(_next_stat_id_max_T, 1) node _next_stat_id_T_1 = add(ln_stat_id, UInt<1>(0h1)) node _next_stat_id_T_2 = tail(_next_stat_id_T_1, 1) node _next_stat_id_T_3 = eq(_next_stat_id_T, UInt<1>(0h0)) node _next_stat_id_T_4 = add(ln_stat_id, UInt<1>(0h1)) node _next_stat_id_T_5 = gt(_next_stat_id_T_4, next_stat_id_max) node _next_stat_id_T_6 = mux(_next_stat_id_T_5, UInt<1>(0h0), _next_stat_id_T_2) node next_stat_id = mux(_next_stat_id_T_3, ln_stat_id, _next_stat_id_T_6) node _next_cmd_T = eq(next_j_1, UInt<1>(0h0)) node _next_cmd_T_1 = eq(next_stat_id, UInt<1>(0h0)) node _next_cmd_T_2 = and(_next_cmd_T, _next_cmd_T_1) node _next_cmd_max_T = sub(UInt<2>(0h3), UInt<1>(0h1)) node next_cmd_max = tail(_next_cmd_max_T, 1) node _next_cmd_T_3 = add(ln_cmd, UInt<1>(0h1)) node _next_cmd_T_4 = tail(_next_cmd_T_3, 1) node _next_cmd_T_5 = eq(_next_cmd_T_2, UInt<1>(0h0)) node _next_cmd_T_6 = add(ln_cmd, UInt<1>(0h1)) node _next_cmd_T_7 = gt(_next_cmd_T_6, next_cmd_max) node _next_cmd_T_8 = mux(_next_cmd_T_7, UInt<1>(0h0), _next_cmd_T_4) node next_cmd = mux(_next_cmd_T_5, ln_cmd, _next_cmd_T_8) node _next_row_T = eq(next_j_1, UInt<1>(0h0)) node _next_row_T_1 = eq(next_stat_id, UInt<1>(0h0)) node _next_row_T_2 = and(_next_row_T, _next_row_T_1) node _next_row_T_3 = eq(next_cmd, UInt<1>(0h0)) node _next_row_T_4 = and(_next_row_T_2, _next_row_T_3) node _next_row_max_T = sub(rows, UInt<1>(0h1)) node next_row_max = tail(_next_row_max_T, 1) node _next_row_T_5 = add(ln_row, UInt<2>(0h2)) node _next_row_T_6 = tail(_next_row_T_5, 1) node _next_row_T_7 = eq(_next_row_T_4, UInt<1>(0h0)) node _next_row_T_8 = add(ln_row, UInt<2>(0h2)) node _next_row_T_9 = gt(_next_row_T_8, next_row_max) node _next_row_T_10 = mux(_next_row_T_9, UInt<1>(0h0), _next_row_T_6) node next_row = mux(_next_row_T_7, ln_row, _next_row_T_10) node _next_i_T_6 = eq(next_j_1, UInt<1>(0h0)) node _next_i_T_7 = eq(next_stat_id, UInt<1>(0h0)) node _next_i_T_8 = and(_next_i_T_6, _next_i_T_7) node _next_i_T_9 = eq(next_cmd, UInt<1>(0h0)) node _next_i_T_10 = and(_next_i_T_8, _next_i_T_9) node _next_i_T_11 = eq(next_row, UInt<1>(0h0)) node _next_i_T_12 = and(_next_i_T_10, _next_i_T_11) node _next_i_max_T_1 = sub(req.max_i, UInt<1>(0h1)) node next_i_max_1 = tail(_next_i_max_T_1, 1) node _next_i_T_13 = add(i, UInt<1>(0h1)) node _next_i_T_14 = tail(_next_i_T_13, 1) node _next_i_T_15 = eq(_next_i_T_12, UInt<1>(0h0)) node _next_i_T_16 = add(i, UInt<1>(0h1)) node _next_i_T_17 = gt(_next_i_T_16, next_i_max_1) node _next_i_T_18 = mux(_next_i_T_17, UInt<1>(0h0), _next_i_T_14) node next_i_1 = mux(_next_i_T_15, i, _next_i_T_18) connect j, next_j_1 connect ln_stat_id, next_stat_id connect ln_cmd, next_cmd connect ln_row, next_row connect i, next_i_1 node _T_13 = eq(next_i_1, UInt<1>(0h0)) node _T_14 = eq(next_row, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(next_cmd, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(next_stat_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(next_j_1, UInt<1>(0h0)) node _T_21 = and(_T_19, _T_20) when _T_21 : connect state, UInt<1>(0h0) else : node _T_22 = eq(next_j_1, UInt<1>(0h0)) when _T_22 : connect state, UInt<2>(0h2) node _T_23 = and(io.req.ready, io.req.valid) when _T_23 : connect req, io.req.bits node _state_T = eq(io.req.bits.act, UInt<2>(0h2)) node _state_T_1 = eq(io.req.bits.act, UInt<3>(0h4)) node _state_T_2 = or(_state_T, _state_T_1) node _state_T_3 = mux(_state_T_2, UInt<2>(0h2), UInt<1>(0h1)) connect state, _state_T_3 connect j, UInt<1>(0h0) connect i, UInt<1>(0h0) connect ln_row, UInt<1>(0h0) connect ln_cmd, UInt<1>(0h0) connect ln_stat_id, UInt<1>(0h0)

module LoopMatmulStC( // @[LoopMatmul.scala:514:7] input clock, // @[LoopMatmul.scala:514:7] input reset, // @[LoopMatmul.scala:514:7] output io_req_ready, // @[LoopMatmul.scala:516:14] input io_req_valid, // @[LoopMatmul.scala:516:14] input [15:0] io_req_bits_max_k, // @[LoopMatmul.scala:516:14] input [15:0] io_req_bits_max_j, // @[LoopMatmul.scala:516:14] input [15:0] io_req_bits_max_i, // @[LoopMatmul.scala:516:14] input [1:0] io_req_bits_pad_j, // @[LoopMatmul.scala:516:14] input [1:0] io_req_bits_pad_i, // @[LoopMatmul.scala:516:14] input [39:0] io_req_bits_dram_addr, // @[LoopMatmul.scala:516:14] input [39:0] io_req_bits_dram_stride, // @[LoopMatmul.scala:516:14] input io_req_bits_full_c, // @[LoopMatmul.scala:516:14] input [2:0] io_req_bits_act, // @[LoopMatmul.scala:516:14] input [11:0] io_req_bits_addr_start, // @[LoopMatmul.scala:516:14] input io_req_bits_loop_id, // @[LoopMatmul.scala:516:14] input io_req_bits_is_resadd, // @[LoopMatmul.scala:516:14] input io_cmd_ready, // @[LoopMatmul.scala:516:14] output io_cmd_valid, // @[LoopMatmul.scala:516:14] output [6:0] io_cmd_bits_inst_funct, // @[LoopMatmul.scala:516:14] output [63:0] io_cmd_bits_rs1, // @[LoopMatmul.scala:516:14] output [63:0] io_cmd_bits_rs2, // @[LoopMatmul.scala:516:14] input [15:0] io_ex_k, // @[LoopMatmul.scala:516:14] input [15:0] io_ex_j, // @[LoopMatmul.scala:516:14] input [15:0] io_ex_i, // @[LoopMatmul.scala:516:14] input io_ex_completed, // @[LoopMatmul.scala:516:14] output io_idle, // @[LoopMatmul.scala:516:14] input io_rob_overloaded, // @[LoopMatmul.scala:516:14] output io_loop_id // @[LoopMatmul.scala:516:14] ); wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [4:0] mvout_cmd_rs2_num_cols; // @[LoopMatmul.scala:563:27] wire [2:0] mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:563:27] wire io_req_valid_0 = io_req_valid; // @[LoopMatmul.scala:514:7] wire [15:0] io_req_bits_max_k_0 = io_req_bits_max_k; // @[LoopMatmul.scala:514:7] wire [15:0] io_req_bits_max_j_0 = io_req_bits_max_j; // @[LoopMatmul.scala:514:7] wire [15:0] io_req_bits_max_i_0 = io_req_bits_max_i; // @[LoopMatmul.scala:514:7] wire [1:0] io_req_bits_pad_j_0 = io_req_bits_pad_j; // @[LoopMatmul.scala:514:7] wire [1:0] io_req_bits_pad_i_0 = io_req_bits_pad_i; // @[LoopMatmul.scala:514:7] wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopMatmul.scala:514:7] wire [39:0] io_req_bits_dram_stride_0 = io_req_bits_dram_stride; // @[LoopMatmul.scala:514:7] wire io_req_bits_full_c_0 = io_req_bits_full_c; // @[LoopMatmul.scala:514:7] wire [2:0] io_req_bits_act_0 = io_req_bits_act; // @[LoopMatmul.scala:514:7] wire [11:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopMatmul.scala:514:7] wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopMatmul.scala:514:7] wire io_req_bits_is_resadd_0 = io_req_bits_is_resadd; // @[LoopMatmul.scala:514:7] wire io_cmd_ready_0 = io_cmd_ready; // @[LoopMatmul.scala:514:7] wire [15:0] io_ex_k_0 = io_ex_k; // @[LoopMatmul.scala:514:7] wire [15:0] io_ex_j_0 = io_ex_j; // @[LoopMatmul.scala:514:7] wire [15:0] io_ex_i_0 = io_ex_i; // @[LoopMatmul.scala:514:7] wire io_ex_completed_0 = io_ex_completed; // @[LoopMatmul.scala:514:7] wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopMatmul.scala:514:7] wire [3:0][2:0] _GEN = '{3'h5, 3'h0, 3'h6, 3'h5}; wire [3:0][2:0] _GEN_0 = '{3'h1, 3'h0, 3'h3, 3'h1}; wire [3:0][2:0] _GEN_1 = '{3'h5, 3'h0, 3'h7, 3'h5}; wire [3:0][2:0] _GEN_2 = '{3'h2, 3'h0, 3'h4, 3'h2}; wire [2:0] _ln_norm_cmds_WIRE_1_0 = 3'h3; // @[LoopMatmul.scala:577:73] wire [2:0] ln_norm_cmds_1_0 = 3'h3; // @[LoopMatmul.scala:577:29] wire [2:0] _ln_norm_cmds_WIRE_1_1 = 3'h4; // @[LoopMatmul.scala:577:73] wire [2:0] ln_norm_cmds_1_1 = 3'h4; // @[LoopMatmul.scala:577:29] wire [2:0] _sm_norm_cmds_WIRE_0 = 3'h5; // @[LoopMatmul.scala:580:37] wire [2:0] _sm_norm_cmds_WIRE_1 = 3'h5; // @[LoopMatmul.scala:580:37] wire [2:0] sm_norm_cmds_0_0 = 3'h5; // @[LoopMatmul.scala:580:29] wire [2:0] sm_norm_cmds_0_1 = 3'h5; // @[LoopMatmul.scala:580:29] wire [2:0] _sm_norm_cmds_WIRE_1_0 = 3'h6; // @[LoopMatmul.scala:580:72] wire [2:0] sm_norm_cmds_1_0 = 3'h6; // @[LoopMatmul.scala:580:29] wire [2:0] _sm_norm_cmds_WIRE_1_1 = 3'h7; // @[LoopMatmul.scala:580:72] wire [2:0] sm_norm_cmds_1_1 = 3'h7; // @[LoopMatmul.scala:580:29] wire [2:0] _ln_norm_cmds_WIRE_2_0 = 3'h0; // @[LoopMatmul.scala:578:12] wire [2:0] _ln_norm_cmds_WIRE_2_1 = 3'h0; // @[LoopMatmul.scala:578:12] wire [2:0] ln_norm_cmds_2_0 = 3'h0; // @[LoopMatmul.scala:577:29] wire [2:0] ln_norm_cmds_2_1 = 3'h0; // @[LoopMatmul.scala:577:29] wire [2:0] _sm_norm_cmds_WIRE_2_0 = 3'h0; // @[LoopMatmul.scala:581:12] wire [2:0] _sm_norm_cmds_WIRE_2_1 = 3'h0; // @[LoopMatmul.scala:581:12] wire [2:0] sm_norm_cmds_2_0 = 3'h0; // @[LoopMatmul.scala:580:29] wire [2:0] sm_norm_cmds_2_1 = 3'h0; // @[LoopMatmul.scala:580:29] wire [5:0] ln_config_norm_rs1__spacer0 = 6'h0; // @[LoopMatmul.scala:596:32] wire [1:0] ln_config_norm_rs1_cmd_type = 2'h3; // @[LoopMatmul.scala:596:32] wire [63:0] ln_config_norm_rs2 = 64'h0; // @[LoopMatmul.scala:602:28] wire [7:0] ln_config_norm_rs1_lo_lo = 8'h3; // @[LoopMatmul.scala:605:44] wire [1:0] ln_config_norm_rs1_hi_lo = 2'h1; // @[LoopMatmul.scala:605:44, :646:36] wire [44:0] ln_config_norm_rs1_hi_hi = 45'h0; // @[LoopMatmul.scala:605:44] wire [46:0] ln_config_norm_rs1_hi = 47'h1; // @[LoopMatmul.scala:605:44] wire [12:0] mvout_cmd_rs2__spacer2 = 13'h0; // @[LoopMatmul.scala:563:27] wire [12:0] ln_config_norm_rs1__spacer1 = 13'h0; // @[LoopMatmul.scala:596:32] wire [12:0] ln_mvout_cmd_rs2__spacer2 = 13'h0; // @[LoopMatmul.scala:613:30] wire [2:0] _ln_norm_cmds_WIRE_0 = 3'h1; // @[LoopMatmul.scala:577:37] wire [2:0] ln_norm_cmds_0_0 = 3'h1; // @[LoopMatmul.scala:577:29] wire [2:0] ln_mvout_cmd_rs2_num_rows = 3'h1; // @[LoopMatmul.scala:613:30] wire mvout_cmd_rs2_local_addr_is_acc_addr = 1'h1; // @[LoopMatmul.scala:563:27] wire mvout_cmd_rs2_local_addr_result_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire ln_config_norm_rs1_set_stats_id_only = 1'h1; // @[LoopMatmul.scala:596:32] wire ln_mvout_cmd_rs2_local_addr_is_acc_addr = 1'h1; // @[LoopMatmul.scala:613:30] wire ln_mvout_cmd_rs2_local_addr_result_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire [10:0] mvout_cmd_rs2__spacer1 = 11'h0; // @[LoopMatmul.scala:563:27] wire [10:0] mvout_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopMatmul.scala:563:27] wire [10:0] mvout_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvout_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [10:0] ln_mvout_cmd_rs2__spacer1 = 11'h0; // @[LoopMatmul.scala:613:30] wire [10:0] ln_mvout_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopMatmul.scala:613:30] wire [10:0] ln_mvout_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] ln_mvout_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [15:0] ln_mvout_cmd_rs2_hi_hi_1 = 16'h1; // @[LoopMatmul.scala:619:40] wire [26:0] ln_mvout_cmd_rs2_hi_1 = 27'h800; // @[LoopMatmul.scala:619:40] wire [6:0] mvout_cmd_inst_funct = 7'h3; // @[LoopMatmul.scala:558:23] wire [6:0] ln_mvout_cmd_inst_funct = 7'h3; // @[LoopMatmul.scala:608:26] wire [6:0] _io_cmd_bits_T_2_inst_funct = 7'h3; // @[Mux.scala:126:16] wire [2:0] _ln_norm_cmds_WIRE_1 = 3'h2; // @[LoopMatmul.scala:577:37, :589:17] wire [2:0] ln_norm_cmds_0_1 = 3'h2; // @[LoopMatmul.scala:577:29, :589:17] wire [2:0] _next_cmd_max_T = 3'h2; // @[Util.scala:39:28] wire [1:0] mvout_cmd_rs2_hi_hi = 2'h2; // @[LoopMatmul.scala:568:34] wire [1:0] ln_mvout_cmd_rs2_hi_hi = 2'h2; // @[LoopMatmul.scala:619:40] wire [1:0] next_cmd_max = 2'h2; // @[Util.scala:39:28] wire [7:0] io_cmd_bits_status_zero1 = 8'h0; // @[LoopMatmul.scala:514:7] wire [7:0] mvout_cmd_status_zero1 = 8'h0; // @[LoopMatmul.scala:558:23] wire [7:0] ln_config_norm_status_zero1 = 8'h0; // @[LoopMatmul.scala:602:28] wire [7:0] ln_mvout_cmd_status_zero1 = 8'h0; // @[LoopMatmul.scala:608:26] wire [7:0] _io_cmd_bits_T_2_status_zero1 = 8'h0; // @[Mux.scala:126:16] wire [7:0] _io_cmd_bits_T_3_status_zero1 = 8'h0; // @[Mux.scala:126:16] wire [22:0] io_cmd_bits_status_zero2 = 23'h0; // @[LoopMatmul.scala:514:7] wire [22:0] mvout_cmd_status_zero2 = 23'h0; // @[LoopMatmul.scala:558:23] wire [22:0] ln_config_norm_status_zero2 = 23'h0; // @[LoopMatmul.scala:602:28] wire [22:0] ln_mvout_cmd_status_zero2 = 23'h0; // @[LoopMatmul.scala:608:26] wire [22:0] _io_cmd_bits_T_2_status_zero2 = 23'h0; // @[Mux.scala:126:16] wire [22:0] _io_cmd_bits_T_3_status_zero2 = 23'h0; // @[Mux.scala:126:16] wire [1:0] io_cmd_bits_status_dprv = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_prv = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_sxl = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_uxl = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_xs = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_fs = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_mpp = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] io_cmd_bits_status_vs = 2'h0; // @[LoopMatmul.scala:514:7] wire [1:0] mvout_cmd_status_dprv = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_prv = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_sxl = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_uxl = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_xs = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_fs = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_mpp = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] mvout_cmd_status_vs = 2'h0; // @[LoopMatmul.scala:558:23] wire [1:0] ln_config_norm_status_dprv = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_prv = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_sxl = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_uxl = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_xs = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_fs = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_mpp = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_config_norm_status_vs = 2'h0; // @[LoopMatmul.scala:602:28] wire [1:0] ln_mvout_cmd_status_dprv = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_prv = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_sxl = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_uxl = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_xs = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_fs = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_mpp = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] ln_mvout_cmd_status_vs = 2'h0; // @[LoopMatmul.scala:608:26] wire [1:0] _io_cmd_bits_T_2_status_dprv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_prv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_sxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_uxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_xs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_fs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_mpp = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_2_status_vs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_dprv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_prv = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_sxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_uxl = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_xs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_fs = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_mpp = 2'h0; // @[Mux.scala:126:16] wire [1:0] _io_cmd_bits_T_3_status_vs = 2'h0; // @[Mux.scala:126:16] wire [31:0] io_cmd_bits_status_isa = 32'h0; // @[LoopMatmul.scala:514:7] wire [31:0] mvout_cmd_status_isa = 32'h0; // @[LoopMatmul.scala:558:23] wire [31:0] ln_config_norm_rs1_q_const = 32'h0; // @[LoopMatmul.scala:596:32] wire [31:0] ln_config_norm_status_isa = 32'h0; // @[LoopMatmul.scala:602:28] wire [31:0] ln_mvout_cmd_status_isa = 32'h0; // @[LoopMatmul.scala:608:26] wire [31:0] _io_cmd_bits_T_2_status_isa = 32'h0; // @[Mux.scala:126:16] wire [31:0] _io_cmd_bits_T_3_status_isa = 32'h0; // @[Mux.scala:126:16] wire [6:0] io_cmd_bits_inst_opcode = 7'h0; // @[LoopMatmul.scala:514:7] wire [6:0] mvout_cmd_inst_opcode = 7'h0; // @[LoopMatmul.scala:558:23] wire [6:0] ln_config_norm_inst_funct = 7'h0; // @[LoopMatmul.scala:602:28] wire [6:0] ln_config_norm_inst_opcode = 7'h0; // @[LoopMatmul.scala:602:28] wire [6:0] ln_mvout_cmd_inst_opcode = 7'h0; // @[LoopMatmul.scala:608:26] wire [6:0] _io_cmd_bits_T_2_inst_opcode = 7'h0; // @[Mux.scala:126:16] wire [6:0] _io_cmd_bits_T_3_inst_opcode = 7'h0; // @[Mux.scala:126:16] wire io_cmd_bits_inst_xd = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_inst_xs1 = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_inst_xs2 = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_debug = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_cease = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_wfi = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_dv = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_v = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sd = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mpv = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_gva = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mbe = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sbe = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_tsr = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_tw = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_tvm = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mxr = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sum = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mprv = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_spp = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mpie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_ube = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_spie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_upie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_mie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_hie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_sie = 1'h0; // @[LoopMatmul.scala:514:7] wire io_cmd_bits_status_uie = 1'h0; // @[LoopMatmul.scala:514:7] wire mvout_cmd_inst_xd = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_inst_xs1 = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_inst_xs2 = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_debug = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_cease = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_wfi = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_dv = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_v = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sd = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mpv = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_gva = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mbe = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sbe = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_tsr = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_tw = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_tvm = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mxr = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sum = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mprv = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_spp = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mpie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_ube = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_spie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_upie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_mie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_hie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_sie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_status_uie = 1'h0; // @[LoopMatmul.scala:558:23] wire mvout_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopMatmul.scala:563:27] wire mvout_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire ln_config_norm_rs1_q_const_type = 1'h0; // @[LoopMatmul.scala:596:32] wire ln_config_norm_rs1_act_msb = 1'h0; // @[LoopMatmul.scala:596:32] wire ln_config_norm_inst_xd = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_inst_xs1 = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_inst_xs2 = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_debug = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_cease = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_wfi = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_dv = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_v = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sd = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mpv = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_gva = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mbe = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sbe = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_tsr = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_tw = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_tvm = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mxr = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sum = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mprv = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_spp = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mpie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_ube = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_spie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_upie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_mie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_hie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_sie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_config_norm_status_uie = 1'h0; // @[LoopMatmul.scala:602:28] wire ln_mvout_cmd_inst_xd = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_inst_xs1 = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_inst_xs2 = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_debug = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_cease = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_wfi = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_dv = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_v = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sd = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mpv = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_gva = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mbe = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sbe = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_tsr = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_tw = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_tvm = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mxr = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sum = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mprv = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_spp = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mpie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_ube = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_spie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_upie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_mie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_hie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_sie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_status_uie = 1'h0; // @[LoopMatmul.scala:608:26] wire ln_mvout_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopMatmul.scala:613:30] wire ln_mvout_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire _io_cmd_bits_T_2_inst_xd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_inst_xs1 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_inst_xs2 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_debug = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_cease = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_wfi = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_dv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_v = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mpv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_gva = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sd_rv32 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_tsr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_tw = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_tvm = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mxr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sum = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mprv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_spp = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mpie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_ube = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_spie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_upie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_mie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_hie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_sie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_2_status_uie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_inst_xd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_inst_xs1 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_inst_xs2 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_debug = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_cease = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_wfi = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_dv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_v = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sd = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mpv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_gva = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sbe = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sd_rv32 = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_tsr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_tw = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_tvm = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mxr = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sum = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mprv = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_spp = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mpie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_ube = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_spie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_upie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_mie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_hie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_sie = 1'h0; // @[Mux.scala:126:16] wire _io_cmd_bits_T_3_status_uie = 1'h0; // @[Mux.scala:126:16] wire _next_i_T_2 = 1'h0; // @[Util.scala:42:8] wire _next_j_T_9 = 1'h0; // @[Util.scala:42:8] wire [4:0] io_cmd_bits_inst_rs2 = 5'h0; // @[LoopMatmul.scala:514:7] wire [4:0] io_cmd_bits_inst_rs1 = 5'h0; // @[LoopMatmul.scala:514:7] wire [4:0] io_cmd_bits_inst_rd = 5'h0; // @[LoopMatmul.scala:514:7] wire [4:0] mvout_cmd_inst_rs2 = 5'h0; // @[LoopMatmul.scala:558:23] wire [4:0] mvout_cmd_inst_rs1 = 5'h0; // @[LoopMatmul.scala:558:23] wire [4:0] mvout_cmd_inst_rd = 5'h0; // @[LoopMatmul.scala:558:23] wire [4:0] ln_config_norm_inst_rs2 = 5'h0; // @[LoopMatmul.scala:602:28] wire [4:0] ln_config_norm_inst_rs1 = 5'h0; // @[LoopMatmul.scala:602:28] wire [4:0] ln_config_norm_inst_rd = 5'h0; // @[LoopMatmul.scala:602:28] wire [4:0] ln_mvout_cmd_inst_rs2 = 5'h0; // @[LoopMatmul.scala:608:26] wire [4:0] ln_mvout_cmd_inst_rs1 = 5'h0; // @[LoopMatmul.scala:608:26] wire [4:0] ln_mvout_cmd_inst_rd = 5'h0; // @[LoopMatmul.scala:608:26] wire _io_req_ready_T; // @[LoopMatmul.scala:621:25] wire [4:0] _io_cmd_bits_T_2_inst_rs2 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_2_inst_rs1 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_2_inst_rd = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_3_inst_rs2 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_3_inst_rs1 = 5'h0; // @[Mux.scala:126:16] wire [4:0] _io_cmd_bits_T_3_inst_rd = 5'h0; // @[Mux.scala:126:16] wire _io_cmd_valid_T_5; // @[LoopMatmul.scala:636:68] wire [6:0] _io_cmd_bits_T_3_inst_funct; // @[Mux.scala:126:16] wire [63:0] _io_cmd_bits_T_3_rs1; // @[Mux.scala:126:16] wire [63:0] _io_cmd_bits_T_3_rs2; // @[Mux.scala:126:16] wire _io_idle_T; // @[LoopMatmul.scala:624:20] wire io_req_ready_0; // @[LoopMatmul.scala:514:7] wire [6:0] io_cmd_bits_inst_funct_0; // @[LoopMatmul.scala:514:7] wire [63:0] io_cmd_bits_rs1_0; // @[LoopMatmul.scala:514:7] wire [63:0] io_cmd_bits_rs2_0; // @[LoopMatmul.scala:514:7] wire io_cmd_valid_0; // @[LoopMatmul.scala:514:7] wire [15:0] io_j; // @[LoopMatmul.scala:514:7] wire [15:0] io_i; // @[LoopMatmul.scala:514:7] wire io_idle_0; // @[LoopMatmul.scala:514:7] wire io_loop_id_0; // @[LoopMatmul.scala:514:7] reg [1:0] state; // @[LoopMatmul.scala:538:22] reg [15:0] req_max_k; // @[LoopMatmul.scala:540:16] reg [15:0] req_max_j; // @[LoopMatmul.scala:540:16] reg [15:0] req_max_i; // @[LoopMatmul.scala:540:16] reg [1:0] req_pad_j; // @[LoopMatmul.scala:540:16] reg [1:0] req_pad_i; // @[LoopMatmul.scala:540:16] reg [39:0] req_dram_addr; // @[LoopMatmul.scala:540:16] reg [39:0] req_dram_stride; // @[LoopMatmul.scala:540:16] reg req_full_c; // @[LoopMatmul.scala:540:16] wire mvout_cmd_rs2_local_addr_result_read_full_acc_row = req_full_c; // @[LoopMatmul.scala:540:16] wire ln_mvout_cmd_rs2_local_addr_result_read_full_acc_row = req_full_c; // @[LoopMatmul.scala:540:16] reg [2:0] req_act; // @[LoopMatmul.scala:540:16] reg [11:0] req_addr_start; // @[LoopMatmul.scala:540:16] reg req_loop_id; // @[LoopMatmul.scala:540:16] assign io_loop_id_0 = req_loop_id; // @[LoopMatmul.scala:514:7, :540:16] reg req_is_resadd; // @[LoopMatmul.scala:540:16] wire _max_blocks_T = req_max_j < 16'h5; // @[LoopMatmul.scala:540:16, :542:55] wire [15:0] _max_blocks_T_1 = _max_blocks_T ? req_max_j : 16'h4; // @[LoopMatmul.scala:540:16, :542:{44,55}] wire [15:0] max_blocks = req_full_c ? 16'h1 : _max_blocks_T_1; // @[LoopMatmul.scala:540:16, :542:{23,44}] reg [15:0] j; // @[LoopMatmul.scala:545:14] assign io_j = j; // @[LoopMatmul.scala:514:7, :545:14] reg [15:0] i; // @[LoopMatmul.scala:546:14] assign io_i = i; // @[LoopMatmul.scala:514:7, :546:14] wire [55:0] _GEN_3 = {40'h0, i} * {16'h0, req_dram_stride}; // @[LoopMatmul.scala:540:16, :546:14, :550:40] wire [55:0] _dram_offset_T; // @[LoopMatmul.scala:550:40] assign _dram_offset_T = _GEN_3; // @[LoopMatmul.scala:550:40] wire [55:0] _dram_offset_T_5; // @[LoopMatmul.scala:551:8] assign _dram_offset_T_5 = _GEN_3; // @[LoopMatmul.scala:550:40, :551:8] wire [55:0] _ln_dram_offset_T; // @[LoopMatmul.scala:593:28] assign _ln_dram_offset_T = _GEN_3; // @[LoopMatmul.scala:550:40, :593:28] wire [56:0] _GEN_4 = {41'h0, j}; // @[LoopMatmul.scala:545:14, :550:58] wire [56:0] _dram_offset_T_1 = {1'h0, _dram_offset_T} + _GEN_4; // @[LoopMatmul.scala:550:{40,58}] wire [55:0] _dram_offset_T_2 = _dram_offset_T_1[55:0]; // @[LoopMatmul.scala:550:58] wire [58:0] _dram_offset_T_3 = {1'h0, _dram_offset_T_2, 2'h0}; // @[LoopMatmul.scala:550:{58,63}] wire [61:0] _dram_offset_T_4 = {1'h0, _dram_offset_T_3, 2'h0}; // @[LoopMatmul.scala:550:{63,78}] wire [56:0] _dram_offset_T_6 = {1'h0, _dram_offset_T_5} + _GEN_4; // @[LoopMatmul.scala:550:58, :551:{8,26}] wire [55:0] _dram_offset_T_7 = _dram_offset_T_6[55:0]; // @[LoopMatmul.scala:551:26] wire [58:0] _dram_offset_T_8 = {1'h0, _dram_offset_T_7, 2'h0}; // @[LoopMatmul.scala:551:{26,31}] wire [61:0] _dram_offset_T_9 = {1'h0, _dram_offset_T_8, 2'h0}; // @[LoopMatmul.scala:551:{31,46}] wire [61:0] dram_offset = req_full_c ? _dram_offset_T_4 : _dram_offset_T_9; // @[LoopMatmul.scala:540:16, :550:{24,78}, :551:46] wire [61:0] _dram_addr_T = {30'h0, dram_offset[31:0]}; // @[LoopMatmul.scala:550:24, :1139:17] wire [62:0] _dram_addr_T_1 = {23'h0, req_dram_addr} + {1'h0, _dram_addr_T}; // @[LoopMatmul.scala:540:16, :552:33, :1139:17] wire [61:0] dram_addr = _dram_addr_T_1[61:0]; // @[LoopMatmul.scala:552:33] wire [31:0] _GEN_5 = {16'h0, i} * {16'h0, req_max_j}; // @[LoopMatmul.scala:540:16, :546:14, :553:37] wire [31:0] _sp_addr_T; // @[LoopMatmul.scala:553:37] assign _sp_addr_T = _GEN_5; // @[LoopMatmul.scala:553:37] wire [31:0] _ln_sp_addr_T; // @[LoopMatmul.scala:587:41] assign _ln_sp_addr_T = _GEN_5; // @[LoopMatmul.scala:553:37, :587:41] wire [32:0] _GEN_6 = {17'h0, j}; // @[LoopMatmul.scala:545:14, :553:49] wire [32:0] _sp_addr_T_1 = {1'h0, _sp_addr_T} + _GEN_6; // @[LoopMatmul.scala:553:{37,49}] wire [31:0] _sp_addr_T_2 = _sp_addr_T_1[31:0]; // @[LoopMatmul.scala:553:49] wire [34:0] _sp_addr_T_3 = {1'h0, _sp_addr_T_2, 2'h0}; // @[LoopMatmul.scala:553:{49,54}] wire [35:0] _sp_addr_T_4 = {24'h0, req_addr_start} + {1'h0, _sp_addr_T_3}; // @[LoopMatmul.scala:540:16, :553:{32,54}] wire [34:0] sp_addr = _sp_addr_T_4[34:0]; // @[LoopMatmul.scala:553:32] wire [16:0] _GEN_7 = {1'h0, j}; // @[LoopMatmul.scala:545:14, :554:22] wire [16:0] _GEN_8 = _GEN_7 + {1'h0, max_blocks}; // @[LoopMatmul.scala:542:23, :554:22] wire [16:0] _blocks_T; // @[LoopMatmul.scala:554:22] assign _blocks_T = _GEN_8; // @[LoopMatmul.scala:554:22] wire [16:0] _ln_norm_cmd_T; // @[LoopMatmul.scala:588:27] assign _ln_norm_cmd_T = _GEN_8; // @[LoopMatmul.scala:554:22, :588:27] wire [16:0] _next_j_T_1; // @[Util.scala:41:15] assign _next_j_T_1 = _GEN_8; // @[Util.scala:41:15] wire [16:0] _next_j_T_4; // @[Util.scala:43:11] assign _next_j_T_4 = _GEN_8; // @[Util.scala:43:11] wire [16:0] _next_j_T_7; // @[Util.scala:41:15] assign _next_j_T_7 = _GEN_8; // @[Util.scala:41:15] wire [16:0] _next_j_T_10; // @[Util.scala:43:11] assign _next_j_T_10 = _GEN_8; // @[Util.scala:43:11] wire [15:0] _blocks_T_1 = _blocks_T[15:0]; // @[LoopMatmul.scala:554:22] wire _blocks_T_2 = _blocks_T_1 <= req_max_j; // @[LoopMatmul.scala:540:16, :554:{22,35}] wire [16:0] _GEN_9 = {1'h0, req_max_j}; // @[LoopMatmul.scala:540:16, :554:70] wire [16:0] _blocks_T_3 = _GEN_9 - _GEN_7; // @[LoopMatmul.scala:554:{22,70}] wire [15:0] _blocks_T_4 = _blocks_T_3[15:0]; // @[LoopMatmul.scala:554:70] wire [15:0] blocks = _blocks_T_2 ? max_blocks : _blocks_T_4; // @[LoopMatmul.scala:542:23, :554:{19,35,70}] wire [18:0] _cols_T = {1'h0, blocks, 2'h0}; // @[LoopMatmul.scala:554:19, :555:22] wire [16:0] _GEN_10 = _GEN_7 + {1'h0, blocks}; // @[LoopMatmul.scala:554:{19,22}, :555:46] wire [16:0] _cols_T_1; // @[LoopMatmul.scala:555:46] assign _cols_T_1 = _GEN_10; // @[LoopMatmul.scala:555:46] wire [16:0] _ex_ahead_T_6; // @[LoopMatmul.scala:630:23] assign _ex_ahead_T_6 = _GEN_10; // @[LoopMatmul.scala:555:46, :630:23] wire [16:0] _ex_ahead_T_9; // @[LoopMatmul.scala:631:27] assign _ex_ahead_T_9 = _GEN_10; // @[LoopMatmul.scala:555:46, :631:27] wire [16:0] _ex_ahead_T_22; // @[LoopMatmul.scala:633:83] assign _ex_ahead_T_22 = _GEN_10; // @[LoopMatmul.scala:555:46, :633:83] wire [15:0] _cols_T_2 = _cols_T_1[15:0]; // @[LoopMatmul.scala:555:46] wire _cols_T_3 = _cols_T_2 >= req_max_j; // @[LoopMatmul.scala:540:16, :555:{46,55}] wire [1:0] _cols_T_4 = _cols_T_3 ? req_pad_j : 2'h0; // @[LoopMatmul.scala:540:16, :555:{43,55}] wire [19:0] _cols_T_5 = {1'h0, _cols_T} - {18'h0, _cols_T_4}; // @[LoopMatmul.scala:555:{22,38,43}] wire [18:0] cols = _cols_T_5[18:0]; // @[LoopMatmul.scala:555:38] wire [16:0] _GEN_11 = {1'h0, req_max_i} - 17'h1; // @[LoopMatmul.scala:540:16, :556:48] wire [16:0] _rows_T; // @[LoopMatmul.scala:556:48] assign _rows_T = _GEN_11; // @[LoopMatmul.scala:556:48] wire [16:0] _next_i_max_T; // @[Util.scala:39:28] assign _next_i_max_T = _GEN_11; // @[Util.scala:39:28] wire [16:0] _next_i_max_T_1; // @[Util.scala:39:28] assign _next_i_max_T_1 = _GEN_11; // @[Util.scala:39:28] wire [15:0] _rows_T_1 = _rows_T[15:0]; // @[LoopMatmul.scala:556:48] wire _rows_T_2 = i == _rows_T_1; // @[LoopMatmul.scala:546:14, :556:{35,48}] wire [1:0] _rows_T_3 = _rows_T_2 ? req_pad_i : 2'h0; // @[LoopMatmul.scala:540:16, :556:{32,35}] wire [3:0] _rows_T_4 = 4'h4 - {2'h0, _rows_T_3}; // @[LoopMatmul.scala:556:{27,32}] wire [2:0] rows = _rows_T_4[2:0]; // @[LoopMatmul.scala:556:27] wire [2:0] mvout_cmd_rs2_num_rows = rows; // @[LoopMatmul.scala:556:27, :563:27] wire [63:0] _mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:568:34] wire [63:0] mvout_cmd_rs1; // @[LoopMatmul.scala:558:23] wire [63:0] mvout_cmd_rs2; // @[LoopMatmul.scala:558:23] assign mvout_cmd_rs1 = {2'h0, dram_addr}; // @[LoopMatmul.scala:552:33, :558:23, :561:17] wire [4:0] mvout_cmd_rs2_lo_hi_1 = mvout_cmd_rs2_num_cols; // @[LoopMatmul.scala:563:27, :568:34] wire [2:0] mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LocalAddr.scala:129:26] wire [2:0] _mvout_cmd_rs2_T = mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:563:27, :568:34] wire mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:129:26] wire [13:0] mvout_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:129:26] wire mvout_cmd_rs2_local_addr_read_full_acc_row; // @[LoopMatmul.scala:563:27] wire mvout_cmd_rs2_local_addr_garbage_bit; // @[LoopMatmul.scala:563:27] wire [13:0] mvout_cmd_rs2_local_addr_data; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_num_cols = cols[4:0]; // @[LoopMatmul.scala:555:38, :563:27, :566:26] wire _mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire [4:0] ln_mvout_cmd_rs2_num_cols = cols[4:0]; // @[LoopMatmul.scala:555:38, :566:26, :613:30] wire _mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_is_acc_addr = _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_accumulate = _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] mvout_cmd_rs2_local_addr_result_result_norm_cmd = _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_garbage_bit = _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvout_cmd_rs2_local_addr_result_result_data = _mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_1 = sp_addr[31:0]; // @[LoopMatmul.scala:553:32] assign _mvout_cmd_rs2_local_addr_result_result_T = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_data = _mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_1 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_2 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_T_3 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_2 = _mvout_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_3 = _mvout_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_4 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_5 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_6 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] assign mvout_cmd_rs2_local_addr_result_norm_cmd = mvout_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_result_garbage_bit = mvout_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_result_data = mvout_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_read_full_acc_row = mvout_cmd_rs2_local_addr_result_read_full_acc_row; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_local_addr_norm_cmd = mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_local_addr_garbage_bit = mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LoopMatmul.scala:563:27] assign mvout_cmd_rs2_local_addr_data = mvout_cmd_rs2_local_addr_result_data; // @[LoopMatmul.scala:563:27] wire [11:0] mvout_cmd_rs2_lo_hi = {11'h0, mvout_cmd_rs2_local_addr_garbage_bit}; // @[LoopMatmul.scala:563:27, :568:34] wire [25:0] mvout_cmd_rs2_lo = {mvout_cmd_rs2_lo_hi, mvout_cmd_rs2_local_addr_data}; // @[LoopMatmul.scala:563:27, :568:34] wire [3:0] mvout_cmd_rs2_hi_lo = {mvout_cmd_rs2_local_addr_read_full_acc_row, _mvout_cmd_rs2_T}; // @[LoopMatmul.scala:563:27, :568:34] wire [5:0] mvout_cmd_rs2_hi = {2'h2, mvout_cmd_rs2_hi_lo}; // @[LoopMatmul.scala:568:34] wire [31:0] _mvout_cmd_rs2_T_1 = {mvout_cmd_rs2_hi, mvout_cmd_rs2_lo}; // @[LoopMatmul.scala:568:34] wire [36:0] mvout_cmd_rs2_lo_1 = {mvout_cmd_rs2_lo_hi_1, _mvout_cmd_rs2_T_1}; // @[LoopMatmul.scala:568:34] wire [15:0] mvout_cmd_rs2_hi_hi_1 = {13'h0, mvout_cmd_rs2_num_rows}; // @[LoopMatmul.scala:563:27, :568:34] wire [26:0] mvout_cmd_rs2_hi_1 = {mvout_cmd_rs2_hi_hi_1, 11'h0}; // @[LoopMatmul.scala:568:34] assign _mvout_cmd_rs2_T_2 = {mvout_cmd_rs2_hi_1, mvout_cmd_rs2_lo_1}; // @[LoopMatmul.scala:568:34] assign mvout_cmd_rs2 = _mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:558:23, :568:34] reg [15:0] ln_row; // @[LoopMatmul.scala:571:19] reg [15:0] ln_cmd; // @[LoopMatmul.scala:572:19] reg [15:0] ln_stat_id; // @[LoopMatmul.scala:573:23] wire [16:0] _GEN_12 = {1'h0, ln_row}; // @[LoopMatmul.scala:571:19, :583:30] wire [16:0] _GEN_13 = {14'h0, rows} - _GEN_12; // @[LoopMatmul.scala:556:27, :583:30] wire [16:0] _ln_stat_ids_T; // @[LoopMatmul.scala:583:30] assign _ln_stat_ids_T = _GEN_13; // @[LoopMatmul.scala:583:30] wire [16:0] _ln_stat_ids_T_3; // @[LoopMatmul.scala:583:81] assign _ln_stat_ids_T_3 = _GEN_13; // @[LoopMatmul.scala:583:{30,81}] wire [16:0] _ln_stat_ids_T_1 = _ln_stat_ids_T; // @[LoopMatmul.scala:583:30] wire _ln_stat_ids_T_2 = _ln_stat_ids_T_1 > 17'h2; // @[LoopMatmul.scala:583:{30,40}] wire [16:0] _ln_stat_ids_T_4 = _ln_stat_ids_T_3; // @[LoopMatmul.scala:583:81] wire [16:0] ln_stat_ids = _ln_stat_ids_T_2 ? 17'h2 : _ln_stat_ids_T_4; // @[LoopMatmul.scala:583:{24,40,81}] wire [16:0] _GEN_14 = {1'h0, ln_stat_id}; // @[LoopMatmul.scala:573:23, :585:21] wire [16:0] ln_r = _GEN_12 + _GEN_14; // @[LoopMatmul.scala:583:30, :585:21] wire [32:0] _ln_sp_addr_T_1 = {1'h0, _ln_sp_addr_T} + _GEN_6; // @[LoopMatmul.scala:553:49, :587:{41,53}] wire [35:0] _ln_sp_addr_T_2 = {1'h0, _ln_sp_addr_T_1, 2'h0}; // @[LoopMatmul.scala:587:{53,59}] wire [36:0] _ln_sp_addr_T_3 = {25'h0, req_addr_start} + {1'h0, _ln_sp_addr_T_2}; // @[LoopMatmul.scala:540:16, :587:{35,59}] wire [37:0] ln_sp_addr = {1'h0, _ln_sp_addr_T_3} + {21'h0, ln_r}; // @[LoopMatmul.scala:585:21, :587:{35,74}] wire _ln_norm_cmd_T_1 = _ln_norm_cmd_T >= _GEN_9; // @[LoopMatmul.scala:554:70, :588:{27,41}] wire _GEN_15 = req_act == 3'h2; // @[LoopMatmul.scala:540:16, :589:17] wire _ln_norm_cmd_T_2; // @[LoopMatmul.scala:589:17] assign _ln_norm_cmd_T_2 = _GEN_15; // @[LoopMatmul.scala:589:17] wire _ln_norm_cmd_T_6; // @[LoopMatmul.scala:590:17] assign _ln_norm_cmd_T_6 = _GEN_15; // @[LoopMatmul.scala:589:17, :590:17] wire [1:0] _ln_norm_cmd_T_3 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [1:0] _ln_norm_cmd_T_4 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [1:0] _ln_norm_cmd_T_7 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [1:0] _ln_norm_cmd_T_8 = ln_cmd[1:0]; // @[LoopMatmul.scala:572:19] wire [2:0] _ln_norm_cmd_T_5 = _ln_norm_cmd_T_2 ? _GEN_2[_ln_norm_cmd_T_3] : _GEN_1[_ln_norm_cmd_T_4]; // @[LoopMatmul.scala:589:{8,17}] wire [2:0] _ln_norm_cmd_T_9 = _ln_norm_cmd_T_6 ? _GEN_0[_ln_norm_cmd_T_7] : _GEN[_ln_norm_cmd_T_8]; // @[LoopMatmul.scala:590:{8,17}] wire [2:0] ln_norm_cmd = _ln_norm_cmd_T_1 ? _ln_norm_cmd_T_5 : _ln_norm_cmd_T_9; // @[LoopMatmul.scala:588:{24,41}, :589:8, :590:8] wire [2:0] ln_mvout_cmd_rs2_local_addr_norm_cmd = ln_norm_cmd; // @[LoopMatmul.scala:588:24, :613:30] wire [56:0] _ln_dram_offset_T_1 = {1'h0, _ln_dram_offset_T} + _GEN_4; // @[LoopMatmul.scala:550:58, :593:{28,46}] wire [59:0] _ln_dram_offset_T_2 = {1'h0, _ln_dram_offset_T_1, 2'h0}; // @[LoopMatmul.scala:593:{46,52}] wire [56:0] _ln_dram_offset_T_3 = {40'h0, ln_r} * {17'h0, req_dram_stride}; // @[LoopMatmul.scala:540:16, :550:40, :553:49, :585:21, :593:75] wire [60:0] _ln_dram_offset_T_4 = {1'h0, _ln_dram_offset_T_2} + {4'h0, _ln_dram_offset_T_3}; // @[LoopMatmul.scala:593:{52,67,75}] wire [63:0] ln_dram_offset = {1'h0, _ln_dram_offset_T_4, 2'h0}; // @[LoopMatmul.scala:593:{67,94}] wire [63:0] _ln_dram_addr_T = {32'h0, ln_dram_offset[31:0]}; // @[LoopMatmul.scala:593:94, :1139:17] wire [64:0] _ln_dram_addr_T_1 = {25'h0, req_dram_addr} + {1'h0, _ln_dram_addr_T}; // @[LoopMatmul.scala:540:16, :587:35, :594:36, :1139:17] wire [63:0] ln_dram_addr = _ln_dram_addr_T_1[63:0]; // @[LoopMatmul.scala:594:36] wire [63:0] ln_mvout_cmd_rs1 = ln_dram_addr; // @[LoopMatmul.scala:594:36, :608:26] wire [7:0] ln_config_norm_rs1_norm_stats_id; // @[LoopMatmul.scala:596:32] assign ln_config_norm_rs1_norm_stats_id = ln_stat_id[7:0]; // @[LoopMatmul.scala:573:23, :596:32, :600:36] wire [63:0] _ln_config_norm_rs1_T; // @[LoopMatmul.scala:605:44] wire [63:0] ln_config_norm_rs1; // @[LoopMatmul.scala:602:28] wire [8:0] ln_config_norm_rs1_lo_hi = {1'h0, ln_config_norm_rs1_norm_stats_id}; // @[LoopMatmul.scala:596:32, :605:44] wire [16:0] ln_config_norm_rs1_lo = {ln_config_norm_rs1_lo_hi, 8'h3}; // @[LoopMatmul.scala:605:44] assign _ln_config_norm_rs1_T = {47'h1, ln_config_norm_rs1_lo}; // @[LoopMatmul.scala:605:44] assign ln_config_norm_rs1 = _ln_config_norm_rs1_T; // @[LoopMatmul.scala:602:28, :605:44] wire [63:0] _ln_mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:619:40] wire [63:0] ln_mvout_cmd_rs2; // @[LoopMatmul.scala:608:26] wire [4:0] ln_mvout_cmd_rs2_lo_hi_1 = ln_mvout_cmd_rs2_num_cols; // @[LoopMatmul.scala:613:30, :619:40] wire [2:0] _ln_mvout_cmd_rs2_T = ln_mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:613:30, :619:40] wire ln_mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:129:26] wire [13:0] ln_mvout_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:129:26] wire ln_mvout_cmd_rs2_local_addr_read_full_acc_row; // @[LoopMatmul.scala:613:30] wire ln_mvout_cmd_rs2_local_addr_garbage_bit; // @[LoopMatmul.scala:613:30] wire [13:0] ln_mvout_cmd_rs2_local_addr_data; // @[LoopMatmul.scala:613:30] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_is_acc_addr = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_accumulate = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_read_full_acc_row = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _ln_mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] ln_mvout_cmd_rs2_local_addr_result_result_norm_cmd = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _ln_mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _ln_mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire ln_mvout_cmd_rs2_local_addr_result_result_garbage_bit = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] ln_mvout_cmd_rs2_local_addr_result_result_data = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1 = ln_sp_addr[31:0]; // @[LoopMatmul.scala:587:74] assign _ln_mvout_cmd_rs2_local_addr_result_result_T = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_data = _ln_mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_1 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _ln_mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_2 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage = _ln_mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_T_3 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2 = _ln_mvout_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_4 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _ln_mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_5 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate = _ln_mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_T_6 = _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _ln_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _ln_mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire [2:0] ln_mvout_cmd_rs2_local_addr_result_norm_cmd = ln_mvout_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] assign ln_mvout_cmd_rs2_local_addr_result_garbage_bit = ln_mvout_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] assign ln_mvout_cmd_rs2_local_addr_result_data = ln_mvout_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :129:26] assign ln_mvout_cmd_rs2_local_addr_read_full_acc_row = ln_mvout_cmd_rs2_local_addr_result_read_full_acc_row; // @[LoopMatmul.scala:613:30] assign ln_mvout_cmd_rs2_local_addr_garbage_bit = ln_mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LoopMatmul.scala:613:30] assign ln_mvout_cmd_rs2_local_addr_data = ln_mvout_cmd_rs2_local_addr_result_data; // @[LoopMatmul.scala:613:30] wire [11:0] ln_mvout_cmd_rs2_lo_hi = {11'h0, ln_mvout_cmd_rs2_local_addr_garbage_bit}; // @[LoopMatmul.scala:613:30, :619:40] wire [25:0] ln_mvout_cmd_rs2_lo = {ln_mvout_cmd_rs2_lo_hi, ln_mvout_cmd_rs2_local_addr_data}; // @[LoopMatmul.scala:613:30, :619:40] wire [3:0] ln_mvout_cmd_rs2_hi_lo = {ln_mvout_cmd_rs2_local_addr_read_full_acc_row, _ln_mvout_cmd_rs2_T}; // @[LoopMatmul.scala:613:30, :619:40] wire [5:0] ln_mvout_cmd_rs2_hi = {2'h2, ln_mvout_cmd_rs2_hi_lo}; // @[LoopMatmul.scala:619:40] wire [31:0] _ln_mvout_cmd_rs2_T_1 = {ln_mvout_cmd_rs2_hi, ln_mvout_cmd_rs2_lo}; // @[LoopMatmul.scala:619:40] wire [36:0] ln_mvout_cmd_rs2_lo_1 = {ln_mvout_cmd_rs2_lo_hi_1, _ln_mvout_cmd_rs2_T_1}; // @[LoopMatmul.scala:619:40] assign _ln_mvout_cmd_rs2_T_2 = {27'h800, ln_mvout_cmd_rs2_lo_1}; // @[LoopMatmul.scala:619:40] assign ln_mvout_cmd_rs2 = _ln_mvout_cmd_rs2_T_2; // @[LoopMatmul.scala:608:26, :619:40] assign _io_req_ready_T = ~(|state); // @[LoopMatmul.scala:538:22, :621:25] assign io_req_ready_0 = _io_req_ready_T; // @[LoopMatmul.scala:514:7, :621:25] assign _io_idle_T = ~(|state); // @[LoopMatmul.scala:538:22, :621:25, :624:20] assign io_idle_0 = _io_idle_T; // @[LoopMatmul.scala:514:7, :624:20] wire _ex_ahead_T = req_act != 3'h2; // @[LoopMatmul.scala:540:16, :589:17, :628:15] wire _ex_ahead_T_1 = req_act != 3'h4; // @[LoopMatmul.scala:540:16, :628:53] wire _ex_ahead_T_2 = _ex_ahead_T & _ex_ahead_T_1; // @[LoopMatmul.scala:628:{15,41,53}] wire [16:0] _ex_ahead_T_3 = {1'h0, req_max_k} - 17'h1; // @[LoopMatmul.scala:540:16, :629:30] wire [15:0] _ex_ahead_T_4 = _ex_ahead_T_3[15:0]; // @[LoopMatmul.scala:629:30] wire _ex_ahead_T_5 = io_ex_k_0 == _ex_ahead_T_4; // @[LoopMatmul.scala:514:7, :629:{16,30}] wire [15:0] _ex_ahead_T_7 = _ex_ahead_T_6[15:0]; // @[LoopMatmul.scala:630:23] wire _ex_ahead_T_8 = io_ex_j_0 >= _ex_ahead_T_7; // @[LoopMatmul.scala:514:7, :630:{18,23}] wire [15:0] _ex_ahead_T_10 = _ex_ahead_T_9[15:0]; // @[LoopMatmul.scala:631:27] wire [16:0] _ex_ahead_T_11 = {1'h0, _ex_ahead_T_10} - 17'h1; // @[LoopMatmul.scala:631:{27,36}] wire [15:0] _ex_ahead_T_12 = _ex_ahead_T_11[15:0]; // @[LoopMatmul.scala:631:36] wire _ex_ahead_T_13 = io_ex_j_0 == _ex_ahead_T_12; // @[LoopMatmul.scala:514:7, :631:{21,36}] wire _GEN_16 = io_ex_i_0 > i; // @[LoopMatmul.scala:514:7, :546:14, :631:54] wire _ex_ahead_T_14; // @[LoopMatmul.scala:631:54] assign _ex_ahead_T_14 = _GEN_16; // @[LoopMatmul.scala:631:54] wire _ex_ahead_T_20; // @[LoopMatmul.scala:633:45] assign _ex_ahead_T_20 = _GEN_16; // @[LoopMatmul.scala:631:54, :633:45] wire _ex_ahead_T_15 = _ex_ahead_T_13 & _ex_ahead_T_14; // @[LoopMatmul.scala:631:{21,43,54}] wire _ex_ahead_T_16 = _ex_ahead_T_8 | _ex_ahead_T_15; // @[LoopMatmul.scala:630:{18,32}, :631:43] wire _ex_ahead_T_17 = _ex_ahead_T_5 & _ex_ahead_T_16; // @[LoopMatmul.scala:629:{16,36}, :630:32] wire _ex_ahead_T_18 = _ex_ahead_T_2 & _ex_ahead_T_17; // @[LoopMatmul.scala:628:{41,77}, :629:36] wire _ex_ahead_T_19 = io_ex_completed_0 | _ex_ahead_T_18; // @[LoopMatmul.scala:514:7, :627:43, :628:77] wire ex_ahead; // @[LoopMatmul.scala:627:26] wire _ex_ahead_T_21 = io_ex_i_0 == i; // @[LoopMatmul.scala:514:7, :546:14, :633:61] wire [15:0] _ex_ahead_T_23 = _ex_ahead_T_22[15:0]; // @[LoopMatmul.scala:633:83] wire _ex_ahead_T_24 = io_ex_j_0 >= _ex_ahead_T_23; // @[LoopMatmul.scala:514:7, :633:{78,83}] wire _ex_ahead_T_25 = _ex_ahead_T_21 & _ex_ahead_T_24; // @[LoopMatmul.scala:633:{61,67,78}] wire _ex_ahead_T_26 = _ex_ahead_T_20 | _ex_ahead_T_25; // @[LoopMatmul.scala:633:{45,49,67}] wire _ex_ahead_T_27 = io_ex_completed_0 | _ex_ahead_T_26; // @[LoopMatmul.scala:514:7, :633:{33,49}] assign ex_ahead = req_is_resadd ? _ex_ahead_T_27 : _ex_ahead_T_19; // @[LoopMatmul.scala:540:16, :627:{26,43}, :632:22, :633:{14,33}] wire _io_cmd_valid_T = |state; // @[LoopMatmul.scala:538:22, :621:25, :636:25] wire _io_cmd_valid_T_1 = ~io_rob_overloaded_0; // @[LoopMatmul.scala:514:7, :636:37] wire _io_cmd_valid_T_2 = _io_cmd_valid_T & _io_cmd_valid_T_1; // @[LoopMatmul.scala:636:{25,34,37}] wire _io_cmd_valid_T_3 = _io_cmd_valid_T_2 & ex_ahead; // @[LoopMatmul.scala:627:26, :636:{34,56}] wire _io_cmd_valid_T_4 = |req_dram_addr; // @[LoopMatmul.scala:540:16, :636:85] assign _io_cmd_valid_T_5 = _io_cmd_valid_T_3 & _io_cmd_valid_T_4; // @[LoopMatmul.scala:636:{56,68,85}] assign io_cmd_valid_0 = _io_cmd_valid_T_5; // @[LoopMatmul.scala:514:7, :636:68] wire _io_cmd_bits_T = state == 2'h2; // @[LoopMatmul.scala:538:22, :638:12] wire _io_cmd_bits_T_1 = &state; // @[LoopMatmul.scala:538:22, :639:12] wire [63:0] _io_cmd_bits_T_2_rs1 = _io_cmd_bits_T_1 ? ln_mvout_cmd_rs1 : mvout_cmd_rs1; // @[Mux.scala:126:16] wire [63:0] _io_cmd_bits_T_2_rs2 = _io_cmd_bits_T_1 ? ln_mvout_cmd_rs2 : mvout_cmd_rs2; // @[Mux.scala:126:16] assign _io_cmd_bits_T_3_inst_funct = _io_cmd_bits_T ? 7'h0 : 7'h3; // @[Mux.scala:126:16] assign _io_cmd_bits_T_3_rs1 = _io_cmd_bits_T ? ln_config_norm_rs1 : _io_cmd_bits_T_2_rs1; // @[Mux.scala:126:16] assign _io_cmd_bits_T_3_rs2 = _io_cmd_bits_T ? 64'h0 : _io_cmd_bits_T_2_rs2; // @[Mux.scala:126:16] assign io_cmd_bits_inst_funct_0 = _io_cmd_bits_T_3_inst_funct; // @[Mux.scala:126:16] assign io_cmd_bits_rs1_0 = _io_cmd_bits_T_3_rs1; // @[Mux.scala:126:16] assign io_cmd_bits_rs2_0 = _io_cmd_bits_T_3_rs2; // @[Mux.scala:126:16] wire [15:0] next_i_max = _next_i_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_17 = {1'h0, i} + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_i_T; // @[Util.scala:41:15] assign _next_i_T = _GEN_17; // @[Util.scala:41:15] wire [16:0] _next_i_T_3; // @[Util.scala:43:11] assign _next_i_T_3 = _GEN_17; // @[Util.scala:41:15, :43:11] wire [16:0] _next_i_T_13; // @[Util.scala:41:15] assign _next_i_T_13 = _GEN_17; // @[Util.scala:41:15] wire [16:0] _next_i_T_16; // @[Util.scala:43:11] assign _next_i_T_16 = _GEN_17; // @[Util.scala:41:15, :43:11] wire [15:0] _next_i_T_1 = _next_i_T[15:0]; // @[Util.scala:41:15] wire _next_i_T_4 = _next_i_T_3 > {1'h0, next_i_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_i_T_5 = _next_i_T_4 ? 16'h0 : _next_i_T_1; // @[Mux.scala:126:16] wire [15:0] next_i = _next_i_T_5; // @[Mux.scala:126:16] wire _next_j_T = next_i == 16'h0; // @[Mux.scala:126:16] wire [16:0] _GEN_18 = _GEN_9 - 17'h1; // @[Util.scala:39:28] wire [16:0] _next_j_max_T; // @[Util.scala:39:28] assign _next_j_max_T = _GEN_18; // @[Util.scala:39:28] wire [16:0] _next_j_max_T_1; // @[Util.scala:39:28] assign _next_j_max_T_1 = _GEN_18; // @[Util.scala:39:28] wire [15:0] next_j_max = _next_j_max_T[15:0]; // @[Util.scala:39:28] wire [15:0] _next_j_T_2 = _next_j_T_1[15:0]; // @[Util.scala:41:15] wire _next_j_T_3 = ~_next_j_T; // @[Util.scala:42:8] wire _next_j_T_5 = _next_j_T_4 > {1'h0, next_j_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_j_T_6 = _next_j_T_5 ? 16'h0 : _next_j_T_2; // @[Mux.scala:126:16] wire [15:0] next_j = _next_j_T_3 ? j : _next_j_T_6; // @[Mux.scala:126:16] wire [15:0] next_j_max_1 = _next_j_max_T_1[15:0]; // @[Util.scala:39:28] wire [15:0] _next_j_T_8 = _next_j_T_7[15:0]; // @[Util.scala:41:15] wire _next_j_T_11 = _next_j_T_10 > {1'h0, next_j_max_1}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_j_T_12 = _next_j_T_11 ? 16'h0 : _next_j_T_8; // @[Mux.scala:126:16] wire [15:0] next_j_1 = _next_j_T_12; // @[Mux.scala:126:16] wire _T_22 = next_j_1 == 16'h0; // @[Mux.scala:126:16] wire _next_stat_id_T; // @[LoopMatmul.scala:661:70] assign _next_stat_id_T = _T_22; // @[LoopMatmul.scala:661:70] wire _next_cmd_T; // @[LoopMatmul.scala:662:70] assign _next_cmd_T = _T_22; // @[LoopMatmul.scala:661:70, :662:70] wire _next_row_T; // @[LoopMatmul.scala:663:67] assign _next_row_T = _T_22; // @[LoopMatmul.scala:661:70, :663:67] wire _next_i_T_6; // @[LoopMatmul.scala:665:14] assign _next_i_T_6 = _T_22; // @[LoopMatmul.scala:661:70, :665:14] wire [17:0] _next_stat_id_max_T = {1'h0, ln_stat_ids} - 18'h1; // @[Util.scala:39:28] wire [16:0] next_stat_id_max = _next_stat_id_max_T[16:0]; // @[Util.scala:39:28] wire [16:0] _GEN_19 = _GEN_14 + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_stat_id_T_1; // @[Util.scala:41:15] assign _next_stat_id_T_1 = _GEN_19; // @[Util.scala:41:15] wire [16:0] _next_stat_id_T_4; // @[Util.scala:43:11] assign _next_stat_id_T_4 = _GEN_19; // @[Util.scala:41:15, :43:11] wire [15:0] _next_stat_id_T_2 = _next_stat_id_T_1[15:0]; // @[Util.scala:41:15] wire _next_stat_id_T_3 = ~_next_stat_id_T; // @[Util.scala:42:8] wire _next_stat_id_T_5 = _next_stat_id_T_4 > next_stat_id_max; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_stat_id_T_6 = _next_stat_id_T_5 ? 16'h0 : _next_stat_id_T_2; // @[Mux.scala:126:16] wire [15:0] next_stat_id = _next_stat_id_T_3 ? ln_stat_id : _next_stat_id_T_6; // @[Mux.scala:126:16] wire _T_18 = next_stat_id == 16'h0; // @[Mux.scala:126:16] wire _next_cmd_T_1; // @[LoopMatmul.scala:662:94] assign _next_cmd_T_1 = _T_18; // @[LoopMatmul.scala:662:94] wire _next_row_T_1; // @[LoopMatmul.scala:663:91] assign _next_row_T_1 = _T_18; // @[LoopMatmul.scala:662:94, :663:91] wire _next_i_T_7; // @[LoopMatmul.scala:665:38] assign _next_i_T_7 = _T_18; // @[LoopMatmul.scala:662:94, :665:38] wire _next_cmd_T_2 = _next_cmd_T & _next_cmd_T_1; // @[LoopMatmul.scala:662:{70,78,94}] wire [16:0] _GEN_20 = {1'h0, ln_cmd} + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_cmd_T_3; // @[Util.scala:41:15] assign _next_cmd_T_3 = _GEN_20; // @[Util.scala:41:15] wire [16:0] _next_cmd_T_6; // @[Util.scala:43:11] assign _next_cmd_T_6 = _GEN_20; // @[Util.scala:41:15, :43:11] wire [15:0] _next_cmd_T_4 = _next_cmd_T_3[15:0]; // @[Util.scala:41:15] wire _next_cmd_T_5 = ~_next_cmd_T_2; // @[Util.scala:42:8] wire _next_cmd_T_7 = _next_cmd_T_6 > 17'h2; // @[Util.scala:43:{11,17}] wire [15:0] _next_cmd_T_8 = _next_cmd_T_7 ? 16'h0 : _next_cmd_T_4; // @[Mux.scala:126:16] wire [15:0] next_cmd = _next_cmd_T_5 ? ln_cmd : _next_cmd_T_8; // @[Mux.scala:126:16] wire _next_row_T_2 = _next_row_T & _next_row_T_1; // @[LoopMatmul.scala:663:{67,75,91}] wire _T_16 = next_cmd == 16'h0; // @[Mux.scala:126:16] wire _next_row_T_3; // @[LoopMatmul.scala:663:111] assign _next_row_T_3 = _T_16; // @[LoopMatmul.scala:663:111] wire _next_i_T_9; // @[LoopMatmul.scala:665:58] assign _next_i_T_9 = _T_16; // @[LoopMatmul.scala:663:111, :665:58] wire _next_row_T_4 = _next_row_T_2 & _next_row_T_3; // @[LoopMatmul.scala:663:{75,99,111}] wire [3:0] _next_row_max_T = {1'h0, rows} - 4'h1; // @[Util.scala:39:28] wire [2:0] next_row_max = _next_row_max_T[2:0]; // @[Util.scala:39:28] wire [16:0] _GEN_21 = _GEN_12 + 17'h2; // @[Util.scala:41:15] wire [16:0] _next_row_T_5; // @[Util.scala:41:15] assign _next_row_T_5 = _GEN_21; // @[Util.scala:41:15] wire [16:0] _next_row_T_8; // @[Util.scala:43:11] assign _next_row_T_8 = _GEN_21; // @[Util.scala:41:15, :43:11] wire [15:0] _next_row_T_6 = _next_row_T_5[15:0]; // @[Util.scala:41:15] wire _next_row_T_7 = ~_next_row_T_4; // @[Util.scala:42:8] wire _next_row_T_9 = _next_row_T_8 > {14'h0, next_row_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_row_T_10 = _next_row_T_9 ? 16'h0 : _next_row_T_6; // @[Mux.scala:126:16] wire [15:0] next_row = _next_row_T_7 ? ln_row : _next_row_T_10; // @[Mux.scala:126:16] wire _next_i_T_8 = _next_i_T_6 & _next_i_T_7; // @[LoopMatmul.scala:665:{14,22,38}] wire _next_i_T_10 = _next_i_T_8 & _next_i_T_9; // @[LoopMatmul.scala:665:{22,46,58}] wire _next_i_T_11 = next_row == 16'h0; // @[Mux.scala:126:16] wire _next_i_T_12 = _next_i_T_10 & _next_i_T_11; // @[LoopMatmul.scala:665:{46,66,78}] wire [15:0] next_i_max_1 = _next_i_max_T_1[15:0]; // @[Util.scala:39:28] wire [15:0] _next_i_T_14 = _next_i_T_13[15:0]; // @[Util.scala:41:15] wire _next_i_T_15 = ~_next_i_T_12; // @[Util.scala:42:8] wire _next_i_T_17 = _next_i_T_16 > {1'h0, next_i_max_1}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_i_T_18 = _next_i_T_17 ? 16'h0 : _next_i_T_14; // @[Mux.scala:126:16] wire [15:0] next_i_1 = _next_i_T_15 ? i : _next_i_T_18; // @[Mux.scala:126:16] wire _state_T = io_req_bits_act_0 == 3'h2; // @[LoopMatmul.scala:514:7, :589:17, :682:35] wire _state_T_1 = io_req_bits_act_0 == 3'h4; // @[LoopMatmul.scala:514:7, :682:81] wire _state_T_2 = _state_T | _state_T_1; // @[LoopMatmul.scala:682:{35,61,81}] wire [1:0] _state_T_3 = _state_T_2 ? 2'h2 : 2'h1; // @[LoopMatmul.scala:646:36, :682:{17,61}] wire _T_10 = io_cmd_ready_0 & io_cmd_valid_0; // @[Decoupled.scala:51:35] wire _T_3 = _T_10 & state == 2'h1; // @[Decoupled.scala:51:35] wire _T_9 = _T_10 & _io_cmd_bits_T; // @[Decoupled.scala:51:35] wire _T_12 = _T_10 & (&state); // @[Decoupled.scala:51:35] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoopMatmul.scala:514:7] if (reset) // @[LoopMatmul.scala:514:7] state <= 2'h0; // @[LoopMatmul.scala:538:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[LoopMatmul.scala:538:22, :682:17] else if (|req_dram_addr) begin // @[LoopMatmul.scala:540:16, :636:85] if (_T_3) begin // @[LoopMatmul.scala:646:27] if (_next_j_T & next_j == 16'h0) // @[Mux.scala:126:16] state <= 2'h0; // @[LoopMatmul.scala:538:22] end else if (_T_9) // @[LoopMatmul.scala:657:27] state <= 2'h3; // @[LoopMatmul.scala:538:22] else if (_T_12) begin // @[LoopMatmul.scala:659:27] if (next_i_1 == 16'h0 & _next_i_T_11 & _T_16 & _T_18 & _T_22) // @[Mux.scala:126:16] state <= 2'h0; // @[LoopMatmul.scala:538:22] else if (_T_22) // @[LoopMatmul.scala:661:70] state <= 2'h2; // @[LoopMatmul.scala:538:22] end end else // @[LoopMatmul.scala:636:85] state <= 2'h0; // @[LoopMatmul.scala:538:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_max_k <= io_req_bits_max_k_0; // @[LoopMatmul.scala:514:7, :540:16] req_max_j <= io_req_bits_max_j_0; // @[LoopMatmul.scala:514:7, :540:16] req_max_i <= io_req_bits_max_i_0; // @[LoopMatmul.scala:514:7, :540:16] req_pad_j <= io_req_bits_pad_j_0; // @[LoopMatmul.scala:514:7, :540:16] req_pad_i <= io_req_bits_pad_i_0; // @[LoopMatmul.scala:514:7, :540:16] req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopMatmul.scala:514:7, :540:16] req_dram_stride <= io_req_bits_dram_stride_0; // @[LoopMatmul.scala:514:7, :540:16] req_full_c <= io_req_bits_full_c_0; // @[LoopMatmul.scala:514:7, :540:16] req_act <= io_req_bits_act_0; // @[LoopMatmul.scala:514:7, :540:16] req_addr_start <= io_req_bits_addr_start_0; // @[LoopMatmul.scala:514:7, :540:16] req_loop_id <= io_req_bits_loop_id_0; // @[LoopMatmul.scala:514:7, :540:16] req_is_resadd <= io_req_bits_is_resadd_0; // @[LoopMatmul.scala:514:7, :540:16] j <= 16'h0; // @[LoopMatmul.scala:545:14] i <= 16'h0; // @[LoopMatmul.scala:546:14] ln_row <= 16'h0; // @[LoopMatmul.scala:571:19] ln_cmd <= 16'h0; // @[LoopMatmul.scala:572:19] ln_stat_id <= 16'h0; // @[LoopMatmul.scala:573:23] end else begin // @[Decoupled.scala:51:35] if (|req_dram_addr) begin // @[LoopMatmul.scala:540:16, :636:85] if (_T_3) begin // @[LoopMatmul.scala:646:27] j <= next_j; // @[Mux.scala:126:16] i <= next_i; // @[Mux.scala:126:16] end else if (_T_9 | ~_T_12) begin // @[LoopMatmul.scala:545:14, :546:14, :657:{27,51}, :659:{27,47}] end else begin // @[LoopMatmul.scala:546:14, :657:51, :659:47] j <= next_j_1; // @[Mux.scala:126:16] i <= next_i_1; // @[Mux.scala:126:16] end end if (~(|req_dram_addr) | _T_3 | _T_9 | ~_T_12) begin // @[LoopMatmul.scala:540:16, :545:14, :573:23, :636:85, :644:{23,32}, :646:{27,44}, :657:{27,51}, :659:{27,47}] end else begin // @[LoopMatmul.scala:573:23, :644:32, :646:44, :657:51, :659:47] ln_row <= next_row; // @[Mux.scala:126:16] ln_cmd <= next_cmd; // @[Mux.scala:126:16] ln_stat_id <= next_stat_id; // @[Mux.scala:126:16] end end always @(posedge) assign io_req_ready = io_req_ready_0; // @[LoopMatmul.scala:514:7] assign io_cmd_valid = io_cmd_valid_0; // @[LoopMatmul.scala:514:7] assign io_cmd_bits_inst_funct = io_cmd_bits_inst_funct_0; // @[LoopMatmul.scala:514:7] assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopMatmul.scala:514:7] assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopMatmul.scala:514:7] assign io_idle = io_idle_0; // @[LoopMatmul.scala:514:7] assign io_loop_id = io_loop_id_0; // @[LoopMatmul.scala:514:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module FPToInt_3 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : connect in, io.in.bits reg valid : UInt<1>, clock connect valid, io.in.valid inst dcmp of CompareRecFN_3 connect dcmp.io.a, in.in1 connect dcmp.io.b, in.in2 node _dcmp_io_signaling_T = bits(in.rm, 1, 1) node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0)) connect dcmp.io.signaling, _dcmp_io_signaling_T_1 node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9) node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp) connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T) node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3 node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T) node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1) node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist) node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0) node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1) node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2) node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf) node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5) node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T) node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1) node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut) node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut) node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1) node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_unrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T) node toint_ieee_prevUnrecoded_unrecoded_fractOut = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, toint_ieee_prevUnrecoded_unrecoded_denormFract, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_unrecoded_hi = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, toint_ieee_prevUnrecoded_unrecoded_expOut) node toint_ieee_prevUnrecoded_unrecoded = cat(toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut) node _toint_ieee_prevUnrecoded_prevRecoded_T = bits(toint_ieee_prevRecoded, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_1 = bits(toint_ieee_prevRecoded, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_2 = bits(toint_ieee_prevRecoded, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi = cat(_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1) node toint_ieee_prevUnrecoded_prevRecoded = cat(toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevUnrecoded_prevRecoded, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevUnrecoded_prevRecoded, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut) node toint_ieee_prevUnrecoded_prevUnrecoded = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut) node _toint_ieee_prevUnrecoded_T = shr(toint_ieee_prevUnrecoded_unrecoded, 16) node _toint_ieee_prevUnrecoded_T_1 = bits(toint_ieee_prevRecoded, 31, 29) node _toint_ieee_prevUnrecoded_T_2 = andr(_toint_ieee_prevUnrecoded_T_1) node _toint_ieee_prevUnrecoded_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded, 15, 0) node _toint_ieee_prevUnrecoded_T_4 = mux(_toint_ieee_prevUnrecoded_T_2, toint_ieee_prevUnrecoded_prevUnrecoded, _toint_ieee_prevUnrecoded_T_3) node toint_ieee_prevUnrecoded = cat(_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4) node _toint_ieee_T = shr(toint_ieee_unrecoded, 32) node _toint_ieee_T_1 = bits(in.in1, 63, 61) node _toint_ieee_T_2 = andr(_toint_ieee_T_1) node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0) node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3) node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4) node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 15, 0) node _toint_ieee_T_7 = bits(_toint_ieee_T_6, 15, 15) node _toint_ieee_T_8 = mux(_toint_ieee_T_7, UInt<16>(0hffff), UInt<16>(0h0)) node _toint_ieee_T_9 = cat(_toint_ieee_T_8, _toint_ieee_T_6) node _toint_ieee_T_10 = cat(_toint_ieee_T_9, _toint_ieee_T_9) node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1 node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1) connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7 node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2) node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1) node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1) node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0) node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1) node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8) node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf) node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11) node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2) node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3) node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1) node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1) node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4) node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_unrecoded_denormFract_1, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_unrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1) node toint_ieee_prevUnrecoded_unrecoded_1 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_prevRecoded_T_3 = bits(toint_ieee_prevRecoded_1, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_4 = bits(toint_ieee_prevRecoded_1, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_5 = bits(toint_ieee_prevRecoded_1, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_1 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4) node toint_ieee_prevUnrecoded_prevRecoded_1 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1) node toint_ieee_prevUnrecoded_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_T_5 = shr(toint_ieee_prevUnrecoded_unrecoded_1, 16) node _toint_ieee_prevUnrecoded_T_6 = bits(toint_ieee_prevRecoded_1, 31, 29) node _toint_ieee_prevUnrecoded_T_7 = andr(_toint_ieee_prevUnrecoded_T_6) node _toint_ieee_prevUnrecoded_T_8 = bits(toint_ieee_prevUnrecoded_unrecoded_1, 15, 0) node _toint_ieee_prevUnrecoded_T_9 = mux(_toint_ieee_prevUnrecoded_T_7, toint_ieee_prevUnrecoded_prevUnrecoded_1, _toint_ieee_prevUnrecoded_T_8) node toint_ieee_prevUnrecoded_1 = cat(_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9) node _toint_ieee_T_11 = shr(toint_ieee_unrecoded_1, 32) node _toint_ieee_T_12 = bits(in.in1, 63, 61) node _toint_ieee_T_13 = andr(_toint_ieee_T_12) node _toint_ieee_T_14 = bits(toint_ieee_unrecoded_1, 31, 0) node _toint_ieee_T_15 = mux(_toint_ieee_T_13, toint_ieee_prevUnrecoded_1, _toint_ieee_T_14) node _toint_ieee_T_16 = cat(_toint_ieee_T_11, _toint_ieee_T_15) node _toint_ieee_T_17 = bits(_toint_ieee_T_16, 31, 0) node _toint_ieee_T_18 = cat(_toint_ieee_T_17, _toint_ieee_T_17) node toint_ieee_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_unrecoded_rawIn_2.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_unrecoded_rawIn_2.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_unrecoded_rawIn_2.isZero, toint_ieee_unrecoded_rawIn_isZero_2 node _toint_ieee_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_2.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_unrecoded_rawIn_exp_2) connect toint_ieee_unrecoded_rawIn_2.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_unrecoded_rawIn_2.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_11 node toint_ieee_unrecoded_isSubnormal_2 = lt(toint_ieee_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_4) node toint_ieee_unrecoded_denormShiftDist_2 = tail(_toint_ieee_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_unrecoded_denormFract_T_4 = shr(toint_ieee_unrecoded_rawIn_2.sig, 1) node _toint_ieee_unrecoded_denormFract_T_5 = dshr(_toint_ieee_unrecoded_denormFract_T_4, toint_ieee_unrecoded_denormShiftDist_2) node toint_ieee_unrecoded_denormFract_2 = bits(_toint_ieee_unrecoded_denormFract_T_5, 51, 0) node _toint_ieee_unrecoded_expOut_T_12 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_13 = sub(_toint_ieee_unrecoded_expOut_T_12, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_14 = tail(_toint_ieee_unrecoded_expOut_T_13, 1) node _toint_ieee_unrecoded_expOut_T_15 = mux(toint_ieee_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_14) node _toint_ieee_unrecoded_expOut_T_16 = or(toint_ieee_unrecoded_rawIn_2.isNaN, toint_ieee_unrecoded_rawIn_2.isInf) node _toint_ieee_unrecoded_expOut_T_17 = mux(_toint_ieee_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_2 = or(_toint_ieee_unrecoded_expOut_T_15, _toint_ieee_unrecoded_expOut_T_17) node _toint_ieee_unrecoded_fractOut_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_5 = mux(toint_ieee_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_4) node toint_ieee_unrecoded_fractOut_2 = mux(toint_ieee_unrecoded_isSubnormal_2, toint_ieee_unrecoded_denormFract_2, _toint_ieee_unrecoded_fractOut_T_5) node toint_ieee_unrecoded_hi_2 = cat(toint_ieee_unrecoded_rawIn_2.sign, toint_ieee_unrecoded_expOut_2) node toint_ieee_unrecoded_2 = cat(toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2) node _toint_ieee_prevRecoded_T_6 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_7 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_8 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_2 = cat(_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7) node toint_ieee_prevRecoded_2 = cat(toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(toint_ieee_prevRecoded_2, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevRecoded_2, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevRecoded_2, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_unrecoded_denormFract_2, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_unrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2) node toint_ieee_prevUnrecoded_unrecoded_2 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_prevRecoded_T_6 = bits(toint_ieee_prevRecoded_2, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_7 = bits(toint_ieee_prevRecoded_2, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_8 = bits(toint_ieee_prevRecoded_2, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_2 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7) node toint_ieee_prevUnrecoded_prevRecoded_2 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2) node toint_ieee_prevUnrecoded_prevUnrecoded_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_T_10 = shr(toint_ieee_prevUnrecoded_unrecoded_2, 16) node _toint_ieee_prevUnrecoded_T_11 = bits(toint_ieee_prevRecoded_2, 31, 29) node _toint_ieee_prevUnrecoded_T_12 = andr(_toint_ieee_prevUnrecoded_T_11) node _toint_ieee_prevUnrecoded_T_13 = bits(toint_ieee_prevUnrecoded_unrecoded_2, 15, 0) node _toint_ieee_prevUnrecoded_T_14 = mux(_toint_ieee_prevUnrecoded_T_12, toint_ieee_prevUnrecoded_prevUnrecoded_2, _toint_ieee_prevUnrecoded_T_13) node toint_ieee_prevUnrecoded_2 = cat(_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14) node _toint_ieee_T_19 = shr(toint_ieee_unrecoded_2, 32) node _toint_ieee_T_20 = bits(in.in1, 63, 61) node _toint_ieee_T_21 = andr(_toint_ieee_T_20) node _toint_ieee_T_22 = bits(toint_ieee_unrecoded_2, 31, 0) node _toint_ieee_T_23 = mux(_toint_ieee_T_21, toint_ieee_prevUnrecoded_2, _toint_ieee_T_22) node _toint_ieee_T_24 = cat(_toint_ieee_T_19, _toint_ieee_T_23) node _toint_ieee_T_25 = bits(_toint_ieee_T_24, 63, 0) node _toint_ieee_T_26 = eq(in.typeTagOut, UInt<1>(0h1)) node _toint_ieee_T_27 = mux(_toint_ieee_T_26, _toint_ieee_T_18, _toint_ieee_T_10) node _toint_ieee_T_28 = eq(in.typeTagOut, UInt<2>(0h2)) node _toint_ieee_T_29 = mux(_toint_ieee_T_28, _toint_ieee_T_25, _toint_ieee_T_27) node _toint_ieee_T_30 = eq(in.typeTagOut, UInt<2>(0h3)) node toint_ieee = mux(_toint_ieee_T_30, _toint_ieee_T_25, _toint_ieee_T_29) wire toint : UInt connect toint, toint_ieee node _intType_T = bits(in.fmt, 0, 0) wire intType : UInt<1> connect intType, _intType_T node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp) connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T) node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist) node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0) node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1) node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2) node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf) node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5) node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T) node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1) node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut) node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut) node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1) node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_unrecoded_denormFract, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_unrecoded_hi = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut) node io_out_bits_store_prevUnrecoded_unrecoded = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_prevRecoded_T = bits(io_out_bits_store_prevRecoded, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = bits(io_out_bits_store_prevRecoded, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = bits(io_out_bits_store_prevRecoded, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1) node io_out_bits_store_prevUnrecoded_prevRecoded = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut) node io_out_bits_store_prevUnrecoded_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_T = shr(io_out_bits_store_prevUnrecoded_unrecoded, 16) node _io_out_bits_store_prevUnrecoded_T_1 = bits(io_out_bits_store_prevRecoded, 31, 29) node _io_out_bits_store_prevUnrecoded_T_2 = andr(_io_out_bits_store_prevUnrecoded_T_1) node _io_out_bits_store_prevUnrecoded_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded, 15, 0) node _io_out_bits_store_prevUnrecoded_T_4 = mux(_io_out_bits_store_prevUnrecoded_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded, _io_out_bits_store_prevUnrecoded_T_3) node io_out_bits_store_prevUnrecoded = cat(_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4) node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32) node _io_out_bits_store_T_1 = bits(in.in1, 63, 61) node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1) node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0) node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3) node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4) node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 15, 0) node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6) node _io_out_bits_store_T_8 = cat(_io_out_bits_store_T_7, _io_out_bits_store_T_7) node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1) connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2) node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1) node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1) node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8) node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf) node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11) node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2) node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3) node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1) node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1) node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4) node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_unrecoded_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = bits(io_out_bits_store_prevRecoded_1, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = bits(io_out_bits_store_prevRecoded_1, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = bits(io_out_bits_store_prevRecoded_1, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4) node io_out_bits_store_prevUnrecoded_prevRecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_T_5 = shr(io_out_bits_store_prevUnrecoded_unrecoded_1, 16) node _io_out_bits_store_prevUnrecoded_T_6 = bits(io_out_bits_store_prevRecoded_1, 31, 29) node _io_out_bits_store_prevUnrecoded_T_7 = andr(_io_out_bits_store_prevUnrecoded_T_6) node _io_out_bits_store_prevUnrecoded_T_8 = bits(io_out_bits_store_prevUnrecoded_unrecoded_1, 15, 0) node _io_out_bits_store_prevUnrecoded_T_9 = mux(_io_out_bits_store_prevUnrecoded_T_7, io_out_bits_store_prevUnrecoded_prevUnrecoded_1, _io_out_bits_store_prevUnrecoded_T_8) node io_out_bits_store_prevUnrecoded_1 = cat(_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9) node _io_out_bits_store_T_9 = shr(io_out_bits_store_unrecoded_1, 32) node _io_out_bits_store_T_10 = bits(in.in1, 63, 61) node _io_out_bits_store_T_11 = andr(_io_out_bits_store_T_10) node _io_out_bits_store_T_12 = bits(io_out_bits_store_unrecoded_1, 31, 0) node _io_out_bits_store_T_13 = mux(_io_out_bits_store_T_11, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_12) node _io_out_bits_store_T_14 = cat(_io_out_bits_store_T_9, _io_out_bits_store_T_13) node _io_out_bits_store_T_15 = bits(_io_out_bits_store_T_14, 31, 0) node _io_out_bits_store_T_16 = cat(_io_out_bits_store_T_15, _io_out_bits_store_T_15) node io_out_bits_store_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_unrecoded_rawIn_2.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_unrecoded_rawIn_2.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_unrecoded_rawIn_2.isZero, io_out_bits_store_unrecoded_rawIn_isZero_2 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_2.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_unrecoded_rawIn_exp_2) connect io_out_bits_store_unrecoded_rawIn_2.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_unrecoded_rawIn_2.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_unrecoded_isSubnormal_2 = lt(io_out_bits_store_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_4) node io_out_bits_store_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_unrecoded_denormFract_T_4 = shr(io_out_bits_store_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_unrecoded_denormFract_T_4, io_out_bits_store_unrecoded_denormShiftDist_2) node io_out_bits_store_unrecoded_denormFract_2 = bits(_io_out_bits_store_unrecoded_denormFract_T_5, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_12 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_13 = sub(_io_out_bits_store_unrecoded_expOut_T_12, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_14 = tail(_io_out_bits_store_unrecoded_expOut_T_13, 1) node _io_out_bits_store_unrecoded_expOut_T_15 = mux(io_out_bits_store_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_14) node _io_out_bits_store_unrecoded_expOut_T_16 = or(io_out_bits_store_unrecoded_rawIn_2.isNaN, io_out_bits_store_unrecoded_rawIn_2.isInf) node _io_out_bits_store_unrecoded_expOut_T_17 = mux(_io_out_bits_store_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_2 = or(_io_out_bits_store_unrecoded_expOut_T_15, _io_out_bits_store_unrecoded_expOut_T_17) node _io_out_bits_store_unrecoded_fractOut_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_5 = mux(io_out_bits_store_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_4) node io_out_bits_store_unrecoded_fractOut_2 = mux(io_out_bits_store_unrecoded_isSubnormal_2, io_out_bits_store_unrecoded_denormFract_2, _io_out_bits_store_unrecoded_fractOut_T_5) node io_out_bits_store_unrecoded_hi_2 = cat(io_out_bits_store_unrecoded_rawIn_2.sign, io_out_bits_store_unrecoded_expOut_2) node io_out_bits_store_unrecoded_2 = cat(io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2) node _io_out_bits_store_prevRecoded_T_6 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_7 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_8 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_2 = cat(_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7) node io_out_bits_store_prevRecoded_2 = cat(io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevRecoded_2, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevRecoded_2, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevRecoded_2, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_unrecoded_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = bits(io_out_bits_store_prevRecoded_2, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = bits(io_out_bits_store_prevRecoded_2, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = bits(io_out_bits_store_prevRecoded_2, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7) node io_out_bits_store_prevUnrecoded_prevRecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_T_10 = shr(io_out_bits_store_prevUnrecoded_unrecoded_2, 16) node _io_out_bits_store_prevUnrecoded_T_11 = bits(io_out_bits_store_prevRecoded_2, 31, 29) node _io_out_bits_store_prevUnrecoded_T_12 = andr(_io_out_bits_store_prevUnrecoded_T_11) node _io_out_bits_store_prevUnrecoded_T_13 = bits(io_out_bits_store_prevUnrecoded_unrecoded_2, 15, 0) node _io_out_bits_store_prevUnrecoded_T_14 = mux(_io_out_bits_store_prevUnrecoded_T_12, io_out_bits_store_prevUnrecoded_prevUnrecoded_2, _io_out_bits_store_prevUnrecoded_T_13) node io_out_bits_store_prevUnrecoded_2 = cat(_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14) node _io_out_bits_store_T_17 = shr(io_out_bits_store_unrecoded_2, 32) node _io_out_bits_store_T_18 = bits(in.in1, 63, 61) node _io_out_bits_store_T_19 = andr(_io_out_bits_store_T_18) node _io_out_bits_store_T_20 = bits(io_out_bits_store_unrecoded_2, 31, 0) node _io_out_bits_store_T_21 = mux(_io_out_bits_store_T_19, io_out_bits_store_prevUnrecoded_2, _io_out_bits_store_T_20) node _io_out_bits_store_T_22 = cat(_io_out_bits_store_T_17, _io_out_bits_store_T_21) node _io_out_bits_store_T_23 = bits(_io_out_bits_store_T_22, 63, 0) node _io_out_bits_store_T_24 = eq(in.typeTagOut, UInt<1>(0h1)) node _io_out_bits_store_T_25 = mux(_io_out_bits_store_T_24, _io_out_bits_store_T_16, _io_out_bits_store_T_8) node _io_out_bits_store_T_26 = eq(in.typeTagOut, UInt<2>(0h2)) node _io_out_bits_store_T_27 = mux(_io_out_bits_store_T_26, _io_out_bits_store_T_23, _io_out_bits_store_T_25) node _io_out_bits_store_T_28 = eq(in.typeTagOut, UInt<2>(0h3)) node _io_out_bits_store_T_29 = mux(_io_out_bits_store_T_28, _io_out_bits_store_T_23, _io_out_bits_store_T_27) connect io.out.bits.store, _io_out_bits_store_T_29 node _io_out_bits_toint_T = bits(toint, 31, 0) node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31) node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T) node _io_out_bits_toint_T_4 = bits(toint, 63, 0) node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1)) node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3) connect io.out.bits.toint, _io_out_bits_toint_T_6 connect io.out.bits.exc, UInt<1>(0h0) node _T = bits(in.rm, 0, 0) when _T : node classify_out_sign = bits(in.in1, 64, 64) node classify_out_fractIn = bits(in.in1, 51, 0) node classify_out_expIn = bits(in.in1, 63, 52) node _classify_out_fractOut_T = shl(classify_out_fractIn, 11) node classify_out_fractOut = shr(_classify_out_fractOut_T, 53) node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9) node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<6>(0h20)) node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1) node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800)) node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1) node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0)) node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6)) node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1) node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 2, 0) node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3) node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 5, 0) node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5) node classify_out_hi = cat(classify_out_sign, classify_out_expOut) node _classify_out_T = cat(classify_out_hi, classify_out_fractOut) node classify_out_sign_1 = bits(_classify_out_T, 16, 16) node classify_out_code = bits(_classify_out_T, 15, 13) node classify_out_codeHi = bits(classify_out_code, 2, 1) node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 13, 10) node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2)) node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1)) node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn) node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2) node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0)) node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1) node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2)) node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3) node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0)) node _classify_out_isInf_T = bits(classify_out_code, 0, 0) node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0)) node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1) node classify_out_isNaN = andr(classify_out_code) node _classify_out_isSNaN_T = bits(_classify_out_T, 9, 9) node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0)) node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1) node _classify_out_isQNaN_T = bits(_classify_out_T, 9, 9) node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T) node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1) node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3) node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5) node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7) node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1) node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1) node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1) node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1) node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12) node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9) node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10) node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo) node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6) node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN) node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2) node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo) node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo) node classify_out_sign_2 = bits(in.in1, 64, 64) node classify_out_fractIn_1 = bits(in.in1, 51, 0) node classify_out_expIn_1 = bits(in.in1, 63, 52) node _classify_out_fractOut_T_1 = shl(classify_out_fractIn_1, 24) node classify_out_fractOut_1 = shr(_classify_out_fractOut_T_1, 53) node classify_out_expOut_expCode_1 = bits(classify_out_expIn_1, 11, 9) node _classify_out_expOut_commonCase_T_3 = add(classify_out_expIn_1, UInt<9>(0h100)) node _classify_out_expOut_commonCase_T_4 = tail(_classify_out_expOut_commonCase_T_3, 1) node _classify_out_expOut_commonCase_T_5 = sub(_classify_out_expOut_commonCase_T_4, UInt<12>(0h800)) node classify_out_expOut_commonCase_1 = tail(_classify_out_expOut_commonCase_T_5, 1) node _classify_out_expOut_T_6 = eq(classify_out_expOut_expCode_1, UInt<1>(0h0)) node _classify_out_expOut_T_7 = geq(classify_out_expOut_expCode_1, UInt<3>(0h6)) node _classify_out_expOut_T_8 = or(_classify_out_expOut_T_6, _classify_out_expOut_T_7) node _classify_out_expOut_T_9 = bits(classify_out_expOut_commonCase_1, 5, 0) node _classify_out_expOut_T_10 = cat(classify_out_expOut_expCode_1, _classify_out_expOut_T_9) node _classify_out_expOut_T_11 = bits(classify_out_expOut_commonCase_1, 8, 0) node classify_out_expOut_1 = mux(_classify_out_expOut_T_8, _classify_out_expOut_T_10, _classify_out_expOut_T_11) node classify_out_hi_2 = cat(classify_out_sign_2, classify_out_expOut_1) node _classify_out_T_14 = cat(classify_out_hi_2, classify_out_fractOut_1) node classify_out_sign_3 = bits(_classify_out_T_14, 32, 32) node classify_out_code_1 = bits(_classify_out_T_14, 31, 29) node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1) node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_1 = bits(_classify_out_T_14, 29, 23) node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2)) node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1) node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5) node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0)) node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5) node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2)) node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7) node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0)) node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0) node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0)) node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3) node classify_out_isNaN_1 = andr(classify_out_code_1) node _classify_out_isSNaN_T_2 = bits(_classify_out_T_14, 22, 22) node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0)) node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3) node _classify_out_isQNaN_T_1 = bits(_classify_out_T_14, 22, 22) node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1) node _classify_out_T_15 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_16 = and(classify_out_isInf_1, _classify_out_T_15) node _classify_out_T_17 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_18 = and(classify_out_isNormal_1, _classify_out_T_17) node _classify_out_T_19 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_20 = and(classify_out_isSubnormal_1, _classify_out_T_19) node _classify_out_T_21 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_22 = and(classify_out_isZero_1, _classify_out_T_21) node _classify_out_T_23 = and(classify_out_isZero_1, classify_out_sign_3) node _classify_out_T_24 = and(classify_out_isSubnormal_1, classify_out_sign_3) node _classify_out_T_25 = and(classify_out_isNormal_1, classify_out_sign_3) node _classify_out_T_26 = and(classify_out_isInf_1, classify_out_sign_3) node classify_out_lo_lo_1 = cat(_classify_out_T_25, _classify_out_T_26) node classify_out_lo_hi_hi_1 = cat(_classify_out_T_22, _classify_out_T_23) node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_24) node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1) node classify_out_hi_lo_1 = cat(_classify_out_T_18, _classify_out_T_20) node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1) node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_16) node classify_out_hi_3 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1) node _classify_out_T_27 = cat(classify_out_hi_3, classify_out_lo_1) node classify_out_sign_4 = bits(in.in1, 64, 64) node classify_out_code_2 = bits(in.in1, 63, 61) node classify_out_codeHi_2 = bits(classify_out_code_2, 2, 1) node classify_out_isSpecial_2 = eq(classify_out_codeHi_2, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_2 = bits(in.in1, 61, 52) node classify_out_isHighSubnormalIn_2 = lt(_classify_out_isHighSubnormalIn_T_2, UInt<2>(0h2)) node _classify_out_isSubnormal_T_6 = eq(classify_out_code_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_7 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_8 = and(_classify_out_isSubnormal_T_7, classify_out_isHighSubnormalIn_2) node classify_out_isSubnormal_2 = or(_classify_out_isSubnormal_T_6, _classify_out_isSubnormal_T_8) node _classify_out_isNormal_T_8 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isNormal_T_9 = eq(classify_out_isHighSubnormalIn_2, UInt<1>(0h0)) node _classify_out_isNormal_T_10 = and(_classify_out_isNormal_T_8, _classify_out_isNormal_T_9) node _classify_out_isNormal_T_11 = eq(classify_out_codeHi_2, UInt<2>(0h2)) node classify_out_isNormal_2 = or(_classify_out_isNormal_T_10, _classify_out_isNormal_T_11) node classify_out_isZero_2 = eq(classify_out_code_2, UInt<1>(0h0)) node _classify_out_isInf_T_4 = bits(classify_out_code_2, 0, 0) node _classify_out_isInf_T_5 = eq(_classify_out_isInf_T_4, UInt<1>(0h0)) node classify_out_isInf_2 = and(classify_out_isSpecial_2, _classify_out_isInf_T_5) node classify_out_isNaN_2 = andr(classify_out_code_2) node _classify_out_isSNaN_T_4 = bits(in.in1, 51, 51) node _classify_out_isSNaN_T_5 = eq(_classify_out_isSNaN_T_4, UInt<1>(0h0)) node classify_out_isSNaN_2 = and(classify_out_isNaN_2, _classify_out_isSNaN_T_5) node _classify_out_isQNaN_T_2 = bits(in.in1, 51, 51) node classify_out_isQNaN_2 = and(classify_out_isNaN_2, _classify_out_isQNaN_T_2) node _classify_out_T_28 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_29 = and(classify_out_isInf_2, _classify_out_T_28) node _classify_out_T_30 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_31 = and(classify_out_isNormal_2, _classify_out_T_30) node _classify_out_T_32 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_33 = and(classify_out_isSubnormal_2, _classify_out_T_32) node _classify_out_T_34 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_35 = and(classify_out_isZero_2, _classify_out_T_34) node _classify_out_T_36 = and(classify_out_isZero_2, classify_out_sign_4) node _classify_out_T_37 = and(classify_out_isSubnormal_2, classify_out_sign_4) node _classify_out_T_38 = and(classify_out_isNormal_2, classify_out_sign_4) node _classify_out_T_39 = and(classify_out_isInf_2, classify_out_sign_4) node classify_out_lo_lo_2 = cat(_classify_out_T_38, _classify_out_T_39) node classify_out_lo_hi_hi_2 = cat(_classify_out_T_35, _classify_out_T_36) node classify_out_lo_hi_2 = cat(classify_out_lo_hi_hi_2, _classify_out_T_37) node classify_out_lo_2 = cat(classify_out_lo_hi_2, classify_out_lo_lo_2) node classify_out_hi_lo_2 = cat(_classify_out_T_31, _classify_out_T_33) node classify_out_hi_hi_hi_2 = cat(classify_out_isQNaN_2, classify_out_isSNaN_2) node classify_out_hi_hi_2 = cat(classify_out_hi_hi_hi_2, _classify_out_T_29) node classify_out_hi_4 = cat(classify_out_hi_hi_2, classify_out_hi_lo_2) node _classify_out_T_40 = cat(classify_out_hi_4, classify_out_lo_2) node _classify_out_T_41 = eq(in.typeTagOut, UInt<1>(0h1)) node _classify_out_T_42 = mux(_classify_out_T_41, _classify_out_T_27, _classify_out_T_13) node _classify_out_T_43 = eq(in.typeTagOut, UInt<2>(0h2)) node _classify_out_T_44 = mux(_classify_out_T_43, _classify_out_T_40, _classify_out_T_42) node _classify_out_T_45 = eq(in.typeTagOut, UInt<2>(0h3)) node classify_out = mux(_classify_out_T_45, _classify_out_T_40, _classify_out_T_44) node _toint_T = shr(toint_ieee, 32) node _toint_T_1 = shl(_toint_T, 32) node _toint_T_2 = or(classify_out, _toint_T_1) connect toint, _toint_T_2 connect intType, UInt<1>(0h0) when in.wflags : node _toint_T_3 = not(in.rm) node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq) node _toint_T_5 = and(_toint_T_3, _toint_T_4) node _toint_T_6 = orr(_toint_T_5) node _toint_T_7 = shr(toint_ieee, 32) node _toint_T_8 = shl(_toint_T_7, 32) node _toint_T_9 = or(_toint_T_6, _toint_T_8) connect toint, _toint_T_9 connect io.out.bits.exc, dcmp.io.exceptionFlags connect intType, UInt<1>(0h0) node _T_1 = eq(in.ren2, UInt<1>(0h0)) when _T_1 : node cvtType = bits(in.typ, 1, 1) connect intType, cvtType inst conv of RecFNToIN_e11_s53_i64_3 connect conv.clock, clock connect conv.reset, reset connect conv.io.in, in.in1 connect conv.io.roundingMode, in.rm node _conv_io_signedOut_T = bits(in.typ, 0, 0) node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T) connect conv.io.signedOut, _conv_io_signedOut_T_1 connect toint, conv.io.out node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1) node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T) node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0) node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0)) node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2) connect io.out.bits.exc, _io_out_bits_exc_T_3 node _T_2 = eq(cvtType, UInt<1>(0h0)) when _T_2 : inst narrow of RecFNToIN_e11_s53_i32_3 connect narrow.clock, clock connect narrow.reset, reset connect narrow.io.in, in.in1 connect narrow.io.roundingMode, in.rm node _narrow_io_signedOut_T = bits(in.typ, 0, 0) node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T) connect narrow.io.signedOut, _narrow_io_signedOut_T_1 node _excSign_T = bits(in.in1, 64, 64) node _excSign_T_1 = bits(in.in1, 63, 61) node _excSign_T_2 = andr(_excSign_T_1) node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0)) node excSign = and(_excSign_T, _excSign_T_3) node _excOut_T = eq(conv.io.signedOut, excSign) node _excOut_T_1 = eq(excSign, UInt<1>(0h0)) node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0)) node excOut = cat(_excOut_T, _excOut_T_2) node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2) node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1) node invalid = or(_invalid_T, _invalid_T_1) when invalid : node _toint_T_10 = shr(conv.io.out, 32) node _toint_T_11 = cat(_toint_T_10, excOut) connect toint, _toint_T_11 node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0)) node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0) node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5) node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0)) node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6) connect io.out.bits.exc, _io_out_bits_exc_T_7 connect io.out.valid, valid node _io_out_bits_lt_T = asSInt(dcmp.io.a) node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b) node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3) node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4) connect io.out.bits.lt, _io_out_bits_lt_T_5 connect io.out.bits.in, in

module FPToInt_3( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input reset, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ldst, // @[FPU.scala:461:14] input io_in_bits_wen, // @[FPU.scala:461:14] input io_in_bits_ren1, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input io_in_bits_ren3, // @[FPU.scala:461:14] input io_in_bits_swap12, // @[FPU.scala:461:14] input io_in_bits_swap23, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_fromint, // @[FPU.scala:461:14] input io_in_bits_toint, // @[FPU.scala:461:14] input io_in_bits_fastpipe, // @[FPU.scala:461:14] input io_in_bits_fma, // @[FPU.scala:461:14] input io_in_bits_div, // @[FPU.scala:461:14] input io_in_bits_sqrt, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input io_in_bits_vec, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] input [64:0] io_in_bits_in3, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2, // @[FPU.scala:461:14] output io_out_bits_lt, // @[FPU.scala:461:14] output [63:0] io_out_bits_store, // @[FPU.scala:461:14] output [63:0] io_out_bits_toint, // @[FPU.scala:461:14] output [4:0] io_out_bits_exc // @[FPU.scala:461:14] ); wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:453:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:453:7] wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32] wire [63:0] _io_out_bits_store_T_29; // @[package.scala:39:76] wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76] wire io_out_bits_in_ldst; // @[FPU.scala:453:7] wire io_out_bits_in_wen; // @[FPU.scala:453:7] wire io_out_bits_in_ren1; // @[FPU.scala:453:7] wire io_out_bits_in_ren2; // @[FPU.scala:453:7] wire io_out_bits_in_ren3; // @[FPU.scala:453:7] wire io_out_bits_in_swap12; // @[FPU.scala:453:7] wire io_out_bits_in_swap23; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagOut; // @[FPU.scala:453:7] wire io_out_bits_in_fromint; // @[FPU.scala:453:7] wire io_out_bits_in_toint; // @[FPU.scala:453:7] wire io_out_bits_in_fastpipe; // @[FPU.scala:453:7] wire io_out_bits_in_fma; // @[FPU.scala:453:7] wire io_out_bits_in_div; // @[FPU.scala:453:7] wire io_out_bits_in_sqrt; // @[FPU.scala:453:7] wire io_out_bits_in_wflags; // @[FPU.scala:453:7] wire io_out_bits_in_vec; // @[FPU.scala:453:7] wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typ; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmt; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in3; // @[FPU.scala:453:7] wire io_out_bits_lt_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_store_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_toint_0; // @[FPU.scala:453:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:453:7] wire io_out_valid; // @[FPU.scala:453:7] reg in_ldst; // @[FPU.scala:466:21] assign io_out_bits_in_ldst = in_ldst; // @[FPU.scala:453:7, :466:21] reg in_wen; // @[FPU.scala:466:21] assign io_out_bits_in_wen = in_wen; // @[FPU.scala:453:7, :466:21] reg in_ren1; // @[FPU.scala:466:21] assign io_out_bits_in_ren1 = in_ren1; // @[FPU.scala:453:7, :466:21] reg in_ren2; // @[FPU.scala:466:21] assign io_out_bits_in_ren2 = in_ren2; // @[FPU.scala:453:7, :466:21] reg in_ren3; // @[FPU.scala:466:21] assign io_out_bits_in_ren3 = in_ren3; // @[FPU.scala:453:7, :466:21] reg in_swap12; // @[FPU.scala:466:21] assign io_out_bits_in_swap12 = in_swap12; // @[FPU.scala:453:7, :466:21] reg in_swap23; // @[FPU.scala:466:21] assign io_out_bits_in_swap23 = in_swap23; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagIn; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagIn = in_typeTagIn; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagOut = in_typeTagOut; // @[FPU.scala:453:7, :466:21] reg in_fromint; // @[FPU.scala:466:21] assign io_out_bits_in_fromint = in_fromint; // @[FPU.scala:453:7, :466:21] reg in_toint; // @[FPU.scala:466:21] assign io_out_bits_in_toint = in_toint; // @[FPU.scala:453:7, :466:21] reg in_fastpipe; // @[FPU.scala:466:21] assign io_out_bits_in_fastpipe = in_fastpipe; // @[FPU.scala:453:7, :466:21] reg in_fma; // @[FPU.scala:466:21] assign io_out_bits_in_fma = in_fma; // @[FPU.scala:453:7, :466:21] reg in_div; // @[FPU.scala:466:21] assign io_out_bits_in_div = in_div; // @[FPU.scala:453:7, :466:21] reg in_sqrt; // @[FPU.scala:466:21] assign io_out_bits_in_sqrt = in_sqrt; // @[FPU.scala:453:7, :466:21] reg in_wflags; // @[FPU.scala:466:21] assign io_out_bits_in_wflags = in_wflags; // @[FPU.scala:453:7, :466:21] reg in_vec; // @[FPU.scala:466:21] assign io_out_bits_in_vec = in_vec; // @[FPU.scala:453:7, :466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmaCmd; // @[FPU.scala:466:21] assign io_out_bits_in_fmaCmd = in_fmaCmd; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] assign io_out_bits_in_typ = in_typ; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmt; // @[FPU.scala:466:21] assign io_out_bits_in_fmt = in_fmt; // @[FPU.scala:453:7, :466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46] reg [64:0] in_in2; // @[FPU.scala:466:21] assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72] reg [64:0] in_in3; // @[FPU.scala:466:21] assign io_out_bits_in_in3 = in_in3; // @[FPU.scala:453:7, :466:21] reg valid; // @[FPU.scala:467:22] assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22] wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30] wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}] wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [11:0] classify_out_expIn_1 = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_4 = in_in1[64]; // @[FPU.scala:253:17, :466:21] wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31] assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] wire [51:0] classify_out_fractIn_1 = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN | toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 | _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? toint_ieee_prevUnrecoded_unrecoded_denormFract : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi = {toint_ieee_prevUnrecoded_unrecoded_rawIn_sign, toint_ieee_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded = {toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T = toint_ieee_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_1 = toint_ieee_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_2 = toint_ieee_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi = {_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded = {toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = toint_ieee_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded = {toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T = toint_ieee_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_1 = toint_ieee_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_2 = &_toint_ieee_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_3 = toint_ieee_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_4 = _toint_ieee_prevUnrecoded_T_2 ? toint_ieee_prevUnrecoded_prevUnrecoded : _toint_ieee_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded = {_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_12 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_20 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_10 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_18 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] classify_out_code_2 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21] wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _toint_ieee_T_6 = _toint_ieee_T_5[15:0]; // @[FPU.scala:446:10, :475:107] wire _toint_ieee_T_7 = _toint_ieee_T_6[15]; // @[package.scala:132:38] wire [15:0] _toint_ieee_T_8 = {16{_toint_ieee_T_7}}; // @[package.scala:132:{20,38}] wire [31:0] _toint_ieee_T_9 = {_toint_ieee_T_8, _toint_ieee_T_6}; // @[package.scala:132:{15,20}] wire [63:0] _toint_ieee_T_10 = {2{_toint_ieee_T_9}}; // @[package.scala:132:15] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN | toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 | _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_1 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_1 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_1 = {toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_3 = toint_ieee_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_4 = toint_ieee_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_5 = toint_ieee_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_1 = {_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_1 = {toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_5 = toint_ieee_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_6 = toint_ieee_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_7 = &_toint_ieee_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_8 = toint_ieee_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_9 = _toint_ieee_prevUnrecoded_T_7 ? toint_ieee_prevUnrecoded_prevUnrecoded_1 : _toint_ieee_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_1 = {_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_13 = &_toint_ieee_T_12; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_14 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_15 = _toint_ieee_T_13 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_14; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_16 = {_toint_ieee_T_11, _toint_ieee_T_15}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_17 = _toint_ieee_T_16[31:0]; // @[FPU.scala:446:10, :476:109] wire [63:0] _toint_ieee_T_18 = {2{_toint_ieee_T_17}}; // @[FPU.scala:476:{63,109}] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_2 = _toint_ieee_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_2_isZero = toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_2_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_2_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_2_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_2_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_2_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_4 = toint_ieee_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_2 = _toint_ieee_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_4 = toint_ieee_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_5 = _toint_ieee_unrecoded_denormFract_T_4 >> toint_ieee_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_2 = _toint_ieee_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_12 = toint_ieee_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_14 = _toint_ieee_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_15 = toint_ieee_unrecoded_isSubnormal_2 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_16 = toint_ieee_unrecoded_rawIn_2_isNaN | toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_17 = {11{_toint_ieee_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_2 = _toint_ieee_unrecoded_expOut_T_15 | _toint_ieee_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_4 = toint_ieee_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_5 = toint_ieee_unrecoded_rawIn_2_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_2 = toint_ieee_unrecoded_isSubnormal_2 ? toint_ieee_unrecoded_denormFract_2 : _toint_ieee_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_2 = {toint_ieee_unrecoded_rawIn_2_sign, toint_ieee_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_2 = {toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_2 = {_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_2 = {toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = toint_ieee_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = toint_ieee_prevRecoded_2[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = toint_ieee_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_2 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_2 = {toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_6 = toint_ieee_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_7 = toint_ieee_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_8 = toint_ieee_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_2 = {_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_2 = {toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = toint_ieee_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = toint_ieee_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = toint_ieee_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_10 = toint_ieee_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_11 = toint_ieee_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_12 = &_toint_ieee_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_13 = toint_ieee_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_14 = _toint_ieee_prevUnrecoded_T_12 ? toint_ieee_prevUnrecoded_prevUnrecoded_2 : _toint_ieee_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_2 = {_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_19 = toint_ieee_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_21 = &_toint_ieee_T_20; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_22 = toint_ieee_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_23 = _toint_ieee_T_21 ? toint_ieee_prevUnrecoded_2 : _toint_ieee_T_22; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_24 = {_toint_ieee_T_19, _toint_ieee_T_23}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _toint_ieee_T_25 = _toint_ieee_T_24; // @[FPU.scala:446:10, :476:109] wire _GEN = in_typeTagOut == 2'h1; // @[package.scala:39:86] wire _toint_ieee_T_26; // @[package.scala:39:86] assign _toint_ieee_T_26 = _GEN; // @[package.scala:39:86] wire _io_out_bits_store_T_24; // @[package.scala:39:86] assign _io_out_bits_store_T_24 = _GEN; // @[package.scala:39:86] wire _classify_out_T_41; // @[package.scala:39:86] assign _classify_out_T_41 = _GEN; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_27 = _toint_ieee_T_26 ? _toint_ieee_T_18 : _toint_ieee_T_10; // @[package.scala:39:{76,86}] wire _GEN_0 = in_typeTagOut == 2'h2; // @[package.scala:39:86] wire _toint_ieee_T_28; // @[package.scala:39:86] assign _toint_ieee_T_28 = _GEN_0; // @[package.scala:39:86] wire _io_out_bits_store_T_26; // @[package.scala:39:86] assign _io_out_bits_store_T_26 = _GEN_0; // @[package.scala:39:86] wire _classify_out_T_43; // @[package.scala:39:86] assign _classify_out_T_43 = _GEN_0; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_29 = _toint_ieee_T_28 ? _toint_ieee_T_25 : _toint_ieee_T_27; // @[package.scala:39:{76,86}] wire _toint_ieee_T_30 = &in_typeTagOut; // @[package.scala:39:86] wire [63:0] toint_ieee = _toint_ieee_T_30 ? _toint_ieee_T_25 : _toint_ieee_T_29; // @[package.scala:39:{76,86}] wire [63:0] toint; // @[FPU.scala:478:26] wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59] wire _intType_T = in_fmt[0]; // @[FPU.scala:466:21, :479:35] wire intType; // @[FPU.scala:479:28] wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN | io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 | _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded = {io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T = io_out_bits_store_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = io_out_bits_store_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = io_out_bits_store_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi = {_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded = {io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = io_out_bits_store_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T = io_out_bits_store_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_1 = io_out_bits_store_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_2 = &_io_out_bits_store_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_3 = io_out_bits_store_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_4 = _io_out_bits_store_prevUnrecoded_T_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded : _io_out_bits_store_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded = {_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[15:0]; // @[FPU.scala:446:10, :480:82] wire [31:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}] wire [63:0] _io_out_bits_store_T_8 = {2{_io_out_bits_store_T_7}}; // @[FPU.scala:480:49] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN | io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 | _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_1 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = io_out_bits_store_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = io_out_bits_store_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = io_out_bits_store_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_1 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_6 = io_out_bits_store_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_7 = &_io_out_bits_store_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_9 = _io_out_bits_store_prevUnrecoded_T_7 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_1 : _io_out_bits_store_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_1 = {_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_9 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_11 = &_io_out_bits_store_T_10; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_12 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_13 = _io_out_bits_store_T_11 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_12; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_14 = {_io_out_bits_store_T_9, _io_out_bits_store_T_13}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_15 = _io_out_bits_store_T_14[31:0]; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_16 = {2{_io_out_bits_store_T_15}}; // @[FPU.scala:480:{49,82}] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_2 = _io_out_bits_store_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_2_isZero = io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_2_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_2_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_2_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_2_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_2_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_4 = io_out_bits_store_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_2 = _io_out_bits_store_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_5 = _io_out_bits_store_unrecoded_denormFract_T_4 >> io_out_bits_store_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_2 = _io_out_bits_store_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_12 = io_out_bits_store_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_14 = _io_out_bits_store_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_15 = io_out_bits_store_unrecoded_isSubnormal_2 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_16 = io_out_bits_store_unrecoded_rawIn_2_isNaN | io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_17 = {11{_io_out_bits_store_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_2 = _io_out_bits_store_unrecoded_expOut_T_15 | _io_out_bits_store_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_5 = io_out_bits_store_unrecoded_rawIn_2_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_2 = io_out_bits_store_unrecoded_isSubnormal_2 ? io_out_bits_store_unrecoded_denormFract_2 : _io_out_bits_store_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_2 = {io_out_bits_store_unrecoded_rawIn_2_sign, io_out_bits_store_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_2 = {io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_2 = {_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_2 = {io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = io_out_bits_store_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevRecoded_2[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_2 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = io_out_bits_store_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = io_out_bits_store_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = io_out_bits_store_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_2 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_11 = io_out_bits_store_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_12 = &_io_out_bits_store_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_13 = io_out_bits_store_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_14 = _io_out_bits_store_prevUnrecoded_T_12 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_2 : _io_out_bits_store_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_2 = {_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_17 = io_out_bits_store_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_19 = &_io_out_bits_store_T_18; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_20 = io_out_bits_store_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_21 = _io_out_bits_store_T_19 ? io_out_bits_store_prevUnrecoded_2 : _io_out_bits_store_T_20; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_22 = {_io_out_bits_store_T_17, _io_out_bits_store_T_21}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _io_out_bits_store_T_23 = _io_out_bits_store_T_22; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_25 = _io_out_bits_store_T_24 ? _io_out_bits_store_T_16 : _io_out_bits_store_T_8; // @[package.scala:39:{76,86}] wire [63:0] _io_out_bits_store_T_27 = _io_out_bits_store_T_26 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_25; // @[package.scala:39:{76,86}] wire _io_out_bits_store_T_28 = &in_typeTagOut; // @[package.scala:39:86] assign _io_out_bits_store_T_29 = _io_out_bits_store_T_28 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_27; // @[package.scala:39:{76,86}] assign io_out_bits_store_0 = _io_out_bits_store_T_29; // @[package.scala:39:76] wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59] wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38] wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}] wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}] assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15] assign io_out_bits_toint_0 = _io_out_bits_toint_T_6; // @[package.scala:39:76] wire [62:0] _classify_out_fractOut_T = {classify_out_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] classify_out_fractOut = _classify_out_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_2 = _classify_out_expOut_T | _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_1 = _classify_out_T[16]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code = _classify_out_T[15:13]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28] wire [3:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[13:10]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 4'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_1 = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_1 = _GEN_1; // @[FPU.scala:259:46] wire _classify_out_isNormal_T; // @[FPU.scala:260:27] assign _classify_out_isNormal_T = _GEN_1; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal = _classify_out_isSubnormal_T | _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal = _classify_out_isNormal_T_2 | _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}] wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8] wire [75:0] _classify_out_fractOut_T_1 = {classify_out_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] classify_out_fractOut_1 = _classify_out_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode_1 = classify_out_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T_3 = {1'h0, classify_out_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_4 = _classify_out_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_5 = {1'h0, _classify_out_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase_1 = _classify_out_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T_6 = classify_out_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_7 = classify_out_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_8 = _classify_out_expOut_T_6 | _classify_out_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _classify_out_expOut_T_9 = classify_out_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _classify_out_expOut_T_10 = {classify_out_expOut_expCode_1, _classify_out_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _classify_out_expOut_T_11 = classify_out_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] classify_out_expOut_1 = _classify_out_expOut_T_8 ? _classify_out_expOut_T_10 : _classify_out_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] classify_out_hi_2 = {classify_out_sign_2, classify_out_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _classify_out_T_14 = {classify_out_hi_2, classify_out_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_3 = _classify_out_T_14[32]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code_1 = _classify_out_T_14[31:29]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28] wire [6:0] _classify_out_isHighSubnormalIn_T_1 = _classify_out_T_14[29:23]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 7'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_2 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_4 = _GEN_2; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_4 = _GEN_2; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 | _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 | _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_2 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T_1 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_15 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_16 = classify_out_isInf_1 & _classify_out_T_15; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_17 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_18 = classify_out_isNormal_1 & _classify_out_T_17; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_19 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_20 = classify_out_isSubnormal_1 & _classify_out_T_19; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_21 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_22 = classify_out_isZero_1 & _classify_out_T_21; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_23 = classify_out_isZero_1 & classify_out_sign_3; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_24 = classify_out_isSubnormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_25 = classify_out_isNormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_26 = classify_out_isInf_1 & classify_out_sign_3; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_25, _classify_out_T_26}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_22, _classify_out_T_23}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_24}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_18, _classify_out_T_20}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_16}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_3 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_27 = {classify_out_hi_3, classify_out_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_codeHi_2 = classify_out_code_2[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_2 = &classify_out_codeHi_2; // @[FPU.scala:255:22, :256:28] wire [9:0] _classify_out_isHighSubnormalIn_T_2 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21] wire classify_out_isHighSubnormalIn_2 = _classify_out_isHighSubnormalIn_T_2 < 10'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_6 = classify_out_code_2 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_3 = classify_out_codeHi_2 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_7; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_7 = _GEN_3; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_8; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_8 = _GEN_3; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_8 = _classify_out_isSubnormal_T_7 & classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_2 = _classify_out_isSubnormal_T_6 | _classify_out_isSubnormal_T_8; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_9 = ~classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_10 = _classify_out_isNormal_T_8 & _classify_out_isNormal_T_9; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_11 = classify_out_codeHi_2 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_2 = _classify_out_isNormal_T_10 | _classify_out_isNormal_T_11; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_2 = classify_out_code_2 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_4 = classify_out_code_2[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_5 = ~_classify_out_isInf_T_4; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_2 = classify_out_isSpecial_2 & _classify_out_isInf_T_5; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_2 = &classify_out_code_2; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_4 = in_in1[51]; // @[FPU.scala:264:29, :466:21] wire _classify_out_isQNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21] wire _classify_out_isSNaN_T_5 = ~_classify_out_isSNaN_T_4; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_2 = classify_out_isNaN_2 & _classify_out_isSNaN_T_5; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_2 = classify_out_isNaN_2 & _classify_out_isQNaN_T_2; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_28 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_29 = classify_out_isInf_2 & _classify_out_T_28; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_30 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_31 = classify_out_isNormal_2 & _classify_out_T_30; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_32 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_33 = classify_out_isSubnormal_2 & _classify_out_T_32; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_34 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_35 = classify_out_isZero_2 & _classify_out_T_34; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_36 = classify_out_isZero_2 & classify_out_sign_4; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_37 = classify_out_isSubnormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_38 = classify_out_isNormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_39 = classify_out_isInf_2 & classify_out_sign_4; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_2 = {_classify_out_T_38, _classify_out_T_39}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_2 = {_classify_out_T_35, _classify_out_T_36}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_2 = {classify_out_lo_hi_hi_2, _classify_out_T_37}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_2 = {classify_out_lo_hi_2, classify_out_lo_lo_2}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_2 = {_classify_out_T_31, _classify_out_T_33}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_2 = {classify_out_isQNaN_2, classify_out_isSNaN_2}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_2 = {classify_out_hi_hi_hi_2, _classify_out_T_29}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_4 = {classify_out_hi_hi_2, classify_out_hi_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_40 = {classify_out_hi_4, classify_out_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_42 = _classify_out_T_41 ? _classify_out_T_27 : _classify_out_T_13; // @[package.scala:39:{76,86}] wire [9:0] _classify_out_T_44 = _classify_out_T_43 ? _classify_out_T_40 : _classify_out_T_42; // @[package.scala:39:{76,86}] wire _classify_out_T_45 = &in_typeTagOut; // @[package.scala:39:86] wire [9:0] classify_out = _classify_out_T_45 ? _classify_out_T_40 : _classify_out_T_44; // @[package.scala:39:{76,86}] wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76] wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76] wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}] wire [63:0] _toint_T_2 = {54'h0, classify_out} | _toint_T_1; // @[package.scala:39:76] wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15] wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27] wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}] wire _toint_T_6 = |_toint_T_5; // @[FPU.scala:491:{22,53}] wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}] wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} | _toint_T_8; // @[FPU.scala:491:{53,57,82}] wire cvtType = in_typ[1]; // @[package.scala:163:13] assign intType = in_wflags ? ~in_ren2 & cvtType : ~(in_rm[0]) & _intType_T; // @[package.scala:163:13] wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41] wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}] wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55] wire _io_out_bits_exc_T_1 = |_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}] wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102] wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90] wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}] wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}] wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}] wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}] wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62] wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}] wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46] wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69] wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}] wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}] wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50] wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84] wire invalid = _invalid_T | _invalid_T_1; // @[FPU.scala:515:{50,54,84}] wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53] wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}] assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13] wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53] wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}] wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33] wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}] assign io_out_bits_exc_0 = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13] wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}] wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}] wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}] assign _io_out_bits_lt_T_5 = _dcmp_io_lt | _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}] assign io_out_bits_lt_0 = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid_0) begin // @[FPU.scala:453:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21] in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21] in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21] in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21] in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21] in_vec <= io_in_bits_vec_0; // @[FPU.scala:453:7, :466:21] in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:453:7, :466:21] in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:453:7, :466:21] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21] in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21] in_in3 <= io_in_bits_in3_0; // @[FPU.scala:453:7, :466:21] end valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22] always @(posedge) CompareRecFN_3 dcmp ( // @[FPU.scala:469:20] .io_a (in_in1), // @[FPU.scala:466:21] .io_b (in_in2), // @[FPU.scala:466:21] .io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24] .io_lt (_dcmp_io_lt), .io_eq (_dcmp_io_eq), .io_exceptionFlags (_dcmp_io_exceptionFlags) ); // @[FPU.scala:469:20] RecFNToIN_e11_s53_i64_3 conv ( // @[FPU.scala:498:24] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28] .io_out (_conv_io_out), .io_intExceptionFlags (_conv_io_intExceptionFlags) ); // @[FPU.scala:498:24] RecFNToIN_e11_s53_i32_3 narrow ( // @[FPU.scala:508:30] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34] .io_intExceptionFlags (_narrow_io_intExceptionFlags) ); // @[FPU.scala:508:30] assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7] assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7] assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7] assign io_out_bits_lt = io_out_bits_lt_0; // @[FPU.scala:453:7] assign io_out_bits_store = io_out_bits_store_0; // @[FPU.scala:453:7] assign io_out_bits_toint = io_out_bits_toint_0; // @[FPU.scala:453:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:453:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget16 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_3 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a29d128s6k1z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 127, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<4>(0hf), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 3, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 3, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) wire repeat_anonOut_a_bits_data_mux : UInt<64>[2] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[2] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<4>(0hf), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 3, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<1>, clock, reset, UInt<1>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[1], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLWidthWidget16( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [15:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71] wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24] wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24] wire repeat_sel = cated_bits_address[3]; // @[WidthWidget.scala:116:39, :161:25] wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [18:0] _limit_T = 19'hF << anonOut_d_bits_size; // @[package.scala:243:71] wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire limit = _limit_T_2[3]; // @[package.scala:243:46] reg count; // @[WidthWidget.scala:40:27] wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = ~count; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56] wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24] wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] always @(posedge) TLMonitor_3 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a29d128s6k1z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_104 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_4.bits.sink, UInt<5>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_248 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_249 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_104( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module SBToTL : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} input rf_reset : Reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset sbState : UInt, clock, reset, UInt<1>(0h0) inst d_q of Queue2_TLBundleD_a32d8s1k3z4u connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect d_q.io.enq.bits.data, nodeOut.d.bits.data connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect d_q.io.enq.bits.source, nodeOut.d.bits.source connect d_q.io.enq.bits.size, nodeOut.d.bits.size connect d_q.io.enq.bits.param, nodeOut.d.bits.param connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, d_q.io.enq.ready node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 wire muxedData : UInt<8> connect muxedData, UInt<8>(0h0) regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) wire vecData : UInt<8>[8] node _vecData_0_T = bits(io.dataIn, 7, 0) connect vecData[0], _vecData_0_T node _vecData_1_T = bits(io.dataIn, 15, 8) connect vecData[1], _vecData_1_T node _vecData_2_T = bits(io.dataIn, 23, 16) connect vecData[2], _vecData_2_T node _vecData_3_T = bits(io.dataIn, 31, 24) connect vecData[3], _vecData_3_T node _vecData_4_T = bits(io.dataIn, 39, 32) connect vecData[4], _vecData_4_T node _vecData_5_T = bits(io.dataIn, 47, 40) connect vecData[5], _vecData_5_T node _vecData_6_T = bits(io.dataIn, 55, 48) connect vecData[6], _vecData_6_T node _vecData_7_T = bits(io.dataIn, 63, 56) connect vecData[7], _vecData_7_T node _muxedData_T = bits(counter, 2, 0) connect muxedData, vecData[_muxedData_T] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2400)) node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<9>(0h100))) node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<18>(0h2f000))) node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<28>(0hc000000)) node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44) node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<27>(0h4000000))) node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46) node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<29>(0h10020000)) node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49) node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51) node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _rdLegal_addr_T_55 = cvt(_rdLegal_addr_T_54) node _rdLegal_addr_T_56 = and(_rdLegal_addr_T_55, asSInt(UInt<29>(0h10000000))) node _rdLegal_addr_T_57 = asSInt(_rdLegal_addr_T_56) node _rdLegal_addr_T_58 = eq(_rdLegal_addr_T_57, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_59 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) node _rdLegal_addr_T_60 = or(_rdLegal_addr_T_59, _rdLegal_addr_T_18) node _rdLegal_addr_T_61 = or(_rdLegal_addr_T_60, _rdLegal_addr_T_23) node _rdLegal_addr_T_62 = or(_rdLegal_addr_T_61, _rdLegal_addr_T_28) node _rdLegal_addr_T_63 = or(_rdLegal_addr_T_62, _rdLegal_addr_T_33) node _rdLegal_addr_T_64 = or(_rdLegal_addr_T_63, _rdLegal_addr_T_38) node _rdLegal_addr_T_65 = or(_rdLegal_addr_T_64, _rdLegal_addr_T_43) node _rdLegal_addr_T_66 = or(_rdLegal_addr_T_65, _rdLegal_addr_T_48) node _rdLegal_addr_T_67 = or(_rdLegal_addr_T_66, _rdLegal_addr_T_53) node _rdLegal_addr_T_68 = or(_rdLegal_addr_T_67, _rdLegal_addr_T_58) node _rdLegal_addr_T_69 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_68) node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_69) node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h2400)) node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<9>(0h100))) node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<14>(0h3000)) node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<18>(0h2f000))) node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2010000)) node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0hc000000)) node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39) node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<27>(0h4000000))) node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41) node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h10020000)) node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44) node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46) node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) node _wrLegal_addr_T_50 = cvt(_wrLegal_addr_T_49) node _wrLegal_addr_T_51 = and(_wrLegal_addr_T_50, asSInt(UInt<29>(0h10000000))) node _wrLegal_addr_T_52 = asSInt(_wrLegal_addr_T_51) node _wrLegal_addr_T_53 = eq(_wrLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_54 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) node _wrLegal_addr_T_55 = or(_wrLegal_addr_T_54, _wrLegal_addr_T_18) node _wrLegal_addr_T_56 = or(_wrLegal_addr_T_55, _wrLegal_addr_T_23) node _wrLegal_addr_T_57 = or(_wrLegal_addr_T_56, _wrLegal_addr_T_28) node _wrLegal_addr_T_58 = or(_wrLegal_addr_T_57, _wrLegal_addr_T_33) node _wrLegal_addr_T_59 = or(_wrLegal_addr_T_58, _wrLegal_addr_T_38) node _wrLegal_addr_T_60 = or(_wrLegal_addr_T_59, _wrLegal_addr_T_43) node _wrLegal_addr_T_61 = or(_wrLegal_addr_T_60, _wrLegal_addr_T_48) node _wrLegal_addr_T_62 = or(_wrLegal_addr_T_61, _wrLegal_addr_T_53) node _wrLegal_addr_T_63 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_62) node _wrLegal_addr_T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) node _wrLegal_addr_T_65 = xor(io.addrIn, UInt<17>(0h10000)) node _wrLegal_addr_T_66 = cvt(_wrLegal_addr_T_65) node _wrLegal_addr_T_67 = and(_wrLegal_addr_T_66, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_68 = asSInt(_wrLegal_addr_T_67) node _wrLegal_addr_T_69 = eq(_wrLegal_addr_T_68, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_70 = and(_wrLegal_addr_T_64, _wrLegal_addr_T_69) node _wrLegal_addr_T_71 = or(UInt<1>(0h0), _wrLegal_addr_T_63) node wrLegal_addr = or(_wrLegal_addr_T_71, _wrLegal_addr_T_70) node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) node _gbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) node _gbits_legal_T_24 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h98013000))) node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) node _gbits_legal_T_29 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) node _gbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2000000)) node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) node _gbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) node _gbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_45 = cvt(_gbits_legal_T_44) node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46) node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0))) node _gbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _gbits_legal_T_50 = cvt(_gbits_legal_T_49) node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51) node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0))) node _gbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _gbits_legal_T_55 = cvt(_gbits_legal_T_54) node _gbits_legal_T_56 = and(_gbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _gbits_legal_T_57 = asSInt(_gbits_legal_T_56) node _gbits_legal_T_58 = eq(_gbits_legal_T_57, asSInt(UInt<1>(0h0))) node _gbits_legal_T_59 = or(_gbits_legal_T_18, _gbits_legal_T_23) node _gbits_legal_T_60 = or(_gbits_legal_T_59, _gbits_legal_T_28) node _gbits_legal_T_61 = or(_gbits_legal_T_60, _gbits_legal_T_33) node _gbits_legal_T_62 = or(_gbits_legal_T_61, _gbits_legal_T_38) node _gbits_legal_T_63 = or(_gbits_legal_T_62, _gbits_legal_T_43) node _gbits_legal_T_64 = or(_gbits_legal_T_63, _gbits_legal_T_48) node _gbits_legal_T_65 = or(_gbits_legal_T_64, _gbits_legal_T_53) node _gbits_legal_T_66 = or(_gbits_legal_T_65, _gbits_legal_T_58) node _gbits_legal_T_67 = and(_gbits_legal_T_13, _gbits_legal_T_66) node _gbits_legal_T_68 = or(UInt<1>(0h0), _gbits_legal_T_9) node gbits_legal = or(_gbits_legal_T_68, _gbits_legal_T_67) wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect gbits.opcode, UInt<3>(0h4) connect gbits.param, UInt<1>(0h0) connect gbits.size, io.sizeIn connect gbits.source, UInt<1>(0h0) connect gbits.address, io.addrIn node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect gbits.mask, UInt<1>(0h1) invalidate gbits.data connect gbits.corrupt, UInt<1>(0h0) node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_19 = xor(io.addrIn, UInt<14>(0h2000)) node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h9a103000))) node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39) node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0h98000000))) node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41) node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44) node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46) node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10000000)) node _pfbits_legal_T_50 = cvt(_pfbits_legal_T_49) node _pfbits_legal_T_51 = and(_pfbits_legal_T_50, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_52 = asSInt(_pfbits_legal_T_51) node _pfbits_legal_T_53 = eq(_pfbits_legal_T_52, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _pfbits_legal_T_55 = cvt(_pfbits_legal_T_54) node _pfbits_legal_T_56 = and(_pfbits_legal_T_55, asSInt(UInt<33>(0h90000000))) node _pfbits_legal_T_57 = asSInt(_pfbits_legal_T_56) node _pfbits_legal_T_58 = eq(_pfbits_legal_T_57, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_59 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) node _pfbits_legal_T_60 = or(_pfbits_legal_T_59, _pfbits_legal_T_28) node _pfbits_legal_T_61 = or(_pfbits_legal_T_60, _pfbits_legal_T_33) node _pfbits_legal_T_62 = or(_pfbits_legal_T_61, _pfbits_legal_T_38) node _pfbits_legal_T_63 = or(_pfbits_legal_T_62, _pfbits_legal_T_43) node _pfbits_legal_T_64 = or(_pfbits_legal_T_63, _pfbits_legal_T_48) node _pfbits_legal_T_65 = or(_pfbits_legal_T_64, _pfbits_legal_T_53) node _pfbits_legal_T_66 = or(_pfbits_legal_T_65, _pfbits_legal_T_58) node _pfbits_legal_T_67 = and(_pfbits_legal_T_13, _pfbits_legal_T_66) node _pfbits_legal_T_68 = or(UInt<1>(0h0), UInt<1>(0h0)) node _pfbits_legal_T_69 = xor(io.addrIn, UInt<17>(0h10000)) node _pfbits_legal_T_70 = cvt(_pfbits_legal_T_69) node _pfbits_legal_T_71 = and(_pfbits_legal_T_70, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_72 = asSInt(_pfbits_legal_T_71) node _pfbits_legal_T_73 = eq(_pfbits_legal_T_72, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_74 = and(_pfbits_legal_T_68, _pfbits_legal_T_73) node _pfbits_legal_T_75 = or(UInt<1>(0h0), _pfbits_legal_T_9) node _pfbits_legal_T_76 = or(_pfbits_legal_T_75, _pfbits_legal_T_67) node pfbits_legal = or(_pfbits_legal_T_76, _pfbits_legal_T_74) wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect pfbits.opcode, UInt<1>(0h0) connect pfbits.param, UInt<1>(0h0) connect pfbits.size, io.sizeIn connect pfbits.source, UInt<1>(0h0) connect pfbits.address, io.addrIn node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect pfbits.mask, UInt<1>(0h1) connect pfbits.data, muxedData connect pfbits.corrupt, UInt<1>(0h0) connect io.rdLegal, rdLegal_addr connect io.wrLegal, wrLegal_addr connect io.sbStateOut, sbState node _T = eq(sbState, UInt<1>(0h1)) when _T : connect nodeOut.a.bits, gbits else : connect nodeOut.a.bits, pfbits node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) connect io.respError, respError node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) node _txLast_T_2 = tail(_txLast_T_1, 1) node txLast = eq(counter, _txLast_T_2) node _counter_T = or(wrTxValid, rdTxValid) node _counter_T_1 = and(_counter_T, txLast) node _counter_T_2 = or(wrTxValid, rdTxValid) node _counter_T_3 = add(counter, UInt<1>(0h1)) node _counter_T_4 = tail(_counter_T_3, 1) node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) connect counter, _counter_T_6 node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) connect io.rdLoad[0], _io_rdLoad_0_T_1 node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) connect io.rdLoad[1], _io_rdLoad_1_T_1 node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) connect io.rdLoad[2], _io_rdLoad_2_T_1 node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) connect io.rdLoad[3], _io_rdLoad_3_T_1 node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) connect io.rdLoad[4], _io_rdLoad_4_T_1 node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) connect io.rdLoad[5], _io_rdLoad_5_T_1 node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) connect io.rdLoad[6], _io_rdLoad_6_T_1 node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) connect io.rdLoad[7], _io_rdLoad_7_T_1 node _T_1 = eq(sbState, UInt<1>(0h0)) when _T_1 : node _sbState_T = and(io.rdEn, io.rdLegal) node _sbState_T_1 = and(io.wrEn, io.wrLegal) node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) connect sbState, _sbState_T_3 else : node _T_2 = eq(sbState, UInt<1>(0h1)) when _T_2 : node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) connect sbState, _sbState_T_5 else : node _T_3 = eq(sbState, UInt<2>(0h2)) when _T_3 : node _sbState_T_6 = and(wrTxValid, txLast) node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) connect sbState, _sbState_T_7 else : node _T_4 = eq(sbState, UInt<2>(0h3)) when _T_4 : node _sbState_T_8 = and(rdTxValid, txLast) node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) connect sbState, _sbState_T_9 else : node _T_5 = eq(sbState, UInt<3>(0h4)) when _T_5 : node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) connect sbState, _sbState_T_11 node _io_rdDone_T = and(rdTxValid, txLast) connect io.rdDone, _io_rdDone_T node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) connect io.wrDone, _io_wrDone_T_2 connect io.dataOut, d_q.io.deq.bits.data node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T_6 = eq(sbState, UInt<1>(0h0)) node _T_7 = eq(sbState, UInt<1>(0h1)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(sbState, UInt<2>(0h2)) node _T_10 = or(_T_8, _T_9) node _T_11 = eq(sbState, UInt<2>(0h3)) node _T_12 = or(_T_10, _T_11) node _T_13 = eq(sbState, UInt<3>(0h4)) node _T_14 = or(_T_12, _T_13) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert node _T_18 = eq(sbState, UInt<1>(0h0)) node _T_19 = eq(sbState, UInt<1>(0h1)) node _T_20 = eq(sbState, UInt<2>(0h2)) node _T_21 = eq(sbState, UInt<2>(0h3)) node _T_22 = eq(sbState, UInt<3>(0h4)) node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) node _T_24 = and(io.rdEn, _T_23) node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) node _T_26 = and(io.wrEn, _T_25) extmodule plusarg_reader_97 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module SBToTL( // @[SBA.scala:273:9] input clock, // @[SBA.scala:273:9] input reset, // @[SBA.scala:273:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_rdEn, // @[SBA.scala:274:16] input io_wrEn, // @[SBA.scala:274:16] input [127:0] io_addrIn, // @[SBA.scala:274:16] input [127:0] io_dataIn, // @[SBA.scala:274:16] input [2:0] io_sizeIn, // @[SBA.scala:274:16] output io_rdLegal, // @[SBA.scala:274:16] output io_wrLegal, // @[SBA.scala:274:16] output io_rdDone, // @[SBA.scala:274:16] output io_wrDone, // @[SBA.scala:274:16] output io_respError, // @[SBA.scala:274:16] output [7:0] io_dataOut, // @[SBA.scala:274:16] output io_rdLoad_0, // @[SBA.scala:274:16] output io_rdLoad_1, // @[SBA.scala:274:16] output io_rdLoad_2, // @[SBA.scala:274:16] output io_rdLoad_3, // @[SBA.scala:274:16] output io_rdLoad_4, // @[SBA.scala:274:16] output io_rdLoad_5, // @[SBA.scala:274:16] output io_rdLoad_6, // @[SBA.scala:274:16] output io_rdLoad_7, // @[SBA.scala:274:16] output [2:0] io_sbStateOut // @[SBA.scala:274:16] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] reg [2:0] sbState; // @[SBA.scala:295:26] wire _rdTxValid_T = sbState == 3'h3; // @[SBA.scala:295:26, :299:25] wire _io_wrDone_T = sbState == 3'h4; // @[SBA.scala:295:26, :299:62] wire d_q_io_deq_ready = _rdTxValid_T | _io_wrDone_T; // @[SBA.scala:299:{25,50,62}] reg [3:0] counter; // @[SBA.scala:307:26] wire [7:0][7:0] _GEN = {{io_dataIn[63:56]}, {io_dataIn[55:48]}, {io_dataIn[47:40]}, {io_dataIn[39:32]}, {io_dataIn[31:24]}, {io_dataIn[23:16]}, {io_dataIn[15:8]}, {io_dataIn[7:0]}}; // @[SBA.scala:309:63, :310:15] wire [119:0] _GEN_0 = {io_addrIn[127:14], io_addrIn[13:8] ^ 6'h24}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_1 = {io_addrIn[127:14], ~(io_addrIn[13:12])}; // @[Parameters.scala:137:{31,41,46}] wire [114:0] _GEN_2 = {io_addrIn[127:21], io_addrIn[20:17] ^ 4'h8, io_addrIn[15:12]}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_3 = {io_addrIn[127:26], io_addrIn[25:16] ^ 10'h200}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_4 = {io_addrIn[127:26], io_addrIn[25:12] ^ 14'h2010}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_5 = {io_addrIn[127:28], io_addrIn[27:16] ^ 12'h800}; // @[Parameters.scala:137:{31,41,46}] wire [101:0] _GEN_6 = {io_addrIn[127:28], ~(io_addrIn[27:26])}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_7 = {io_addrIn[127:29], io_addrIn[28:12] ^ 17'h10020}; // @[Parameters.scala:137:{31,41,46}] wire [99:0] _GEN_8 = {io_addrIn[127:32], io_addrIn[31:28] ^ 4'h8}; // @[Parameters.scala:137:{31,41,46}] wire io_rdLegal_0 = ~(|(io_addrIn[127:13])) | ~(|_GEN_0) | ~(|_GEN_1) | {io_addrIn[127:17], ~(io_addrIn[16])} == 112'h0 | ~(|_GEN_2) | ~(|_GEN_3) | ~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8); // @[Parameters.scala:685:42] wire io_wrLegal_0 = ~(|(io_addrIn[127:13])) | ~(|_GEN_0) | ~(|_GEN_1) | ~(|_GEN_2) | ~(|_GEN_3) | ~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8); // @[Parameters.scala:685:42] wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18] wire _nodeOut_a_valid_T_1 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29] wire rdTxValid = _rdTxValid_T & _d_q_io_deq_valid & d_q_io_deq_ready; // @[Decoupled.scala:362:21] wire txLast = {4'h0, counter} == (8'h1 << io_sizeIn) - 8'h1; // @[SBA.scala:307:26, :340:{29,39,53}] wire _GEN_9 = sbState == 3'h0; // @[SBA.scala:295:26, :349:19] wire nodeOut_a_valid = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[SBA.scala:322:18, :338:29, :366:52]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_211 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_211( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_174 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_189 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_174( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_189 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_24 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_25 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_65 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_65( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_6 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 1, 0) node _req_clientBit_T = shr(request.source, 2) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0ha)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<2>(0h2)) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 1, 0) node _req_clientBit_T_6 = shr(request.source, 2) node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<4>(0h8)) node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8) node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<2>(0h2)) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 1, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 2) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0ha)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<2>(0h2)) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 1, 0) node _probe_bit_T_6 = shr(io.sinkc.bits.source, 2) node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<4>(0h8)) node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8) node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<2>(0h2)) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 1, 0) node _new_clientBit_T = shr(new_request.source, 2) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0ha)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<2>(0h2)) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 1, 0) node _new_clientBit_T_6 = shr(new_request.source, 2) node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<4>(0h8)) node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8) node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<2>(0h2)) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_6( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53] wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [5:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [5:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_6 = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = _req_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_6 = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = _probe_bit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [5:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_6 = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = _new_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_55 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_55( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_4 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_4 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_4 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id) when _T_11 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) node _T_12 = eq(UInt<2>(0h3), io.in.flit[0].bits.flow.egress_node_id) when _T_12 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) node _T_13 = eq(UInt<3>(0h4), io.in.flit[0].bits.flow.egress_node_id) when _T_13 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_14 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_14 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_15 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_15 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_16 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_16 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_17 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_17 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_18 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_18 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_19 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_19 : connect states[5].g, UInt<3>(0h2) connect route_arbiter.io.in[6].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[6].bits.flow.egress_node_id invalidate route_arbiter.io.in[6].bits.flow.egress_node invalidate route_arbiter.io.in[6].bits.flow.ingress_node_id invalidate route_arbiter.io.in[6].bits.flow.ingress_node invalidate route_arbiter.io.in[6].bits.flow.vnet_id invalidate route_arbiter.io.in[6].bits.src_virt_id connect route_arbiter.io.in[7].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[7].bits.flow.egress_node_id invalidate route_arbiter.io.in[7].bits.flow.egress_node invalidate route_arbiter.io.in[7].bits.flow.ingress_node_id invalidate route_arbiter.io.in[7].bits.flow.ingress_node invalidate route_arbiter.io.in[7].bits.flow.vnet_id invalidate route_arbiter.io.in[7].bits.src_virt_id node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_20 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_20 : connect states[8].g, UInt<3>(0h2) node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1)) connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9) node _T_21 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid) when _T_21 : connect states[9].g, UInt<3>(0h2) node _T_22 = and(io.router_req.ready, io.router_req.valid) when _T_22 : node _T_23 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_23, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_27 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_27 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_28 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_28 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_29 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_29 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_30 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_30 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[3].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_31 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_31 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[4].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_32 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_32 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[5].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_33 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_33 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[6].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_34 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_34 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[7].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_35 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_35 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[8].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[8].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[8].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_36 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_36 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[9].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[9].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[9].vc_sel.`5`, io.router_resp.vc_sel.`5` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_37 = and(io.router_req.ready, io.router_req.valid) when _T_37 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_38 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_39 = or(_T_38, vcalloc_vals[2]) node _T_40 = or(_T_39, vcalloc_vals[3]) node _T_41 = or(_T_40, vcalloc_vals[4]) node _T_42 = or(_T_41, vcalloc_vals[5]) node _T_43 = or(_T_42, vcalloc_vals[6]) node _T_44 = or(_T_43, vcalloc_vals[7]) node _T_45 = or(_T_44, vcalloc_vals[8]) node _T_46 = or(_T_45, vcalloc_vals[9]) when _T_46 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>[1] node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_15[0], _io_vcalloc_req_bits_WIRE_16 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_15 wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>[1] node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_17[0], _io_vcalloc_req_bits_WIRE_18 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_17 wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>[1] node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_20 : UInt<1> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_19[0], _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_19 wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>[1] node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_21[0], _io_vcalloc_req_bits_WIRE_22 connect _io_vcalloc_req_bits_WIRE_1.`5`, _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_23 : UInt<4> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_23 wire _io_vcalloc_req_bits_WIRE_24 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_25 : UInt<3> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_24.egress_node_id, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_26 : UInt<4> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_24.egress_node, _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_27 : UInt<3> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_24.ingress_node_id, _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375) node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376) node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377) node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378) node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379) node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380) wire _io_vcalloc_req_bits_WIRE_28 : UInt<4> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_389 connect _io_vcalloc_req_bits_WIRE_24.ingress_node, _io_vcalloc_req_bits_WIRE_28 node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391) node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392) node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393) node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394) node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395) node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399) wire _io_vcalloc_req_bits_WIRE_29 : UInt<3> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_408 connect _io_vcalloc_req_bits_WIRE_24.vnet_id, _io_vcalloc_req_bits_WIRE_29 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_24 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].vc_sel.`5`, states[0].vc_sel.`5` connect vcalloc_reqs[0].flow, states[0].flow node _T_47 = bits(vcalloc_sel, 0, 0) node _T_48 = and(vcalloc_vals[0], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, states[1].vc_sel.`5` connect vcalloc_reqs[1].flow, states[1].flow node _T_50 = bits(vcalloc_sel, 1, 1) node _T_51 = and(vcalloc_vals[1], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, states[2].vc_sel.`5` connect vcalloc_reqs[2].flow, states[2].flow node _T_53 = bits(vcalloc_sel, 2, 2) node _T_54 = and(vcalloc_vals[2], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].vc_sel.`4`, states[3].vc_sel.`4` connect vcalloc_reqs[3].vc_sel.`5`, states[3].vc_sel.`5` connect vcalloc_reqs[3].flow, states[3].flow node _T_56 = bits(vcalloc_sel, 3, 3) node _T_57 = and(vcalloc_vals[3], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].vc_sel.`4`, states[4].vc_sel.`4` connect vcalloc_reqs[4].vc_sel.`5`, states[4].vc_sel.`5` connect vcalloc_reqs[4].flow, states[4].flow node _T_59 = bits(vcalloc_sel, 4, 4) node _T_60 = and(vcalloc_vals[4], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].vc_sel.`4`, states[5].vc_sel.`4` connect vcalloc_reqs[5].vc_sel.`5`, states[5].vc_sel.`5` connect vcalloc_reqs[5].flow, states[5].flow node _T_62 = bits(vcalloc_sel, 5, 5) node _T_63 = and(vcalloc_vals[5], _T_62) node _T_64 = and(_T_63, io.vcalloc_req.ready) when _T_64 : connect states[5].g, UInt<3>(0h3) connect vcalloc_vals[6], UInt<1>(0h0) invalidate vcalloc_reqs[6].vc_sel.`0`[0] invalidate vcalloc_reqs[6].vc_sel.`0`[1] invalidate vcalloc_reqs[6].vc_sel.`0`[2] invalidate vcalloc_reqs[6].vc_sel.`0`[3] invalidate vcalloc_reqs[6].vc_sel.`0`[4] invalidate vcalloc_reqs[6].vc_sel.`0`[5] invalidate vcalloc_reqs[6].vc_sel.`0`[6] invalidate vcalloc_reqs[6].vc_sel.`0`[7] invalidate vcalloc_reqs[6].vc_sel.`0`[8] invalidate vcalloc_reqs[6].vc_sel.`0`[9] invalidate vcalloc_reqs[6].vc_sel.`1`[0] invalidate vcalloc_reqs[6].vc_sel.`2`[0] invalidate vcalloc_reqs[6].vc_sel.`3`[0] invalidate vcalloc_reqs[6].vc_sel.`4`[0] invalidate vcalloc_reqs[6].vc_sel.`5`[0] invalidate vcalloc_reqs[6].in_vc invalidate vcalloc_reqs[6].flow.egress_node_id invalidate vcalloc_reqs[6].flow.egress_node invalidate vcalloc_reqs[6].flow.ingress_node_id invalidate vcalloc_reqs[6].flow.ingress_node invalidate vcalloc_reqs[6].flow.vnet_id connect vcalloc_vals[7], UInt<1>(0h0) invalidate vcalloc_reqs[7].vc_sel.`0`[0] invalidate vcalloc_reqs[7].vc_sel.`0`[1] invalidate vcalloc_reqs[7].vc_sel.`0`[2] invalidate vcalloc_reqs[7].vc_sel.`0`[3] invalidate vcalloc_reqs[7].vc_sel.`0`[4] invalidate vcalloc_reqs[7].vc_sel.`0`[5] invalidate vcalloc_reqs[7].vc_sel.`0`[6] invalidate vcalloc_reqs[7].vc_sel.`0`[7] invalidate vcalloc_reqs[7].vc_sel.`0`[8] invalidate vcalloc_reqs[7].vc_sel.`0`[9] invalidate vcalloc_reqs[7].vc_sel.`1`[0] invalidate vcalloc_reqs[7].vc_sel.`2`[0] invalidate vcalloc_reqs[7].vc_sel.`3`[0] invalidate vcalloc_reqs[7].vc_sel.`4`[0] invalidate vcalloc_reqs[7].vc_sel.`5`[0] invalidate vcalloc_reqs[7].in_vc invalidate vcalloc_reqs[7].flow.egress_node_id invalidate vcalloc_reqs[7].flow.egress_node invalidate vcalloc_reqs[7].flow.ingress_node_id invalidate vcalloc_reqs[7].flow.ingress_node invalidate vcalloc_reqs[7].flow.vnet_id node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].vc_sel.`3`, states[8].vc_sel.`3` connect vcalloc_reqs[8].vc_sel.`4`, states[8].vc_sel.`4` connect vcalloc_reqs[8].vc_sel.`5`, states[8].vc_sel.`5` connect vcalloc_reqs[8].flow, states[8].flow node _T_65 = bits(vcalloc_sel, 8, 8) node _T_66 = and(vcalloc_vals[8], _T_65) node _T_67 = and(_T_66, io.vcalloc_req.ready) when _T_67 : connect states[8].g, UInt<3>(0h3) node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2)) node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1) connect vcalloc_vals[9], _vcalloc_vals_9_T_2 connect vcalloc_reqs[9].in_vc, UInt<4>(0h9) connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0` connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1` connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2` connect vcalloc_reqs[9].vc_sel.`3`, states[9].vc_sel.`3` connect vcalloc_reqs[9].vc_sel.`4`, states[9].vc_sel.`4` connect vcalloc_reqs[9].vc_sel.`5`, states[9].vc_sel.`5` connect vcalloc_reqs[9].flow, states[9].flow node _T_68 = bits(vcalloc_sel, 9, 9) node _T_69 = and(vcalloc_vals[9], _T_68) node _T_70 = and(_T_69, io.vcalloc_req.ready) when _T_70 : connect states[9].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_71 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_71 : node _T_72 = bits(vcalloc_sel, 0, 0) when _T_72 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[0].g, UInt<3>(0h3) node _T_73 = eq(states[0].g, UInt<3>(0h2)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_73, UInt<1>(0h1), "") : assert_3 node _T_77 = bits(vcalloc_sel, 1, 1) when _T_77 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[1].g, UInt<3>(0h3) node _T_78 = eq(states[1].g, UInt<3>(0h2)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_78, UInt<1>(0h1), "") : assert_4 node _T_82 = bits(vcalloc_sel, 2, 2) when _T_82 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[2].g, UInt<3>(0h3) node _T_83 = eq(states[2].g, UInt<3>(0h2)) node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : node _T_86 = eq(_T_83, UInt<1>(0h0)) when _T_86 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_83, UInt<1>(0h1), "") : assert_5 node _T_87 = bits(vcalloc_sel, 3, 3) when _T_87 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[3].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[3].g, UInt<3>(0h3) node _T_88 = eq(states[3].g, UInt<3>(0h2)) node _T_89 = asUInt(reset) node _T_90 = eq(_T_89, UInt<1>(0h0)) when _T_90 : node _T_91 = eq(_T_88, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_88, UInt<1>(0h1), "") : assert_6 node _T_92 = bits(vcalloc_sel, 4, 4) when _T_92 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[4].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[4].g, UInt<3>(0h3) node _T_93 = eq(states[4].g, UInt<3>(0h2)) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_93, UInt<1>(0h1), "") : assert_7 node _T_97 = bits(vcalloc_sel, 5, 5) when _T_97 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[5].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[5].g, UInt<3>(0h3) node _T_98 = eq(states[5].g, UInt<3>(0h2)) node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(_T_98, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_98, UInt<1>(0h1), "") : assert_8 node _T_102 = bits(vcalloc_sel, 6, 6) when _T_102 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[6].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[6].g, UInt<3>(0h3) node _T_103 = eq(states[6].g, UInt<3>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_103, UInt<1>(0h1), "") : assert_9 node _T_107 = bits(vcalloc_sel, 7, 7) when _T_107 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[7].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[7].g, UInt<3>(0h3) node _T_108 = eq(states[7].g, UInt<3>(0h2)) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_108, UInt<1>(0h1), "") : assert_10 node _T_112 = bits(vcalloc_sel, 8, 8) when _T_112 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[8].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[8].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[8].g, UInt<3>(0h3) node _T_113 = eq(states[8].g, UInt<3>(0h2)) node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : node _T_116 = eq(_T_113, UInt<1>(0h0)) when _T_116 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_113, UInt<1>(0h1), "") : assert_11 node _T_117 = bits(vcalloc_sel, 9, 9) when _T_117 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[9].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[9].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[9].g, UInt<3>(0h3) node _T_118 = eq(states[9].g, UInt<3>(0h2)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_118, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_16 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[0].vc_sel.`0`[4], states[0].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[0].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[0].vc_sel.`0`[6], states[0].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[0].vc_sel.`0`[9], states[0].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[0].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_hi_1 = cat(states[0].vc_sel.`2`[0], states[0].vc_sel.`1`[0]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, _credit_available_T) node credit_available_hi_hi_1 = cat(states[0].vc_sel.`5`[0], states[0].vc_sel.`4`[0]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[0].vc_sel.`3`[0]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_1, io.out_credit_available.`0`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_1, io.out_credit_available.`0`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_1) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, _credit_available_T_2) node credit_available_hi_hi_3 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`3`[0]) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] connect salloc_arb.io.in[0].bits.vc_sel.`0`[8], states[0].vc_sel.`0`[8] connect salloc_arb.io.in[0].bits.vc_sel.`0`[9], states[0].vc_sel.`0`[9] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`5`[0], states[0].vc_sel.`5`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_122 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_123 = and(_T_122, input_buffer.io.deq[0].bits.tail) when _T_123 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_lo_2 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi_hi_2 = cat(states[1].vc_sel.`0`[4], states[1].vc_sel.`0`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_2, states[1].vc_sel.`0`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`0`[6], states[1].vc_sel.`0`[5]) node credit_available_hi_hi_hi_2 = cat(states[1].vc_sel.`0`[9], states[1].vc_sel.`0`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_2, states[1].vc_sel.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, credit_available_hi_lo_2) node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_hi_5 = cat(states[1].vc_sel.`2`[0], states[1].vc_sel.`1`[0]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, _credit_available_T_5) node credit_available_hi_hi_5 = cat(states[1].vc_sel.`5`[0], states[1].vc_sel.`4`[0]) node credit_available_hi_5 = cat(credit_available_hi_hi_5, states[1].vc_sel.`3`[0]) node _credit_available_T_6 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, credit_available_hi_lo_3) node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_hi_7 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, _credit_available_T_7) node credit_available_hi_hi_7 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, io.out_credit_available.`3`[0]) node _credit_available_T_8 = cat(credit_available_hi_7, credit_available_lo_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`0`[8], states[1].vc_sel.`0`[8] connect salloc_arb.io.in[1].bits.vc_sel.`0`[9], states[1].vc_sel.`0`[9] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`5`[0], states[1].vc_sel.`5`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_124 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_125 = and(_T_124, input_buffer.io.deq[1].bits.tail) when _T_125 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_4 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_hi_4 = cat(states[2].vc_sel.`0`[4], states[2].vc_sel.`0`[3]) node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_4, states[2].vc_sel.`0`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[2].vc_sel.`0`[6], states[2].vc_sel.`0`[5]) node credit_available_hi_hi_hi_4 = cat(states[2].vc_sel.`0`[9], states[2].vc_sel.`0`[8]) node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_4, states[2].vc_sel.`0`[7]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, credit_available_hi_lo_4) node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_hi_9 = cat(states[2].vc_sel.`2`[0], states[2].vc_sel.`1`[0]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, _credit_available_T_10) node credit_available_hi_hi_9 = cat(states[2].vc_sel.`5`[0], states[2].vc_sel.`4`[0]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, states[2].vc_sel.`3`[0]) node _credit_available_T_11 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`0`[7]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, credit_available_hi_lo_5) node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_hi_11 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, _credit_available_T_12) node credit_available_hi_hi_11 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_11 = cat(credit_available_hi_hi_11, io.out_credit_available.`3`[0]) node _credit_available_T_13 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`0`[8], states[2].vc_sel.`0`[8] connect salloc_arb.io.in[2].bits.vc_sel.`0`[9], states[2].vc_sel.`0`[9] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`5`[0], states[2].vc_sel.`5`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_126 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_127 = and(_T_126, input_buffer.io.deq[2].bits.tail) when _T_127 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_6 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_hi_6 = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3]) node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_6, states[3].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5]) node credit_available_hi_hi_hi_6 = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8]) node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_6, states[3].vc_sel.`0`[7]) node credit_available_hi_12 = cat(credit_available_hi_hi_12, credit_available_hi_lo_6) node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_hi_13 = cat(states[3].vc_sel.`2`[0], states[3].vc_sel.`1`[0]) node credit_available_lo_13 = cat(credit_available_lo_hi_13, _credit_available_T_15) node credit_available_hi_hi_13 = cat(states[3].vc_sel.`5`[0], states[3].vc_sel.`4`[0]) node credit_available_hi_13 = cat(credit_available_hi_hi_13, states[3].vc_sel.`3`[0]) node _credit_available_T_16 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_lo_7 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_7 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_7, io.out_credit_available.`0`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_7 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_7, io.out_credit_available.`0`[7]) node credit_available_hi_14 = cat(credit_available_hi_hi_14, credit_available_hi_lo_7) node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_hi_15 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_15 = cat(credit_available_lo_hi_15, _credit_available_T_17) node credit_available_hi_hi_15 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_15 = cat(credit_available_hi_hi_15, io.out_credit_available.`3`[0]) node _credit_available_T_18 = cat(credit_available_hi_15, credit_available_lo_15) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8] connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`4`[0], states[3].vc_sel.`4`[0] connect salloc_arb.io.in[3].bits.vc_sel.`5`[0], states[3].vc_sel.`5`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_128 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_129 = and(_T_128, input_buffer.io.deq[3].bits.tail) when _T_129 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_8 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_hi_8 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_lo_hi_16 = cat(credit_available_lo_hi_hi_8, states[4].vc_sel.`0`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5]) node credit_available_hi_hi_hi_8 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8]) node credit_available_hi_hi_16 = cat(credit_available_hi_hi_hi_8, states[4].vc_sel.`0`[7]) node credit_available_hi_16 = cat(credit_available_hi_hi_16, credit_available_hi_lo_8) node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_hi_17 = cat(states[4].vc_sel.`2`[0], states[4].vc_sel.`1`[0]) node credit_available_lo_17 = cat(credit_available_lo_hi_17, _credit_available_T_20) node credit_available_hi_hi_17 = cat(states[4].vc_sel.`5`[0], states[4].vc_sel.`4`[0]) node credit_available_hi_17 = cat(credit_available_hi_hi_17, states[4].vc_sel.`3`[0]) node _credit_available_T_21 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_18 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_18 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7]) node credit_available_hi_18 = cat(credit_available_hi_hi_18, credit_available_hi_lo_9) node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_hi_19 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_19 = cat(credit_available_lo_hi_19, _credit_available_T_22) node credit_available_hi_hi_19 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_19 = cat(credit_available_hi_hi_19, io.out_credit_available.`3`[0]) node _credit_available_T_23 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8] connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`4`[0], states[4].vc_sel.`4`[0] connect salloc_arb.io.in[4].bits.vc_sel.`5`[0], states[4].vc_sel.`5`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_130 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_131 = and(_T_130, input_buffer.io.deq[4].bits.tail) when _T_131 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_10 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_hi_10 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3]) node credit_available_lo_hi_20 = cat(credit_available_lo_hi_hi_10, states[5].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5]) node credit_available_hi_hi_hi_10 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8]) node credit_available_hi_hi_20 = cat(credit_available_hi_hi_hi_10, states[5].vc_sel.`0`[7]) node credit_available_hi_20 = cat(credit_available_hi_hi_20, credit_available_hi_lo_10) node _credit_available_T_25 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_hi_21 = cat(states[5].vc_sel.`2`[0], states[5].vc_sel.`1`[0]) node credit_available_lo_21 = cat(credit_available_lo_hi_21, _credit_available_T_25) node credit_available_hi_hi_21 = cat(states[5].vc_sel.`5`[0], states[5].vc_sel.`4`[0]) node credit_available_hi_21 = cat(credit_available_hi_hi_21, states[5].vc_sel.`3`[0]) node _credit_available_T_26 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_11 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_22 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`0`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_22 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`0`[7]) node credit_available_hi_22 = cat(credit_available_hi_hi_22, credit_available_hi_lo_11) node _credit_available_T_27 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_hi_23 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_23 = cat(credit_available_lo_hi_23, _credit_available_T_27) node credit_available_hi_hi_23 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_23 = cat(credit_available_hi_hi_23, io.out_credit_available.`3`[0]) node _credit_available_T_28 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8] connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`4`[0], states[5].vc_sel.`4`[0] connect salloc_arb.io.in[5].bits.vc_sel.`5`[0], states[5].vc_sel.`5`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_132 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_133 = and(_T_132, input_buffer.io.deq[5].bits.tail) when _T_133 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready connect salloc_arb.io.in[6].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[6].bits.tail invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`5`[0] connect salloc_arb.io.in[7].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[7].bits.tail invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`5`[0] node credit_available_lo_lo_12 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi_12 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi_24 = cat(credit_available_lo_hi_hi_12, states[8].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi_12 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi_24 = cat(credit_available_hi_hi_hi_12, states[8].vc_sel.`0`[7]) node credit_available_hi_24 = cat(credit_available_hi_hi_24, credit_available_hi_lo_12) node _credit_available_T_30 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_hi_25 = cat(states[8].vc_sel.`2`[0], states[8].vc_sel.`1`[0]) node credit_available_lo_25 = cat(credit_available_lo_hi_25, _credit_available_T_30) node credit_available_hi_hi_25 = cat(states[8].vc_sel.`5`[0], states[8].vc_sel.`4`[0]) node credit_available_hi_25 = cat(credit_available_hi_hi_25, states[8].vc_sel.`3`[0]) node _credit_available_T_31 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_13 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_13 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_26 = cat(credit_available_lo_hi_hi_13, io.out_credit_available.`0`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_13 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_26 = cat(credit_available_hi_hi_hi_13, io.out_credit_available.`0`[7]) node credit_available_hi_26 = cat(credit_available_hi_hi_26, credit_available_hi_lo_13) node _credit_available_T_32 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_hi_27 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_27 = cat(credit_available_lo_hi_27, _credit_available_T_32) node credit_available_hi_hi_27 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_27 = cat(credit_available_hi_hi_27, io.out_credit_available.`3`[0]) node _credit_available_T_33 = cat(credit_available_hi_27, credit_available_lo_27) node _credit_available_T_34 = and(_credit_available_T_31, _credit_available_T_33) node credit_available_6 = neq(_credit_available_T_34, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_6) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`3`[0], states[8].vc_sel.`3`[0] connect salloc_arb.io.in[8].bits.vc_sel.`4`[0], states[8].vc_sel.`4`[0] connect salloc_arb.io.in[8].bits.vc_sel.`5`[0], states[8].vc_sel.`5`[0] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_134 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_135 = and(_T_134, input_buffer.io.deq[8].bits.tail) when _T_135 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready node credit_available_lo_lo_14 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0]) node credit_available_lo_hi_hi_14 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3]) node credit_available_lo_hi_28 = cat(credit_available_lo_hi_hi_14, states[9].vc_sel.`0`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5]) node credit_available_hi_hi_hi_14 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8]) node credit_available_hi_hi_28 = cat(credit_available_hi_hi_hi_14, states[9].vc_sel.`0`[7]) node credit_available_hi_28 = cat(credit_available_hi_hi_28, credit_available_hi_lo_14) node _credit_available_T_35 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_hi_29 = cat(states[9].vc_sel.`2`[0], states[9].vc_sel.`1`[0]) node credit_available_lo_29 = cat(credit_available_lo_hi_29, _credit_available_T_35) node credit_available_hi_hi_29 = cat(states[9].vc_sel.`5`[0], states[9].vc_sel.`4`[0]) node credit_available_hi_29 = cat(credit_available_hi_hi_29, states[9].vc_sel.`3`[0]) node _credit_available_T_36 = cat(credit_available_hi_29, credit_available_lo_29) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_30 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_30 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7]) node credit_available_hi_30 = cat(credit_available_hi_hi_30, credit_available_hi_lo_15) node _credit_available_T_37 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_hi_31 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node credit_available_lo_31 = cat(credit_available_lo_hi_31, _credit_available_T_37) node credit_available_hi_hi_31 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_31 = cat(credit_available_hi_hi_31, io.out_credit_available.`3`[0]) node _credit_available_T_38 = cat(credit_available_hi_31, credit_available_lo_31) node _credit_available_T_39 = and(_credit_available_T_36, _credit_available_T_38) node credit_available_7 = neq(_credit_available_T_39, UInt<1>(0h0)) node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3)) node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_7) node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid) connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2 connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0] connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1] connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2] connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3] connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4] connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5] connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6] connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7] connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8] connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9] connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0] connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0] connect salloc_arb.io.in[9].bits.vc_sel.`3`[0], states[9].vc_sel.`3`[0] connect salloc_arb.io.in[9].bits.vc_sel.`4`[0], states[9].vc_sel.`4`[0] connect salloc_arb.io.in[9].bits.vc_sel.`5`[0], states[9].vc_sel.`5`[0] connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail node _T_136 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid) node _T_137 = and(_T_136, input_buffer.io.deq[9].bits.tail) when _T_137 : connect states[9].g, UInt<3>(0h0) connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[1] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_13 : UInt<1>[1] node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_237 connect _vc_sel_WIRE_13[0], _vc_sel_WIRE_14 connect vc_sel.`2`, _vc_sel_WIRE_13 wire _vc_sel_WIRE_15 : UInt<1>[1] node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_256 connect _vc_sel_WIRE_15[0], _vc_sel_WIRE_16 connect vc_sel.`3`, _vc_sel_WIRE_15 wire _vc_sel_WIRE_17 : UInt<1>[1] node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258) node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259) node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260) node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261) node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266) wire _vc_sel_WIRE_18 : UInt<1> connect _vc_sel_WIRE_18, _vc_sel_T_275 connect _vc_sel_WIRE_17[0], _vc_sel_WIRE_18 connect vc_sel.`4`, _vc_sel_WIRE_17 wire _vc_sel_WIRE_19 : UInt<1>[1] node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283) node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284) node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_294 connect _vc_sel_WIRE_19[0], _vc_sel_WIRE_20 connect vc_sel.`5`, _vc_sel_WIRE_19 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node _virt_channel_T_11 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_12 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_13 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_14 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_15 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_16 = mux(vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_17 = or(_virt_channel_T_11, _virt_channel_T_12) node _virt_channel_T_18 = or(_virt_channel_T_17, _virt_channel_T_13) node _virt_channel_T_19 = or(_virt_channel_T_18, _virt_channel_T_14) node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_15) node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_16) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_21 node _T_138 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_138 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`0`[3], UInt<1>(0h0) connect states[0].vc_sel.`0`[4], UInt<1>(0h0) connect states[0].vc_sel.`0`[5], UInt<1>(0h0) connect states[0].vc_sel.`0`[6], UInt<1>(0h0) connect states[0].vc_sel.`0`[7], UInt<1>(0h0) connect states[0].vc_sel.`0`[8], UInt<1>(0h0) connect states[0].vc_sel.`0`[9], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[1].vc_sel.`0`[6], UInt<1>(0h0) connect states[1].vc_sel.`0`[7], UInt<1>(0h0) connect states[1].vc_sel.`0`[8], UInt<1>(0h0) connect states[1].vc_sel.`0`[9], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[6], UInt<1>(0h0) connect states[2].vc_sel.`0`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[8], UInt<1>(0h0) connect states[2].vc_sel.`0`[9], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[2], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[6], UInt<1>(0h0) connect states[3].vc_sel.`0`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[8], UInt<1>(0h0) connect states[3].vc_sel.`0`[9], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[6], UInt<1>(0h0) connect states[4].vc_sel.`0`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[8], UInt<1>(0h0) connect states[4].vc_sel.`0`[9], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) connect states[5].vc_sel.`0`[6], UInt<1>(0h0) connect states[5].vc_sel.`0`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[8], UInt<1>(0h0) connect states[5].vc_sel.`0`[9], UInt<1>(0h0) invalidate states[6].fifo_deps invalidate states[6].flow.egress_node_id invalidate states[6].flow.egress_node invalidate states[6].flow.ingress_node_id invalidate states[6].flow.ingress_node invalidate states[6].flow.vnet_id invalidate states[6].vc_sel.`0`[0] invalidate states[6].vc_sel.`0`[1] invalidate states[6].vc_sel.`0`[2] invalidate states[6].vc_sel.`0`[3] invalidate states[6].vc_sel.`0`[4] invalidate states[6].vc_sel.`0`[5] invalidate states[6].vc_sel.`0`[6] invalidate states[6].vc_sel.`0`[7] invalidate states[6].vc_sel.`0`[8] invalidate states[6].vc_sel.`0`[9] invalidate states[6].vc_sel.`1`[0] invalidate states[6].vc_sel.`2`[0] invalidate states[6].vc_sel.`3`[0] invalidate states[6].vc_sel.`4`[0] invalidate states[6].vc_sel.`5`[0] invalidate states[6].g invalidate states[7].fifo_deps invalidate states[7].flow.egress_node_id invalidate states[7].flow.egress_node invalidate states[7].flow.ingress_node_id invalidate states[7].flow.ingress_node invalidate states[7].flow.vnet_id invalidate states[7].vc_sel.`0`[0] invalidate states[7].vc_sel.`0`[1] invalidate states[7].vc_sel.`0`[2] invalidate states[7].vc_sel.`0`[3] invalidate states[7].vc_sel.`0`[4] invalidate states[7].vc_sel.`0`[5] invalidate states[7].vc_sel.`0`[6] invalidate states[7].vc_sel.`0`[7] invalidate states[7].vc_sel.`0`[8] invalidate states[7].vc_sel.`0`[9] invalidate states[7].vc_sel.`1`[0] invalidate states[7].vc_sel.`2`[0] invalidate states[7].vc_sel.`3`[0] invalidate states[7].vc_sel.`4`[0] invalidate states[7].vc_sel.`5`[0] invalidate states[7].g connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`0`[9], UInt<1>(0h0) connect states[9].vc_sel.`0`[0], UInt<1>(0h0) connect states[9].vc_sel.`0`[1], UInt<1>(0h0) connect states[9].vc_sel.`0`[2], UInt<1>(0h0) connect states[9].vc_sel.`0`[3], UInt<1>(0h0) connect states[9].vc_sel.`0`[4], UInt<1>(0h0) connect states[9].vc_sel.`0`[5], UInt<1>(0h0) connect states[9].vc_sel.`0`[6], UInt<1>(0h0) connect states[9].vc_sel.`0`[7], UInt<1>(0h0) node _T_139 = asUInt(reset) when _T_139 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)

module InputUnit_4( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, 2'h0, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_0 ? 20'h400 : vcalloc_vals_1 ? 20'h800 : vcalloc_vals_2 ? 20'h1000 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_3 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_3( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]

Generate the Verilog code corresponding to this FIRRTL code module PE_235 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_235( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_111 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_111( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_184 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_184( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_169 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_425 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_169( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_425 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_11 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_11( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Switch_4 : input clock : Clock input reset : Reset output io : { in : { flip `5` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `4` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `3` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `2` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `1` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], flip `0` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1]}, out : { `5` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `4` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `3` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `2` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `1` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], `0` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1]}, sel : { `5` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `4` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `3` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `2` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `1` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `0` : { flip `5` : UInt<1>[1], flip `4` : UInt<1>[1], flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1]}} wire in_flat : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[6] connect in_flat[0], io.in.`0`[0] connect in_flat[1], io.in.`1`[0] connect in_flat[2], io.in.`2`[0] connect in_flat[3], io.in.`3`[0] connect in_flat[4], io.in.`4`[0] connect in_flat[5], io.in.`5`[0] node sel_flat_lo_hi = cat(io.sel.`0`[0].`2`[0], io.sel.`0`[0].`1`[0]) node sel_flat_lo = cat(sel_flat_lo_hi, io.sel.`0`[0].`0`[0]) node sel_flat_hi_hi = cat(io.sel.`0`[0].`5`[0], io.sel.`0`[0].`4`[0]) node sel_flat_hi = cat(sel_flat_hi_hi, io.sel.`0`[0].`3`[0]) node sel_flat = cat(sel_flat_hi, sel_flat_lo) node _T = bits(sel_flat, 0, 0) node _T_1 = bits(sel_flat, 1, 1) node _T_2 = bits(sel_flat, 2, 2) node _T_3 = bits(sel_flat, 3, 3) node _T_4 = bits(sel_flat, 4, 4) node _T_5 = bits(sel_flat, 5, 5) node _T_6 = add(_T_1, _T_2) node _T_7 = bits(_T_6, 1, 0) node _T_8 = add(_T, _T_7) node _T_9 = bits(_T_8, 1, 0) node _T_10 = add(_T_4, _T_5) node _T_11 = bits(_T_10, 1, 0) node _T_12 = add(_T_3, _T_11) node _T_13 = bits(_T_12, 1, 0) node _T_14 = add(_T_9, _T_13) node _T_15 = bits(_T_14, 2, 0) node _T_16 = leq(_T_15, UInt<1>(0h1)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf assert(clock, _T_16, UInt<1>(0h1), "") : assert node _io_out_0_0_valid_T = bits(sel_flat, 0, 0) node _io_out_0_0_valid_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_valid_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_valid_T_3 = bits(sel_flat, 3, 3) node _io_out_0_0_valid_T_4 = bits(sel_flat, 4, 4) node _io_out_0_0_valid_T_5 = bits(sel_flat, 5, 5) node _io_out_0_0_valid_T_6 = mux(_io_out_0_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_7 = mux(_io_out_0_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_8 = mux(_io_out_0_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_9 = mux(_io_out_0_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_10 = mux(_io_out_0_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_11 = mux(_io_out_0_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_12 = or(_io_out_0_0_valid_T_6, _io_out_0_0_valid_T_7) node _io_out_0_0_valid_T_13 = or(_io_out_0_0_valid_T_12, _io_out_0_0_valid_T_8) node _io_out_0_0_valid_T_14 = or(_io_out_0_0_valid_T_13, _io_out_0_0_valid_T_9) node _io_out_0_0_valid_T_15 = or(_io_out_0_0_valid_T_14, _io_out_0_0_valid_T_10) node _io_out_0_0_valid_T_16 = or(_io_out_0_0_valid_T_15, _io_out_0_0_valid_T_11) wire _io_out_0_0_valid_WIRE : UInt<1> connect _io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_16 node _io_out_0_0_valid_T_17 = neq(sel_flat, UInt<1>(0h0)) node _io_out_0_0_valid_T_18 = and(_io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_17) connect io.out.`0`[0].valid, _io_out_0_0_valid_T_18 node _io_out_0_0_bits_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_bits_T_3 = bits(sel_flat, 3, 3) node _io_out_0_0_bits_T_4 = bits(sel_flat, 4, 4) node _io_out_0_0_bits_T_5 = bits(sel_flat, 5, 5) wire _io_out_0_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_0_0_bits_T_6 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_7 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_8 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_9 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_10 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_11 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_12 = or(_io_out_0_0_bits_T_6, _io_out_0_0_bits_T_7) node _io_out_0_0_bits_T_13 = or(_io_out_0_0_bits_T_12, _io_out_0_0_bits_T_8) node _io_out_0_0_bits_T_14 = or(_io_out_0_0_bits_T_13, _io_out_0_0_bits_T_9) node _io_out_0_0_bits_T_15 = or(_io_out_0_0_bits_T_14, _io_out_0_0_bits_T_10) node _io_out_0_0_bits_T_16 = or(_io_out_0_0_bits_T_15, _io_out_0_0_bits_T_11) wire _io_out_0_0_bits_WIRE_1 : UInt<4> connect _io_out_0_0_bits_WIRE_1, _io_out_0_0_bits_T_16 connect _io_out_0_0_bits_WIRE.virt_channel_id, _io_out_0_0_bits_WIRE_1 wire _io_out_0_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_0_0_bits_T_17 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_18 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_19 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_20 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_21 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_22 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_23 = or(_io_out_0_0_bits_T_17, _io_out_0_0_bits_T_18) node _io_out_0_0_bits_T_24 = or(_io_out_0_0_bits_T_23, _io_out_0_0_bits_T_19) node _io_out_0_0_bits_T_25 = or(_io_out_0_0_bits_T_24, _io_out_0_0_bits_T_20) node _io_out_0_0_bits_T_26 = or(_io_out_0_0_bits_T_25, _io_out_0_0_bits_T_21) node _io_out_0_0_bits_T_27 = or(_io_out_0_0_bits_T_26, _io_out_0_0_bits_T_22) wire _io_out_0_0_bits_WIRE_3 : UInt<3> connect _io_out_0_0_bits_WIRE_3, _io_out_0_0_bits_T_27 connect _io_out_0_0_bits_WIRE_2.egress_node_id, _io_out_0_0_bits_WIRE_3 node _io_out_0_0_bits_T_28 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_29 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_30 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_31 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_32 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_33 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_34 = or(_io_out_0_0_bits_T_28, _io_out_0_0_bits_T_29) node _io_out_0_0_bits_T_35 = or(_io_out_0_0_bits_T_34, _io_out_0_0_bits_T_30) node _io_out_0_0_bits_T_36 = or(_io_out_0_0_bits_T_35, _io_out_0_0_bits_T_31) node _io_out_0_0_bits_T_37 = or(_io_out_0_0_bits_T_36, _io_out_0_0_bits_T_32) node _io_out_0_0_bits_T_38 = or(_io_out_0_0_bits_T_37, _io_out_0_0_bits_T_33) wire _io_out_0_0_bits_WIRE_4 : UInt<4> connect _io_out_0_0_bits_WIRE_4, _io_out_0_0_bits_T_38 connect _io_out_0_0_bits_WIRE_2.egress_node, _io_out_0_0_bits_WIRE_4 node _io_out_0_0_bits_T_39 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_40 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_41 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_42 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_43 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_44 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_45 = or(_io_out_0_0_bits_T_39, _io_out_0_0_bits_T_40) node _io_out_0_0_bits_T_46 = or(_io_out_0_0_bits_T_45, _io_out_0_0_bits_T_41) node _io_out_0_0_bits_T_47 = or(_io_out_0_0_bits_T_46, _io_out_0_0_bits_T_42) node _io_out_0_0_bits_T_48 = or(_io_out_0_0_bits_T_47, _io_out_0_0_bits_T_43) node _io_out_0_0_bits_T_49 = or(_io_out_0_0_bits_T_48, _io_out_0_0_bits_T_44) wire _io_out_0_0_bits_WIRE_5 : UInt<3> connect _io_out_0_0_bits_WIRE_5, _io_out_0_0_bits_T_49 connect _io_out_0_0_bits_WIRE_2.ingress_node_id, _io_out_0_0_bits_WIRE_5 node _io_out_0_0_bits_T_50 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_51 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_52 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_53 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_54 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_55 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_56 = or(_io_out_0_0_bits_T_50, _io_out_0_0_bits_T_51) node _io_out_0_0_bits_T_57 = or(_io_out_0_0_bits_T_56, _io_out_0_0_bits_T_52) node _io_out_0_0_bits_T_58 = or(_io_out_0_0_bits_T_57, _io_out_0_0_bits_T_53) node _io_out_0_0_bits_T_59 = or(_io_out_0_0_bits_T_58, _io_out_0_0_bits_T_54) node _io_out_0_0_bits_T_60 = or(_io_out_0_0_bits_T_59, _io_out_0_0_bits_T_55) wire _io_out_0_0_bits_WIRE_6 : UInt<4> connect _io_out_0_0_bits_WIRE_6, _io_out_0_0_bits_T_60 connect _io_out_0_0_bits_WIRE_2.ingress_node, _io_out_0_0_bits_WIRE_6 node _io_out_0_0_bits_T_61 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_62 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_63 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_64 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_65 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_66 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_67 = or(_io_out_0_0_bits_T_61, _io_out_0_0_bits_T_62) node _io_out_0_0_bits_T_68 = or(_io_out_0_0_bits_T_67, _io_out_0_0_bits_T_63) node _io_out_0_0_bits_T_69 = or(_io_out_0_0_bits_T_68, _io_out_0_0_bits_T_64) node _io_out_0_0_bits_T_70 = or(_io_out_0_0_bits_T_69, _io_out_0_0_bits_T_65) node _io_out_0_0_bits_T_71 = or(_io_out_0_0_bits_T_70, _io_out_0_0_bits_T_66) wire _io_out_0_0_bits_WIRE_7 : UInt<3> connect _io_out_0_0_bits_WIRE_7, _io_out_0_0_bits_T_71 connect _io_out_0_0_bits_WIRE_2.vnet_id, _io_out_0_0_bits_WIRE_7 connect _io_out_0_0_bits_WIRE.flow, _io_out_0_0_bits_WIRE_2 node _io_out_0_0_bits_T_72 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_73 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_74 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_75 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_76 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_77 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_78 = or(_io_out_0_0_bits_T_72, _io_out_0_0_bits_T_73) node _io_out_0_0_bits_T_79 = or(_io_out_0_0_bits_T_78, _io_out_0_0_bits_T_74) node _io_out_0_0_bits_T_80 = or(_io_out_0_0_bits_T_79, _io_out_0_0_bits_T_75) node _io_out_0_0_bits_T_81 = or(_io_out_0_0_bits_T_80, _io_out_0_0_bits_T_76) node _io_out_0_0_bits_T_82 = or(_io_out_0_0_bits_T_81, _io_out_0_0_bits_T_77) wire _io_out_0_0_bits_WIRE_8 : UInt<73> connect _io_out_0_0_bits_WIRE_8, _io_out_0_0_bits_T_82 connect _io_out_0_0_bits_WIRE.payload, _io_out_0_0_bits_WIRE_8 node _io_out_0_0_bits_T_83 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_84 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_85 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_86 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_87 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_88 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_89 = or(_io_out_0_0_bits_T_83, _io_out_0_0_bits_T_84) node _io_out_0_0_bits_T_90 = or(_io_out_0_0_bits_T_89, _io_out_0_0_bits_T_85) node _io_out_0_0_bits_T_91 = or(_io_out_0_0_bits_T_90, _io_out_0_0_bits_T_86) node _io_out_0_0_bits_T_92 = or(_io_out_0_0_bits_T_91, _io_out_0_0_bits_T_87) node _io_out_0_0_bits_T_93 = or(_io_out_0_0_bits_T_92, _io_out_0_0_bits_T_88) wire _io_out_0_0_bits_WIRE_9 : UInt<1> connect _io_out_0_0_bits_WIRE_9, _io_out_0_0_bits_T_93 connect _io_out_0_0_bits_WIRE.tail, _io_out_0_0_bits_WIRE_9 node _io_out_0_0_bits_T_94 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_95 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_96 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_97 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_98 = mux(_io_out_0_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_99 = mux(_io_out_0_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_100 = or(_io_out_0_0_bits_T_94, _io_out_0_0_bits_T_95) node _io_out_0_0_bits_T_101 = or(_io_out_0_0_bits_T_100, _io_out_0_0_bits_T_96) node _io_out_0_0_bits_T_102 = or(_io_out_0_0_bits_T_101, _io_out_0_0_bits_T_97) node _io_out_0_0_bits_T_103 = or(_io_out_0_0_bits_T_102, _io_out_0_0_bits_T_98) node _io_out_0_0_bits_T_104 = or(_io_out_0_0_bits_T_103, _io_out_0_0_bits_T_99) wire _io_out_0_0_bits_WIRE_10 : UInt<1> connect _io_out_0_0_bits_WIRE_10, _io_out_0_0_bits_T_104 connect _io_out_0_0_bits_WIRE.head, _io_out_0_0_bits_WIRE_10 connect io.out.`0`[0].bits, _io_out_0_0_bits_WIRE node _io_out_0_0_bits_virt_channel_id_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_virt_channel_id_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_virt_channel_id_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_bits_virt_channel_id_T_3 = bits(sel_flat, 3, 3) node _io_out_0_0_bits_virt_channel_id_T_4 = bits(sel_flat, 4, 4) node _io_out_0_0_bits_virt_channel_id_T_5 = bits(sel_flat, 5, 5) node _io_out_0_0_bits_virt_channel_id_T_6 = mux(_io_out_0_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_7 = mux(_io_out_0_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_8 = mux(_io_out_0_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_9 = mux(_io_out_0_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_10 = mux(_io_out_0_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_11 = mux(_io_out_0_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_12 = or(_io_out_0_0_bits_virt_channel_id_T_6, _io_out_0_0_bits_virt_channel_id_T_7) node _io_out_0_0_bits_virt_channel_id_T_13 = or(_io_out_0_0_bits_virt_channel_id_T_12, _io_out_0_0_bits_virt_channel_id_T_8) node _io_out_0_0_bits_virt_channel_id_T_14 = or(_io_out_0_0_bits_virt_channel_id_T_13, _io_out_0_0_bits_virt_channel_id_T_9) node _io_out_0_0_bits_virt_channel_id_T_15 = or(_io_out_0_0_bits_virt_channel_id_T_14, _io_out_0_0_bits_virt_channel_id_T_10) node _io_out_0_0_bits_virt_channel_id_T_16 = or(_io_out_0_0_bits_virt_channel_id_T_15, _io_out_0_0_bits_virt_channel_id_T_11) wire _io_out_0_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_0_0_bits_virt_channel_id_WIRE, _io_out_0_0_bits_virt_channel_id_T_16 connect io.out.`0`[0].bits.virt_channel_id, _io_out_0_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_1 = cat(io.sel.`1`[0].`2`[0], io.sel.`1`[0].`1`[0]) node sel_flat_lo_1 = cat(sel_flat_lo_hi_1, io.sel.`1`[0].`0`[0]) node sel_flat_hi_hi_1 = cat(io.sel.`1`[0].`5`[0], io.sel.`1`[0].`4`[0]) node sel_flat_hi_1 = cat(sel_flat_hi_hi_1, io.sel.`1`[0].`3`[0]) node sel_flat_1 = cat(sel_flat_hi_1, sel_flat_lo_1) node _T_20 = bits(sel_flat_1, 0, 0) node _T_21 = bits(sel_flat_1, 1, 1) node _T_22 = bits(sel_flat_1, 2, 2) node _T_23 = bits(sel_flat_1, 3, 3) node _T_24 = bits(sel_flat_1, 4, 4) node _T_25 = bits(sel_flat_1, 5, 5) node _T_26 = add(_T_21, _T_22) node _T_27 = bits(_T_26, 1, 0) node _T_28 = add(_T_20, _T_27) node _T_29 = bits(_T_28, 1, 0) node _T_30 = add(_T_24, _T_25) node _T_31 = bits(_T_30, 1, 0) node _T_32 = add(_T_23, _T_31) node _T_33 = bits(_T_32, 1, 0) node _T_34 = add(_T_29, _T_33) node _T_35 = bits(_T_34, 2, 0) node _T_36 = leq(_T_35, UInt<1>(0h1)) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_1 assert(clock, _T_36, UInt<1>(0h1), "") : assert_1 node _io_out_1_0_valid_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_valid_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_valid_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_valid_T_3 = bits(sel_flat_1, 3, 3) node _io_out_1_0_valid_T_4 = bits(sel_flat_1, 4, 4) node _io_out_1_0_valid_T_5 = bits(sel_flat_1, 5, 5) node _io_out_1_0_valid_T_6 = mux(_io_out_1_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_7 = mux(_io_out_1_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_8 = mux(_io_out_1_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_9 = mux(_io_out_1_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_10 = mux(_io_out_1_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_11 = mux(_io_out_1_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_12 = or(_io_out_1_0_valid_T_6, _io_out_1_0_valid_T_7) node _io_out_1_0_valid_T_13 = or(_io_out_1_0_valid_T_12, _io_out_1_0_valid_T_8) node _io_out_1_0_valid_T_14 = or(_io_out_1_0_valid_T_13, _io_out_1_0_valid_T_9) node _io_out_1_0_valid_T_15 = or(_io_out_1_0_valid_T_14, _io_out_1_0_valid_T_10) node _io_out_1_0_valid_T_16 = or(_io_out_1_0_valid_T_15, _io_out_1_0_valid_T_11) wire _io_out_1_0_valid_WIRE : UInt<1> connect _io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_16 node _io_out_1_0_valid_T_17 = neq(sel_flat_1, UInt<1>(0h0)) node _io_out_1_0_valid_T_18 = and(_io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_17) connect io.out.`1`[0].valid, _io_out_1_0_valid_T_18 node _io_out_1_0_bits_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_bits_T_3 = bits(sel_flat_1, 3, 3) node _io_out_1_0_bits_T_4 = bits(sel_flat_1, 4, 4) node _io_out_1_0_bits_T_5 = bits(sel_flat_1, 5, 5) wire _io_out_1_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_1_0_bits_T_6 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_7 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_8 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_9 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_10 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_11 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_12 = or(_io_out_1_0_bits_T_6, _io_out_1_0_bits_T_7) node _io_out_1_0_bits_T_13 = or(_io_out_1_0_bits_T_12, _io_out_1_0_bits_T_8) node _io_out_1_0_bits_T_14 = or(_io_out_1_0_bits_T_13, _io_out_1_0_bits_T_9) node _io_out_1_0_bits_T_15 = or(_io_out_1_0_bits_T_14, _io_out_1_0_bits_T_10) node _io_out_1_0_bits_T_16 = or(_io_out_1_0_bits_T_15, _io_out_1_0_bits_T_11) wire _io_out_1_0_bits_WIRE_1 : UInt<4> connect _io_out_1_0_bits_WIRE_1, _io_out_1_0_bits_T_16 connect _io_out_1_0_bits_WIRE.virt_channel_id, _io_out_1_0_bits_WIRE_1 wire _io_out_1_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_1_0_bits_T_17 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_18 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_19 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_20 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_21 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_22 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_23 = or(_io_out_1_0_bits_T_17, _io_out_1_0_bits_T_18) node _io_out_1_0_bits_T_24 = or(_io_out_1_0_bits_T_23, _io_out_1_0_bits_T_19) node _io_out_1_0_bits_T_25 = or(_io_out_1_0_bits_T_24, _io_out_1_0_bits_T_20) node _io_out_1_0_bits_T_26 = or(_io_out_1_0_bits_T_25, _io_out_1_0_bits_T_21) node _io_out_1_0_bits_T_27 = or(_io_out_1_0_bits_T_26, _io_out_1_0_bits_T_22) wire _io_out_1_0_bits_WIRE_3 : UInt<3> connect _io_out_1_0_bits_WIRE_3, _io_out_1_0_bits_T_27 connect _io_out_1_0_bits_WIRE_2.egress_node_id, _io_out_1_0_bits_WIRE_3 node _io_out_1_0_bits_T_28 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_29 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_30 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_31 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_32 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_33 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_34 = or(_io_out_1_0_bits_T_28, _io_out_1_0_bits_T_29) node _io_out_1_0_bits_T_35 = or(_io_out_1_0_bits_T_34, _io_out_1_0_bits_T_30) node _io_out_1_0_bits_T_36 = or(_io_out_1_0_bits_T_35, _io_out_1_0_bits_T_31) node _io_out_1_0_bits_T_37 = or(_io_out_1_0_bits_T_36, _io_out_1_0_bits_T_32) node _io_out_1_0_bits_T_38 = or(_io_out_1_0_bits_T_37, _io_out_1_0_bits_T_33) wire _io_out_1_0_bits_WIRE_4 : UInt<4> connect _io_out_1_0_bits_WIRE_4, _io_out_1_0_bits_T_38 connect _io_out_1_0_bits_WIRE_2.egress_node, _io_out_1_0_bits_WIRE_4 node _io_out_1_0_bits_T_39 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_40 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_41 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_42 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_43 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_44 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_45 = or(_io_out_1_0_bits_T_39, _io_out_1_0_bits_T_40) node _io_out_1_0_bits_T_46 = or(_io_out_1_0_bits_T_45, _io_out_1_0_bits_T_41) node _io_out_1_0_bits_T_47 = or(_io_out_1_0_bits_T_46, _io_out_1_0_bits_T_42) node _io_out_1_0_bits_T_48 = or(_io_out_1_0_bits_T_47, _io_out_1_0_bits_T_43) node _io_out_1_0_bits_T_49 = or(_io_out_1_0_bits_T_48, _io_out_1_0_bits_T_44) wire _io_out_1_0_bits_WIRE_5 : UInt<3> connect _io_out_1_0_bits_WIRE_5, _io_out_1_0_bits_T_49 connect _io_out_1_0_bits_WIRE_2.ingress_node_id, _io_out_1_0_bits_WIRE_5 node _io_out_1_0_bits_T_50 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_51 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_52 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_53 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_54 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_55 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_56 = or(_io_out_1_0_bits_T_50, _io_out_1_0_bits_T_51) node _io_out_1_0_bits_T_57 = or(_io_out_1_0_bits_T_56, _io_out_1_0_bits_T_52) node _io_out_1_0_bits_T_58 = or(_io_out_1_0_bits_T_57, _io_out_1_0_bits_T_53) node _io_out_1_0_bits_T_59 = or(_io_out_1_0_bits_T_58, _io_out_1_0_bits_T_54) node _io_out_1_0_bits_T_60 = or(_io_out_1_0_bits_T_59, _io_out_1_0_bits_T_55) wire _io_out_1_0_bits_WIRE_6 : UInt<4> connect _io_out_1_0_bits_WIRE_6, _io_out_1_0_bits_T_60 connect _io_out_1_0_bits_WIRE_2.ingress_node, _io_out_1_0_bits_WIRE_6 node _io_out_1_0_bits_T_61 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_62 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_63 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_64 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_65 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_66 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_67 = or(_io_out_1_0_bits_T_61, _io_out_1_0_bits_T_62) node _io_out_1_0_bits_T_68 = or(_io_out_1_0_bits_T_67, _io_out_1_0_bits_T_63) node _io_out_1_0_bits_T_69 = or(_io_out_1_0_bits_T_68, _io_out_1_0_bits_T_64) node _io_out_1_0_bits_T_70 = or(_io_out_1_0_bits_T_69, _io_out_1_0_bits_T_65) node _io_out_1_0_bits_T_71 = or(_io_out_1_0_bits_T_70, _io_out_1_0_bits_T_66) wire _io_out_1_0_bits_WIRE_7 : UInt<3> connect _io_out_1_0_bits_WIRE_7, _io_out_1_0_bits_T_71 connect _io_out_1_0_bits_WIRE_2.vnet_id, _io_out_1_0_bits_WIRE_7 connect _io_out_1_0_bits_WIRE.flow, _io_out_1_0_bits_WIRE_2 node _io_out_1_0_bits_T_72 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_73 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_74 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_75 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_76 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_77 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_78 = or(_io_out_1_0_bits_T_72, _io_out_1_0_bits_T_73) node _io_out_1_0_bits_T_79 = or(_io_out_1_0_bits_T_78, _io_out_1_0_bits_T_74) node _io_out_1_0_bits_T_80 = or(_io_out_1_0_bits_T_79, _io_out_1_0_bits_T_75) node _io_out_1_0_bits_T_81 = or(_io_out_1_0_bits_T_80, _io_out_1_0_bits_T_76) node _io_out_1_0_bits_T_82 = or(_io_out_1_0_bits_T_81, _io_out_1_0_bits_T_77) wire _io_out_1_0_bits_WIRE_8 : UInt<73> connect _io_out_1_0_bits_WIRE_8, _io_out_1_0_bits_T_82 connect _io_out_1_0_bits_WIRE.payload, _io_out_1_0_bits_WIRE_8 node _io_out_1_0_bits_T_83 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_84 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_85 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_86 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_87 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_88 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_89 = or(_io_out_1_0_bits_T_83, _io_out_1_0_bits_T_84) node _io_out_1_0_bits_T_90 = or(_io_out_1_0_bits_T_89, _io_out_1_0_bits_T_85) node _io_out_1_0_bits_T_91 = or(_io_out_1_0_bits_T_90, _io_out_1_0_bits_T_86) node _io_out_1_0_bits_T_92 = or(_io_out_1_0_bits_T_91, _io_out_1_0_bits_T_87) node _io_out_1_0_bits_T_93 = or(_io_out_1_0_bits_T_92, _io_out_1_0_bits_T_88) wire _io_out_1_0_bits_WIRE_9 : UInt<1> connect _io_out_1_0_bits_WIRE_9, _io_out_1_0_bits_T_93 connect _io_out_1_0_bits_WIRE.tail, _io_out_1_0_bits_WIRE_9 node _io_out_1_0_bits_T_94 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_95 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_96 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_97 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_98 = mux(_io_out_1_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_99 = mux(_io_out_1_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_100 = or(_io_out_1_0_bits_T_94, _io_out_1_0_bits_T_95) node _io_out_1_0_bits_T_101 = or(_io_out_1_0_bits_T_100, _io_out_1_0_bits_T_96) node _io_out_1_0_bits_T_102 = or(_io_out_1_0_bits_T_101, _io_out_1_0_bits_T_97) node _io_out_1_0_bits_T_103 = or(_io_out_1_0_bits_T_102, _io_out_1_0_bits_T_98) node _io_out_1_0_bits_T_104 = or(_io_out_1_0_bits_T_103, _io_out_1_0_bits_T_99) wire _io_out_1_0_bits_WIRE_10 : UInt<1> connect _io_out_1_0_bits_WIRE_10, _io_out_1_0_bits_T_104 connect _io_out_1_0_bits_WIRE.head, _io_out_1_0_bits_WIRE_10 connect io.out.`1`[0].bits, _io_out_1_0_bits_WIRE node _io_out_1_0_bits_virt_channel_id_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_virt_channel_id_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_virt_channel_id_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_bits_virt_channel_id_T_3 = bits(sel_flat_1, 3, 3) node _io_out_1_0_bits_virt_channel_id_T_4 = bits(sel_flat_1, 4, 4) node _io_out_1_0_bits_virt_channel_id_T_5 = bits(sel_flat_1, 5, 5) node _io_out_1_0_bits_virt_channel_id_T_6 = mux(_io_out_1_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_7 = mux(_io_out_1_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_8 = mux(_io_out_1_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_9 = mux(_io_out_1_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_10 = mux(_io_out_1_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_11 = mux(_io_out_1_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_12 = or(_io_out_1_0_bits_virt_channel_id_T_6, _io_out_1_0_bits_virt_channel_id_T_7) node _io_out_1_0_bits_virt_channel_id_T_13 = or(_io_out_1_0_bits_virt_channel_id_T_12, _io_out_1_0_bits_virt_channel_id_T_8) node _io_out_1_0_bits_virt_channel_id_T_14 = or(_io_out_1_0_bits_virt_channel_id_T_13, _io_out_1_0_bits_virt_channel_id_T_9) node _io_out_1_0_bits_virt_channel_id_T_15 = or(_io_out_1_0_bits_virt_channel_id_T_14, _io_out_1_0_bits_virt_channel_id_T_10) node _io_out_1_0_bits_virt_channel_id_T_16 = or(_io_out_1_0_bits_virt_channel_id_T_15, _io_out_1_0_bits_virt_channel_id_T_11) wire _io_out_1_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_1_0_bits_virt_channel_id_WIRE, _io_out_1_0_bits_virt_channel_id_T_16 connect io.out.`1`[0].bits.virt_channel_id, _io_out_1_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_2 = cat(io.sel.`2`[0].`2`[0], io.sel.`2`[0].`1`[0]) node sel_flat_lo_2 = cat(sel_flat_lo_hi_2, io.sel.`2`[0].`0`[0]) node sel_flat_hi_hi_2 = cat(io.sel.`2`[0].`5`[0], io.sel.`2`[0].`4`[0]) node sel_flat_hi_2 = cat(sel_flat_hi_hi_2, io.sel.`2`[0].`3`[0]) node sel_flat_2 = cat(sel_flat_hi_2, sel_flat_lo_2) node _T_40 = bits(sel_flat_2, 0, 0) node _T_41 = bits(sel_flat_2, 1, 1) node _T_42 = bits(sel_flat_2, 2, 2) node _T_43 = bits(sel_flat_2, 3, 3) node _T_44 = bits(sel_flat_2, 4, 4) node _T_45 = bits(sel_flat_2, 5, 5) node _T_46 = add(_T_41, _T_42) node _T_47 = bits(_T_46, 1, 0) node _T_48 = add(_T_40, _T_47) node _T_49 = bits(_T_48, 1, 0) node _T_50 = add(_T_44, _T_45) node _T_51 = bits(_T_50, 1, 0) node _T_52 = add(_T_43, _T_51) node _T_53 = bits(_T_52, 1, 0) node _T_54 = add(_T_49, _T_53) node _T_55 = bits(_T_54, 2, 0) node _T_56 = leq(_T_55, UInt<1>(0h1)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_2 assert(clock, _T_56, UInt<1>(0h1), "") : assert_2 node _io_out_2_0_valid_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_valid_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_valid_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_valid_T_3 = bits(sel_flat_2, 3, 3) node _io_out_2_0_valid_T_4 = bits(sel_flat_2, 4, 4) node _io_out_2_0_valid_T_5 = bits(sel_flat_2, 5, 5) node _io_out_2_0_valid_T_6 = mux(_io_out_2_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_7 = mux(_io_out_2_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_8 = mux(_io_out_2_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_9 = mux(_io_out_2_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_10 = mux(_io_out_2_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_11 = mux(_io_out_2_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_12 = or(_io_out_2_0_valid_T_6, _io_out_2_0_valid_T_7) node _io_out_2_0_valid_T_13 = or(_io_out_2_0_valid_T_12, _io_out_2_0_valid_T_8) node _io_out_2_0_valid_T_14 = or(_io_out_2_0_valid_T_13, _io_out_2_0_valid_T_9) node _io_out_2_0_valid_T_15 = or(_io_out_2_0_valid_T_14, _io_out_2_0_valid_T_10) node _io_out_2_0_valid_T_16 = or(_io_out_2_0_valid_T_15, _io_out_2_0_valid_T_11) wire _io_out_2_0_valid_WIRE : UInt<1> connect _io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_16 node _io_out_2_0_valid_T_17 = neq(sel_flat_2, UInt<1>(0h0)) node _io_out_2_0_valid_T_18 = and(_io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_17) connect io.out.`2`[0].valid, _io_out_2_0_valid_T_18 node _io_out_2_0_bits_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_bits_T_3 = bits(sel_flat_2, 3, 3) node _io_out_2_0_bits_T_4 = bits(sel_flat_2, 4, 4) node _io_out_2_0_bits_T_5 = bits(sel_flat_2, 5, 5) wire _io_out_2_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_2_0_bits_T_6 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_7 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_8 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_9 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_10 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_11 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_12 = or(_io_out_2_0_bits_T_6, _io_out_2_0_bits_T_7) node _io_out_2_0_bits_T_13 = or(_io_out_2_0_bits_T_12, _io_out_2_0_bits_T_8) node _io_out_2_0_bits_T_14 = or(_io_out_2_0_bits_T_13, _io_out_2_0_bits_T_9) node _io_out_2_0_bits_T_15 = or(_io_out_2_0_bits_T_14, _io_out_2_0_bits_T_10) node _io_out_2_0_bits_T_16 = or(_io_out_2_0_bits_T_15, _io_out_2_0_bits_T_11) wire _io_out_2_0_bits_WIRE_1 : UInt<4> connect _io_out_2_0_bits_WIRE_1, _io_out_2_0_bits_T_16 connect _io_out_2_0_bits_WIRE.virt_channel_id, _io_out_2_0_bits_WIRE_1 wire _io_out_2_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_2_0_bits_T_17 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_18 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_19 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_20 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_21 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_22 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_23 = or(_io_out_2_0_bits_T_17, _io_out_2_0_bits_T_18) node _io_out_2_0_bits_T_24 = or(_io_out_2_0_bits_T_23, _io_out_2_0_bits_T_19) node _io_out_2_0_bits_T_25 = or(_io_out_2_0_bits_T_24, _io_out_2_0_bits_T_20) node _io_out_2_0_bits_T_26 = or(_io_out_2_0_bits_T_25, _io_out_2_0_bits_T_21) node _io_out_2_0_bits_T_27 = or(_io_out_2_0_bits_T_26, _io_out_2_0_bits_T_22) wire _io_out_2_0_bits_WIRE_3 : UInt<3> connect _io_out_2_0_bits_WIRE_3, _io_out_2_0_bits_T_27 connect _io_out_2_0_bits_WIRE_2.egress_node_id, _io_out_2_0_bits_WIRE_3 node _io_out_2_0_bits_T_28 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_29 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_30 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_31 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_32 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_33 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_34 = or(_io_out_2_0_bits_T_28, _io_out_2_0_bits_T_29) node _io_out_2_0_bits_T_35 = or(_io_out_2_0_bits_T_34, _io_out_2_0_bits_T_30) node _io_out_2_0_bits_T_36 = or(_io_out_2_0_bits_T_35, _io_out_2_0_bits_T_31) node _io_out_2_0_bits_T_37 = or(_io_out_2_0_bits_T_36, _io_out_2_0_bits_T_32) node _io_out_2_0_bits_T_38 = or(_io_out_2_0_bits_T_37, _io_out_2_0_bits_T_33) wire _io_out_2_0_bits_WIRE_4 : UInt<4> connect _io_out_2_0_bits_WIRE_4, _io_out_2_0_bits_T_38 connect _io_out_2_0_bits_WIRE_2.egress_node, _io_out_2_0_bits_WIRE_4 node _io_out_2_0_bits_T_39 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_40 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_41 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_42 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_43 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_44 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_45 = or(_io_out_2_0_bits_T_39, _io_out_2_0_bits_T_40) node _io_out_2_0_bits_T_46 = or(_io_out_2_0_bits_T_45, _io_out_2_0_bits_T_41) node _io_out_2_0_bits_T_47 = or(_io_out_2_0_bits_T_46, _io_out_2_0_bits_T_42) node _io_out_2_0_bits_T_48 = or(_io_out_2_0_bits_T_47, _io_out_2_0_bits_T_43) node _io_out_2_0_bits_T_49 = or(_io_out_2_0_bits_T_48, _io_out_2_0_bits_T_44) wire _io_out_2_0_bits_WIRE_5 : UInt<3> connect _io_out_2_0_bits_WIRE_5, _io_out_2_0_bits_T_49 connect _io_out_2_0_bits_WIRE_2.ingress_node_id, _io_out_2_0_bits_WIRE_5 node _io_out_2_0_bits_T_50 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_51 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_52 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_53 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_54 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_55 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_56 = or(_io_out_2_0_bits_T_50, _io_out_2_0_bits_T_51) node _io_out_2_0_bits_T_57 = or(_io_out_2_0_bits_T_56, _io_out_2_0_bits_T_52) node _io_out_2_0_bits_T_58 = or(_io_out_2_0_bits_T_57, _io_out_2_0_bits_T_53) node _io_out_2_0_bits_T_59 = or(_io_out_2_0_bits_T_58, _io_out_2_0_bits_T_54) node _io_out_2_0_bits_T_60 = or(_io_out_2_0_bits_T_59, _io_out_2_0_bits_T_55) wire _io_out_2_0_bits_WIRE_6 : UInt<4> connect _io_out_2_0_bits_WIRE_6, _io_out_2_0_bits_T_60 connect _io_out_2_0_bits_WIRE_2.ingress_node, _io_out_2_0_bits_WIRE_6 node _io_out_2_0_bits_T_61 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_62 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_63 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_64 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_65 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_66 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_67 = or(_io_out_2_0_bits_T_61, _io_out_2_0_bits_T_62) node _io_out_2_0_bits_T_68 = or(_io_out_2_0_bits_T_67, _io_out_2_0_bits_T_63) node _io_out_2_0_bits_T_69 = or(_io_out_2_0_bits_T_68, _io_out_2_0_bits_T_64) node _io_out_2_0_bits_T_70 = or(_io_out_2_0_bits_T_69, _io_out_2_0_bits_T_65) node _io_out_2_0_bits_T_71 = or(_io_out_2_0_bits_T_70, _io_out_2_0_bits_T_66) wire _io_out_2_0_bits_WIRE_7 : UInt<3> connect _io_out_2_0_bits_WIRE_7, _io_out_2_0_bits_T_71 connect _io_out_2_0_bits_WIRE_2.vnet_id, _io_out_2_0_bits_WIRE_7 connect _io_out_2_0_bits_WIRE.flow, _io_out_2_0_bits_WIRE_2 node _io_out_2_0_bits_T_72 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_73 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_74 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_75 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_76 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_77 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_78 = or(_io_out_2_0_bits_T_72, _io_out_2_0_bits_T_73) node _io_out_2_0_bits_T_79 = or(_io_out_2_0_bits_T_78, _io_out_2_0_bits_T_74) node _io_out_2_0_bits_T_80 = or(_io_out_2_0_bits_T_79, _io_out_2_0_bits_T_75) node _io_out_2_0_bits_T_81 = or(_io_out_2_0_bits_T_80, _io_out_2_0_bits_T_76) node _io_out_2_0_bits_T_82 = or(_io_out_2_0_bits_T_81, _io_out_2_0_bits_T_77) wire _io_out_2_0_bits_WIRE_8 : UInt<73> connect _io_out_2_0_bits_WIRE_8, _io_out_2_0_bits_T_82 connect _io_out_2_0_bits_WIRE.payload, _io_out_2_0_bits_WIRE_8 node _io_out_2_0_bits_T_83 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_84 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_85 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_86 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_87 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_88 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_89 = or(_io_out_2_0_bits_T_83, _io_out_2_0_bits_T_84) node _io_out_2_0_bits_T_90 = or(_io_out_2_0_bits_T_89, _io_out_2_0_bits_T_85) node _io_out_2_0_bits_T_91 = or(_io_out_2_0_bits_T_90, _io_out_2_0_bits_T_86) node _io_out_2_0_bits_T_92 = or(_io_out_2_0_bits_T_91, _io_out_2_0_bits_T_87) node _io_out_2_0_bits_T_93 = or(_io_out_2_0_bits_T_92, _io_out_2_0_bits_T_88) wire _io_out_2_0_bits_WIRE_9 : UInt<1> connect _io_out_2_0_bits_WIRE_9, _io_out_2_0_bits_T_93 connect _io_out_2_0_bits_WIRE.tail, _io_out_2_0_bits_WIRE_9 node _io_out_2_0_bits_T_94 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_95 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_96 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_97 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_98 = mux(_io_out_2_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_99 = mux(_io_out_2_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_100 = or(_io_out_2_0_bits_T_94, _io_out_2_0_bits_T_95) node _io_out_2_0_bits_T_101 = or(_io_out_2_0_bits_T_100, _io_out_2_0_bits_T_96) node _io_out_2_0_bits_T_102 = or(_io_out_2_0_bits_T_101, _io_out_2_0_bits_T_97) node _io_out_2_0_bits_T_103 = or(_io_out_2_0_bits_T_102, _io_out_2_0_bits_T_98) node _io_out_2_0_bits_T_104 = or(_io_out_2_0_bits_T_103, _io_out_2_0_bits_T_99) wire _io_out_2_0_bits_WIRE_10 : UInt<1> connect _io_out_2_0_bits_WIRE_10, _io_out_2_0_bits_T_104 connect _io_out_2_0_bits_WIRE.head, _io_out_2_0_bits_WIRE_10 connect io.out.`2`[0].bits, _io_out_2_0_bits_WIRE node _io_out_2_0_bits_virt_channel_id_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_virt_channel_id_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_virt_channel_id_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_bits_virt_channel_id_T_3 = bits(sel_flat_2, 3, 3) node _io_out_2_0_bits_virt_channel_id_T_4 = bits(sel_flat_2, 4, 4) node _io_out_2_0_bits_virt_channel_id_T_5 = bits(sel_flat_2, 5, 5) node _io_out_2_0_bits_virt_channel_id_T_6 = mux(_io_out_2_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_7 = mux(_io_out_2_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_8 = mux(_io_out_2_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_9 = mux(_io_out_2_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_10 = mux(_io_out_2_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_11 = mux(_io_out_2_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_12 = or(_io_out_2_0_bits_virt_channel_id_T_6, _io_out_2_0_bits_virt_channel_id_T_7) node _io_out_2_0_bits_virt_channel_id_T_13 = or(_io_out_2_0_bits_virt_channel_id_T_12, _io_out_2_0_bits_virt_channel_id_T_8) node _io_out_2_0_bits_virt_channel_id_T_14 = or(_io_out_2_0_bits_virt_channel_id_T_13, _io_out_2_0_bits_virt_channel_id_T_9) node _io_out_2_0_bits_virt_channel_id_T_15 = or(_io_out_2_0_bits_virt_channel_id_T_14, _io_out_2_0_bits_virt_channel_id_T_10) node _io_out_2_0_bits_virt_channel_id_T_16 = or(_io_out_2_0_bits_virt_channel_id_T_15, _io_out_2_0_bits_virt_channel_id_T_11) wire _io_out_2_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_2_0_bits_virt_channel_id_WIRE, _io_out_2_0_bits_virt_channel_id_T_16 connect io.out.`2`[0].bits.virt_channel_id, _io_out_2_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_3 = cat(io.sel.`3`[0].`2`[0], io.sel.`3`[0].`1`[0]) node sel_flat_lo_3 = cat(sel_flat_lo_hi_3, io.sel.`3`[0].`0`[0]) node sel_flat_hi_hi_3 = cat(io.sel.`3`[0].`5`[0], io.sel.`3`[0].`4`[0]) node sel_flat_hi_3 = cat(sel_flat_hi_hi_3, io.sel.`3`[0].`3`[0]) node sel_flat_3 = cat(sel_flat_hi_3, sel_flat_lo_3) node _T_60 = bits(sel_flat_3, 0, 0) node _T_61 = bits(sel_flat_3, 1, 1) node _T_62 = bits(sel_flat_3, 2, 2) node _T_63 = bits(sel_flat_3, 3, 3) node _T_64 = bits(sel_flat_3, 4, 4) node _T_65 = bits(sel_flat_3, 5, 5) node _T_66 = add(_T_61, _T_62) node _T_67 = bits(_T_66, 1, 0) node _T_68 = add(_T_60, _T_67) node _T_69 = bits(_T_68, 1, 0) node _T_70 = add(_T_64, _T_65) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(_T_63, _T_71) node _T_73 = bits(_T_72, 1, 0) node _T_74 = add(_T_69, _T_73) node _T_75 = bits(_T_74, 2, 0) node _T_76 = leq(_T_75, UInt<1>(0h1)) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_3 assert(clock, _T_76, UInt<1>(0h1), "") : assert_3 node _io_out_3_0_valid_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_valid_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_valid_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_valid_T_3 = bits(sel_flat_3, 3, 3) node _io_out_3_0_valid_T_4 = bits(sel_flat_3, 4, 4) node _io_out_3_0_valid_T_5 = bits(sel_flat_3, 5, 5) node _io_out_3_0_valid_T_6 = mux(_io_out_3_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_7 = mux(_io_out_3_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_8 = mux(_io_out_3_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_9 = mux(_io_out_3_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_10 = mux(_io_out_3_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_11 = mux(_io_out_3_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_12 = or(_io_out_3_0_valid_T_6, _io_out_3_0_valid_T_7) node _io_out_3_0_valid_T_13 = or(_io_out_3_0_valid_T_12, _io_out_3_0_valid_T_8) node _io_out_3_0_valid_T_14 = or(_io_out_3_0_valid_T_13, _io_out_3_0_valid_T_9) node _io_out_3_0_valid_T_15 = or(_io_out_3_0_valid_T_14, _io_out_3_0_valid_T_10) node _io_out_3_0_valid_T_16 = or(_io_out_3_0_valid_T_15, _io_out_3_0_valid_T_11) wire _io_out_3_0_valid_WIRE : UInt<1> connect _io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_16 node _io_out_3_0_valid_T_17 = neq(sel_flat_3, UInt<1>(0h0)) node _io_out_3_0_valid_T_18 = and(_io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_17) connect io.out.`3`[0].valid, _io_out_3_0_valid_T_18 node _io_out_3_0_bits_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_bits_T_3 = bits(sel_flat_3, 3, 3) node _io_out_3_0_bits_T_4 = bits(sel_flat_3, 4, 4) node _io_out_3_0_bits_T_5 = bits(sel_flat_3, 5, 5) wire _io_out_3_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_3_0_bits_T_6 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_7 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_8 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_9 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_10 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_11 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_12 = or(_io_out_3_0_bits_T_6, _io_out_3_0_bits_T_7) node _io_out_3_0_bits_T_13 = or(_io_out_3_0_bits_T_12, _io_out_3_0_bits_T_8) node _io_out_3_0_bits_T_14 = or(_io_out_3_0_bits_T_13, _io_out_3_0_bits_T_9) node _io_out_3_0_bits_T_15 = or(_io_out_3_0_bits_T_14, _io_out_3_0_bits_T_10) node _io_out_3_0_bits_T_16 = or(_io_out_3_0_bits_T_15, _io_out_3_0_bits_T_11) wire _io_out_3_0_bits_WIRE_1 : UInt<4> connect _io_out_3_0_bits_WIRE_1, _io_out_3_0_bits_T_16 connect _io_out_3_0_bits_WIRE.virt_channel_id, _io_out_3_0_bits_WIRE_1 wire _io_out_3_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_3_0_bits_T_17 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_18 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_19 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_20 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_21 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_22 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_23 = or(_io_out_3_0_bits_T_17, _io_out_3_0_bits_T_18) node _io_out_3_0_bits_T_24 = or(_io_out_3_0_bits_T_23, _io_out_3_0_bits_T_19) node _io_out_3_0_bits_T_25 = or(_io_out_3_0_bits_T_24, _io_out_3_0_bits_T_20) node _io_out_3_0_bits_T_26 = or(_io_out_3_0_bits_T_25, _io_out_3_0_bits_T_21) node _io_out_3_0_bits_T_27 = or(_io_out_3_0_bits_T_26, _io_out_3_0_bits_T_22) wire _io_out_3_0_bits_WIRE_3 : UInt<3> connect _io_out_3_0_bits_WIRE_3, _io_out_3_0_bits_T_27 connect _io_out_3_0_bits_WIRE_2.egress_node_id, _io_out_3_0_bits_WIRE_3 node _io_out_3_0_bits_T_28 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_29 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_30 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_31 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_32 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_33 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_34 = or(_io_out_3_0_bits_T_28, _io_out_3_0_bits_T_29) node _io_out_3_0_bits_T_35 = or(_io_out_3_0_bits_T_34, _io_out_3_0_bits_T_30) node _io_out_3_0_bits_T_36 = or(_io_out_3_0_bits_T_35, _io_out_3_0_bits_T_31) node _io_out_3_0_bits_T_37 = or(_io_out_3_0_bits_T_36, _io_out_3_0_bits_T_32) node _io_out_3_0_bits_T_38 = or(_io_out_3_0_bits_T_37, _io_out_3_0_bits_T_33) wire _io_out_3_0_bits_WIRE_4 : UInt<4> connect _io_out_3_0_bits_WIRE_4, _io_out_3_0_bits_T_38 connect _io_out_3_0_bits_WIRE_2.egress_node, _io_out_3_0_bits_WIRE_4 node _io_out_3_0_bits_T_39 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_40 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_41 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_42 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_43 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_44 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_45 = or(_io_out_3_0_bits_T_39, _io_out_3_0_bits_T_40) node _io_out_3_0_bits_T_46 = or(_io_out_3_0_bits_T_45, _io_out_3_0_bits_T_41) node _io_out_3_0_bits_T_47 = or(_io_out_3_0_bits_T_46, _io_out_3_0_bits_T_42) node _io_out_3_0_bits_T_48 = or(_io_out_3_0_bits_T_47, _io_out_3_0_bits_T_43) node _io_out_3_0_bits_T_49 = or(_io_out_3_0_bits_T_48, _io_out_3_0_bits_T_44) wire _io_out_3_0_bits_WIRE_5 : UInt<3> connect _io_out_3_0_bits_WIRE_5, _io_out_3_0_bits_T_49 connect _io_out_3_0_bits_WIRE_2.ingress_node_id, _io_out_3_0_bits_WIRE_5 node _io_out_3_0_bits_T_50 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_51 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_52 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_53 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_54 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_55 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_56 = or(_io_out_3_0_bits_T_50, _io_out_3_0_bits_T_51) node _io_out_3_0_bits_T_57 = or(_io_out_3_0_bits_T_56, _io_out_3_0_bits_T_52) node _io_out_3_0_bits_T_58 = or(_io_out_3_0_bits_T_57, _io_out_3_0_bits_T_53) node _io_out_3_0_bits_T_59 = or(_io_out_3_0_bits_T_58, _io_out_3_0_bits_T_54) node _io_out_3_0_bits_T_60 = or(_io_out_3_0_bits_T_59, _io_out_3_0_bits_T_55) wire _io_out_3_0_bits_WIRE_6 : UInt<4> connect _io_out_3_0_bits_WIRE_6, _io_out_3_0_bits_T_60 connect _io_out_3_0_bits_WIRE_2.ingress_node, _io_out_3_0_bits_WIRE_6 node _io_out_3_0_bits_T_61 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_62 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_63 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_64 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_65 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_66 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_67 = or(_io_out_3_0_bits_T_61, _io_out_3_0_bits_T_62) node _io_out_3_0_bits_T_68 = or(_io_out_3_0_bits_T_67, _io_out_3_0_bits_T_63) node _io_out_3_0_bits_T_69 = or(_io_out_3_0_bits_T_68, _io_out_3_0_bits_T_64) node _io_out_3_0_bits_T_70 = or(_io_out_3_0_bits_T_69, _io_out_3_0_bits_T_65) node _io_out_3_0_bits_T_71 = or(_io_out_3_0_bits_T_70, _io_out_3_0_bits_T_66) wire _io_out_3_0_bits_WIRE_7 : UInt<3> connect _io_out_3_0_bits_WIRE_7, _io_out_3_0_bits_T_71 connect _io_out_3_0_bits_WIRE_2.vnet_id, _io_out_3_0_bits_WIRE_7 connect _io_out_3_0_bits_WIRE.flow, _io_out_3_0_bits_WIRE_2 node _io_out_3_0_bits_T_72 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_73 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_74 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_75 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_76 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_77 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_78 = or(_io_out_3_0_bits_T_72, _io_out_3_0_bits_T_73) node _io_out_3_0_bits_T_79 = or(_io_out_3_0_bits_T_78, _io_out_3_0_bits_T_74) node _io_out_3_0_bits_T_80 = or(_io_out_3_0_bits_T_79, _io_out_3_0_bits_T_75) node _io_out_3_0_bits_T_81 = or(_io_out_3_0_bits_T_80, _io_out_3_0_bits_T_76) node _io_out_3_0_bits_T_82 = or(_io_out_3_0_bits_T_81, _io_out_3_0_bits_T_77) wire _io_out_3_0_bits_WIRE_8 : UInt<73> connect _io_out_3_0_bits_WIRE_8, _io_out_3_0_bits_T_82 connect _io_out_3_0_bits_WIRE.payload, _io_out_3_0_bits_WIRE_8 node _io_out_3_0_bits_T_83 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_84 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_85 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_86 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_87 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_88 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_89 = or(_io_out_3_0_bits_T_83, _io_out_3_0_bits_T_84) node _io_out_3_0_bits_T_90 = or(_io_out_3_0_bits_T_89, _io_out_3_0_bits_T_85) node _io_out_3_0_bits_T_91 = or(_io_out_3_0_bits_T_90, _io_out_3_0_bits_T_86) node _io_out_3_0_bits_T_92 = or(_io_out_3_0_bits_T_91, _io_out_3_0_bits_T_87) node _io_out_3_0_bits_T_93 = or(_io_out_3_0_bits_T_92, _io_out_3_0_bits_T_88) wire _io_out_3_0_bits_WIRE_9 : UInt<1> connect _io_out_3_0_bits_WIRE_9, _io_out_3_0_bits_T_93 connect _io_out_3_0_bits_WIRE.tail, _io_out_3_0_bits_WIRE_9 node _io_out_3_0_bits_T_94 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_95 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_96 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_97 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_98 = mux(_io_out_3_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_99 = mux(_io_out_3_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_100 = or(_io_out_3_0_bits_T_94, _io_out_3_0_bits_T_95) node _io_out_3_0_bits_T_101 = or(_io_out_3_0_bits_T_100, _io_out_3_0_bits_T_96) node _io_out_3_0_bits_T_102 = or(_io_out_3_0_bits_T_101, _io_out_3_0_bits_T_97) node _io_out_3_0_bits_T_103 = or(_io_out_3_0_bits_T_102, _io_out_3_0_bits_T_98) node _io_out_3_0_bits_T_104 = or(_io_out_3_0_bits_T_103, _io_out_3_0_bits_T_99) wire _io_out_3_0_bits_WIRE_10 : UInt<1> connect _io_out_3_0_bits_WIRE_10, _io_out_3_0_bits_T_104 connect _io_out_3_0_bits_WIRE.head, _io_out_3_0_bits_WIRE_10 connect io.out.`3`[0].bits, _io_out_3_0_bits_WIRE node _io_out_3_0_bits_virt_channel_id_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_virt_channel_id_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_virt_channel_id_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_bits_virt_channel_id_T_3 = bits(sel_flat_3, 3, 3) node _io_out_3_0_bits_virt_channel_id_T_4 = bits(sel_flat_3, 4, 4) node _io_out_3_0_bits_virt_channel_id_T_5 = bits(sel_flat_3, 5, 5) node _io_out_3_0_bits_virt_channel_id_T_6 = mux(_io_out_3_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_7 = mux(_io_out_3_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_8 = mux(_io_out_3_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_9 = mux(_io_out_3_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_10 = mux(_io_out_3_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_11 = mux(_io_out_3_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_12 = or(_io_out_3_0_bits_virt_channel_id_T_6, _io_out_3_0_bits_virt_channel_id_T_7) node _io_out_3_0_bits_virt_channel_id_T_13 = or(_io_out_3_0_bits_virt_channel_id_T_12, _io_out_3_0_bits_virt_channel_id_T_8) node _io_out_3_0_bits_virt_channel_id_T_14 = or(_io_out_3_0_bits_virt_channel_id_T_13, _io_out_3_0_bits_virt_channel_id_T_9) node _io_out_3_0_bits_virt_channel_id_T_15 = or(_io_out_3_0_bits_virt_channel_id_T_14, _io_out_3_0_bits_virt_channel_id_T_10) node _io_out_3_0_bits_virt_channel_id_T_16 = or(_io_out_3_0_bits_virt_channel_id_T_15, _io_out_3_0_bits_virt_channel_id_T_11) wire _io_out_3_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_3_0_bits_virt_channel_id_WIRE, _io_out_3_0_bits_virt_channel_id_T_16 connect io.out.`3`[0].bits.virt_channel_id, _io_out_3_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_4 = cat(io.sel.`4`[0].`2`[0], io.sel.`4`[0].`1`[0]) node sel_flat_lo_4 = cat(sel_flat_lo_hi_4, io.sel.`4`[0].`0`[0]) node sel_flat_hi_hi_4 = cat(io.sel.`4`[0].`5`[0], io.sel.`4`[0].`4`[0]) node sel_flat_hi_4 = cat(sel_flat_hi_hi_4, io.sel.`4`[0].`3`[0]) node sel_flat_4 = cat(sel_flat_hi_4, sel_flat_lo_4) node _T_80 = bits(sel_flat_4, 0, 0) node _T_81 = bits(sel_flat_4, 1, 1) node _T_82 = bits(sel_flat_4, 2, 2) node _T_83 = bits(sel_flat_4, 3, 3) node _T_84 = bits(sel_flat_4, 4, 4) node _T_85 = bits(sel_flat_4, 5, 5) node _T_86 = add(_T_81, _T_82) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(_T_80, _T_87) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_84, _T_85) node _T_91 = bits(_T_90, 1, 0) node _T_92 = add(_T_83, _T_91) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_89, _T_93) node _T_95 = bits(_T_94, 2, 0) node _T_96 = leq(_T_95, UInt<1>(0h1)) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_4 assert(clock, _T_96, UInt<1>(0h1), "") : assert_4 node _io_out_4_0_valid_T = bits(sel_flat_4, 0, 0) node _io_out_4_0_valid_T_1 = bits(sel_flat_4, 1, 1) node _io_out_4_0_valid_T_2 = bits(sel_flat_4, 2, 2) node _io_out_4_0_valid_T_3 = bits(sel_flat_4, 3, 3) node _io_out_4_0_valid_T_4 = bits(sel_flat_4, 4, 4) node _io_out_4_0_valid_T_5 = bits(sel_flat_4, 5, 5) node _io_out_4_0_valid_T_6 = mux(_io_out_4_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_7 = mux(_io_out_4_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_8 = mux(_io_out_4_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_9 = mux(_io_out_4_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_10 = mux(_io_out_4_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_11 = mux(_io_out_4_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_4_0_valid_T_12 = or(_io_out_4_0_valid_T_6, _io_out_4_0_valid_T_7) node _io_out_4_0_valid_T_13 = or(_io_out_4_0_valid_T_12, _io_out_4_0_valid_T_8) node _io_out_4_0_valid_T_14 = or(_io_out_4_0_valid_T_13, _io_out_4_0_valid_T_9) node _io_out_4_0_valid_T_15 = or(_io_out_4_0_valid_T_14, _io_out_4_0_valid_T_10) node _io_out_4_0_valid_T_16 = or(_io_out_4_0_valid_T_15, _io_out_4_0_valid_T_11) wire _io_out_4_0_valid_WIRE : UInt<1> connect _io_out_4_0_valid_WIRE, _io_out_4_0_valid_T_16 node _io_out_4_0_valid_T_17 = neq(sel_flat_4, UInt<1>(0h0)) node _io_out_4_0_valid_T_18 = and(_io_out_4_0_valid_WIRE, _io_out_4_0_valid_T_17) connect io.out.`4`[0].valid, _io_out_4_0_valid_T_18 node _io_out_4_0_bits_T = bits(sel_flat_4, 0, 0) node _io_out_4_0_bits_T_1 = bits(sel_flat_4, 1, 1) node _io_out_4_0_bits_T_2 = bits(sel_flat_4, 2, 2) node _io_out_4_0_bits_T_3 = bits(sel_flat_4, 3, 3) node _io_out_4_0_bits_T_4 = bits(sel_flat_4, 4, 4) node _io_out_4_0_bits_T_5 = bits(sel_flat_4, 5, 5) wire _io_out_4_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_4_0_bits_T_6 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_7 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_8 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_9 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_10 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_11 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_12 = or(_io_out_4_0_bits_T_6, _io_out_4_0_bits_T_7) node _io_out_4_0_bits_T_13 = or(_io_out_4_0_bits_T_12, _io_out_4_0_bits_T_8) node _io_out_4_0_bits_T_14 = or(_io_out_4_0_bits_T_13, _io_out_4_0_bits_T_9) node _io_out_4_0_bits_T_15 = or(_io_out_4_0_bits_T_14, _io_out_4_0_bits_T_10) node _io_out_4_0_bits_T_16 = or(_io_out_4_0_bits_T_15, _io_out_4_0_bits_T_11) wire _io_out_4_0_bits_WIRE_1 : UInt<4> connect _io_out_4_0_bits_WIRE_1, _io_out_4_0_bits_T_16 connect _io_out_4_0_bits_WIRE.virt_channel_id, _io_out_4_0_bits_WIRE_1 wire _io_out_4_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_4_0_bits_T_17 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_18 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_19 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_20 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_21 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_22 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_23 = or(_io_out_4_0_bits_T_17, _io_out_4_0_bits_T_18) node _io_out_4_0_bits_T_24 = or(_io_out_4_0_bits_T_23, _io_out_4_0_bits_T_19) node _io_out_4_0_bits_T_25 = or(_io_out_4_0_bits_T_24, _io_out_4_0_bits_T_20) node _io_out_4_0_bits_T_26 = or(_io_out_4_0_bits_T_25, _io_out_4_0_bits_T_21) node _io_out_4_0_bits_T_27 = or(_io_out_4_0_bits_T_26, _io_out_4_0_bits_T_22) wire _io_out_4_0_bits_WIRE_3 : UInt<3> connect _io_out_4_0_bits_WIRE_3, _io_out_4_0_bits_T_27 connect _io_out_4_0_bits_WIRE_2.egress_node_id, _io_out_4_0_bits_WIRE_3 node _io_out_4_0_bits_T_28 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_29 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_30 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_31 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_32 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_33 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_34 = or(_io_out_4_0_bits_T_28, _io_out_4_0_bits_T_29) node _io_out_4_0_bits_T_35 = or(_io_out_4_0_bits_T_34, _io_out_4_0_bits_T_30) node _io_out_4_0_bits_T_36 = or(_io_out_4_0_bits_T_35, _io_out_4_0_bits_T_31) node _io_out_4_0_bits_T_37 = or(_io_out_4_0_bits_T_36, _io_out_4_0_bits_T_32) node _io_out_4_0_bits_T_38 = or(_io_out_4_0_bits_T_37, _io_out_4_0_bits_T_33) wire _io_out_4_0_bits_WIRE_4 : UInt<4> connect _io_out_4_0_bits_WIRE_4, _io_out_4_0_bits_T_38 connect _io_out_4_0_bits_WIRE_2.egress_node, _io_out_4_0_bits_WIRE_4 node _io_out_4_0_bits_T_39 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_40 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_41 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_42 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_43 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_44 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_45 = or(_io_out_4_0_bits_T_39, _io_out_4_0_bits_T_40) node _io_out_4_0_bits_T_46 = or(_io_out_4_0_bits_T_45, _io_out_4_0_bits_T_41) node _io_out_4_0_bits_T_47 = or(_io_out_4_0_bits_T_46, _io_out_4_0_bits_T_42) node _io_out_4_0_bits_T_48 = or(_io_out_4_0_bits_T_47, _io_out_4_0_bits_T_43) node _io_out_4_0_bits_T_49 = or(_io_out_4_0_bits_T_48, _io_out_4_0_bits_T_44) wire _io_out_4_0_bits_WIRE_5 : UInt<3> connect _io_out_4_0_bits_WIRE_5, _io_out_4_0_bits_T_49 connect _io_out_4_0_bits_WIRE_2.ingress_node_id, _io_out_4_0_bits_WIRE_5 node _io_out_4_0_bits_T_50 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_51 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_52 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_53 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_54 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_55 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_4_0_bits_T_56 = or(_io_out_4_0_bits_T_50, _io_out_4_0_bits_T_51) node _io_out_4_0_bits_T_57 = or(_io_out_4_0_bits_T_56, _io_out_4_0_bits_T_52) node _io_out_4_0_bits_T_58 = or(_io_out_4_0_bits_T_57, _io_out_4_0_bits_T_53) node _io_out_4_0_bits_T_59 = or(_io_out_4_0_bits_T_58, _io_out_4_0_bits_T_54) node _io_out_4_0_bits_T_60 = or(_io_out_4_0_bits_T_59, _io_out_4_0_bits_T_55) wire _io_out_4_0_bits_WIRE_6 : UInt<4> connect _io_out_4_0_bits_WIRE_6, _io_out_4_0_bits_T_60 connect _io_out_4_0_bits_WIRE_2.ingress_node, _io_out_4_0_bits_WIRE_6 node _io_out_4_0_bits_T_61 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_62 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_63 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_64 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_65 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_66 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_4_0_bits_T_67 = or(_io_out_4_0_bits_T_61, _io_out_4_0_bits_T_62) node _io_out_4_0_bits_T_68 = or(_io_out_4_0_bits_T_67, _io_out_4_0_bits_T_63) node _io_out_4_0_bits_T_69 = or(_io_out_4_0_bits_T_68, _io_out_4_0_bits_T_64) node _io_out_4_0_bits_T_70 = or(_io_out_4_0_bits_T_69, _io_out_4_0_bits_T_65) node _io_out_4_0_bits_T_71 = or(_io_out_4_0_bits_T_70, _io_out_4_0_bits_T_66) wire _io_out_4_0_bits_WIRE_7 : UInt<3> connect _io_out_4_0_bits_WIRE_7, _io_out_4_0_bits_T_71 connect _io_out_4_0_bits_WIRE_2.vnet_id, _io_out_4_0_bits_WIRE_7 connect _io_out_4_0_bits_WIRE.flow, _io_out_4_0_bits_WIRE_2 node _io_out_4_0_bits_T_72 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_73 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_74 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_75 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_76 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_77 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_4_0_bits_T_78 = or(_io_out_4_0_bits_T_72, _io_out_4_0_bits_T_73) node _io_out_4_0_bits_T_79 = or(_io_out_4_0_bits_T_78, _io_out_4_0_bits_T_74) node _io_out_4_0_bits_T_80 = or(_io_out_4_0_bits_T_79, _io_out_4_0_bits_T_75) node _io_out_4_0_bits_T_81 = or(_io_out_4_0_bits_T_80, _io_out_4_0_bits_T_76) node _io_out_4_0_bits_T_82 = or(_io_out_4_0_bits_T_81, _io_out_4_0_bits_T_77) wire _io_out_4_0_bits_WIRE_8 : UInt<73> connect _io_out_4_0_bits_WIRE_8, _io_out_4_0_bits_T_82 connect _io_out_4_0_bits_WIRE.payload, _io_out_4_0_bits_WIRE_8 node _io_out_4_0_bits_T_83 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_84 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_85 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_86 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_87 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_88 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_4_0_bits_T_89 = or(_io_out_4_0_bits_T_83, _io_out_4_0_bits_T_84) node _io_out_4_0_bits_T_90 = or(_io_out_4_0_bits_T_89, _io_out_4_0_bits_T_85) node _io_out_4_0_bits_T_91 = or(_io_out_4_0_bits_T_90, _io_out_4_0_bits_T_86) node _io_out_4_0_bits_T_92 = or(_io_out_4_0_bits_T_91, _io_out_4_0_bits_T_87) node _io_out_4_0_bits_T_93 = or(_io_out_4_0_bits_T_92, _io_out_4_0_bits_T_88) wire _io_out_4_0_bits_WIRE_9 : UInt<1> connect _io_out_4_0_bits_WIRE_9, _io_out_4_0_bits_T_93 connect _io_out_4_0_bits_WIRE.tail, _io_out_4_0_bits_WIRE_9 node _io_out_4_0_bits_T_94 = mux(_io_out_4_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_95 = mux(_io_out_4_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_96 = mux(_io_out_4_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_97 = mux(_io_out_4_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_98 = mux(_io_out_4_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_99 = mux(_io_out_4_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_4_0_bits_T_100 = or(_io_out_4_0_bits_T_94, _io_out_4_0_bits_T_95) node _io_out_4_0_bits_T_101 = or(_io_out_4_0_bits_T_100, _io_out_4_0_bits_T_96) node _io_out_4_0_bits_T_102 = or(_io_out_4_0_bits_T_101, _io_out_4_0_bits_T_97) node _io_out_4_0_bits_T_103 = or(_io_out_4_0_bits_T_102, _io_out_4_0_bits_T_98) node _io_out_4_0_bits_T_104 = or(_io_out_4_0_bits_T_103, _io_out_4_0_bits_T_99) wire _io_out_4_0_bits_WIRE_10 : UInt<1> connect _io_out_4_0_bits_WIRE_10, _io_out_4_0_bits_T_104 connect _io_out_4_0_bits_WIRE.head, _io_out_4_0_bits_WIRE_10 connect io.out.`4`[0].bits, _io_out_4_0_bits_WIRE node _io_out_4_0_bits_virt_channel_id_T = bits(sel_flat_4, 0, 0) node _io_out_4_0_bits_virt_channel_id_T_1 = bits(sel_flat_4, 1, 1) node _io_out_4_0_bits_virt_channel_id_T_2 = bits(sel_flat_4, 2, 2) node _io_out_4_0_bits_virt_channel_id_T_3 = bits(sel_flat_4, 3, 3) node _io_out_4_0_bits_virt_channel_id_T_4 = bits(sel_flat_4, 4, 4) node _io_out_4_0_bits_virt_channel_id_T_5 = bits(sel_flat_4, 5, 5) node _io_out_4_0_bits_virt_channel_id_T_6 = mux(_io_out_4_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_7 = mux(_io_out_4_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_8 = mux(_io_out_4_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_9 = mux(_io_out_4_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_10 = mux(_io_out_4_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_11 = mux(_io_out_4_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_4_0_bits_virt_channel_id_T_12 = or(_io_out_4_0_bits_virt_channel_id_T_6, _io_out_4_0_bits_virt_channel_id_T_7) node _io_out_4_0_bits_virt_channel_id_T_13 = or(_io_out_4_0_bits_virt_channel_id_T_12, _io_out_4_0_bits_virt_channel_id_T_8) node _io_out_4_0_bits_virt_channel_id_T_14 = or(_io_out_4_0_bits_virt_channel_id_T_13, _io_out_4_0_bits_virt_channel_id_T_9) node _io_out_4_0_bits_virt_channel_id_T_15 = or(_io_out_4_0_bits_virt_channel_id_T_14, _io_out_4_0_bits_virt_channel_id_T_10) node _io_out_4_0_bits_virt_channel_id_T_16 = or(_io_out_4_0_bits_virt_channel_id_T_15, _io_out_4_0_bits_virt_channel_id_T_11) wire _io_out_4_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_4_0_bits_virt_channel_id_WIRE, _io_out_4_0_bits_virt_channel_id_T_16 connect io.out.`4`[0].bits.virt_channel_id, _io_out_4_0_bits_virt_channel_id_WIRE node sel_flat_lo_hi_5 = cat(io.sel.`5`[0].`2`[0], io.sel.`5`[0].`1`[0]) node sel_flat_lo_5 = cat(sel_flat_lo_hi_5, io.sel.`5`[0].`0`[0]) node sel_flat_hi_hi_5 = cat(io.sel.`5`[0].`5`[0], io.sel.`5`[0].`4`[0]) node sel_flat_hi_5 = cat(sel_flat_hi_hi_5, io.sel.`5`[0].`3`[0]) node sel_flat_5 = cat(sel_flat_hi_5, sel_flat_lo_5) node _T_100 = bits(sel_flat_5, 0, 0) node _T_101 = bits(sel_flat_5, 1, 1) node _T_102 = bits(sel_flat_5, 2, 2) node _T_103 = bits(sel_flat_5, 3, 3) node _T_104 = bits(sel_flat_5, 4, 4) node _T_105 = bits(sel_flat_5, 5, 5) node _T_106 = add(_T_101, _T_102) node _T_107 = bits(_T_106, 1, 0) node _T_108 = add(_T_100, _T_107) node _T_109 = bits(_T_108, 1, 0) node _T_110 = add(_T_104, _T_105) node _T_111 = bits(_T_110, 1, 0) node _T_112 = add(_T_103, _T_111) node _T_113 = bits(_T_112, 1, 0) node _T_114 = add(_T_109, _T_113) node _T_115 = bits(_T_114, 2, 0) node _T_116 = leq(_T_115, UInt<1>(0h1)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_5 assert(clock, _T_116, UInt<1>(0h1), "") : assert_5 node _io_out_5_0_valid_T = bits(sel_flat_5, 0, 0) node _io_out_5_0_valid_T_1 = bits(sel_flat_5, 1, 1) node _io_out_5_0_valid_T_2 = bits(sel_flat_5, 2, 2) node _io_out_5_0_valid_T_3 = bits(sel_flat_5, 3, 3) node _io_out_5_0_valid_T_4 = bits(sel_flat_5, 4, 4) node _io_out_5_0_valid_T_5 = bits(sel_flat_5, 5, 5) node _io_out_5_0_valid_T_6 = mux(_io_out_5_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_7 = mux(_io_out_5_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_8 = mux(_io_out_5_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_9 = mux(_io_out_5_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_10 = mux(_io_out_5_0_valid_T_4, in_flat[4].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_11 = mux(_io_out_5_0_valid_T_5, in_flat[5].valid, UInt<1>(0h0)) node _io_out_5_0_valid_T_12 = or(_io_out_5_0_valid_T_6, _io_out_5_0_valid_T_7) node _io_out_5_0_valid_T_13 = or(_io_out_5_0_valid_T_12, _io_out_5_0_valid_T_8) node _io_out_5_0_valid_T_14 = or(_io_out_5_0_valid_T_13, _io_out_5_0_valid_T_9) node _io_out_5_0_valid_T_15 = or(_io_out_5_0_valid_T_14, _io_out_5_0_valid_T_10) node _io_out_5_0_valid_T_16 = or(_io_out_5_0_valid_T_15, _io_out_5_0_valid_T_11) wire _io_out_5_0_valid_WIRE : UInt<1> connect _io_out_5_0_valid_WIRE, _io_out_5_0_valid_T_16 node _io_out_5_0_valid_T_17 = neq(sel_flat_5, UInt<1>(0h0)) node _io_out_5_0_valid_T_18 = and(_io_out_5_0_valid_WIRE, _io_out_5_0_valid_T_17) connect io.out.`5`[0].valid, _io_out_5_0_valid_T_18 node _io_out_5_0_bits_T = bits(sel_flat_5, 0, 0) node _io_out_5_0_bits_T_1 = bits(sel_flat_5, 1, 1) node _io_out_5_0_bits_T_2 = bits(sel_flat_5, 2, 2) node _io_out_5_0_bits_T_3 = bits(sel_flat_5, 3, 3) node _io_out_5_0_bits_T_4 = bits(sel_flat_5, 4, 4) node _io_out_5_0_bits_T_5 = bits(sel_flat_5, 5, 5) wire _io_out_5_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>} node _io_out_5_0_bits_T_6 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_7 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_8 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_9 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_10 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_11 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_12 = or(_io_out_5_0_bits_T_6, _io_out_5_0_bits_T_7) node _io_out_5_0_bits_T_13 = or(_io_out_5_0_bits_T_12, _io_out_5_0_bits_T_8) node _io_out_5_0_bits_T_14 = or(_io_out_5_0_bits_T_13, _io_out_5_0_bits_T_9) node _io_out_5_0_bits_T_15 = or(_io_out_5_0_bits_T_14, _io_out_5_0_bits_T_10) node _io_out_5_0_bits_T_16 = or(_io_out_5_0_bits_T_15, _io_out_5_0_bits_T_11) wire _io_out_5_0_bits_WIRE_1 : UInt<4> connect _io_out_5_0_bits_WIRE_1, _io_out_5_0_bits_T_16 connect _io_out_5_0_bits_WIRE.virt_channel_id, _io_out_5_0_bits_WIRE_1 wire _io_out_5_0_bits_WIRE_2 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_out_5_0_bits_T_17 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_18 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_19 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_20 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_21 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_22 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_23 = or(_io_out_5_0_bits_T_17, _io_out_5_0_bits_T_18) node _io_out_5_0_bits_T_24 = or(_io_out_5_0_bits_T_23, _io_out_5_0_bits_T_19) node _io_out_5_0_bits_T_25 = or(_io_out_5_0_bits_T_24, _io_out_5_0_bits_T_20) node _io_out_5_0_bits_T_26 = or(_io_out_5_0_bits_T_25, _io_out_5_0_bits_T_21) node _io_out_5_0_bits_T_27 = or(_io_out_5_0_bits_T_26, _io_out_5_0_bits_T_22) wire _io_out_5_0_bits_WIRE_3 : UInt<3> connect _io_out_5_0_bits_WIRE_3, _io_out_5_0_bits_T_27 connect _io_out_5_0_bits_WIRE_2.egress_node_id, _io_out_5_0_bits_WIRE_3 node _io_out_5_0_bits_T_28 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_29 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_30 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_31 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_32 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_33 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_34 = or(_io_out_5_0_bits_T_28, _io_out_5_0_bits_T_29) node _io_out_5_0_bits_T_35 = or(_io_out_5_0_bits_T_34, _io_out_5_0_bits_T_30) node _io_out_5_0_bits_T_36 = or(_io_out_5_0_bits_T_35, _io_out_5_0_bits_T_31) node _io_out_5_0_bits_T_37 = or(_io_out_5_0_bits_T_36, _io_out_5_0_bits_T_32) node _io_out_5_0_bits_T_38 = or(_io_out_5_0_bits_T_37, _io_out_5_0_bits_T_33) wire _io_out_5_0_bits_WIRE_4 : UInt<4> connect _io_out_5_0_bits_WIRE_4, _io_out_5_0_bits_T_38 connect _io_out_5_0_bits_WIRE_2.egress_node, _io_out_5_0_bits_WIRE_4 node _io_out_5_0_bits_T_39 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_40 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_41 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_42 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_43 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_44 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_45 = or(_io_out_5_0_bits_T_39, _io_out_5_0_bits_T_40) node _io_out_5_0_bits_T_46 = or(_io_out_5_0_bits_T_45, _io_out_5_0_bits_T_41) node _io_out_5_0_bits_T_47 = or(_io_out_5_0_bits_T_46, _io_out_5_0_bits_T_42) node _io_out_5_0_bits_T_48 = or(_io_out_5_0_bits_T_47, _io_out_5_0_bits_T_43) node _io_out_5_0_bits_T_49 = or(_io_out_5_0_bits_T_48, _io_out_5_0_bits_T_44) wire _io_out_5_0_bits_WIRE_5 : UInt<3> connect _io_out_5_0_bits_WIRE_5, _io_out_5_0_bits_T_49 connect _io_out_5_0_bits_WIRE_2.ingress_node_id, _io_out_5_0_bits_WIRE_5 node _io_out_5_0_bits_T_50 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_51 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_52 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_53 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_54 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_55 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_5_0_bits_T_56 = or(_io_out_5_0_bits_T_50, _io_out_5_0_bits_T_51) node _io_out_5_0_bits_T_57 = or(_io_out_5_0_bits_T_56, _io_out_5_0_bits_T_52) node _io_out_5_0_bits_T_58 = or(_io_out_5_0_bits_T_57, _io_out_5_0_bits_T_53) node _io_out_5_0_bits_T_59 = or(_io_out_5_0_bits_T_58, _io_out_5_0_bits_T_54) node _io_out_5_0_bits_T_60 = or(_io_out_5_0_bits_T_59, _io_out_5_0_bits_T_55) wire _io_out_5_0_bits_WIRE_6 : UInt<4> connect _io_out_5_0_bits_WIRE_6, _io_out_5_0_bits_T_60 connect _io_out_5_0_bits_WIRE_2.ingress_node, _io_out_5_0_bits_WIRE_6 node _io_out_5_0_bits_T_61 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_62 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_63 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_64 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_65 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_66 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_5_0_bits_T_67 = or(_io_out_5_0_bits_T_61, _io_out_5_0_bits_T_62) node _io_out_5_0_bits_T_68 = or(_io_out_5_0_bits_T_67, _io_out_5_0_bits_T_63) node _io_out_5_0_bits_T_69 = or(_io_out_5_0_bits_T_68, _io_out_5_0_bits_T_64) node _io_out_5_0_bits_T_70 = or(_io_out_5_0_bits_T_69, _io_out_5_0_bits_T_65) node _io_out_5_0_bits_T_71 = or(_io_out_5_0_bits_T_70, _io_out_5_0_bits_T_66) wire _io_out_5_0_bits_WIRE_7 : UInt<3> connect _io_out_5_0_bits_WIRE_7, _io_out_5_0_bits_T_71 connect _io_out_5_0_bits_WIRE_2.vnet_id, _io_out_5_0_bits_WIRE_7 connect _io_out_5_0_bits_WIRE.flow, _io_out_5_0_bits_WIRE_2 node _io_out_5_0_bits_T_72 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_73 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_74 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_75 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_76 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_77 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.payload, UInt<1>(0h0)) node _io_out_5_0_bits_T_78 = or(_io_out_5_0_bits_T_72, _io_out_5_0_bits_T_73) node _io_out_5_0_bits_T_79 = or(_io_out_5_0_bits_T_78, _io_out_5_0_bits_T_74) node _io_out_5_0_bits_T_80 = or(_io_out_5_0_bits_T_79, _io_out_5_0_bits_T_75) node _io_out_5_0_bits_T_81 = or(_io_out_5_0_bits_T_80, _io_out_5_0_bits_T_76) node _io_out_5_0_bits_T_82 = or(_io_out_5_0_bits_T_81, _io_out_5_0_bits_T_77) wire _io_out_5_0_bits_WIRE_8 : UInt<73> connect _io_out_5_0_bits_WIRE_8, _io_out_5_0_bits_T_82 connect _io_out_5_0_bits_WIRE.payload, _io_out_5_0_bits_WIRE_8 node _io_out_5_0_bits_T_83 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_84 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_85 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_86 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_87 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_88 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.tail, UInt<1>(0h0)) node _io_out_5_0_bits_T_89 = or(_io_out_5_0_bits_T_83, _io_out_5_0_bits_T_84) node _io_out_5_0_bits_T_90 = or(_io_out_5_0_bits_T_89, _io_out_5_0_bits_T_85) node _io_out_5_0_bits_T_91 = or(_io_out_5_0_bits_T_90, _io_out_5_0_bits_T_86) node _io_out_5_0_bits_T_92 = or(_io_out_5_0_bits_T_91, _io_out_5_0_bits_T_87) node _io_out_5_0_bits_T_93 = or(_io_out_5_0_bits_T_92, _io_out_5_0_bits_T_88) wire _io_out_5_0_bits_WIRE_9 : UInt<1> connect _io_out_5_0_bits_WIRE_9, _io_out_5_0_bits_T_93 connect _io_out_5_0_bits_WIRE.tail, _io_out_5_0_bits_WIRE_9 node _io_out_5_0_bits_T_94 = mux(_io_out_5_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_95 = mux(_io_out_5_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_96 = mux(_io_out_5_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_97 = mux(_io_out_5_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_98 = mux(_io_out_5_0_bits_T_4, in_flat[4].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_99 = mux(_io_out_5_0_bits_T_5, in_flat[5].bits.flit.head, UInt<1>(0h0)) node _io_out_5_0_bits_T_100 = or(_io_out_5_0_bits_T_94, _io_out_5_0_bits_T_95) node _io_out_5_0_bits_T_101 = or(_io_out_5_0_bits_T_100, _io_out_5_0_bits_T_96) node _io_out_5_0_bits_T_102 = or(_io_out_5_0_bits_T_101, _io_out_5_0_bits_T_97) node _io_out_5_0_bits_T_103 = or(_io_out_5_0_bits_T_102, _io_out_5_0_bits_T_98) node _io_out_5_0_bits_T_104 = or(_io_out_5_0_bits_T_103, _io_out_5_0_bits_T_99) wire _io_out_5_0_bits_WIRE_10 : UInt<1> connect _io_out_5_0_bits_WIRE_10, _io_out_5_0_bits_T_104 connect _io_out_5_0_bits_WIRE.head, _io_out_5_0_bits_WIRE_10 connect io.out.`5`[0].bits, _io_out_5_0_bits_WIRE node _io_out_5_0_bits_virt_channel_id_T = bits(sel_flat_5, 0, 0) node _io_out_5_0_bits_virt_channel_id_T_1 = bits(sel_flat_5, 1, 1) node _io_out_5_0_bits_virt_channel_id_T_2 = bits(sel_flat_5, 2, 2) node _io_out_5_0_bits_virt_channel_id_T_3 = bits(sel_flat_5, 3, 3) node _io_out_5_0_bits_virt_channel_id_T_4 = bits(sel_flat_5, 4, 4) node _io_out_5_0_bits_virt_channel_id_T_5 = bits(sel_flat_5, 5, 5) node _io_out_5_0_bits_virt_channel_id_T_6 = mux(_io_out_5_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_7 = mux(_io_out_5_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_8 = mux(_io_out_5_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_9 = mux(_io_out_5_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_10 = mux(_io_out_5_0_bits_virt_channel_id_T_4, in_flat[4].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_11 = mux(_io_out_5_0_bits_virt_channel_id_T_5, in_flat[5].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_5_0_bits_virt_channel_id_T_12 = or(_io_out_5_0_bits_virt_channel_id_T_6, _io_out_5_0_bits_virt_channel_id_T_7) node _io_out_5_0_bits_virt_channel_id_T_13 = or(_io_out_5_0_bits_virt_channel_id_T_12, _io_out_5_0_bits_virt_channel_id_T_8) node _io_out_5_0_bits_virt_channel_id_T_14 = or(_io_out_5_0_bits_virt_channel_id_T_13, _io_out_5_0_bits_virt_channel_id_T_9) node _io_out_5_0_bits_virt_channel_id_T_15 = or(_io_out_5_0_bits_virt_channel_id_T_14, _io_out_5_0_bits_virt_channel_id_T_10) node _io_out_5_0_bits_virt_channel_id_T_16 = or(_io_out_5_0_bits_virt_channel_id_T_15, _io_out_5_0_bits_virt_channel_id_T_11) wire _io_out_5_0_bits_virt_channel_id_WIRE : UInt<4> connect _io_out_5_0_bits_virt_channel_id_WIRE, _io_out_5_0_bits_virt_channel_id_T_16 connect io.out.`5`[0].bits.virt_channel_id, _io_out_5_0_bits_virt_channel_id_WIRE

module Switch_4( // @[Switch.scala:16:7] input clock, // @[Switch.scala:16:7] input reset, // @[Switch.scala:16:7] input io_in_5_0_valid, // @[Switch.scala:27:14] input io_in_5_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_5_0_bits_flit_tail, // @[Switch.scala:27:14] input [72:0] io_in_5_0_bits_flit_payload, // @[Switch.scala:27:14] input [2:0] io_in_5_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_5_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [2:0] io_in_5_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_1_0_valid, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14] input [72:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14] input [2:0] io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [2:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_0_0_valid, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14] input [72:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14] input [2:0] io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [2:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14] output io_out_5_0_valid, // @[Switch.scala:27:14] output io_out_5_0_bits_head, // @[Switch.scala:27:14] output io_out_5_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_5_0_bits_payload, // @[Switch.scala:27:14] output io_out_4_0_valid, // @[Switch.scala:27:14] output io_out_4_0_bits_head, // @[Switch.scala:27:14] output io_out_4_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_4_0_bits_payload, // @[Switch.scala:27:14] output io_out_3_0_valid, // @[Switch.scala:27:14] output io_out_3_0_bits_head, // @[Switch.scala:27:14] output io_out_3_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_3_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_3_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_2_0_valid, // @[Switch.scala:27:14] output io_out_2_0_bits_head, // @[Switch.scala:27:14] output io_out_2_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_2_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_2_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_1_0_valid, // @[Switch.scala:27:14] output io_out_1_0_bits_head, // @[Switch.scala:27:14] output io_out_1_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14] output io_out_0_0_valid, // @[Switch.scala:27:14] output io_out_0_0_bits_head, // @[Switch.scala:27:14] output io_out_0_0_bits_tail, // @[Switch.scala:27:14] output [72:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14] output [2:0] io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [2:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14] input io_sel_5_0_5_0, // @[Switch.scala:27:14] input io_sel_5_0_1_0, // @[Switch.scala:27:14] input io_sel_5_0_0_0, // @[Switch.scala:27:14] input io_sel_4_0_5_0, // @[Switch.scala:27:14] input io_sel_4_0_1_0, // @[Switch.scala:27:14] input io_sel_4_0_0_0, // @[Switch.scala:27:14] input io_sel_3_0_5_0, // @[Switch.scala:27:14] input io_sel_3_0_1_0, // @[Switch.scala:27:14] input io_sel_3_0_0_0, // @[Switch.scala:27:14] input io_sel_2_0_5_0, // @[Switch.scala:27:14] input io_sel_2_0_1_0, // @[Switch.scala:27:14] input io_sel_2_0_0_0, // @[Switch.scala:27:14] input io_sel_1_0_5_0, // @[Switch.scala:27:14] input io_sel_1_0_1_0, // @[Switch.scala:27:14] input io_sel_1_0_0_0, // @[Switch.scala:27:14] input io_sel_0_0_5_0, // @[Switch.scala:27:14] input io_sel_0_0_1_0, // @[Switch.scala:27:14] input io_sel_0_0_0_0 // @[Switch.scala:27:14] );

Generate the Verilog code corresponding to this FIRRTL code module Tile_210 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_466 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_210( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_466 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_406 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_150 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_406( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_150 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s4k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_14 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s4k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s4k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLBuffer_a32d64s4k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_14 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_198 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_358 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_198( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_358 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_182 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_182( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_181 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_202 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_181( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_202 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_64 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_128 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_64 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = and(io.in.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail invalidate route_buffer.io.enq.bits.flow.egress_node_id invalidate route_buffer.io.enq.bits.flow.egress_node invalidate route_buffer.io.enq.bits.flow.ingress_node_id invalidate route_buffer.io.enq.bits.flow.ingress_node invalidate route_buffer.io.enq.bits.flow.vnet_id connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_6 = and(io.in.ready, io.in.valid) node _T_7 = and(_T_6, io.in.bits.head) node _T_8 = and(_T_7, at_dest) when _T_8 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_9 = eq(UInt<2>(0h2), io.in.bits.egress_id) when _T_9 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<2>(0h3), io.in.bits.egress_id) when _T_10 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(route_q.io.enq.valid, _T_11) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_129 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_64 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_17 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(vcalloc_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_19, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_14, _out_bundle_bits_out_virt_channel_T_13) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_15 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1 connect io.in.ready, UInt<1>(0h0) connect io.router_req.valid, UInt<1>(0h0) invalidate io.router_req.bits.flow.egress_node_id invalidate io.router_req.bits.flow.egress_node invalidate io.router_req.bits.flow.ingress_node_id invalidate io.router_req.bits.flow.ingress_node invalidate io.router_req.bits.flow.vnet_id invalidate io.router_req.bits.src_virt_id connect io.vcalloc_req.valid, UInt<1>(0h0) invalidate io.vcalloc_req.bits.vc_sel.`0`[0] invalidate io.vcalloc_req.bits.vc_sel.`0`[1] invalidate io.vcalloc_req.bits.vc_sel.`0`[2] invalidate io.vcalloc_req.bits.vc_sel.`0`[3] invalidate io.vcalloc_req.bits.vc_sel.`0`[4] invalidate io.vcalloc_req.bits.vc_sel.`0`[5] invalidate io.vcalloc_req.bits.vc_sel.`0`[6] invalidate io.vcalloc_req.bits.vc_sel.`0`[7] invalidate io.vcalloc_req.bits.vc_sel.`0`[8] invalidate io.vcalloc_req.bits.vc_sel.`0`[9] invalidate io.vcalloc_req.bits.vc_sel.`1`[0] invalidate io.vcalloc_req.bits.vc_sel.`2`[0] invalidate io.vcalloc_req.bits.in_vc invalidate io.vcalloc_req.bits.flow.egress_node_id invalidate io.vcalloc_req.bits.flow.egress_node invalidate io.vcalloc_req.bits.flow.ingress_node_id invalidate io.vcalloc_req.bits.flow.ingress_node invalidate io.vcalloc_req.bits.flow.vnet_id connect io.salloc_req[0].valid, UInt<1>(0h0) invalidate io.salloc_req[0].bits.tail invalidate io.salloc_req[0].bits.vc_sel.`0`[0] invalidate io.salloc_req[0].bits.vc_sel.`0`[1] invalidate io.salloc_req[0].bits.vc_sel.`0`[2] invalidate io.salloc_req[0].bits.vc_sel.`0`[3] invalidate io.salloc_req[0].bits.vc_sel.`0`[4] invalidate io.salloc_req[0].bits.vc_sel.`0`[5] invalidate io.salloc_req[0].bits.vc_sel.`0`[6] invalidate io.salloc_req[0].bits.vc_sel.`0`[7] invalidate io.salloc_req[0].bits.vc_sel.`0`[8] invalidate io.salloc_req[0].bits.vc_sel.`0`[9] invalidate io.salloc_req[0].bits.vc_sel.`1`[0] invalidate io.salloc_req[0].bits.vc_sel.`2`[0] connect io.out[0].valid, UInt<1>(0h0) invalidate io.out[0].bits.out_virt_channel invalidate io.out[0].bits.flit.virt_channel_id invalidate io.out[0].bits.flit.flow.egress_node_id invalidate io.out[0].bits.flit.flow.egress_node invalidate io.out[0].bits.flit.flow.ingress_node_id invalidate io.out[0].bits.flit.flow.ingress_node invalidate io.out[0].bits.flit.flow.vnet_id invalidate io.out[0].bits.flit.payload invalidate io.out[0].bits.flit.tail invalidate io.out[0].bits.flit.head

module IngressUnit_64( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_337 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_337( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_49 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_98 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_99 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Tile_174 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_430 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_174( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_430 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget32_8 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_66 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a32d256s2k3z4u_2 connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 255, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<5>(0h1f), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 4, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<2>, clock, reset, UInt<2>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 4, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) node _repeat_anonOut_a_bits_data_mux_T_2 = bits(cated.bits.data, 191, 128) node _repeat_anonOut_a_bits_data_mux_T_3 = bits(cated.bits.data, 255, 192) wire repeat_anonOut_a_bits_data_mux : UInt<64>[4] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect repeat_anonOut_a_bits_data_mux[2], _repeat_anonOut_a_bits_data_mux_T_2 connect repeat_anonOut_a_bits_data_mux[3], _repeat_anonOut_a_bits_data_mux_T_3 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) node _repeat_anonOut_a_bits_mask_mux_T_2 = bits(cated.bits.mask, 23, 16) node _repeat_anonOut_a_bits_mask_mux_T_3 = bits(cated.bits.mask, 31, 24) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[4] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect repeat_anonOut_a_bits_mask_mux[2], _repeat_anonOut_a_bits_mask_mux_T_2 connect repeat_anonOut_a_bits_mask_mux[3], _repeat_anonOut_a_bits_mask_mux_T_3 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<5>(0h1f), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 4, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<2>, clock, reset, UInt<2>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) node _enable_T_6 = xor(count, UInt<2>(0h2)) node _enable_T_7 = and(_enable_T_6, limit) node _enable_T_8 = orr(_enable_T_7) node enable_2 = eq(_enable_T_8, UInt<1>(0h0)) node _enable_T_9 = xor(count, UInt<2>(0h3)) node _enable_T_10 = and(_enable_T_9, limit) node _enable_T_11 = orr(_enable_T_10) node enable_3 = eq(_enable_T_11, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) node _anonIn_d_bits_data_masked_enable_T_2 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_2 = or(enable_2, _anonIn_d_bits_data_masked_enable_T_2) node _anonIn_d_bits_data_masked_enable_T_3 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_3 = or(enable_3, _anonIn_d_bits_data_masked_enable_T_3) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data wire anonIn_d_bits_data_odata_2 : UInt connect anonIn_d_bits_data_odata_2, anonOut.d.bits.data wire anonIn_d_bits_data_odata_3 : UInt connect anonIn_d_bits_data_odata_3, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[3], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonIn_d_bits_data_rdata[1]) node anonIn_d_bits_data_mdata_2 = mux(anonIn_d_bits_data_masked_enable_2, anonIn_d_bits_data_odata_2, anonIn_d_bits_data_rdata[2]) node anonIn_d_bits_data_mdata_3 = mux(anonIn_d_bits_data_masked_enable_3, anonIn_d_bits_data_odata_3, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 connect anonIn_d_bits_data_rdata[1], anonIn_d_bits_data_mdata_1 connect anonIn_d_bits_data_rdata[2], anonIn_d_bits_data_mdata_2 node anonIn_d_bits_data_lo = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) node anonIn_d_bits_data_hi = cat(anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2) node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_hi, anonIn_d_bits_data_lo) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<2>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<2>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<2>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<2>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLWidthWidget32_8( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71] wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24] wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24] wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25] wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53] assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71] wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] count; // @[WidthWidget.scala:40:27] wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24] wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 2'h0; // @[WidthWidget.scala:105:26] count <= 2'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] end always @(posedge) TLMonitor_66 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a32d256s2k3z4u_2 repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BTBBranchPredictorBank : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 4) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask node _s0_pc_T = not(io.f0_pc) node _s0_pc_T_1 = or(_s0_pc_T, UInt<3>(0h7)) node s0_pc = not(_s0_pc_T_1) reg s1_pc : UInt, clock connect s1_pc, s0_pc reg s2_pc : UInt, clock connect s2_pc, s1_pc node s0_update_idx = shr(io.update.bits.pc, 4) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid node _s1_update_bits_pc_T = not(io.update.bits.pc) node _s1_update_bits_pc_T_1 = or(_s1_update_bits_pc_T, UInt<3>(0h7)) node _s1_update_bits_pc_T_2 = not(_s1_update_bits_pc_T_1) connect s1_update.bits.pc, _s1_update_bits_pc_T_2 reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire s1_meta : { write_way : UInt<1>} reg f3_meta_REG : { write_way : UInt<1>}, clock connect f3_meta_REG, s1_meta reg f3_meta : { write_way : UInt<1>}, clock connect f3_meta, f3_meta_REG connect io.f3_meta, f3_meta.write_way regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) wire s1_req_rmeta : { is_br : UInt<1>, tag : UInt<29>}[4][2] wire s1_req_rbtb : { offset : SInt<13>, extended : UInt<1>}[4][2] wire s1_req_rebtb : UInt<40> node s1_req_tag = shr(s1_idx, 7) wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4] wire s1_is_br : UInt<1>[4] wire s1_is_jal : UInt<1>[4] node _s1_hit_ohs_T = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_1 = eq(s1_req_rmeta[0][0].tag, _s1_hit_ohs_T) node _s1_hit_ohs_T_2 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_3 = eq(s1_req_rmeta[1][0].tag, _s1_hit_ohs_T_2) wire _s1_hit_ohs_WIRE : UInt<1>[2] connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1 connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3 node _s1_hit_ohs_T_4 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_5 = eq(s1_req_rmeta[0][1].tag, _s1_hit_ohs_T_4) node _s1_hit_ohs_T_6 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_7 = eq(s1_req_rmeta[1][1].tag, _s1_hit_ohs_T_6) wire _s1_hit_ohs_WIRE_1 : UInt<1>[2] connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_5 connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_7 node _s1_hit_ohs_T_8 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_9 = eq(s1_req_rmeta[0][2].tag, _s1_hit_ohs_T_8) node _s1_hit_ohs_T_10 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_11 = eq(s1_req_rmeta[1][2].tag, _s1_hit_ohs_T_10) wire _s1_hit_ohs_WIRE_2 : UInt<1>[2] connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_9 connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_11 node _s1_hit_ohs_T_12 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_13 = eq(s1_req_rmeta[0][3].tag, _s1_hit_ohs_T_12) node _s1_hit_ohs_T_14 = bits(s1_req_tag, 28, 0) node _s1_hit_ohs_T_15 = eq(s1_req_rmeta[1][3].tag, _s1_hit_ohs_T_14) wire _s1_hit_ohs_WIRE_3 : UInt<1>[2] connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_13 connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_15 wire s1_hit_ohs : UInt<1>[2][4] connect s1_hit_ohs[0], _s1_hit_ohs_WIRE connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1 connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2 connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3 node s1_hits_0 = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1]) node s1_hits_1 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1]) node s1_hits_2 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1]) node s1_hits_3 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1]) node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), UInt<1>(0h1)) wire s1_targs : UInt<40>[4][2] wire entry_btb : { offset : SInt<13>, extended : UInt<1>} connect entry_btb, s1_req_rbtb[0][0] node _s1_targs_0_0_T = asSInt(s1_pc) node _s1_targs_0_0_T_1 = add(_s1_targs_0_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_0_0_T_2 = tail(_s1_targs_0_0_T_1, 1) node _s1_targs_0_0_T_3 = asSInt(_s1_targs_0_0_T_2) node _s1_targs_0_0_T_4 = add(_s1_targs_0_0_T_3, entry_btb.offset) node _s1_targs_0_0_T_5 = tail(_s1_targs_0_0_T_4, 1) node _s1_targs_0_0_T_6 = asSInt(_s1_targs_0_0_T_5) node _s1_targs_0_0_T_7 = asUInt(_s1_targs_0_0_T_6) node _s1_targs_0_0_T_8 = mux(entry_btb.extended, s1_req_rebtb, _s1_targs_0_0_T_7) connect s1_targs[0][0], _s1_targs_0_0_T_8 wire entry_btb_1 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_1, s1_req_rbtb[1][0] node _s1_targs_1_0_T = asSInt(s1_pc) node _s1_targs_1_0_T_1 = add(_s1_targs_1_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_1_0_T_2 = tail(_s1_targs_1_0_T_1, 1) node _s1_targs_1_0_T_3 = asSInt(_s1_targs_1_0_T_2) node _s1_targs_1_0_T_4 = add(_s1_targs_1_0_T_3, entry_btb_1.offset) node _s1_targs_1_0_T_5 = tail(_s1_targs_1_0_T_4, 1) node _s1_targs_1_0_T_6 = asSInt(_s1_targs_1_0_T_5) node _s1_targs_1_0_T_7 = asUInt(_s1_targs_1_0_T_6) node _s1_targs_1_0_T_8 = mux(entry_btb_1.extended, s1_req_rebtb, _s1_targs_1_0_T_7) connect s1_targs[1][0], _s1_targs_1_0_T_8 node _s1_resp_0_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_0_valid_T_1 = and(_s1_resp_0_valid_T, s1_valid) node _s1_resp_0_valid_T_2 = and(_s1_resp_0_valid_T_1, s1_hits_0) connect s1_resp[0].valid, _s1_resp_0_valid_T_2 connect s1_resp[0].bits, s1_targs[s1_hit_ways_0][0] node _s1_is_br_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_0_T_1 = and(_s1_is_br_0_T, s1_resp[0].valid) node _s1_is_br_0_T_2 = and(_s1_is_br_0_T_1, s1_req_rmeta[s1_hit_ways_0][0].is_br) connect s1_is_br[0], _s1_is_br_0_T_2 node _s1_is_jal_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_0_T_1 = and(_s1_is_jal_0_T, s1_resp[0].valid) node _s1_is_jal_0_T_2 = eq(s1_req_rmeta[s1_hit_ways_0][0].is_br, UInt<1>(0h0)) node _s1_is_jal_0_T_3 = and(_s1_is_jal_0_T_1, _s1_is_jal_0_T_2) connect s1_is_jal[0], _s1_is_jal_0_T_3 connect io.resp.f1[0], io.resp_in[0].f1[0] connect io.resp.f2[0], io.resp_in[0].f2[0] connect io.resp.f3[0], io.resp_in[0].f3[0] reg REG : UInt<1>, clock connect REG, s1_hits_0 when REG : reg io_resp_f2_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_0_predicted_pc_REG, s1_resp[0] connect io.resp.f2[0].predicted_pc, io_resp_f2_0_predicted_pc_REG reg io_resp_f2_0_is_br_REG : UInt<1>, clock connect io_resp_f2_0_is_br_REG, s1_is_br[0] connect io.resp.f2[0].is_br, io_resp_f2_0_is_br_REG reg io_resp_f2_0_is_jal_REG : UInt<1>, clock connect io_resp_f2_0_is_jal_REG, s1_is_jal[0] connect io.resp.f2[0].is_jal, io_resp_f2_0_is_jal_REG reg REG_1 : UInt<1>, clock connect REG_1, s1_is_jal[0] when REG_1 : connect io.resp.f2[0].taken, UInt<1>(0h1) reg REG_2 : UInt<1>, clock connect REG_2, s1_hits_0 reg REG_3 : UInt<1>, clock connect REG_3, REG_2 when REG_3 : reg io_resp_f3_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_0_predicted_pc_REG.bits, io.resp.f2[0].predicted_pc.bits connect io_resp_f3_0_predicted_pc_REG.valid, io.resp.f2[0].predicted_pc.valid connect io.resp.f3[0].predicted_pc, io_resp_f3_0_predicted_pc_REG reg io_resp_f3_0_is_br_REG : UInt<1>, clock connect io_resp_f3_0_is_br_REG, io.resp.f2[0].is_br connect io.resp.f3[0].is_br, io_resp_f3_0_is_br_REG reg io_resp_f3_0_is_jal_REG : UInt<1>, clock connect io_resp_f3_0_is_jal_REG, io.resp.f2[0].is_jal connect io.resp.f3[0].is_jal, io_resp_f3_0_is_jal_REG reg REG_4 : UInt<1>, clock connect REG_4, s1_is_jal[0] reg REG_5 : UInt<1>, clock connect REG_5, REG_4 when REG_5 : connect io.resp.f3[0].taken, UInt<1>(0h1) wire entry_btb_2 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_2, s1_req_rbtb[0][1] node _s1_targs_0_1_T = asSInt(s1_pc) node _s1_targs_0_1_T_1 = add(_s1_targs_0_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_0_1_T_2 = tail(_s1_targs_0_1_T_1, 1) node _s1_targs_0_1_T_3 = asSInt(_s1_targs_0_1_T_2) node _s1_targs_0_1_T_4 = add(_s1_targs_0_1_T_3, entry_btb_2.offset) node _s1_targs_0_1_T_5 = tail(_s1_targs_0_1_T_4, 1) node _s1_targs_0_1_T_6 = asSInt(_s1_targs_0_1_T_5) node _s1_targs_0_1_T_7 = asUInt(_s1_targs_0_1_T_6) node _s1_targs_0_1_T_8 = mux(entry_btb_2.extended, s1_req_rebtb, _s1_targs_0_1_T_7) connect s1_targs[0][1], _s1_targs_0_1_T_8 wire entry_btb_3 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_3, s1_req_rbtb[1][1] node _s1_targs_1_1_T = asSInt(s1_pc) node _s1_targs_1_1_T_1 = add(_s1_targs_1_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_1_1_T_2 = tail(_s1_targs_1_1_T_1, 1) node _s1_targs_1_1_T_3 = asSInt(_s1_targs_1_1_T_2) node _s1_targs_1_1_T_4 = add(_s1_targs_1_1_T_3, entry_btb_3.offset) node _s1_targs_1_1_T_5 = tail(_s1_targs_1_1_T_4, 1) node _s1_targs_1_1_T_6 = asSInt(_s1_targs_1_1_T_5) node _s1_targs_1_1_T_7 = asUInt(_s1_targs_1_1_T_6) node _s1_targs_1_1_T_8 = mux(entry_btb_3.extended, s1_req_rebtb, _s1_targs_1_1_T_7) connect s1_targs[1][1], _s1_targs_1_1_T_8 node _s1_resp_1_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_1_valid_T_1 = and(_s1_resp_1_valid_T, s1_valid) node _s1_resp_1_valid_T_2 = and(_s1_resp_1_valid_T_1, s1_hits_1) connect s1_resp[1].valid, _s1_resp_1_valid_T_2 connect s1_resp[1].bits, s1_targs[s1_hit_ways_1][1] node _s1_is_br_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_1_T_1 = and(_s1_is_br_1_T, s1_resp[1].valid) node _s1_is_br_1_T_2 = and(_s1_is_br_1_T_1, s1_req_rmeta[s1_hit_ways_1][1].is_br) connect s1_is_br[1], _s1_is_br_1_T_2 node _s1_is_jal_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_1_T_1 = and(_s1_is_jal_1_T, s1_resp[1].valid) node _s1_is_jal_1_T_2 = eq(s1_req_rmeta[s1_hit_ways_1][1].is_br, UInt<1>(0h0)) node _s1_is_jal_1_T_3 = and(_s1_is_jal_1_T_1, _s1_is_jal_1_T_2) connect s1_is_jal[1], _s1_is_jal_1_T_3 connect io.resp.f1[1], io.resp_in[0].f1[1] connect io.resp.f2[1], io.resp_in[0].f2[1] connect io.resp.f3[1], io.resp_in[0].f3[1] reg REG_6 : UInt<1>, clock connect REG_6, s1_hits_1 when REG_6 : reg io_resp_f2_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_1_predicted_pc_REG, s1_resp[1] connect io.resp.f2[1].predicted_pc, io_resp_f2_1_predicted_pc_REG reg io_resp_f2_1_is_br_REG : UInt<1>, clock connect io_resp_f2_1_is_br_REG, s1_is_br[1] connect io.resp.f2[1].is_br, io_resp_f2_1_is_br_REG reg io_resp_f2_1_is_jal_REG : UInt<1>, clock connect io_resp_f2_1_is_jal_REG, s1_is_jal[1] connect io.resp.f2[1].is_jal, io_resp_f2_1_is_jal_REG reg REG_7 : UInt<1>, clock connect REG_7, s1_is_jal[1] when REG_7 : connect io.resp.f2[1].taken, UInt<1>(0h1) reg REG_8 : UInt<1>, clock connect REG_8, s1_hits_1 reg REG_9 : UInt<1>, clock connect REG_9, REG_8 when REG_9 : reg io_resp_f3_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_1_predicted_pc_REG.bits, io.resp.f2[1].predicted_pc.bits connect io_resp_f3_1_predicted_pc_REG.valid, io.resp.f2[1].predicted_pc.valid connect io.resp.f3[1].predicted_pc, io_resp_f3_1_predicted_pc_REG reg io_resp_f3_1_is_br_REG : UInt<1>, clock connect io_resp_f3_1_is_br_REG, io.resp.f2[1].is_br connect io.resp.f3[1].is_br, io_resp_f3_1_is_br_REG reg io_resp_f3_1_is_jal_REG : UInt<1>, clock connect io_resp_f3_1_is_jal_REG, io.resp.f2[1].is_jal connect io.resp.f3[1].is_jal, io_resp_f3_1_is_jal_REG reg REG_10 : UInt<1>, clock connect REG_10, s1_is_jal[1] reg REG_11 : UInt<1>, clock connect REG_11, REG_10 when REG_11 : connect io.resp.f3[1].taken, UInt<1>(0h1) wire entry_btb_4 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_4, s1_req_rbtb[0][2] node _s1_targs_0_2_T = asSInt(s1_pc) node _s1_targs_0_2_T_1 = add(_s1_targs_0_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_0_2_T_2 = tail(_s1_targs_0_2_T_1, 1) node _s1_targs_0_2_T_3 = asSInt(_s1_targs_0_2_T_2) node _s1_targs_0_2_T_4 = add(_s1_targs_0_2_T_3, entry_btb_4.offset) node _s1_targs_0_2_T_5 = tail(_s1_targs_0_2_T_4, 1) node _s1_targs_0_2_T_6 = asSInt(_s1_targs_0_2_T_5) node _s1_targs_0_2_T_7 = asUInt(_s1_targs_0_2_T_6) node _s1_targs_0_2_T_8 = mux(entry_btb_4.extended, s1_req_rebtb, _s1_targs_0_2_T_7) connect s1_targs[0][2], _s1_targs_0_2_T_8 wire entry_btb_5 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_5, s1_req_rbtb[1][2] node _s1_targs_1_2_T = asSInt(s1_pc) node _s1_targs_1_2_T_1 = add(_s1_targs_1_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_1_2_T_2 = tail(_s1_targs_1_2_T_1, 1) node _s1_targs_1_2_T_3 = asSInt(_s1_targs_1_2_T_2) node _s1_targs_1_2_T_4 = add(_s1_targs_1_2_T_3, entry_btb_5.offset) node _s1_targs_1_2_T_5 = tail(_s1_targs_1_2_T_4, 1) node _s1_targs_1_2_T_6 = asSInt(_s1_targs_1_2_T_5) node _s1_targs_1_2_T_7 = asUInt(_s1_targs_1_2_T_6) node _s1_targs_1_2_T_8 = mux(entry_btb_5.extended, s1_req_rebtb, _s1_targs_1_2_T_7) connect s1_targs[1][2], _s1_targs_1_2_T_8 node _s1_resp_2_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_2_valid_T_1 = and(_s1_resp_2_valid_T, s1_valid) node _s1_resp_2_valid_T_2 = and(_s1_resp_2_valid_T_1, s1_hits_2) connect s1_resp[2].valid, _s1_resp_2_valid_T_2 connect s1_resp[2].bits, s1_targs[s1_hit_ways_2][2] node _s1_is_br_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_2_T_1 = and(_s1_is_br_2_T, s1_resp[2].valid) node _s1_is_br_2_T_2 = and(_s1_is_br_2_T_1, s1_req_rmeta[s1_hit_ways_2][2].is_br) connect s1_is_br[2], _s1_is_br_2_T_2 node _s1_is_jal_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_2_T_1 = and(_s1_is_jal_2_T, s1_resp[2].valid) node _s1_is_jal_2_T_2 = eq(s1_req_rmeta[s1_hit_ways_2][2].is_br, UInt<1>(0h0)) node _s1_is_jal_2_T_3 = and(_s1_is_jal_2_T_1, _s1_is_jal_2_T_2) connect s1_is_jal[2], _s1_is_jal_2_T_3 connect io.resp.f1[2], io.resp_in[0].f1[2] connect io.resp.f2[2], io.resp_in[0].f2[2] connect io.resp.f3[2], io.resp_in[0].f3[2] reg REG_12 : UInt<1>, clock connect REG_12, s1_hits_2 when REG_12 : reg io_resp_f2_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_2_predicted_pc_REG, s1_resp[2] connect io.resp.f2[2].predicted_pc, io_resp_f2_2_predicted_pc_REG reg io_resp_f2_2_is_br_REG : UInt<1>, clock connect io_resp_f2_2_is_br_REG, s1_is_br[2] connect io.resp.f2[2].is_br, io_resp_f2_2_is_br_REG reg io_resp_f2_2_is_jal_REG : UInt<1>, clock connect io_resp_f2_2_is_jal_REG, s1_is_jal[2] connect io.resp.f2[2].is_jal, io_resp_f2_2_is_jal_REG reg REG_13 : UInt<1>, clock connect REG_13, s1_is_jal[2] when REG_13 : connect io.resp.f2[2].taken, UInt<1>(0h1) reg REG_14 : UInt<1>, clock connect REG_14, s1_hits_2 reg REG_15 : UInt<1>, clock connect REG_15, REG_14 when REG_15 : reg io_resp_f3_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_2_predicted_pc_REG.bits, io.resp.f2[2].predicted_pc.bits connect io_resp_f3_2_predicted_pc_REG.valid, io.resp.f2[2].predicted_pc.valid connect io.resp.f3[2].predicted_pc, io_resp_f3_2_predicted_pc_REG reg io_resp_f3_2_is_br_REG : UInt<1>, clock connect io_resp_f3_2_is_br_REG, io.resp.f2[2].is_br connect io.resp.f3[2].is_br, io_resp_f3_2_is_br_REG reg io_resp_f3_2_is_jal_REG : UInt<1>, clock connect io_resp_f3_2_is_jal_REG, io.resp.f2[2].is_jal connect io.resp.f3[2].is_jal, io_resp_f3_2_is_jal_REG reg REG_16 : UInt<1>, clock connect REG_16, s1_is_jal[2] reg REG_17 : UInt<1>, clock connect REG_17, REG_16 when REG_17 : connect io.resp.f3[2].taken, UInt<1>(0h1) wire entry_btb_6 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_6, s1_req_rbtb[0][3] node _s1_targs_0_3_T = asSInt(s1_pc) node _s1_targs_0_3_T_1 = add(_s1_targs_0_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_0_3_T_2 = tail(_s1_targs_0_3_T_1, 1) node _s1_targs_0_3_T_3 = asSInt(_s1_targs_0_3_T_2) node _s1_targs_0_3_T_4 = add(_s1_targs_0_3_T_3, entry_btb_6.offset) node _s1_targs_0_3_T_5 = tail(_s1_targs_0_3_T_4, 1) node _s1_targs_0_3_T_6 = asSInt(_s1_targs_0_3_T_5) node _s1_targs_0_3_T_7 = asUInt(_s1_targs_0_3_T_6) node _s1_targs_0_3_T_8 = mux(entry_btb_6.extended, s1_req_rebtb, _s1_targs_0_3_T_7) connect s1_targs[0][3], _s1_targs_0_3_T_8 wire entry_btb_7 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_7, s1_req_rbtb[1][3] node _s1_targs_1_3_T = asSInt(s1_pc) node _s1_targs_1_3_T_1 = add(_s1_targs_1_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_1_3_T_2 = tail(_s1_targs_1_3_T_1, 1) node _s1_targs_1_3_T_3 = asSInt(_s1_targs_1_3_T_2) node _s1_targs_1_3_T_4 = add(_s1_targs_1_3_T_3, entry_btb_7.offset) node _s1_targs_1_3_T_5 = tail(_s1_targs_1_3_T_4, 1) node _s1_targs_1_3_T_6 = asSInt(_s1_targs_1_3_T_5) node _s1_targs_1_3_T_7 = asUInt(_s1_targs_1_3_T_6) node _s1_targs_1_3_T_8 = mux(entry_btb_7.extended, s1_req_rebtb, _s1_targs_1_3_T_7) connect s1_targs[1][3], _s1_targs_1_3_T_8 node _s1_resp_3_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_3_valid_T_1 = and(_s1_resp_3_valid_T, s1_valid) node _s1_resp_3_valid_T_2 = and(_s1_resp_3_valid_T_1, s1_hits_3) connect s1_resp[3].valid, _s1_resp_3_valid_T_2 connect s1_resp[3].bits, s1_targs[s1_hit_ways_3][3] node _s1_is_br_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_3_T_1 = and(_s1_is_br_3_T, s1_resp[3].valid) node _s1_is_br_3_T_2 = and(_s1_is_br_3_T_1, s1_req_rmeta[s1_hit_ways_3][3].is_br) connect s1_is_br[3], _s1_is_br_3_T_2 node _s1_is_jal_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_3_T_1 = and(_s1_is_jal_3_T, s1_resp[3].valid) node _s1_is_jal_3_T_2 = eq(s1_req_rmeta[s1_hit_ways_3][3].is_br, UInt<1>(0h0)) node _s1_is_jal_3_T_3 = and(_s1_is_jal_3_T_1, _s1_is_jal_3_T_2) connect s1_is_jal[3], _s1_is_jal_3_T_3 connect io.resp.f1[3], io.resp_in[0].f1[3] connect io.resp.f2[3], io.resp_in[0].f2[3] connect io.resp.f3[3], io.resp_in[0].f3[3] reg REG_18 : UInt<1>, clock connect REG_18, s1_hits_3 when REG_18 : reg io_resp_f2_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_3_predicted_pc_REG, s1_resp[3] connect io.resp.f2[3].predicted_pc, io_resp_f2_3_predicted_pc_REG reg io_resp_f2_3_is_br_REG : UInt<1>, clock connect io_resp_f2_3_is_br_REG, s1_is_br[3] connect io.resp.f2[3].is_br, io_resp_f2_3_is_br_REG reg io_resp_f2_3_is_jal_REG : UInt<1>, clock connect io_resp_f2_3_is_jal_REG, s1_is_jal[3] connect io.resp.f2[3].is_jal, io_resp_f2_3_is_jal_REG reg REG_19 : UInt<1>, clock connect REG_19, s1_is_jal[3] when REG_19 : connect io.resp.f2[3].taken, UInt<1>(0h1) reg REG_20 : UInt<1>, clock connect REG_20, s1_hits_3 reg REG_21 : UInt<1>, clock connect REG_21, REG_20 when REG_21 : reg io_resp_f3_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_3_predicted_pc_REG.bits, io.resp.f2[3].predicted_pc.bits connect io_resp_f3_3_predicted_pc_REG.valid, io.resp.f2[3].predicted_pc.valid connect io.resp.f3[3].predicted_pc, io_resp_f3_3_predicted_pc_REG reg io_resp_f3_3_is_br_REG : UInt<1>, clock connect io_resp_f3_3_is_br_REG, io.resp.f2[3].is_br connect io.resp.f3[3].is_br, io_resp_f3_3_is_br_REG reg io_resp_f3_3_is_jal_REG : UInt<1>, clock connect io_resp_f3_3_is_jal_REG, io.resp.f2[3].is_jal connect io.resp.f3[3].is_jal, io_resp_f3_3_is_jal_REG reg REG_22 : UInt<1>, clock connect REG_22, s1_is_jal[3] reg REG_23 : UInt<1>, clock connect REG_23, REG_22 when REG_23 : connect io.resp.f3[3].taken, UInt<1>(0h1) wire _alloc_way_r_metas_WIRE : UInt<29>[4] connect _alloc_way_r_metas_WIRE[0], s1_req_rmeta[0][0].tag connect _alloc_way_r_metas_WIRE[1], s1_req_rmeta[0][1].tag connect _alloc_way_r_metas_WIRE[2], s1_req_rmeta[0][2].tag connect _alloc_way_r_metas_WIRE[3], s1_req_rmeta[0][3].tag wire _alloc_way_r_metas_WIRE_1 : UInt<29>[4] connect _alloc_way_r_metas_WIRE_1[0], s1_req_rmeta[1][0].tag connect _alloc_way_r_metas_WIRE_1[1], s1_req_rmeta[1][1].tag connect _alloc_way_r_metas_WIRE_1[2], s1_req_rmeta[1][2].tag connect _alloc_way_r_metas_WIRE_1[3], s1_req_rmeta[1][3].tag wire _alloc_way_r_metas_WIRE_2 : UInt<29>[4][2] connect _alloc_way_r_metas_WIRE_2[0], _alloc_way_r_metas_WIRE connect _alloc_way_r_metas_WIRE_2[1], _alloc_way_r_metas_WIRE_1 node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_2[0][1], _alloc_way_r_metas_WIRE_2[0][0]) node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_2[0][3], _alloc_way_r_metas_WIRE_2[0][2]) node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo) node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_2[1][1], _alloc_way_r_metas_WIRE_2[1][0]) node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_2[1][3], _alloc_way_r_metas_WIRE_2[1][2]) node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1) node _alloc_way_r_metas_T_2 = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T) node _alloc_way_r_metas_T_3 = bits(s1_req_tag, 28, 0) node alloc_way_r_metas = cat(_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3) node alloc_way_chunks_0 = bits(alloc_way_r_metas, 0, 0) node alloc_way_chunks_1 = bits(alloc_way_r_metas, 1, 1) node alloc_way_chunks_2 = bits(alloc_way_r_metas, 2, 2) node alloc_way_chunks_3 = bits(alloc_way_r_metas, 3, 3) node alloc_way_chunks_4 = bits(alloc_way_r_metas, 4, 4) node alloc_way_chunks_5 = bits(alloc_way_r_metas, 5, 5) node alloc_way_chunks_6 = bits(alloc_way_r_metas, 6, 6) node alloc_way_chunks_7 = bits(alloc_way_r_metas, 7, 7) node alloc_way_chunks_8 = bits(alloc_way_r_metas, 8, 8) node alloc_way_chunks_9 = bits(alloc_way_r_metas, 9, 9) node alloc_way_chunks_10 = bits(alloc_way_r_metas, 10, 10) node alloc_way_chunks_11 = bits(alloc_way_r_metas, 11, 11) node alloc_way_chunks_12 = bits(alloc_way_r_metas, 12, 12) node alloc_way_chunks_13 = bits(alloc_way_r_metas, 13, 13) node alloc_way_chunks_14 = bits(alloc_way_r_metas, 14, 14) node alloc_way_chunks_15 = bits(alloc_way_r_metas, 15, 15) node alloc_way_chunks_16 = bits(alloc_way_r_metas, 16, 16) node alloc_way_chunks_17 = bits(alloc_way_r_metas, 17, 17) node alloc_way_chunks_18 = bits(alloc_way_r_metas, 18, 18) node alloc_way_chunks_19 = bits(alloc_way_r_metas, 19, 19) node alloc_way_chunks_20 = bits(alloc_way_r_metas, 20, 20) node alloc_way_chunks_21 = bits(alloc_way_r_metas, 21, 21) node alloc_way_chunks_22 = bits(alloc_way_r_metas, 22, 22) node alloc_way_chunks_23 = bits(alloc_way_r_metas, 23, 23) node alloc_way_chunks_24 = bits(alloc_way_r_metas, 24, 24) node alloc_way_chunks_25 = bits(alloc_way_r_metas, 25, 25) node alloc_way_chunks_26 = bits(alloc_way_r_metas, 26, 26) node alloc_way_chunks_27 = bits(alloc_way_r_metas, 27, 27) node alloc_way_chunks_28 = bits(alloc_way_r_metas, 28, 28) node alloc_way_chunks_29 = bits(alloc_way_r_metas, 29, 29) node alloc_way_chunks_30 = bits(alloc_way_r_metas, 30, 30) node alloc_way_chunks_31 = bits(alloc_way_r_metas, 31, 31) node alloc_way_chunks_32 = bits(alloc_way_r_metas, 32, 32) node alloc_way_chunks_33 = bits(alloc_way_r_metas, 33, 33) node alloc_way_chunks_34 = bits(alloc_way_r_metas, 34, 34) node alloc_way_chunks_35 = bits(alloc_way_r_metas, 35, 35) node alloc_way_chunks_36 = bits(alloc_way_r_metas, 36, 36) node alloc_way_chunks_37 = bits(alloc_way_r_metas, 37, 37) node alloc_way_chunks_38 = bits(alloc_way_r_metas, 38, 38) node alloc_way_chunks_39 = bits(alloc_way_r_metas, 39, 39) node alloc_way_chunks_40 = bits(alloc_way_r_metas, 40, 40) node alloc_way_chunks_41 = bits(alloc_way_r_metas, 41, 41) node alloc_way_chunks_42 = bits(alloc_way_r_metas, 42, 42) node alloc_way_chunks_43 = bits(alloc_way_r_metas, 43, 43) node alloc_way_chunks_44 = bits(alloc_way_r_metas, 44, 44) node alloc_way_chunks_45 = bits(alloc_way_r_metas, 45, 45) node alloc_way_chunks_46 = bits(alloc_way_r_metas, 46, 46) node alloc_way_chunks_47 = bits(alloc_way_r_metas, 47, 47) node alloc_way_chunks_48 = bits(alloc_way_r_metas, 48, 48) node alloc_way_chunks_49 = bits(alloc_way_r_metas, 49, 49) node alloc_way_chunks_50 = bits(alloc_way_r_metas, 50, 50) node alloc_way_chunks_51 = bits(alloc_way_r_metas, 51, 51) node alloc_way_chunks_52 = bits(alloc_way_r_metas, 52, 52) node alloc_way_chunks_53 = bits(alloc_way_r_metas, 53, 53) node alloc_way_chunks_54 = bits(alloc_way_r_metas, 54, 54) node alloc_way_chunks_55 = bits(alloc_way_r_metas, 55, 55) node alloc_way_chunks_56 = bits(alloc_way_r_metas, 56, 56) node alloc_way_chunks_57 = bits(alloc_way_r_metas, 57, 57) node alloc_way_chunks_58 = bits(alloc_way_r_metas, 58, 58) node alloc_way_chunks_59 = bits(alloc_way_r_metas, 59, 59) node alloc_way_chunks_60 = bits(alloc_way_r_metas, 60, 60) node alloc_way_chunks_61 = bits(alloc_way_r_metas, 61, 61) node alloc_way_chunks_62 = bits(alloc_way_r_metas, 62, 62) node alloc_way_chunks_63 = bits(alloc_way_r_metas, 63, 63) node alloc_way_chunks_64 = bits(alloc_way_r_metas, 64, 64) node alloc_way_chunks_65 = bits(alloc_way_r_metas, 65, 65) node alloc_way_chunks_66 = bits(alloc_way_r_metas, 66, 66) node alloc_way_chunks_67 = bits(alloc_way_r_metas, 67, 67) node alloc_way_chunks_68 = bits(alloc_way_r_metas, 68, 68) node alloc_way_chunks_69 = bits(alloc_way_r_metas, 69, 69) node alloc_way_chunks_70 = bits(alloc_way_r_metas, 70, 70) node alloc_way_chunks_71 = bits(alloc_way_r_metas, 71, 71) node alloc_way_chunks_72 = bits(alloc_way_r_metas, 72, 72) node alloc_way_chunks_73 = bits(alloc_way_r_metas, 73, 73) node alloc_way_chunks_74 = bits(alloc_way_r_metas, 74, 74) node alloc_way_chunks_75 = bits(alloc_way_r_metas, 75, 75) node alloc_way_chunks_76 = bits(alloc_way_r_metas, 76, 76) node alloc_way_chunks_77 = bits(alloc_way_r_metas, 77, 77) node alloc_way_chunks_78 = bits(alloc_way_r_metas, 78, 78) node alloc_way_chunks_79 = bits(alloc_way_r_metas, 79, 79) node alloc_way_chunks_80 = bits(alloc_way_r_metas, 80, 80) node alloc_way_chunks_81 = bits(alloc_way_r_metas, 81, 81) node alloc_way_chunks_82 = bits(alloc_way_r_metas, 82, 82) node alloc_way_chunks_83 = bits(alloc_way_r_metas, 83, 83) node alloc_way_chunks_84 = bits(alloc_way_r_metas, 84, 84) node alloc_way_chunks_85 = bits(alloc_way_r_metas, 85, 85) node alloc_way_chunks_86 = bits(alloc_way_r_metas, 86, 86) node alloc_way_chunks_87 = bits(alloc_way_r_metas, 87, 87) node alloc_way_chunks_88 = bits(alloc_way_r_metas, 88, 88) node alloc_way_chunks_89 = bits(alloc_way_r_metas, 89, 89) node alloc_way_chunks_90 = bits(alloc_way_r_metas, 90, 90) node alloc_way_chunks_91 = bits(alloc_way_r_metas, 91, 91) node alloc_way_chunks_92 = bits(alloc_way_r_metas, 92, 92) node alloc_way_chunks_93 = bits(alloc_way_r_metas, 93, 93) node alloc_way_chunks_94 = bits(alloc_way_r_metas, 94, 94) node alloc_way_chunks_95 = bits(alloc_way_r_metas, 95, 95) node alloc_way_chunks_96 = bits(alloc_way_r_metas, 96, 96) node alloc_way_chunks_97 = bits(alloc_way_r_metas, 97, 97) node alloc_way_chunks_98 = bits(alloc_way_r_metas, 98, 98) node alloc_way_chunks_99 = bits(alloc_way_r_metas, 99, 99) node alloc_way_chunks_100 = bits(alloc_way_r_metas, 100, 100) node alloc_way_chunks_101 = bits(alloc_way_r_metas, 101, 101) node alloc_way_chunks_102 = bits(alloc_way_r_metas, 102, 102) node alloc_way_chunks_103 = bits(alloc_way_r_metas, 103, 103) node alloc_way_chunks_104 = bits(alloc_way_r_metas, 104, 104) node alloc_way_chunks_105 = bits(alloc_way_r_metas, 105, 105) node alloc_way_chunks_106 = bits(alloc_way_r_metas, 106, 106) node alloc_way_chunks_107 = bits(alloc_way_r_metas, 107, 107) node alloc_way_chunks_108 = bits(alloc_way_r_metas, 108, 108) node alloc_way_chunks_109 = bits(alloc_way_r_metas, 109, 109) node alloc_way_chunks_110 = bits(alloc_way_r_metas, 110, 110) node alloc_way_chunks_111 = bits(alloc_way_r_metas, 111, 111) node alloc_way_chunks_112 = bits(alloc_way_r_metas, 112, 112) node alloc_way_chunks_113 = bits(alloc_way_r_metas, 113, 113) node alloc_way_chunks_114 = bits(alloc_way_r_metas, 114, 114) node alloc_way_chunks_115 = bits(alloc_way_r_metas, 115, 115) node alloc_way_chunks_116 = bits(alloc_way_r_metas, 116, 116) node alloc_way_chunks_117 = bits(alloc_way_r_metas, 117, 117) node alloc_way_chunks_118 = bits(alloc_way_r_metas, 118, 118) node alloc_way_chunks_119 = bits(alloc_way_r_metas, 119, 119) node alloc_way_chunks_120 = bits(alloc_way_r_metas, 120, 120) node alloc_way_chunks_121 = bits(alloc_way_r_metas, 121, 121) node alloc_way_chunks_122 = bits(alloc_way_r_metas, 122, 122) node alloc_way_chunks_123 = bits(alloc_way_r_metas, 123, 123) node alloc_way_chunks_124 = bits(alloc_way_r_metas, 124, 124) node alloc_way_chunks_125 = bits(alloc_way_r_metas, 125, 125) node alloc_way_chunks_126 = bits(alloc_way_r_metas, 126, 126) node alloc_way_chunks_127 = bits(alloc_way_r_metas, 127, 127) node alloc_way_chunks_128 = bits(alloc_way_r_metas, 128, 128) node alloc_way_chunks_129 = bits(alloc_way_r_metas, 129, 129) node alloc_way_chunks_130 = bits(alloc_way_r_metas, 130, 130) node alloc_way_chunks_131 = bits(alloc_way_r_metas, 131, 131) node alloc_way_chunks_132 = bits(alloc_way_r_metas, 132, 132) node alloc_way_chunks_133 = bits(alloc_way_r_metas, 133, 133) node alloc_way_chunks_134 = bits(alloc_way_r_metas, 134, 134) node alloc_way_chunks_135 = bits(alloc_way_r_metas, 135, 135) node alloc_way_chunks_136 = bits(alloc_way_r_metas, 136, 136) node alloc_way_chunks_137 = bits(alloc_way_r_metas, 137, 137) node alloc_way_chunks_138 = bits(alloc_way_r_metas, 138, 138) node alloc_way_chunks_139 = bits(alloc_way_r_metas, 139, 139) node alloc_way_chunks_140 = bits(alloc_way_r_metas, 140, 140) node alloc_way_chunks_141 = bits(alloc_way_r_metas, 141, 141) node alloc_way_chunks_142 = bits(alloc_way_r_metas, 142, 142) node alloc_way_chunks_143 = bits(alloc_way_r_metas, 143, 143) node alloc_way_chunks_144 = bits(alloc_way_r_metas, 144, 144) node alloc_way_chunks_145 = bits(alloc_way_r_metas, 145, 145) node alloc_way_chunks_146 = bits(alloc_way_r_metas, 146, 146) node alloc_way_chunks_147 = bits(alloc_way_r_metas, 147, 147) node alloc_way_chunks_148 = bits(alloc_way_r_metas, 148, 148) node alloc_way_chunks_149 = bits(alloc_way_r_metas, 149, 149) node alloc_way_chunks_150 = bits(alloc_way_r_metas, 150, 150) node alloc_way_chunks_151 = bits(alloc_way_r_metas, 151, 151) node alloc_way_chunks_152 = bits(alloc_way_r_metas, 152, 152) node alloc_way_chunks_153 = bits(alloc_way_r_metas, 153, 153) node alloc_way_chunks_154 = bits(alloc_way_r_metas, 154, 154) node alloc_way_chunks_155 = bits(alloc_way_r_metas, 155, 155) node alloc_way_chunks_156 = bits(alloc_way_r_metas, 156, 156) node alloc_way_chunks_157 = bits(alloc_way_r_metas, 157, 157) node alloc_way_chunks_158 = bits(alloc_way_r_metas, 158, 158) node alloc_way_chunks_159 = bits(alloc_way_r_metas, 159, 159) node alloc_way_chunks_160 = bits(alloc_way_r_metas, 160, 160) node alloc_way_chunks_161 = bits(alloc_way_r_metas, 161, 161) node alloc_way_chunks_162 = bits(alloc_way_r_metas, 162, 162) node alloc_way_chunks_163 = bits(alloc_way_r_metas, 163, 163) node alloc_way_chunks_164 = bits(alloc_way_r_metas, 164, 164) node alloc_way_chunks_165 = bits(alloc_way_r_metas, 165, 165) node alloc_way_chunks_166 = bits(alloc_way_r_metas, 166, 166) node alloc_way_chunks_167 = bits(alloc_way_r_metas, 167, 167) node alloc_way_chunks_168 = bits(alloc_way_r_metas, 168, 168) node alloc_way_chunks_169 = bits(alloc_way_r_metas, 169, 169) node alloc_way_chunks_170 = bits(alloc_way_r_metas, 170, 170) node alloc_way_chunks_171 = bits(alloc_way_r_metas, 171, 171) node alloc_way_chunks_172 = bits(alloc_way_r_metas, 172, 172) node alloc_way_chunks_173 = bits(alloc_way_r_metas, 173, 173) node alloc_way_chunks_174 = bits(alloc_way_r_metas, 174, 174) node alloc_way_chunks_175 = bits(alloc_way_r_metas, 175, 175) node alloc_way_chunks_176 = bits(alloc_way_r_metas, 176, 176) node alloc_way_chunks_177 = bits(alloc_way_r_metas, 177, 177) node alloc_way_chunks_178 = bits(alloc_way_r_metas, 178, 178) node alloc_way_chunks_179 = bits(alloc_way_r_metas, 179, 179) node alloc_way_chunks_180 = bits(alloc_way_r_metas, 180, 180) node alloc_way_chunks_181 = bits(alloc_way_r_metas, 181, 181) node alloc_way_chunks_182 = bits(alloc_way_r_metas, 182, 182) node alloc_way_chunks_183 = bits(alloc_way_r_metas, 183, 183) node alloc_way_chunks_184 = bits(alloc_way_r_metas, 184, 184) node alloc_way_chunks_185 = bits(alloc_way_r_metas, 185, 185) node alloc_way_chunks_186 = bits(alloc_way_r_metas, 186, 186) node alloc_way_chunks_187 = bits(alloc_way_r_metas, 187, 187) node alloc_way_chunks_188 = bits(alloc_way_r_metas, 188, 188) node alloc_way_chunks_189 = bits(alloc_way_r_metas, 189, 189) node alloc_way_chunks_190 = bits(alloc_way_r_metas, 190, 190) node alloc_way_chunks_191 = bits(alloc_way_r_metas, 191, 191) node alloc_way_chunks_192 = bits(alloc_way_r_metas, 192, 192) node alloc_way_chunks_193 = bits(alloc_way_r_metas, 193, 193) node alloc_way_chunks_194 = bits(alloc_way_r_metas, 194, 194) node alloc_way_chunks_195 = bits(alloc_way_r_metas, 195, 195) node alloc_way_chunks_196 = bits(alloc_way_r_metas, 196, 196) node alloc_way_chunks_197 = bits(alloc_way_r_metas, 197, 197) node alloc_way_chunks_198 = bits(alloc_way_r_metas, 198, 198) node alloc_way_chunks_199 = bits(alloc_way_r_metas, 199, 199) node alloc_way_chunks_200 = bits(alloc_way_r_metas, 200, 200) node alloc_way_chunks_201 = bits(alloc_way_r_metas, 201, 201) node alloc_way_chunks_202 = bits(alloc_way_r_metas, 202, 202) node alloc_way_chunks_203 = bits(alloc_way_r_metas, 203, 203) node alloc_way_chunks_204 = bits(alloc_way_r_metas, 204, 204) node alloc_way_chunks_205 = bits(alloc_way_r_metas, 205, 205) node alloc_way_chunks_206 = bits(alloc_way_r_metas, 206, 206) node alloc_way_chunks_207 = bits(alloc_way_r_metas, 207, 207) node alloc_way_chunks_208 = bits(alloc_way_r_metas, 208, 208) node alloc_way_chunks_209 = bits(alloc_way_r_metas, 209, 209) node alloc_way_chunks_210 = bits(alloc_way_r_metas, 210, 210) node alloc_way_chunks_211 = bits(alloc_way_r_metas, 211, 211) node alloc_way_chunks_212 = bits(alloc_way_r_metas, 212, 212) node alloc_way_chunks_213 = bits(alloc_way_r_metas, 213, 213) node alloc_way_chunks_214 = bits(alloc_way_r_metas, 214, 214) node alloc_way_chunks_215 = bits(alloc_way_r_metas, 215, 215) node alloc_way_chunks_216 = bits(alloc_way_r_metas, 216, 216) node alloc_way_chunks_217 = bits(alloc_way_r_metas, 217, 217) node alloc_way_chunks_218 = bits(alloc_way_r_metas, 218, 218) node alloc_way_chunks_219 = bits(alloc_way_r_metas, 219, 219) node alloc_way_chunks_220 = bits(alloc_way_r_metas, 220, 220) node alloc_way_chunks_221 = bits(alloc_way_r_metas, 221, 221) node alloc_way_chunks_222 = bits(alloc_way_r_metas, 222, 222) node alloc_way_chunks_223 = bits(alloc_way_r_metas, 223, 223) node alloc_way_chunks_224 = bits(alloc_way_r_metas, 224, 224) node alloc_way_chunks_225 = bits(alloc_way_r_metas, 225, 225) node alloc_way_chunks_226 = bits(alloc_way_r_metas, 226, 226) node alloc_way_chunks_227 = bits(alloc_way_r_metas, 227, 227) node alloc_way_chunks_228 = bits(alloc_way_r_metas, 228, 228) node alloc_way_chunks_229 = bits(alloc_way_r_metas, 229, 229) node alloc_way_chunks_230 = bits(alloc_way_r_metas, 230, 230) node alloc_way_chunks_231 = bits(alloc_way_r_metas, 231, 231) node alloc_way_chunks_232 = bits(alloc_way_r_metas, 232, 232) node alloc_way_chunks_233 = bits(alloc_way_r_metas, 233, 233) node alloc_way_chunks_234 = bits(alloc_way_r_metas, 234, 234) node alloc_way_chunks_235 = bits(alloc_way_r_metas, 235, 235) node alloc_way_chunks_236 = bits(alloc_way_r_metas, 236, 236) node alloc_way_chunks_237 = bits(alloc_way_r_metas, 237, 237) node alloc_way_chunks_238 = bits(alloc_way_r_metas, 238, 238) node alloc_way_chunks_239 = bits(alloc_way_r_metas, 239, 239) node alloc_way_chunks_240 = bits(alloc_way_r_metas, 240, 240) node alloc_way_chunks_241 = bits(alloc_way_r_metas, 241, 241) node alloc_way_chunks_242 = bits(alloc_way_r_metas, 242, 242) node alloc_way_chunks_243 = bits(alloc_way_r_metas, 243, 243) node alloc_way_chunks_244 = bits(alloc_way_r_metas, 244, 244) node alloc_way_chunks_245 = bits(alloc_way_r_metas, 245, 245) node alloc_way_chunks_246 = bits(alloc_way_r_metas, 246, 246) node alloc_way_chunks_247 = bits(alloc_way_r_metas, 247, 247) node alloc_way_chunks_248 = bits(alloc_way_r_metas, 248, 248) node alloc_way_chunks_249 = bits(alloc_way_r_metas, 249, 249) node alloc_way_chunks_250 = bits(alloc_way_r_metas, 250, 250) node alloc_way_chunks_251 = bits(alloc_way_r_metas, 251, 251) node alloc_way_chunks_252 = bits(alloc_way_r_metas, 252, 252) node alloc_way_chunks_253 = bits(alloc_way_r_metas, 253, 253) node alloc_way_chunks_254 = bits(alloc_way_r_metas, 254, 254) node alloc_way_chunks_255 = bits(alloc_way_r_metas, 255, 255) node alloc_way_chunks_256 = bits(alloc_way_r_metas, 256, 256) node alloc_way_chunks_257 = bits(alloc_way_r_metas, 257, 257) node alloc_way_chunks_258 = bits(alloc_way_r_metas, 258, 258) node alloc_way_chunks_259 = bits(alloc_way_r_metas, 259, 259) node alloc_way_chunks_260 = bits(alloc_way_r_metas, 260, 260) node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1) node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2) node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3) node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4) node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5) node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6) node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7) node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8) node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9) node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10) node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11) node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12) node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13) node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14) node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15) node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16) node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17) node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18) node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19) node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20) node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21) node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22) node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23) node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24) node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25) node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26) node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27) node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28) node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29) node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30) node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31) node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32) node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33) node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34) node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35) node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36) node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37) node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38) node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39) node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40) node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41) node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42) node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43) node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44) node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45) node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46) node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47) node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48) node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49) node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50) node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51) node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52) node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53) node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54) node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55) node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56) node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57) node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58) node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59) node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60) node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61) node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62) node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63) node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64) node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65) node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66) node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67) node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68) node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69) node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70) node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71) node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72) node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73) node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74) node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75) node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76) node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77) node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78) node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79) node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80) node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81) node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82) node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83) node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84) node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85) node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86) node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87) node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88) node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89) node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90) node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91) node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92) node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93) node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94) node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95) node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96) node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97) node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98) node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99) node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100) node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101) node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102) node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103) node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104) node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105) node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106) node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107) node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108) node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109) node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110) node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111) node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112) node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113) node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114) node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115) node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116) node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117) node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118) node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119) node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120) node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121) node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122) node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123) node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124) node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125) node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126) node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127) node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128) node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129) node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130) node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131) node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132) node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133) node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134) node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135) node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136) node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137) node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138) node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139) node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140) node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141) node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142) node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143) node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144) node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145) node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146) node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147) node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148) node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149) node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150) node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151) node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152) node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153) node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154) node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155) node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156) node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157) node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158) node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159) node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160) node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161) node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162) node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163) node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164) node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165) node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166) node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167) node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168) node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169) node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170) node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171) node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172) node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173) node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174) node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175) node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176) node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177) node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178) node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179) node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180) node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181) node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182) node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183) node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184) node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185) node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186) node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187) node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188) node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189) node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190) node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191) node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192) node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193) node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194) node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195) node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196) node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197) node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198) node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199) node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200) node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201) node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202) node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203) node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204) node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205) node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206) node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207) node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208) node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209) node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210) node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211) node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212) node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213) node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214) node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215) node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216) node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217) node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218) node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219) node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220) node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221) node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222) node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223) node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224) node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225) node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226) node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227) node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228) node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229) node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230) node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231) node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232) node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233) node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234) node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235) node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236) node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237) node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238) node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239) node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240) node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241) node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242) node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243) node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244) node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245) node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246) node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247) node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248) node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249) node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250) node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251) node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252) node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253) node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254) node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255) node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256) node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257) node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258) node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259) node alloc_way = xor(_alloc_way_T_258, alloc_way_chunks_260) node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1) node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2) node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3) node _s1_meta_write_way_T_3 = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0]) node _s1_meta_write_way_T_4 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0]) node _s1_meta_write_way_T_5 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0]) node _s1_meta_write_way_T_6 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0]) node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4) node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5) node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6) node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0) node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1) node _s1_meta_write_way_T_12 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), UInt<1>(0h1)) node _s1_meta_write_way_T_13 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_12, alloc_way) connect s1_meta.write_way, _s1_meta_write_way_T_13 wire s1_update_meta : { write_way : UInt<1>} wire _s1_update_meta_WIRE : UInt<1> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 0, 0) connect s1_update_meta.write_way, _s1_update_meta_T node _max_offset_value_T = not(UInt<12>(0h0)) node _max_offset_value_T_1 = cat(UInt<1>(0h0), _max_offset_value_T) node max_offset_value = asSInt(_max_offset_value_T_1) node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0)) node min_offset_value = asSInt(_min_offset_value_T) node _new_offset_value_T = asSInt(s1_update.bits.target) node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1) node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1) node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1) node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3) node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4) node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1) node new_offset_value = asSInt(_new_offset_value_T_6) node _offset_is_extended_T = gt(new_offset_value, max_offset_value) node _offset_is_extended_T_1 = lt(new_offset_value, min_offset_value) node offset_is_extended = or(_offset_is_extended_T, _offset_is_extended_T_1) wire s1_update_wbtb_data : { offset : SInt<13>, extended : UInt<1>} connect s1_update_wbtb_data.extended, offset_is_extended connect s1_update_wbtb_data.offset, new_offset_value node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid) node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken) node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4) node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6) node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8) node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask) node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2) node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4) node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_7 = mux(s1_update.valid, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_8 = and(_s1_update_wmeta_mask_T_7, s1_update.bits.btb_mispredicts) node _s1_update_wmeta_mask_T_9 = or(_s1_update_wmeta_mask_T_6, _s1_update_wmeta_mask_T_8) node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_9) wire s1_update_wmeta_data : { is_br : UInt<1>, tag : UInt<29>}[4] node _s1_update_wmeta_data_0_tag_T = bits(s1_update.bits.btb_mispredicts, 0, 0) node _s1_update_wmeta_data_0_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_0_tag_T_2 = mux(_s1_update_wmeta_data_0_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_0_tag_T_1) connect s1_update_wmeta_data[0].tag, _s1_update_wmeta_data_0_tag_T_2 node _s1_update_wmeta_data_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0) connect s1_update_wmeta_data[0].is_br, _s1_update_wmeta_data_0_is_br_T node _s1_update_wmeta_data_1_tag_T = bits(s1_update.bits.btb_mispredicts, 1, 1) node _s1_update_wmeta_data_1_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_1_tag_T_2 = mux(_s1_update_wmeta_data_1_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_1_tag_T_1) connect s1_update_wmeta_data[1].tag, _s1_update_wmeta_data_1_tag_T_2 node _s1_update_wmeta_data_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1) connect s1_update_wmeta_data[1].is_br, _s1_update_wmeta_data_1_is_br_T node _s1_update_wmeta_data_2_tag_T = bits(s1_update.bits.btb_mispredicts, 2, 2) node _s1_update_wmeta_data_2_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_2_tag_T_2 = mux(_s1_update_wmeta_data_2_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_2_tag_T_1) connect s1_update_wmeta_data[2].tag, _s1_update_wmeta_data_2_tag_T_2 node _s1_update_wmeta_data_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2) connect s1_update_wmeta_data[2].is_br, _s1_update_wmeta_data_2_is_br_T node _s1_update_wmeta_data_3_tag_T = bits(s1_update.bits.btb_mispredicts, 3, 3) node _s1_update_wmeta_data_3_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_3_tag_T_2 = mux(_s1_update_wmeta_data_3_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_3_tag_T_1) connect s1_update_wmeta_data[3].tag, _s1_update_wmeta_data_3_tag_T_2 node _s1_update_wmeta_data_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3) connect s1_update_wmeta_data[3].is_br, _s1_update_wmeta_data_3_is_br_T smem btb_meta_way_0 : UInt<30>[4] [128] smem btb_data_way_0 : UInt<14>[4] [128] wire _WIRE : UInt<36> invalidate _WIRE when io.f0_valid : connect _WIRE, s0_idx node _T_1 = bits(_WIRE, 6, 0) read mport MPORT = btb_meta_way_0[_T_1], clock wire _WIRE_1 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_2 : UInt<30> connect _WIRE_2, MPORT[0] node _T_2 = bits(_WIRE_2, 28, 0) connect _WIRE_1.tag, _T_2 node _T_3 = bits(_WIRE_2, 29, 29) connect _WIRE_1.is_br, _T_3 wire _WIRE_3 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_4 : UInt<30> connect _WIRE_4, MPORT[1] node _T_4 = bits(_WIRE_4, 28, 0) connect _WIRE_3.tag, _T_4 node _T_5 = bits(_WIRE_4, 29, 29) connect _WIRE_3.is_br, _T_5 wire _WIRE_5 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_6 : UInt<30> connect _WIRE_6, MPORT[2] node _T_6 = bits(_WIRE_6, 28, 0) connect _WIRE_5.tag, _T_6 node _T_7 = bits(_WIRE_6, 29, 29) connect _WIRE_5.is_br, _T_7 wire _WIRE_7 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_8 : UInt<30> connect _WIRE_8, MPORT[3] node _T_8 = bits(_WIRE_8, 28, 0) connect _WIRE_7.tag, _T_8 node _T_9 = bits(_WIRE_8, 29, 29) connect _WIRE_7.is_br, _T_9 wire _WIRE_9 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].is_br, _WIRE_1.is_br connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].is_br, _WIRE_3.is_br connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].is_br, _WIRE_5.is_br connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].is_br, _WIRE_7.is_br connect s1_req_rmeta[0], _WIRE_9 wire _WIRE_10 : UInt<36> invalidate _WIRE_10 when io.f0_valid : connect _WIRE_10, s0_idx node _T_10 = bits(_WIRE_10, 6, 0) read mport MPORT_1 = btb_data_way_0[_T_10], clock wire _WIRE_11 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_12 : UInt<14> connect _WIRE_12, MPORT_1[0] node _T_11 = bits(_WIRE_12, 0, 0) connect _WIRE_11.extended, _T_11 node _T_12 = bits(_WIRE_12, 13, 1) node _T_13 = asSInt(_T_12) connect _WIRE_11.offset, _T_13 wire _WIRE_13 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_14 : UInt<14> connect _WIRE_14, MPORT_1[1] node _T_14 = bits(_WIRE_14, 0, 0) connect _WIRE_13.extended, _T_14 node _T_15 = bits(_WIRE_14, 13, 1) node _T_16 = asSInt(_T_15) connect _WIRE_13.offset, _T_16 wire _WIRE_15 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_16 : UInt<14> connect _WIRE_16, MPORT_1[2] node _T_17 = bits(_WIRE_16, 0, 0) connect _WIRE_15.extended, _T_17 node _T_18 = bits(_WIRE_16, 13, 1) node _T_19 = asSInt(_T_18) connect _WIRE_15.offset, _T_19 wire _WIRE_17 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_18 : UInt<14> connect _WIRE_18, MPORT_1[3] node _T_20 = bits(_WIRE_18, 0, 0) connect _WIRE_17.extended, _T_20 node _T_21 = bits(_WIRE_18, 13, 1) node _T_22 = asSInt(_T_21) connect _WIRE_17.offset, _T_22 wire _WIRE_19 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_19[0].extended, _WIRE_11.extended connect _WIRE_19[0].offset, _WIRE_11.offset connect _WIRE_19[1].extended, _WIRE_13.extended connect _WIRE_19[1].offset, _WIRE_13.offset connect _WIRE_19[2].extended, _WIRE_15.extended connect _WIRE_19[2].offset, _WIRE_15.offset connect _WIRE_19[3].extended, _WIRE_17.extended connect _WIRE_19[3].offset, _WIRE_17.offset connect s1_req_rbtb[0], _WIRE_19 node _T_23 = eq(s1_update_meta.write_way, UInt<1>(0h0)) node _T_24 = or(doing_reset, _T_23) node _T_25 = or(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_20 : UInt<14>[4] connect _WIRE_20[0], UInt<14>(0h0) connect _WIRE_20[1], UInt<14>(0h0) connect _WIRE_20[2], UInt<14>(0h0) connect _WIRE_20[3], UInt<14>(0h0) node _T_27 = asUInt(s1_update_wbtb_data.offset) node _T_28 = cat(_T_27, s1_update_wbtb_data.extended) node _T_29 = asUInt(s1_update_wbtb_data.offset) node _T_30 = cat(_T_29, s1_update_wbtb_data.extended) node _T_31 = asUInt(s1_update_wbtb_data.offset) node _T_32 = cat(_T_31, s1_update_wbtb_data.extended) node _T_33 = asUInt(s1_update_wbtb_data.offset) node _T_34 = cat(_T_33, s1_update_wbtb_data.extended) wire _WIRE_21 : UInt<14>[4] connect _WIRE_21[0], _T_28 connect _WIRE_21[1], _T_30 connect _WIRE_21[2], _T_32 connect _WIRE_21[3], _T_34 node _T_35 = mux(doing_reset, _WIRE_20, _WIRE_21) node _T_36 = not(UInt<4>(0h0)) node _T_37 = mux(doing_reset, _T_36, s1_update_wbtb_mask) node _T_38 = bits(_T_37, 0, 0) node _T_39 = bits(_T_37, 1, 1) node _T_40 = bits(_T_37, 2, 2) node _T_41 = bits(_T_37, 3, 3) node _T_42 = or(_T_26, UInt<7>(0h0)) node _T_43 = bits(_T_42, 6, 0) write mport MPORT_2 = btb_data_way_0[_T_43], clock when _T_38 : connect MPORT_2[0], _T_35[0] when _T_39 : connect MPORT_2[1], _T_35[1] when _T_40 : connect MPORT_2[2], _T_35[2] when _T_41 : connect MPORT_2[3], _T_35[3] node _T_44 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_22 : UInt<30>[4] connect _WIRE_22[0], UInt<30>(0h0) connect _WIRE_22[1], UInt<30>(0h0) connect _WIRE_22[2], UInt<30>(0h0) connect _WIRE_22[3], UInt<30>(0h0) node _T_45 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_46 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_47 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_48 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_23 : UInt<30>[4] connect _WIRE_23[0], _T_45 connect _WIRE_23[1], _T_46 connect _WIRE_23[2], _T_47 connect _WIRE_23[3], _T_48 node _T_49 = mux(doing_reset, _WIRE_22, _WIRE_23) node _T_50 = not(UInt<4>(0h0)) node _T_51 = mux(doing_reset, _T_50, s1_update_wmeta_mask) node _T_52 = bits(_T_51, 0, 0) node _T_53 = bits(_T_51, 1, 1) node _T_54 = bits(_T_51, 2, 2) node _T_55 = bits(_T_51, 3, 3) node _T_56 = or(_T_44, UInt<7>(0h0)) node _T_57 = bits(_T_56, 6, 0) write mport MPORT_3 = btb_meta_way_0[_T_57], clock when _T_52 : connect MPORT_3[0], _T_49[0] when _T_53 : connect MPORT_3[1], _T_49[1] when _T_54 : connect MPORT_3[2], _T_49[2] when _T_55 : connect MPORT_3[3], _T_49[3] smem btb_meta_way_1 : UInt<30>[4] [128] smem btb_data_way_1 : UInt<14>[4] [128] wire _WIRE_24 : UInt<36> invalidate _WIRE_24 when io.f0_valid : connect _WIRE_24, s0_idx node _T_58 = bits(_WIRE_24, 6, 0) read mport MPORT_4 = btb_meta_way_1[_T_58], clock wire _WIRE_25 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_26 : UInt<30> connect _WIRE_26, MPORT_4[0] node _T_59 = bits(_WIRE_26, 28, 0) connect _WIRE_25.tag, _T_59 node _T_60 = bits(_WIRE_26, 29, 29) connect _WIRE_25.is_br, _T_60 wire _WIRE_27 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_28 : UInt<30> connect _WIRE_28, MPORT_4[1] node _T_61 = bits(_WIRE_28, 28, 0) connect _WIRE_27.tag, _T_61 node _T_62 = bits(_WIRE_28, 29, 29) connect _WIRE_27.is_br, _T_62 wire _WIRE_29 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_30 : UInt<30> connect _WIRE_30, MPORT_4[2] node _T_63 = bits(_WIRE_30, 28, 0) connect _WIRE_29.tag, _T_63 node _T_64 = bits(_WIRE_30, 29, 29) connect _WIRE_29.is_br, _T_64 wire _WIRE_31 : { is_br : UInt<1>, tag : UInt<29>} wire _WIRE_32 : UInt<30> connect _WIRE_32, MPORT_4[3] node _T_65 = bits(_WIRE_32, 28, 0) connect _WIRE_31.tag, _T_65 node _T_66 = bits(_WIRE_32, 29, 29) connect _WIRE_31.is_br, _T_66 wire _WIRE_33 : { is_br : UInt<1>, tag : UInt<29>}[4] connect _WIRE_33[0].tag, _WIRE_25.tag connect _WIRE_33[0].is_br, _WIRE_25.is_br connect _WIRE_33[1].tag, _WIRE_27.tag connect _WIRE_33[1].is_br, _WIRE_27.is_br connect _WIRE_33[2].tag, _WIRE_29.tag connect _WIRE_33[2].is_br, _WIRE_29.is_br connect _WIRE_33[3].tag, _WIRE_31.tag connect _WIRE_33[3].is_br, _WIRE_31.is_br connect s1_req_rmeta[1], _WIRE_33 wire _WIRE_34 : UInt<36> invalidate _WIRE_34 when io.f0_valid : connect _WIRE_34, s0_idx node _T_67 = bits(_WIRE_34, 6, 0) read mport MPORT_5 = btb_data_way_1[_T_67], clock wire _WIRE_35 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_36 : UInt<14> connect _WIRE_36, MPORT_5[0] node _T_68 = bits(_WIRE_36, 0, 0) connect _WIRE_35.extended, _T_68 node _T_69 = bits(_WIRE_36, 13, 1) node _T_70 = asSInt(_T_69) connect _WIRE_35.offset, _T_70 wire _WIRE_37 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_38 : UInt<14> connect _WIRE_38, MPORT_5[1] node _T_71 = bits(_WIRE_38, 0, 0) connect _WIRE_37.extended, _T_71 node _T_72 = bits(_WIRE_38, 13, 1) node _T_73 = asSInt(_T_72) connect _WIRE_37.offset, _T_73 wire _WIRE_39 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_40 : UInt<14> connect _WIRE_40, MPORT_5[2] node _T_74 = bits(_WIRE_40, 0, 0) connect _WIRE_39.extended, _T_74 node _T_75 = bits(_WIRE_40, 13, 1) node _T_76 = asSInt(_T_75) connect _WIRE_39.offset, _T_76 wire _WIRE_41 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_42 : UInt<14> connect _WIRE_42, MPORT_5[3] node _T_77 = bits(_WIRE_42, 0, 0) connect _WIRE_41.extended, _T_77 node _T_78 = bits(_WIRE_42, 13, 1) node _T_79 = asSInt(_T_78) connect _WIRE_41.offset, _T_79 wire _WIRE_43 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_43[0].extended, _WIRE_35.extended connect _WIRE_43[0].offset, _WIRE_35.offset connect _WIRE_43[1].extended, _WIRE_37.extended connect _WIRE_43[1].offset, _WIRE_37.offset connect _WIRE_43[2].extended, _WIRE_39.extended connect _WIRE_43[2].offset, _WIRE_39.offset connect _WIRE_43[3].extended, _WIRE_41.extended connect _WIRE_43[3].offset, _WIRE_41.offset connect s1_req_rbtb[1], _WIRE_43 node _T_80 = eq(s1_update_meta.write_way, UInt<1>(0h1)) node _T_81 = or(doing_reset, _T_80) node _T_82 = or(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_44 : UInt<14>[4] connect _WIRE_44[0], UInt<14>(0h0) connect _WIRE_44[1], UInt<14>(0h0) connect _WIRE_44[2], UInt<14>(0h0) connect _WIRE_44[3], UInt<14>(0h0) node _T_84 = asUInt(s1_update_wbtb_data.offset) node _T_85 = cat(_T_84, s1_update_wbtb_data.extended) node _T_86 = asUInt(s1_update_wbtb_data.offset) node _T_87 = cat(_T_86, s1_update_wbtb_data.extended) node _T_88 = asUInt(s1_update_wbtb_data.offset) node _T_89 = cat(_T_88, s1_update_wbtb_data.extended) node _T_90 = asUInt(s1_update_wbtb_data.offset) node _T_91 = cat(_T_90, s1_update_wbtb_data.extended) wire _WIRE_45 : UInt<14>[4] connect _WIRE_45[0], _T_85 connect _WIRE_45[1], _T_87 connect _WIRE_45[2], _T_89 connect _WIRE_45[3], _T_91 node _T_92 = mux(doing_reset, _WIRE_44, _WIRE_45) node _T_93 = not(UInt<4>(0h0)) node _T_94 = mux(doing_reset, _T_93, s1_update_wbtb_mask) node _T_95 = bits(_T_94, 0, 0) node _T_96 = bits(_T_94, 1, 1) node _T_97 = bits(_T_94, 2, 2) node _T_98 = bits(_T_94, 3, 3) node _T_99 = or(_T_83, UInt<7>(0h0)) node _T_100 = bits(_T_99, 6, 0) write mport MPORT_6 = btb_data_way_1[_T_100], clock when _T_95 : connect MPORT_6[0], _T_92[0] when _T_96 : connect MPORT_6[1], _T_92[1] when _T_97 : connect MPORT_6[2], _T_92[2] when _T_98 : connect MPORT_6[3], _T_92[3] node _T_101 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_46 : UInt<30>[4] connect _WIRE_46[0], UInt<30>(0h0) connect _WIRE_46[1], UInt<30>(0h0) connect _WIRE_46[2], UInt<30>(0h0) connect _WIRE_46[3], UInt<30>(0h0) node _T_102 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_103 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_104 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_105 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_47 : UInt<30>[4] connect _WIRE_47[0], _T_102 connect _WIRE_47[1], _T_103 connect _WIRE_47[2], _T_104 connect _WIRE_47[3], _T_105 node _T_106 = mux(doing_reset, _WIRE_46, _WIRE_47) node _T_107 = not(UInt<4>(0h0)) node _T_108 = mux(doing_reset, _T_107, s1_update_wmeta_mask) node _T_109 = bits(_T_108, 0, 0) node _T_110 = bits(_T_108, 1, 1) node _T_111 = bits(_T_108, 2, 2) node _T_112 = bits(_T_108, 3, 3) node _T_113 = or(_T_101, UInt<7>(0h0)) node _T_114 = bits(_T_113, 6, 0) write mport MPORT_7 = btb_meta_way_1[_T_114], clock when _T_109 : connect MPORT_7[0], _T_106[0] when _T_110 : connect MPORT_7[1], _T_106[1] when _T_111 : connect MPORT_7[2], _T_106[2] when _T_112 : connect MPORT_7[3], _T_106[3] smem btb_ebtb : UInt<40> [128] wire _s1_req_rebtb_WIRE : UInt<36> invalidate _s1_req_rebtb_WIRE when io.f0_valid : connect _s1_req_rebtb_WIRE, s0_idx node _s1_req_rebtb_T = bits(_s1_req_rebtb_WIRE, 6, 0) read mport s1_req_rebtb_MPORT = btb_ebtb[_s1_req_rebtb_T], clock connect s1_req_rebtb, s1_req_rebtb_MPORT node _T_115 = neq(s1_update_wbtb_mask, UInt<1>(0h0)) node _T_116 = and(_T_115, offset_is_extended) when _T_116 : node _T_117 = or(s1_update_idx, UInt<7>(0h0)) node _T_118 = bits(_T_117, 6, 0) write mport MPORT_8 = btb_ebtb[_T_118], clock connect MPORT_8, s1_update.bits.target

module BTBBranchPredictorBank( // @[btb.scala:24:7] input clock, // @[btb.scala:24:7] input reset, // @[btb.scala:24:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [29:0] btb_meta_way_1_MPORT_7_data_3; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_2; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_1; // @[btb.scala:207:14] wire [29:0] btb_meta_way_1_MPORT_7_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_1_MPORT_6_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_0; // @[btb.scala:201:14] wire [29:0] btb_meta_way_0_MPORT_3_data_3; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_2; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_1; // @[btb.scala:207:14] wire [29:0] btb_meta_way_0_MPORT_3_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_0_MPORT_2_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_0; // @[btb.scala:201:14] wire _s1_update_meta_WIRE; // @[btb.scala:139:55] wire s1_req_rbtb_1_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_0_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_0_offset; // @[btb.scala:71:26] wire [28:0] s1_req_rmeta_1_3_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_2_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_1_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_1_0_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_3_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_2_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_1_tag; // @[btb.scala:70:26] wire [28:0] s1_req_rmeta_0_0_tag; // @[btb.scala:70:26] wire [55:0] _btb_data_way_1_R0_data; // @[btb.scala:192:29] wire [119:0] _btb_meta_way_1_R0_data; // @[btb.scala:191:29] wire [55:0] _btb_data_way_0_R0_data; // @[btb.scala:192:29] wire [119:0] _btb_meta_way_0_R0_data; // @[btb.scala:191:29] wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:24:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:24:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:24:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:24:7] wire io_update_valid_0 = io_update_valid; // @[btb.scala:24:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:24:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:24:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:24:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:24:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:24:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:24:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:24:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:24:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:24:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:24:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:24:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:24:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:24:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:24:7] wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:141:35] wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:141:{29,59}] wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:141:59] wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:142:{29,59}] wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:142:59] wire io_f1_lhist = 1'h0; // @[btb.scala:24:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_taken_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_1_taken_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_2_taken_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_3_taken_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_0_taken_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_1_taken_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_2_taken_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_3_taken_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] wire [119:0] io_f3_meta_0; // @[btb.scala:24:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:149:35] wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:149:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] wire [39:0] _s0_pc_T = ~io_f0_pc_0; // @[frontend.scala:147:33] wire [39:0] _s0_pc_T_1 = {_s0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] s0_pc = ~_s0_pc_T_1; // @[frontend.scala:147:{31,39}] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_3_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_3_T = s1_pc; // @[predictor.scala:178:22] reg [39:0] s2_pc; // @[predictor.scala:179:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:149:35] reg s1_update_valid; // @[predictor.scala:185:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:185:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:185:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:185:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:185:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:185:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:185:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:185:30] reg s1_update_bits_lhist; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:185:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:185:30] wire [39:0] _s1_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _s1_update_bits_pc_T_1 = {_s1_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _s1_update_bits_pc_T_2 = ~_s1_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] reg [35:0] s1_update_idx; // @[predictor.scala:187:30] reg s1_update_valid_0; // @[predictor.scala:188:32] wire _s1_meta_write_way_T_13; // @[btb.scala:134:27] wire s1_meta_write_way; // @[btb.scala:53:21] reg f3_meta_REG_write_way; // @[btb.scala:54:32] reg f3_meta_write_way; // @[btb.scala:54:24] assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:24:7, :54:24, :57:14] reg doing_reset; // @[btb.scala:61:28] reg [6:0] reset_idx; // @[btb.scala:62:28] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:61:28, :62:28, :63:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:63:26] wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:70:26, :124:62] wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_0_is_br; // @[btb.scala:70:26] wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_3_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_0_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_3_is_br; // @[btb.scala:70:26] wire [12:0] entry_btb_offset = s1_req_rbtb_0_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_extended = s1_req_rbtb_0_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_2_offset = s1_req_rbtb_0_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_2_extended = s1_req_rbtb_0_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_4_offset = s1_req_rbtb_0_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_4_extended = s1_req_rbtb_0_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_6_offset = s1_req_rbtb_0_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_6_extended = s1_req_rbtb_0_3_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_1_offset = s1_req_rbtb_1_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_1_extended = s1_req_rbtb_1_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_3_offset = s1_req_rbtb_1_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_3_extended = s1_req_rbtb_1_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_5_offset = s1_req_rbtb_1_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_5_extended = s1_req_rbtb_1_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_7_offset = s1_req_rbtb_1_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_7_extended = s1_req_rbtb_1_3_extended; // @[btb.scala:71:26, :90:31] wire [39:0] s1_req_rebtb; // @[btb.scala:72:26] wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29] wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:74:29, :124:98] wire _s1_resp_0_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_1_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_2_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_3_valid_T_2; // @[btb.scala:97:50] wire s1_resp_0_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_0_bits; // @[btb.scala:76:23] wire s1_resp_1_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_1_bits; // @[btb.scala:76:23] wire s1_resp_2_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_2_bits; // @[btb.scala:76:23] wire s1_resp_3_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_3_bits; // @[btb.scala:76:23] wire _s1_is_br_0_T_2; // @[btb.scala:99:54] wire _s1_is_br_1_T_2; // @[btb.scala:99:54] wire _s1_is_br_2_T_2; // @[btb.scala:99:54] wire _s1_is_br_3_T_2; // @[btb.scala:99:54] wire s1_is_br_0; // @[btb.scala:77:23] wire s1_is_br_1; // @[btb.scala:77:23] wire s1_is_br_2; // @[btb.scala:77:23] wire s1_is_br_3; // @[btb.scala:77:23] wire _s1_is_jal_0_T_3; // @[btb.scala:100:54] wire _s1_is_jal_1_T_3; // @[btb.scala:100:54] wire _s1_is_jal_2_T_3; // @[btb.scala:100:54] wire _s1_is_jal_3_T_3; // @[btb.scala:100:54] wire s1_is_jal_0; // @[btb.scala:78:23] wire s1_is_jal_1; // @[btb.scala:78:23] wire s1_is_jal_2; // @[btb.scala:78:23] wire s1_is_jal_3; // @[btb.scala:78:23] wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:80:27, :81:12] wire s1_hits_0 = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[btb.scala:80:27, :85:55] wire s1_hits_1 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[btb.scala:80:27, :85:55] wire s1_hits_2 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[btb.scala:80:27, :85:55] wire s1_hits_3 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[btb.scala:80:27, :85:55] wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70] wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70] wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70] wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70] wire [39:0] _s1_targs_0_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_3_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_3_T_8; // @[btb.scala:91:28] wire [39:0] s1_targs_0_0; // @[btb.scala:87:25] wire [39:0] s1_targs_0_1; // @[btb.scala:87:25] wire [39:0] s1_targs_0_2; // @[btb.scala:87:25] wire [39:0] s1_targs_0_3; // @[btb.scala:87:25] wire [39:0] s1_targs_1_0; // @[btb.scala:87:25] wire [39:0] s1_targs_1_1; // @[btb.scala:87:25] wire [39:0] s1_targs_1_2; // @[btb.scala:87:25] wire [39:0] s1_targs_1_3; // @[btb.scala:87:25] wire [40:0] _s1_targs_0_0_T_1 = {_s1_targs_0_0_T[39], _s1_targs_0_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_0_T_2 = _s1_targs_0_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_0_T_3 = _s1_targs_0_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_0_T_4 = {_s1_targs_0_0_T_3[39], _s1_targs_0_0_T_3} + {{28{entry_btb_offset[12]}}, entry_btb_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_0_T_5 = _s1_targs_0_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_6 = _s1_targs_0_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_7 = _s1_targs_0_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_0_T_8 = entry_btb_extended ? s1_req_rebtb : _s1_targs_0_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_0 = _s1_targs_0_0_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_0_T_1 = {_s1_targs_1_0_T[39], _s1_targs_1_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_0_T_2 = _s1_targs_1_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_0_T_3 = _s1_targs_1_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_0_T_4 = {_s1_targs_1_0_T_3[39], _s1_targs_1_0_T_3} + {{28{entry_btb_1_offset[12]}}, entry_btb_1_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_0_T_5 = _s1_targs_1_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_6 = _s1_targs_1_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_7 = _s1_targs_1_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_0_T_8 = entry_btb_1_extended ? s1_req_rebtb : _s1_targs_1_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_0 = _s1_targs_1_0_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_0_bits = s1_hit_ways_0 ? s1_targs_1_0 : s1_targs_0_0; // @[Mux.scala:50:70] wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70] assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN; // @[btb.scala:99:{34,54}] assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_0_T_2 = ~_GEN; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:78:23, :100:54] reg REG; // @[btb.scala:105:18] reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_0_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_0_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_1; // @[btb.scala:109:20] assign io_resp_f2_0_taken_0 = REG & REG_1 | io_resp_in_0_f2_0_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_2; // @[btb.scala:113:26] reg REG_3; // @[btb.scala:113:18] reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_0_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_0_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_4; // @[btb.scala:117:28] reg REG_5; // @[btb.scala:117:20] assign io_resp_f3_0_taken_0 = REG_3 & REG_5 | io_resp_in_0_f3_0_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_1_T_1 = {_s1_targs_0_1_T[39], _s1_targs_0_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_1_T_2 = _s1_targs_0_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_1_T_3 = _s1_targs_0_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_1_T_4 = {_s1_targs_0_1_T_3[39], _s1_targs_0_1_T_3} + {{28{entry_btb_2_offset[12]}}, entry_btb_2_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_1_T_5 = _s1_targs_0_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_6 = _s1_targs_0_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_7 = _s1_targs_0_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_1_T_8 = entry_btb_2_extended ? s1_req_rebtb : _s1_targs_0_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_1 = _s1_targs_0_1_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_1_T_1 = {_s1_targs_1_1_T[39], _s1_targs_1_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_1_T_2 = _s1_targs_1_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_1_T_3 = _s1_targs_1_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_1_T_4 = {_s1_targs_1_1_T_3[39], _s1_targs_1_1_T_3} + {{28{entry_btb_3_offset[12]}}, entry_btb_3_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_1_T_5 = _s1_targs_1_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_6 = _s1_targs_1_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_7 = _s1_targs_1_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_1_T_8 = entry_btb_3_extended ? s1_req_rebtb : _s1_targs_1_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_1 = _s1_targs_1_1_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_1_bits = s1_hit_ways_1 ? s1_targs_1_1 : s1_targs_0_1; // @[Mux.scala:50:70] wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_0 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70] assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_0; // @[btb.scala:99:{34,54}] assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_1_T_2 = ~_GEN_0; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:78:23, :100:54] reg REG_6; // @[btb.scala:105:18] reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_1_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_1_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_7; // @[btb.scala:109:20] assign io_resp_f2_1_taken_0 = REG_6 & REG_7 | io_resp_in_0_f2_1_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_8; // @[btb.scala:113:26] reg REG_9; // @[btb.scala:113:18] reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_1_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_1_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_10; // @[btb.scala:117:28] reg REG_11; // @[btb.scala:117:20] assign io_resp_f3_1_taken_0 = REG_9 & REG_11 | io_resp_in_0_f3_1_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_2_T_1 = {_s1_targs_0_2_T[39], _s1_targs_0_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_2_T_2 = _s1_targs_0_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_2_T_3 = _s1_targs_0_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_2_T_4 = {_s1_targs_0_2_T_3[39], _s1_targs_0_2_T_3} + {{28{entry_btb_4_offset[12]}}, entry_btb_4_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_2_T_5 = _s1_targs_0_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_6 = _s1_targs_0_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_7 = _s1_targs_0_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_2_T_8 = entry_btb_4_extended ? s1_req_rebtb : _s1_targs_0_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_2 = _s1_targs_0_2_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_2_T_1 = {_s1_targs_1_2_T[39], _s1_targs_1_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_2_T_2 = _s1_targs_1_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_2_T_3 = _s1_targs_1_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_2_T_4 = {_s1_targs_1_2_T_3[39], _s1_targs_1_2_T_3} + {{28{entry_btb_5_offset[12]}}, entry_btb_5_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_2_T_5 = _s1_targs_1_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_6 = _s1_targs_1_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_7 = _s1_targs_1_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_2_T_8 = entry_btb_5_extended ? s1_req_rebtb : _s1_targs_1_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_2 = _s1_targs_1_2_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_2_bits = s1_hit_ways_2 ? s1_targs_1_2 : s1_targs_0_2; // @[Mux.scala:50:70] wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_1 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70] assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_1; // @[btb.scala:99:{34,54}] assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_2_T_2 = ~_GEN_1; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:78:23, :100:54] reg REG_12; // @[btb.scala:105:18] reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_2_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_2_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_13; // @[btb.scala:109:20] assign io_resp_f2_2_taken_0 = REG_12 & REG_13 | io_resp_in_0_f2_2_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_14; // @[btb.scala:113:26] reg REG_15; // @[btb.scala:113:18] reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_2_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_2_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_16; // @[btb.scala:117:28] reg REG_17; // @[btb.scala:117:20] assign io_resp_f3_2_taken_0 = REG_15 & REG_17 | io_resp_in_0_f3_2_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_3_T_1 = {_s1_targs_0_3_T[39], _s1_targs_0_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_3_T_2 = _s1_targs_0_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_3_T_3 = _s1_targs_0_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_3_T_4 = {_s1_targs_0_3_T_3[39], _s1_targs_0_3_T_3} + {{28{entry_btb_6_offset[12]}}, entry_btb_6_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_3_T_5 = _s1_targs_0_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_6 = _s1_targs_0_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_7 = _s1_targs_0_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_3_T_8 = entry_btb_6_extended ? s1_req_rebtb : _s1_targs_0_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_3 = _s1_targs_0_3_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_3_T_1 = {_s1_targs_1_3_T[39], _s1_targs_1_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_3_T_2 = _s1_targs_1_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_3_T_3 = _s1_targs_1_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_3_T_4 = {_s1_targs_1_3_T_3[39], _s1_targs_1_3_T_3} + {{28{entry_btb_7_offset[12]}}, entry_btb_7_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_3_T_5 = _s1_targs_1_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_6 = _s1_targs_1_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_7 = _s1_targs_1_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_3_T_8 = entry_btb_7_extended ? s1_req_rebtb : _s1_targs_1_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_3 = _s1_targs_1_3_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_3_bits = s1_hit_ways_3 ? s1_targs_1_3 : s1_targs_0_3; // @[Mux.scala:50:70] wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_2 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70] assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_2; // @[btb.scala:99:{34,54}] assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_3_T_2 = ~_GEN_2; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:78:23, :100:54] reg REG_18; // @[btb.scala:105:18] reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_3_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_3_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_19; // @[btb.scala:109:20] assign io_resp_f2_3_taken_0 = REG_18 & REG_19 | io_resp_in_0_f2_3_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_20; // @[btb.scala:113:26] reg REG_21; // @[btb.scala:113:18] reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_3_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_3_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_22; // @[btb.scala:117:28] reg REG_23; // @[btb.scala:117:20] assign io_resp_f3_3_taken_0 = REG_21 & REG_23 | io_resp_in_0_f3_3_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:124:{30,62}] wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:124:{30,62}] wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:124:{30,80}] wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:124:{30,80}] wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:124:80] wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:124:{30,80}] wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:124:{30,80}] wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:124:80] wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:124:80] wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:124:{22,80,98}] wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:124:22, :128:14] wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:128:14, :130:20] wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:128:14, :130:20] wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[btb.scala:85:55, :134:44] wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[btb.scala:135:{38,54}] wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45] assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70] assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:53:21, :134:27] wire _s1_update_meta_T; // @[btb.scala:139:55] wire s1_update_meta_write_way; // @[btb.scala:139:55] assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:139:55] assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:185:30] assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:139:55] wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:185:30] wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:144:24] wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:144:{24,62}] wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:143:{49,56}, :144:62] wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:143:56] wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:143:56] wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:143:56, :145:46] wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:143:56, :146:46] wire offset_is_extended = _offset_is_extended_T | _offset_is_extended_T_1; // @[btb.scala:145:{46,65}, :146:46] wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:145:65, :149:34] wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:149:34] assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:143:56, :149:34, :151:32] wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:185:30] wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _GEN_3 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :185:30] wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49] assign _s1_update_wbtb_mask_T_3 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49] assign _s1_update_wmeta_mask_T_1 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}] wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26] wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:153:{9,97}] wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35] wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:185:30] wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}] wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :185:30] wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:156:{10,38}] wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 | _s1_update_wmeta_mask_T_8; // @[btb.scala:156:{10,74}, :157:40] wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:155:{52,78}, :156:74] wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:164:62] wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:163:43] wire s1_update_wmeta_data_0_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_1_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_2_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_3_is_br; // @[btb.scala:160:34] wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:160:34] wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:185:30] wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:187:30] assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:160:34, :164:62] assign s1_req_rmeta_0_0_tag = _btb_meta_way_0_R0_data[28:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_0_is_br = _btb_meta_way_0_R0_data[29]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_tag = _btb_meta_way_0_R0_data[58:30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_is_br = _btb_meta_way_0_R0_data[59]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_tag = _btb_meta_way_0_R0_data[88:60]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_is_br = _btb_meta_way_0_R0_data[89]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_tag = _btb_meta_way_0_R0_data[118:90]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_is_br = _btb_meta_way_0_R0_data[119]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_0_0_extended = _btb_data_way_0_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_0_offset = _btb_data_way_0_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_extended = _btb_data_way_0_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_offset = _btb_data_way_0_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_extended = _btb_data_way_0_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_offset = _btb_data_way_0_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_extended = _btb_data_way_0_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_offset = _btb_data_way_0_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_0_MPORT_2_en = doing_reset | ~s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:{25,53}] wire [6:0] _T_56 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_0_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_0_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign s1_req_rmeta_1_0_tag = _btb_meta_way_1_R0_data[28:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_0_is_br = _btb_meta_way_1_R0_data[29]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_tag = _btb_meta_way_1_R0_data[58:30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_is_br = _btb_meta_way_1_R0_data[59]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_tag = _btb_meta_way_1_R0_data[88:60]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_is_br = _btb_meta_way_1_R0_data[89]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_tag = _btb_meta_way_1_R0_data[118:90]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_is_br = _btb_meta_way_1_R0_data[119]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_1_0_extended = _btb_data_way_1_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_0_offset = _btb_data_way_1_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_extended = _btb_data_way_1_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_offset = _btb_data_way_1_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_extended = _btb_data_way_1_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_offset = _btb_data_way_1_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_extended = _btb_data_way_1_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_offset = _btb_data_way_1_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_1_MPORT_6_en = doing_reset | s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:25] wire [6:0] _T_113 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_1_MPORT_6_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_1_MPORT_7_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:215:30] always @(posedge clock) begin // @[btb.scala:24:7] s1_idx <= s0_idx; // @[frontend.scala:149:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= s0_pc; // @[frontend.scala:147:31] s2_pc <= s1_pc; // @[predictor.scala:178:22, :179:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:185:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:185:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:185:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:185:30] s1_update_bits_pc <= _s1_update_bits_pc_T_2; // @[frontend.scala:147:31] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:185:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:185:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:185:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:185:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:185:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:185:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:185:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:149:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:188:32] f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:53:21, :54:32] f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:54:{24,32}] REG <= s1_hits_0; // @[btb.scala:85:55, :105:18] io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:77:23, :107:44] io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:78:23, :108:44] REG_1 <= s1_is_jal_0; // @[btb.scala:78:23, :109:20] REG_2 <= s1_hits_0; // @[btb.scala:85:55, :113:26] REG_3 <= REG_2; // @[btb.scala:113:{18,26}] io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:24:7, :116:44] REG_4 <= s1_is_jal_0; // @[btb.scala:78:23, :117:28] REG_5 <= REG_4; // @[btb.scala:117:{20,28}] REG_6 <= s1_hits_1; // @[btb.scala:85:55, :105:18] io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:77:23, :107:44] io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:78:23, :108:44] REG_7 <= s1_is_jal_1; // @[btb.scala:78:23, :109:20] REG_8 <= s1_hits_1; // @[btb.scala:85:55, :113:26] REG_9 <= REG_8; // @[btb.scala:113:{18,26}] io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:24:7, :116:44] REG_10 <= s1_is_jal_1; // @[btb.scala:78:23, :117:28] REG_11 <= REG_10; // @[btb.scala:117:{20,28}] REG_12 <= s1_hits_2; // @[btb.scala:85:55, :105:18] io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:77:23, :107:44] io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:78:23, :108:44] REG_13 <= s1_is_jal_2; // @[btb.scala:78:23, :109:20] REG_14 <= s1_hits_2; // @[btb.scala:85:55, :113:26] REG_15 <= REG_14; // @[btb.scala:113:{18,26}] io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:24:7, :116:44] REG_16 <= s1_is_jal_2; // @[btb.scala:78:23, :117:28] REG_17 <= REG_16; // @[btb.scala:117:{20,28}] REG_18 <= s1_hits_3; // @[btb.scala:85:55, :105:18] io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:77:23, :107:44] io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:78:23, :108:44] REG_19 <= s1_is_jal_3; // @[btb.scala:78:23, :109:20] REG_20 <= s1_hits_3; // @[btb.scala:85:55, :113:26] REG_21 <= REG_20; // @[btb.scala:113:{18,26}] io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:24:7, :116:44] REG_22 <= s1_is_jal_3; // @[btb.scala:78:23, :117:28] REG_23 <= REG_22; // @[btb.scala:117:{20,28}] if (reset) begin // @[btb.scala:24:7] doing_reset <= 1'h1; // @[btb.scala:61:28] reset_idx <= 7'h0; // @[btb.scala:62:28] end else begin // @[btb.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:61:28, :62:28, :64:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[btb.scala:62:28, :63:26] end always @(posedge) btb_meta_way_0 btb_meta_way_0 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_0_MPORT_3_data_3, btb_meta_way_0_MPORT_3_data_2, btb_meta_way_0_MPORT_3_data_1, btb_meta_way_0_MPORT_3_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_0 btb_data_way_0 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_0_MPORT_2_data_3, btb_data_way_0_MPORT_2_data_2, btb_data_way_0_MPORT_2_data_1, btb_data_way_0_MPORT_2_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_meta_way_1 btb_meta_way_1 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_1_MPORT_7_data_3, btb_meta_way_1_MPORT_7_data_2, btb_meta_way_1_MPORT_7_data_1, btb_meta_way_1_MPORT_7_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_1 btb_data_way_1 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_1_MPORT_6_data_3, btb_data_way_1_MPORT_6_data_2, btb_data_way_1_MPORT_6_data_1, btb_data_way_1_MPORT_6_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_ebtb btb_ebtb ( // @[btb.scala:213:27] .R0_addr (_s1_req_rebtb_T), // @[btb.scala:215:30] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (s1_req_rebtb), .W0_addr (s1_update_idx[6:0]), // @[predictor.scala:187:30] .W0_en ((|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:145:65, :152:58, :216:{31,39}] .W0_clk (clock), .W0_data (s1_update_bits_target) // @[predictor.scala:185:30] ); // @[btb.scala:213:27] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_f3_meta = io_f3_meta_0; // @[btb.scala:24:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_51 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_51( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ProbeUnit : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, rep : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<2>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, flip way_en : UInt<8>, flip mshr_rdy : UInt<1>, flip block_state : { state : UInt<2>}} regreset state : UInt<4>, clock, reset, UInt<4>(0h0) reg req : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node req_idx = bits(req.address, 11, 6) node req_tag = shr(req.address, 12) reg way_en : UInt, clock node tag_matches = orr(way_en) reg old_coh : { state : UInt<2>}, clock wire miss_coh : { state : UInt<2>} connect miss_coh.state, UInt<2>(0h0) node reply_coh = mux(tag_matches, old_coh, miss_coh) node _r_T = cat(req.param, reply_coh.state) node _r_T_1 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_2 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_3 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_4 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_5 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_6 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_7 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_8 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_9 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_10 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_11 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_12 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_13 = eq(_r_T_12, _r_T) node _r_T_14 = mux(_r_T_13, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_15 = mux(_r_T_13, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_16 = mux(_r_T_13, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_17 = eq(_r_T_11, _r_T) node _r_T_18 = mux(_r_T_17, UInt<1>(0h0), _r_T_14) node _r_T_19 = mux(_r_T_17, UInt<3>(0h2), _r_T_15) node _r_T_20 = mux(_r_T_17, UInt<2>(0h0), _r_T_16) node _r_T_21 = eq(_r_T_10, _r_T) node _r_T_22 = mux(_r_T_21, UInt<1>(0h0), _r_T_18) node _r_T_23 = mux(_r_T_21, UInt<3>(0h1), _r_T_19) node _r_T_24 = mux(_r_T_21, UInt<2>(0h0), _r_T_20) node _r_T_25 = eq(_r_T_9, _r_T) node _r_T_26 = mux(_r_T_25, UInt<1>(0h1), _r_T_22) node _r_T_27 = mux(_r_T_25, UInt<3>(0h1), _r_T_23) node _r_T_28 = mux(_r_T_25, UInt<2>(0h0), _r_T_24) node _r_T_29 = eq(_r_T_8, _r_T) node _r_T_30 = mux(_r_T_29, UInt<1>(0h0), _r_T_26) node _r_T_31 = mux(_r_T_29, UInt<3>(0h5), _r_T_27) node _r_T_32 = mux(_r_T_29, UInt<2>(0h0), _r_T_28) node _r_T_33 = eq(_r_T_7, _r_T) node _r_T_34 = mux(_r_T_33, UInt<1>(0h0), _r_T_30) node _r_T_35 = mux(_r_T_33, UInt<3>(0h4), _r_T_31) node _r_T_36 = mux(_r_T_33, UInt<2>(0h1), _r_T_32) node _r_T_37 = eq(_r_T_6, _r_T) node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_34) node _r_T_39 = mux(_r_T_37, UInt<3>(0h0), _r_T_35) node _r_T_40 = mux(_r_T_37, UInt<2>(0h1), _r_T_36) node _r_T_41 = eq(_r_T_5, _r_T) node _r_T_42 = mux(_r_T_41, UInt<1>(0h1), _r_T_38) node _r_T_43 = mux(_r_T_41, UInt<3>(0h0), _r_T_39) node _r_T_44 = mux(_r_T_41, UInt<2>(0h1), _r_T_40) node _r_T_45 = eq(_r_T_4, _r_T) node _r_T_46 = mux(_r_T_45, UInt<1>(0h0), _r_T_42) node _r_T_47 = mux(_r_T_45, UInt<3>(0h5), _r_T_43) node _r_T_48 = mux(_r_T_45, UInt<2>(0h0), _r_T_44) node _r_T_49 = eq(_r_T_3, _r_T) node _r_T_50 = mux(_r_T_49, UInt<1>(0h0), _r_T_46) node _r_T_51 = mux(_r_T_49, UInt<3>(0h4), _r_T_47) node _r_T_52 = mux(_r_T_49, UInt<2>(0h1), _r_T_48) node _r_T_53 = eq(_r_T_2, _r_T) node _r_T_54 = mux(_r_T_53, UInt<1>(0h0), _r_T_50) node _r_T_55 = mux(_r_T_53, UInt<3>(0h3), _r_T_51) node _r_T_56 = mux(_r_T_53, UInt<2>(0h2), _r_T_52) node _r_T_57 = eq(_r_T_1, _r_T) node is_dirty = mux(_r_T_57, UInt<1>(0h1), _r_T_54) node report_param = mux(_r_T_57, UInt<3>(0h3), _r_T_55) node r_3 = mux(_r_T_57, UInt<2>(0h2), _r_T_56) wire new_coh : { state : UInt<2>} connect new_coh.state, r_3 node _io_req_ready_T = eq(state, UInt<4>(0h0)) connect io.req.ready, _io_req_ready_T node _io_rep_valid_T = eq(state, UInt<4>(0h5)) connect io.rep.valid, _io_rep_valid_T wire io_rep_bits_c : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect io_rep_bits_c.opcode, UInt<3>(0h4) connect io_rep_bits_c.param, report_param connect io_rep_bits_c.size, req.size connect io_rep_bits_c.source, req.source connect io_rep_bits_c.address, req.address invalidate io_rep_bits_c.data connect io_rep_bits_c.corrupt, UInt<1>(0h0) connect io.rep.bits, io_rep_bits_c node _T = eq(io.rep.valid, UInt<1>(0h0)) node opdata = bits(io.rep.bits.opcode, 0, 0) node _T_1 = eq(opdata, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it\n at NBDcache.scala:580 assert(!io.rep.valid || !edge.hasData(io.rep.bits),\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_meta_read_valid_T = eq(state, UInt<4>(0h1)) connect io.meta_read.valid, _io_meta_read_valid_T connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag node _io_meta_read_bits_way_en_T = not(UInt<8>(0h0)) connect io.meta_read.bits.way_en, _io_meta_read_bits_way_en_T node _io_meta_write_valid_T = eq(state, UInt<4>(0h8)) connect io.meta_write.valid, _io_meta_write_valid_T connect io.meta_write.bits.way_en, way_en connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.tag, req_tag connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.data.coh, new_coh node _io_wb_req_valid_T = eq(state, UInt<4>(0h6)) connect io.wb_req.valid, _io_wb_req_valid_T connect io.wb_req.bits.source, req.source connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.tag, req_tag connect io.wb_req.bits.param, report_param connect io.wb_req.bits.way_en, way_en connect io.wb_req.bits.voluntary, UInt<1>(0h0) node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect state, UInt<4>(0h1) connect req, io.req.bits node _T_7 = and(io.meta_read.ready, io.meta_read.valid) when _T_7 : connect state, UInt<4>(0h2) node _T_8 = eq(state, UInt<4>(0h2)) when _T_8 : connect state, UInt<4>(0h3) node _T_9 = eq(state, UInt<4>(0h3)) when _T_9 : connect old_coh, io.block_state connect way_en, io.way_en node _state_T = mux(io.mshr_rdy, UInt<4>(0h4), UInt<4>(0h1)) connect state, _state_T node _T_10 = eq(state, UInt<4>(0h4)) when _T_10 : node _state_T_1 = and(tag_matches, is_dirty) node _state_T_2 = mux(_state_T_1, UInt<4>(0h6), UInt<4>(0h5)) connect state, _state_T_2 node _T_11 = eq(state, UInt<4>(0h5)) node _T_12 = and(_T_11, io.rep.ready) when _T_12 : node _state_T_3 = mux(tag_matches, UInt<4>(0h8), UInt<4>(0h0)) connect state, _state_T_3 node _T_13 = and(io.wb_req.ready, io.wb_req.valid) when _T_13 : connect state, UInt<4>(0h7) node _T_14 = eq(state, UInt<4>(0h7)) node _T_15 = and(_T_14, io.wb_req.ready) when _T_15 : connect state, UInt<4>(0h8) node _T_16 = and(io.meta_write.ready, io.meta_write.valid) when _T_16 : connect state, UInt<4>(0h0)

module ProbeUnit( // @[NBDcache.scala:548:7] input clock, // @[NBDcache.scala:548:7] input reset, // @[NBDcache.scala:548:7] output io_req_ready, // @[NBDcache.scala:549:14] input io_req_valid, // @[NBDcache.scala:549:14] input [2:0] io_req_bits_opcode, // @[NBDcache.scala:549:14] input [1:0] io_req_bits_param, // @[NBDcache.scala:549:14] input [3:0] io_req_bits_size, // @[NBDcache.scala:549:14] input [1:0] io_req_bits_source, // @[NBDcache.scala:549:14] input [31:0] io_req_bits_address, // @[NBDcache.scala:549:14] input [7:0] io_req_bits_mask, // @[NBDcache.scala:549:14] input [63:0] io_req_bits_data, // @[NBDcache.scala:549:14] input io_req_bits_corrupt, // @[NBDcache.scala:549:14] input io_rep_ready, // @[NBDcache.scala:549:14] output io_rep_valid, // @[NBDcache.scala:549:14] output [2:0] io_rep_bits_param, // @[NBDcache.scala:549:14] output [3:0] io_rep_bits_size, // @[NBDcache.scala:549:14] output [1:0] io_rep_bits_source, // @[NBDcache.scala:549:14] output [31:0] io_rep_bits_address, // @[NBDcache.scala:549:14] input io_meta_read_ready, // @[NBDcache.scala:549:14] output io_meta_read_valid, // @[NBDcache.scala:549:14] output [5:0] io_meta_read_bits_idx, // @[NBDcache.scala:549:14] output [19:0] io_meta_read_bits_tag, // @[NBDcache.scala:549:14] input io_meta_write_ready, // @[NBDcache.scala:549:14] output io_meta_write_valid, // @[NBDcache.scala:549:14] output [5:0] io_meta_write_bits_idx, // @[NBDcache.scala:549:14] output [7:0] io_meta_write_bits_way_en, // @[NBDcache.scala:549:14] output [19:0] io_meta_write_bits_tag, // @[NBDcache.scala:549:14] output [1:0] io_meta_write_bits_data_coh_state, // @[NBDcache.scala:549:14] output [19:0] io_meta_write_bits_data_tag, // @[NBDcache.scala:549:14] input io_wb_req_ready, // @[NBDcache.scala:549:14] output io_wb_req_valid, // @[NBDcache.scala:549:14] output [19:0] io_wb_req_bits_tag, // @[NBDcache.scala:549:14] output [5:0] io_wb_req_bits_idx, // @[NBDcache.scala:549:14] output [1:0] io_wb_req_bits_source, // @[NBDcache.scala:549:14] output [2:0] io_wb_req_bits_param, // @[NBDcache.scala:549:14] output [7:0] io_wb_req_bits_way_en, // @[NBDcache.scala:549:14] input [7:0] io_way_en, // @[NBDcache.scala:549:14] input io_mshr_rdy, // @[NBDcache.scala:549:14] input [1:0] io_block_state_state // @[NBDcache.scala:549:14] ); wire io_req_valid_0 = io_req_valid; // @[NBDcache.scala:548:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[NBDcache.scala:548:7] wire [1:0] io_req_bits_param_0 = io_req_bits_param; // @[NBDcache.scala:548:7] wire [3:0] io_req_bits_size_0 = io_req_bits_size; // @[NBDcache.scala:548:7] wire [1:0] io_req_bits_source_0 = io_req_bits_source; // @[NBDcache.scala:548:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[NBDcache.scala:548:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[NBDcache.scala:548:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[NBDcache.scala:548:7] wire io_req_bits_corrupt_0 = io_req_bits_corrupt; // @[NBDcache.scala:548:7] wire io_rep_ready_0 = io_rep_ready; // @[NBDcache.scala:548:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[NBDcache.scala:548:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[NBDcache.scala:548:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[NBDcache.scala:548:7] wire [7:0] io_way_en_0 = io_way_en; // @[NBDcache.scala:548:7] wire io_mshr_rdy_0 = io_mshr_rdy; // @[NBDcache.scala:548:7] wire [1:0] io_block_state_state_0 = io_block_state_state; // @[NBDcache.scala:548:7] wire [3:0] _r_T_1 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_2 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_3 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_4 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_5 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_6 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_7 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_8 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_9 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_10 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_11 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_12 = 4'h8; // @[Metadata.scala:133:10] wire [1:0] miss_coh_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_16 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_20 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_24 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_28 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_32 = 2'h0; // @[Misc.scala:38:63] wire [7:0] io_meta_read_bits_way_en = 8'hFF; // @[NBDcache.scala:548:7] wire [7:0] _io_meta_read_bits_way_en_T = 8'hFF; // @[NBDcache.scala:586:31] wire io_rep_bits_corrupt = 1'h0; // @[NBDcache.scala:548:7] wire io_wb_req_bits_voluntary = 1'h0; // @[NBDcache.scala:548:7] wire _r_T_14 = 1'h0; // @[Misc.scala:38:9] wire _r_T_18 = 1'h0; // @[Misc.scala:38:9] wire _r_T_22 = 1'h0; // @[Misc.scala:38:9] wire io_rep_bits_c_corrupt = 1'h0; // @[Edges.scala:416:17] wire opdata = 1'h0; // @[Edges.scala:102:36] wire [63:0] io_rep_bits_data = 64'h0; // @[NBDcache.scala:548:7] wire [63:0] io_rep_bits_c_data = 64'h0; // @[Edges.scala:416:17] wire [2:0] io_rep_bits_opcode = 3'h4; // @[NBDcache.scala:548:7] wire _io_req_ready_T; // @[NBDcache.scala:576:25] wire [2:0] io_rep_bits_c_opcode = 3'h4; // @[Edges.scala:416:17] wire _io_rep_valid_T; // @[NBDcache.scala:577:25] wire [2:0] io_rep_bits_c_param; // @[Edges.scala:416:17] wire [3:0] io_rep_bits_c_size; // @[Edges.scala:416:17] wire [1:0] io_rep_bits_c_source; // @[Edges.scala:416:17] wire [31:0] io_rep_bits_c_address; // @[Edges.scala:416:17] wire _io_meta_read_valid_T; // @[NBDcache.scala:583:31] wire [5:0] req_idx; // @[NBDcache.scala:566:28] wire [19:0] req_tag; // @[NBDcache.scala:567:29] wire _io_meta_write_valid_T; // @[NBDcache.scala:588:32] wire [1:0] new_coh_state; // @[Metadata.scala:160:20] wire _io_wb_req_valid_T; // @[NBDcache.scala:595:28] wire [2:0] report_param; // @[Misc.scala:38:36] wire io_req_ready_0; // @[NBDcache.scala:548:7] wire [2:0] io_rep_bits_param_0; // @[NBDcache.scala:548:7] wire [3:0] io_rep_bits_size_0; // @[NBDcache.scala:548:7] wire [1:0] io_rep_bits_source_0; // @[NBDcache.scala:548:7] wire [31:0] io_rep_bits_address_0; // @[NBDcache.scala:548:7] wire io_rep_valid_0; // @[NBDcache.scala:548:7] wire [5:0] io_meta_read_bits_idx_0; // @[NBDcache.scala:548:7] wire [19:0] io_meta_read_bits_tag_0; // @[NBDcache.scala:548:7] wire io_meta_read_valid_0; // @[NBDcache.scala:548:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:548:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[NBDcache.scala:548:7] wire [5:0] io_meta_write_bits_idx_0; // @[NBDcache.scala:548:7] wire [7:0] io_meta_write_bits_way_en_0; // @[NBDcache.scala:548:7] wire [19:0] io_meta_write_bits_tag_0; // @[NBDcache.scala:548:7] wire io_meta_write_valid_0; // @[NBDcache.scala:548:7] wire [19:0] io_wb_req_bits_tag_0; // @[NBDcache.scala:548:7] wire [5:0] io_wb_req_bits_idx_0; // @[NBDcache.scala:548:7] wire [1:0] io_wb_req_bits_source_0; // @[NBDcache.scala:548:7] wire [2:0] io_wb_req_bits_param_0; // @[NBDcache.scala:548:7] wire [7:0] io_wb_req_bits_way_en_0; // @[NBDcache.scala:548:7] wire io_wb_req_valid_0; // @[NBDcache.scala:548:7] reg [3:0] state; // @[NBDcache.scala:563:22] reg [2:0] req_opcode; // @[NBDcache.scala:565:16] reg [1:0] req_param; // @[NBDcache.scala:565:16] reg [3:0] req_size; // @[NBDcache.scala:565:16] assign io_rep_bits_c_size = req_size; // @[Edges.scala:416:17] reg [1:0] req_source; // @[NBDcache.scala:565:16] assign io_wb_req_bits_source_0 = req_source; // @[NBDcache.scala:548:7, :565:16] assign io_rep_bits_c_source = req_source; // @[Edges.scala:416:17] reg [31:0] req_address; // @[NBDcache.scala:565:16] assign io_rep_bits_c_address = req_address; // @[Edges.scala:416:17] reg [7:0] req_mask; // @[NBDcache.scala:565:16] reg [63:0] req_data; // @[NBDcache.scala:565:16] reg req_corrupt; // @[NBDcache.scala:565:16] assign req_idx = req_address[11:6]; // @[NBDcache.scala:565:16, :566:28] assign io_meta_read_bits_idx_0 = req_idx; // @[NBDcache.scala:548:7, :566:28] assign io_meta_write_bits_idx_0 = req_idx; // @[NBDcache.scala:548:7, :566:28] assign io_wb_req_bits_idx_0 = req_idx; // @[NBDcache.scala:548:7, :566:28] assign req_tag = req_address[31:12]; // @[NBDcache.scala:565:16, :567:29] assign io_meta_read_bits_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] assign io_meta_write_bits_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] assign io_meta_write_bits_data_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] assign io_wb_req_bits_tag_0 = req_tag; // @[NBDcache.scala:548:7, :567:29] reg [7:0] way_en; // @[NBDcache.scala:569:19] assign io_meta_write_bits_way_en_0 = way_en; // @[NBDcache.scala:548:7, :569:19] assign io_wb_req_bits_way_en_0 = way_en; // @[NBDcache.scala:548:7, :569:19] wire tag_matches = |way_en; // @[NBDcache.scala:569:19, :570:28] reg [1:0] old_coh_state; // @[NBDcache.scala:571:20] wire [1:0] reply_coh_state = tag_matches ? old_coh_state : 2'h0; // @[NBDcache.scala:570:28, :571:20, :573:22] wire [3:0] _r_T = {req_param, reply_coh_state}; // @[Metadata.scala:120:19] wire _r_T_13 = _r_T == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_15 = _r_T_13 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_17 = _r_T == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_19 = _r_T_17 ? 3'h2 : _r_T_15; // @[Misc.scala:38:36, :56:20] wire _r_T_21 = _r_T == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_23 = _r_T_21 ? 3'h1 : _r_T_19; // @[Misc.scala:38:36, :56:20] wire _r_T_25 = _r_T == 4'hB; // @[Misc.scala:56:20] wire _r_T_26 = _r_T_25; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_27 = _r_T_25 ? 3'h1 : _r_T_23; // @[Misc.scala:38:36, :56:20] wire _r_T_29 = _r_T == 4'h4; // @[Misc.scala:56:20] wire _r_T_30 = ~_r_T_29 & _r_T_26; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_31 = _r_T_29 ? 3'h5 : _r_T_27; // @[Misc.scala:38:36, :56:20] wire _r_T_33 = _r_T == 4'h5; // @[Misc.scala:56:20] wire _r_T_34 = ~_r_T_33 & _r_T_30; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_35 = _r_T_33 ? 3'h4 : _r_T_31; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_36 = {1'h0, _r_T_33}; // @[Misc.scala:38:63, :56:20] wire _r_T_37 = _r_T == 4'h6; // @[Misc.scala:56:20] wire _r_T_38 = ~_r_T_37 & _r_T_34; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_39 = _r_T_37 ? 3'h0 : _r_T_35; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_40 = _r_T_37 ? 2'h1 : _r_T_36; // @[Misc.scala:38:63, :56:20] wire _r_T_41 = _r_T == 4'h7; // @[Misc.scala:56:20] wire _r_T_42 = _r_T_41 | _r_T_38; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_43 = _r_T_41 ? 3'h0 : _r_T_39; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_44 = _r_T_41 ? 2'h1 : _r_T_40; // @[Misc.scala:38:63, :56:20] wire _r_T_45 = _r_T == 4'h0; // @[Misc.scala:56:20] wire _r_T_46 = ~_r_T_45 & _r_T_42; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_47 = _r_T_45 ? 3'h5 : _r_T_43; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_48 = _r_T_45 ? 2'h0 : _r_T_44; // @[Misc.scala:38:63, :56:20] wire _r_T_49 = _r_T == 4'h1; // @[Misc.scala:56:20] wire _r_T_50 = ~_r_T_49 & _r_T_46; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_51 = _r_T_49 ? 3'h4 : _r_T_47; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_52 = _r_T_49 ? 2'h1 : _r_T_48; // @[Misc.scala:38:63, :56:20] wire _r_T_53 = _r_T == 4'h2; // @[Misc.scala:56:20] wire _r_T_54 = ~_r_T_53 & _r_T_50; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_55 = _r_T_53 ? 3'h3 : _r_T_51; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_56 = _r_T_53 ? 2'h2 : _r_T_52; // @[Misc.scala:38:63, :56:20] wire _r_T_57 = _r_T == 4'h3; // @[Misc.scala:56:20] wire is_dirty = _r_T_57 | _r_T_54; // @[Misc.scala:38:9, :56:20] assign report_param = _r_T_57 ? 3'h3 : _r_T_55; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = report_param; // @[Misc.scala:38:36] assign io_rep_bits_c_param = report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_57 ? 2'h2 : _r_T_56; // @[Misc.scala:38:63, :56:20] assign new_coh_state = r_3; // @[Misc.scala:38:63] assign io_meta_write_bits_data_coh_state_0 = new_coh_state; // @[Metadata.scala:160:20] assign _io_req_ready_T = state == 4'h0; // @[NBDcache.scala:563:22, :576:25] assign io_req_ready_0 = _io_req_ready_T; // @[NBDcache.scala:548:7, :576:25] assign _io_rep_valid_T = state == 4'h5; // @[NBDcache.scala:563:22, :577:25] assign io_rep_valid_0 = _io_rep_valid_T; // @[NBDcache.scala:548:7, :577:25] assign io_rep_bits_param_0 = io_rep_bits_c_param; // @[Edges.scala:416:17] assign io_rep_bits_size_0 = io_rep_bits_c_size; // @[Edges.scala:416:17] assign io_rep_bits_source_0 = io_rep_bits_c_source; // @[Edges.scala:416:17] assign io_rep_bits_address_0 = io_rep_bits_c_address; // @[Edges.scala:416:17] assign _io_meta_read_valid_T = state == 4'h1; // @[NBDcache.scala:563:22, :583:31] assign io_meta_read_valid_0 = _io_meta_read_valid_T; // @[NBDcache.scala:548:7, :583:31] assign _io_meta_write_valid_T = state == 4'h8; // @[NBDcache.scala:563:22, :588:32] assign io_meta_write_valid_0 = _io_meta_write_valid_T; // @[NBDcache.scala:548:7, :588:32] assign _io_wb_req_valid_T = state == 4'h6; // @[NBDcache.scala:563:22, :595:28] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[NBDcache.scala:548:7, :595:28] wire [3:0] _state_T = io_mshr_rdy_0 ? 4'h4 : 4'h1; // @[NBDcache.scala:548:7, :623:17] wire _state_T_1 = tag_matches & is_dirty; // @[Misc.scala:38:9] wire [3:0] _state_T_2 = _state_T_1 ? 4'h6 : 4'h5; // @[NBDcache.scala:627:{17,30}] wire [3:0] _state_T_3 = {tag_matches, 3'h0}; // @[NBDcache.scala:570:28, :631:17] wire _T_6 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _T_9 = state == 4'h3; // @[NBDcache.scala:563:22, :619:15] always @(posedge clock) begin // @[NBDcache.scala:548:7] if (reset) // @[NBDcache.scala:548:7] state <= 4'h0; // @[NBDcache.scala:563:22] else if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] state <= 4'h0; // @[NBDcache.scala:563:22] else if (state == 4'h7 & io_wb_req_ready_0) // @[NBDcache.scala:548:7, :563:22, :640:{15,36}] state <= 4'h8; // @[NBDcache.scala:563:22] else if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h7; // @[NBDcache.scala:563:22] else if (_io_rep_valid_T & io_rep_ready_0) // @[NBDcache.scala:548:7, :577:25, :630:29] state <= _state_T_3; // @[NBDcache.scala:563:22, :631:17] else if (state == 4'h4) // @[NBDcache.scala:563:22, :626:15] state <= _state_T_2; // @[NBDcache.scala:563:22, :627:17] else if (_T_9) // @[NBDcache.scala:619:15] state <= _state_T; // @[NBDcache.scala:563:22, :623:17] else if (state == 4'h2) // @[NBDcache.scala:563:22, :615:15] state <= 4'h3; // @[NBDcache.scala:563:22] else if (io_meta_read_ready_0 & io_meta_read_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[NBDcache.scala:563:22] else if (_T_6) // @[Decoupled.scala:51:35] state <= 4'h1; // @[NBDcache.scala:563:22] if (_T_6) begin // @[Decoupled.scala:51:35] req_opcode <= io_req_bits_opcode_0; // @[NBDcache.scala:548:7, :565:16] req_param <= io_req_bits_param_0; // @[NBDcache.scala:548:7, :565:16] req_size <= io_req_bits_size_0; // @[NBDcache.scala:548:7, :565:16] req_source <= io_req_bits_source_0; // @[NBDcache.scala:548:7, :565:16] req_address <= io_req_bits_address_0; // @[NBDcache.scala:548:7, :565:16] req_mask <= io_req_bits_mask_0; // @[NBDcache.scala:548:7, :565:16] req_data <= io_req_bits_data_0; // @[NBDcache.scala:548:7, :565:16] req_corrupt <= io_req_bits_corrupt_0; // @[NBDcache.scala:548:7, :565:16] end if (_T_9) begin // @[NBDcache.scala:619:15] way_en <= io_way_en_0; // @[NBDcache.scala:548:7, :569:19] old_coh_state <= io_block_state_state_0; // @[NBDcache.scala:548:7, :571:20] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[NBDcache.scala:548:7] assign io_rep_valid = io_rep_valid_0; // @[NBDcache.scala:548:7] assign io_rep_bits_param = io_rep_bits_param_0; // @[NBDcache.scala:548:7] assign io_rep_bits_size = io_rep_bits_size_0; // @[NBDcache.scala:548:7] assign io_rep_bits_source = io_rep_bits_source_0; // @[NBDcache.scala:548:7] assign io_rep_bits_address = io_rep_bits_address_0; // @[NBDcache.scala:548:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[NBDcache.scala:548:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[NBDcache.scala:548:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[NBDcache.scala:548:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:548:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[NBDcache.scala:548:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_source = io_wb_req_bits_source_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[NBDcache.scala:548:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[NBDcache.scala:548:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AccPipe_8 : input clock : Clock input reset : Reset output io : { flip op1 : SInt<32>, flip op2 : SInt<32>, sum : SInt<32>} node _io_sum_T = add(io.op1, io.op2) node _io_sum_T_1 = tail(_io_sum_T, 1) node _io_sum_T_2 = asSInt(_io_sum_T_1) reg io_sum_r : SInt<32>, clock when UInt<1>(0h1) : connect io_sum_r, _io_sum_T_2 connect io.sum, io_sum_r

module AccPipe_8( // @[AccumulatorMem.scala:63:7] input clock, // @[AccumulatorMem.scala:63:7] input reset, // @[AccumulatorMem.scala:63:7] input [31:0] io_op1, // @[AccumulatorMem.scala:64:14] input [31:0] io_op2, // @[AccumulatorMem.scala:64:14] output [31:0] io_sum // @[AccumulatorMem.scala:64:14] ); wire [31:0] io_op1_0 = io_op1; // @[AccumulatorMem.scala:63:7] wire [31:0] io_op2_0 = io_op2; // @[AccumulatorMem.scala:63:7] wire [31:0] io_sum_0; // @[AccumulatorMem.scala:63:7] wire [32:0] _io_sum_T = {io_op1_0[31], io_op1_0} + {io_op2_0[31], io_op2_0}; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_1 = _io_sum_T[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_2 = _io_sum_T_1; // @[Arithmetic.scala:94:38] reg [31:0] io_sum_r; // @[AccumulatorMem.scala:70:26] assign io_sum_0 = io_sum_r; // @[AccumulatorMem.scala:63:7, :70:26] always @(posedge clock) // @[AccumulatorMem.scala:63:7] io_sum_r <= _io_sum_T_2; // @[Arithmetic.scala:94:38] assign io_sum = io_sum_0; // @[AccumulatorMem.scala:63:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Router_40 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_86 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_87 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_88 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_2 of InputUnit_86 connect input_unit_0_from_2.clock, clock connect input_unit_0_from_2.reset, reset inst input_unit_1_from_10 of InputUnit_87 connect input_unit_1_from_10.clock, clock connect input_unit_1_from_10.reset, reset inst input_unit_2_from_12 of InputUnit_88 connect input_unit_2_from_12.clock, clock connect input_unit_2_from_12.reset, reset inst output_unit_0_to_2 of OutputUnit_86 connect output_unit_0_to_2.clock, clock connect output_unit_0_to_2.reset, reset inst output_unit_1_to_10 of OutputUnit_87 connect output_unit_1_to_10.clock, clock connect output_unit_1_to_10.reset, reset inst output_unit_2_to_12 of OutputUnit_88 connect output_unit_2_to_12.clock, clock connect output_unit_2_to_12.reset, reset inst switch of Switch_40 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_40 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_40 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_40 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_6 connect input_unit_0_from_2.io.in, destNodesIn connect input_unit_1_from_10.io.in, destNodesIn_1 connect input_unit_2_from_12.io.in, destNodesIn_2 connect output_unit_0_to_2.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_2.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_2.io.out.flit connect output_unit_1_to_10.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_10.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_10.io.out.flit connect output_unit_2_to_12.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_12.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_12.io.out.flit connect route_computer.io.req.`0`, input_unit_0_from_2.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_10.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_12.io.router_req connect input_unit_0_from_2.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_10.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_12.io.router_resp, route_computer.io.resp.`2` connect vc_allocator.io.req.`0`, input_unit_0_from_2.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_10.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_12.io.vcalloc_req connect input_unit_0_from_2.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_10.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_12.io.vcalloc_resp, vc_allocator.io.resp.`2` connect output_unit_0_to_2.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_10.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_12.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_2.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_2.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_2.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_2.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_2.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_2.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_2.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_2.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_2.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_2.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_2.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_2.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_2.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_2.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_2.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_2.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_2.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_2.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_2.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_2.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_2.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_2.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_2.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_2.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_2.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_2.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_10.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_10.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_10.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_10.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_10.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_10.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_10.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_10.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_10.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_10.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_10.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_10.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_10.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_10.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_10.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_10.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_10.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_10.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_10.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_10.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_10.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_10.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_10.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_10.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_10.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_10.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_12.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_12.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_12.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_12.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_12.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_12.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_12.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_12.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_12.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_12.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_12.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_12.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_12.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_12.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_12.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_12.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_12.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_12.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_12.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_12.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_12.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_12.io.channel_status[4].occupied connect input_unit_0_from_2.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`0`[3], output_unit_0_to_2.io.credit_available[3] connect input_unit_0_from_2.io.out_credit_available.`0`[4], output_unit_0_to_2.io.credit_available[4] connect input_unit_0_from_2.io.out_credit_available.`1`[0], output_unit_1_to_10.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`1`[1], output_unit_1_to_10.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`1`[2], output_unit_1_to_10.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`1`[3], output_unit_1_to_10.io.credit_available[3] connect input_unit_0_from_2.io.out_credit_available.`1`[4], output_unit_1_to_10.io.credit_available[4] connect input_unit_0_from_2.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_0_from_2.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_0_from_2.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_0_from_2.io.out_credit_available.`2`[3], output_unit_2_to_12.io.credit_available[3] connect input_unit_0_from_2.io.out_credit_available.`2`[4], output_unit_2_to_12.io.credit_available[4] connect input_unit_1_from_10.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_1_from_10.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_1_from_10.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_1_from_10.io.out_credit_available.`0`[3], output_unit_0_to_2.io.credit_available[3] connect input_unit_1_from_10.io.out_credit_available.`0`[4], output_unit_0_to_2.io.credit_available[4] connect input_unit_1_from_10.io.out_credit_available.`1`[0], output_unit_1_to_10.io.credit_available[0] connect input_unit_1_from_10.io.out_credit_available.`1`[1], output_unit_1_to_10.io.credit_available[1] connect input_unit_1_from_10.io.out_credit_available.`1`[2], output_unit_1_to_10.io.credit_available[2] connect input_unit_1_from_10.io.out_credit_available.`1`[3], output_unit_1_to_10.io.credit_available[3] connect input_unit_1_from_10.io.out_credit_available.`1`[4], output_unit_1_to_10.io.credit_available[4] connect input_unit_1_from_10.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_1_from_10.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_1_from_10.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_1_from_10.io.out_credit_available.`2`[3], output_unit_2_to_12.io.credit_available[3] connect input_unit_1_from_10.io.out_credit_available.`2`[4], output_unit_2_to_12.io.credit_available[4] connect input_unit_2_from_12.io.out_credit_available.`0`[0], output_unit_0_to_2.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`0`[1], output_unit_0_to_2.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`0`[2], output_unit_0_to_2.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`0`[3], output_unit_0_to_2.io.credit_available[3] connect input_unit_2_from_12.io.out_credit_available.`0`[4], output_unit_0_to_2.io.credit_available[4] connect input_unit_2_from_12.io.out_credit_available.`1`[0], output_unit_1_to_10.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`1`[1], output_unit_1_to_10.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`1`[2], output_unit_1_to_10.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`1`[3], output_unit_1_to_10.io.credit_available[3] connect input_unit_2_from_12.io.out_credit_available.`1`[4], output_unit_1_to_10.io.credit_available[4] connect input_unit_2_from_12.io.out_credit_available.`2`[0], output_unit_2_to_12.io.credit_available[0] connect input_unit_2_from_12.io.out_credit_available.`2`[1], output_unit_2_to_12.io.credit_available[1] connect input_unit_2_from_12.io.out_credit_available.`2`[2], output_unit_2_to_12.io.credit_available[2] connect input_unit_2_from_12.io.out_credit_available.`2`[3], output_unit_2_to_12.io.credit_available[3] connect input_unit_2_from_12.io.out_credit_available.`2`[4], output_unit_2_to_12.io.credit_available[4] connect switch_allocator.io.req.`0`[0], input_unit_0_from_2.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_10.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_12.io.salloc_req[0] connect output_unit_0_to_2.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_2.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_2.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_2.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_2.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_2.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_2.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_2.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_2.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_2.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_1_to_10.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_10.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_10.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_10.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_10.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_10.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_1_to_10.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail connect output_unit_1_to_10.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc connect output_unit_1_to_10.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail connect output_unit_1_to_10.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc connect output_unit_2_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect output_unit_2_to_12.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail connect output_unit_2_to_12.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc connect output_unit_2_to_12.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail connect output_unit_2_to_12.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc connect switch.io.in.`0`[0], input_unit_0_from_2.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_10.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_12.io.out[0] connect output_unit_0_to_2.io.in, switch.io.out.`0` connect output_unit_1_to_10.io.in, switch.io.out.`1` connect output_unit_2_to_12.io.in, switch.io.out.`2` reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect input_unit_0_from_2.io.block, UInt<1>(0h0) connect input_unit_1_from_10.io.block, UInt<1>(0h0) connect input_unit_2_from_12.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_2.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_10.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_12.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_2.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_10.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_12.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_88 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 2 11 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 10 11 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 12 11 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid

module Router_40( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_12_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_12_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_channel_status_4_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_2_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_2_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_2_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_10_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_12_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_127 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_127( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module PE_198 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_198( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_157 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_171 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_157( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_171 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_9 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_18 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_9 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h13), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h3) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h7), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h4), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h3)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_18 = eq(UInt<4>(0h8), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(UInt<4>(0h9), io.in.bits.egress_id) when _T_19 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_21 = and(route_q.io.enq.valid, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_22, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_19 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_9 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_27 = and(vcalloc_q.io.enq.valid, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_14, _out_bundle_bits_out_virt_channel_T_13) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_15 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_9( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hA; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_1, {3{_route_buffer_io_enq_bits_flow_egress_node_id_T}} | {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, 2'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0)}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h3; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h3; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_179 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_323 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_179( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_323 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_118 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_118( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_228 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_228( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_33 : output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync

module IntSyncSyncCrossingSink_n1x1_33( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN : output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} node rawA_exp = bits(io.a, 63, 52) node _rawA_isZero_T = bits(rawA_exp, 11, 9) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 11, 10) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 9, 9) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 64, 64) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 63, 52) node _rawB_isZero_T = bits(rawB_exp, 11, 9) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 11, 10) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 9, 9) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 64, 64) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0)) node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0)) node ordered = and(_ordered_T, _ordered_T_1) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) node _common_ltMags_T = lt(rawA.sExp, rawB.sExp) node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig) node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1) node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2) node _common_eqMags_T = eq(rawA.sig, rawB.sig) node common_eqMags = and(eqExps, _common_eqMags_T) node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0)) node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1) node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0)) node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0)) node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4) node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0)) node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6) node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags) node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9) node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10) node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11) node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12) node _ordered_eq_T = eq(rawA.sign, rawB.sign) node _ordered_eq_T_1 = or(bothInfs, common_eqMags) node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1) node ordered_eq = or(bothZeros, _ordered_eq_T_2) node _invalid_T = bits(rawA.sig, 51, 51) node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0)) node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1) node _invalid_T_3 = bits(rawB.sig, 51, 51) node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0)) node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4) node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5) node _invalid_T_7 = eq(ordered, UInt<1>(0h0)) node _invalid_T_8 = and(io.signaling, _invalid_T_7) node invalid = or(_invalid_T_6, _invalid_T_8) node _io_lt_T = and(ordered, ordered_lt) connect io.lt, _io_lt_T node _io_eq_T = and(ordered, ordered_eq) connect io.eq, _io_eq_T node _io_gt_T = eq(ordered_lt, UInt<1>(0h0)) node _io_gt_T_1 = and(ordered, _io_gt_T) node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0)) node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2) connect io.gt, _io_gt_T_3 node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T

module CompareRecFN( // @[CompareRecFN.scala:42:7] input [64:0] io_a, // @[CompareRecFN.scala:44:16] input [64:0] io_b, // @[CompareRecFN.scala:44:16] input io_signaling, // @[CompareRecFN.scala:44:16] output io_lt, // @[CompareRecFN.scala:44:16] output io_eq, // @[CompareRecFN.scala:44:16] output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16] ); wire rawA_isNaN = (&(io_a[63:62])) & io_a[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] wire rawB_isNaN = (&(io_b[63:62])) & io_b[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] wire ordered = ~rawA_isNaN & ~rawB_isNaN; // @[rawFloatFromRecFN.scala:56:33] wire bothInfs = (&(io_a[63:62])) & ~(io_a[61]) & (&(io_b[63:62])) & ~(io_b[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}] wire bothZeros = ~(|(io_a[63:61])) & ~(|(io_b[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}] wire eqExps = io_a[63:52] == io_b[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [52:0] _GEN = {|(io_a[63:61]), io_a[51:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}] wire [52:0] _GEN_0 = {|(io_b[63:61]), io_b[51:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}] wire common_ltMags = $signed({1'h0, io_a[63:52]}) < $signed({1'h0, io_b[63:52]}) | eqExps & _GEN < _GEN_0; // @[rawFloatFromRecFN.scala:51:21, :60:27, :61:44] wire common_eqMags = eqExps & _GEN == _GEN_0; // @[rawFloatFromRecFN.scala:61:44] assign io_lt = ordered & ~bothZeros & (io_a[64] & ~(io_b[64]) | ~bothInfs & (io_a[64] & ~common_ltMags & ~common_eqMags | ~(io_b[64]) & common_ltMags)); // @[rawFloatFromRecFN.scala:57:33, :59:25] assign io_eq = ordered & (bothZeros | io_a[64] == io_b[64] & (bothInfs | common_eqMags)); // @[rawFloatFromRecFN.scala:57:33, :59:25] assign io_exceptionFlags = {rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | io_signaling & ~ordered, 4'h0}; // @[rawFloatFromRecFN.scala:56:33] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_458 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_458( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_161 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_176 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_161( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_176 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = and(_T_11, _T_24) node _T_94 = and(_T_93, _T_37) node _T_95 = and(_T_94, _T_50) node _T_96 = and(_T_95, _T_63) node _T_97 = and(_T_96, _T_76) node _T_98 = and(_T_97, _T_84) node _T_99 = and(_T_98, _T_92) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_99, UInt<1>(0h1), "") : assert_1 node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_103 : node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_108 = shr(io.in.a.bits.source, 2) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = leq(UInt<1>(0h0), uncommonBits_5) node _T_111 = and(_T_109, _T_110) node _T_112 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_113 = and(_T_111, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_114 = shr(io.in.a.bits.source, 2) node _T_115 = eq(_T_114, UInt<1>(0h1)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_119 = and(_T_117, _T_118) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_120 = shr(io.in.a.bits.source, 2) node _T_121 = eq(_T_120, UInt<2>(0h2)) node _T_122 = leq(UInt<1>(0h0), uncommonBits_7) node _T_123 = and(_T_121, _T_122) node _T_124 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_125 = and(_T_123, _T_124) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<2>(0h3)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_8) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_132 = shr(io.in.a.bits.source, 3) node _T_133 = eq(_T_132, UInt<3>(0h4)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_9) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_140 = or(_T_107, _T_113) node _T_141 = or(_T_140, _T_119) node _T_142 = or(_T_141, _T_125) node _T_143 = or(_T_142, _T_131) node _T_144 = or(_T_143, _T_137) node _T_145 = or(_T_144, _T_138) node _T_146 = or(_T_145, _T_139) node _T_147 = and(_T_106, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_150 = or(UInt<1>(0h0), _T_149) node _T_151 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h101c0))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<29>(0h100001c0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = and(_T_150, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = and(_T_148, _T_163) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_164, UInt<1>(0h1), "") : assert_2 node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_10) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<1>(0h1)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_11) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h2)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_12) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_187 = shr(io.in.a.bits.source, 2) node _T_188 = eq(_T_187, UInt<2>(0h3)) node _T_189 = leq(UInt<1>(0h0), uncommonBits_13) node _T_190 = and(_T_188, _T_189) node _T_191 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_192 = and(_T_190, _T_191) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_193 = shr(io.in.a.bits.source, 3) node _T_194 = eq(_T_193, UInt<3>(0h4)) node _T_195 = leq(UInt<1>(0h0), uncommonBits_14) node _T_196 = and(_T_194, _T_195) node _T_197 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_168 connect _WIRE[1], _T_174 connect _WIRE[2], _T_180 connect _WIRE[3], _T_186 connect _WIRE[4], _T_192 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 node _T_201 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_202 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_204 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[6], _T_201, UInt<1>(0h0)) node _T_209 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = or(_T_202, _T_203) node _T_211 = or(_T_210, _T_204) node _T_212 = or(_T_211, _T_205) node _T_213 = or(_T_212, _T_206) node _T_214 = or(_T_213, _T_207) node _T_215 = or(_T_214, _T_208) node _T_216 = or(_T_215, _T_209) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_216 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<17>(0h101c0))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<29>(0h100001c0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = and(_T_220, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_15) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_16) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_17) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_18) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_290 = shr(io.in.a.bits.source, 3) node _T_291 = eq(_T_290, UInt<3>(0h4)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_19) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_298 = or(_T_265, _T_271) node _T_299 = or(_T_298, _T_277) node _T_300 = or(_T_299, _T_283) node _T_301 = or(_T_300, _T_289) node _T_302 = or(_T_301, _T_295) node _T_303 = or(_T_302, _T_296) node _T_304 = or(_T_303, _T_297) node _T_305 = and(_T_264, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h101c0))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<29>(0h100001c0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = and(_T_308, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = and(_T_306, _T_321) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_322, UInt<1>(0h1), "") : assert_10 node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_327 = shr(io.in.a.bits.source, 2) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_20) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_333 = shr(io.in.a.bits.source, 2) node _T_334 = eq(_T_333, UInt<1>(0h1)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_21) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_338 = and(_T_336, _T_337) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<2>(0h2)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_22) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<2>(0h3)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_23) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_351 = shr(io.in.a.bits.source, 3) node _T_352 = eq(_T_351, UInt<3>(0h4)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_24) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_326 connect _WIRE_2[1], _T_332 connect _WIRE_2[2], _T_338 connect _WIRE_2[3], _T_344 connect _WIRE_2[4], _T_350 connect _WIRE_2[5], _T_356 connect _WIRE_2[6], _T_357 connect _WIRE_2[7], _T_358 node _T_359 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_360 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = mux(_WIRE_2[6], _T_359, UInt<1>(0h0)) node _T_367 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = or(_T_360, _T_361) node _T_369 = or(_T_368, _T_362) node _T_370 = or(_T_369, _T_363) node _T_371 = or(_T_370, _T_364) node _T_372 = or(_T_371, _T_365) node _T_373 = or(_T_372, _T_366) node _T_374 = or(_T_373, _T_367) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_374 node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h101c0))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<29>(0h100001c0))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = or(_T_383, _T_388) node _T_390 = and(_T_378, _T_389) node _T_391 = or(UInt<1>(0h0), _T_390) node _T_392 = and(_WIRE_3, _T_391) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_392, UInt<1>(0h1), "") : assert_11 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(source_ok, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_399 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_399, UInt<1>(0h1), "") : assert_13 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(is_aligned, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_406 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_406, UInt<1>(0h1), "") : assert_15 node _T_410 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_410, UInt<1>(0h1), "") : assert_16 node _T_414 = not(io.in.a.bits.mask) node _T_415 = eq(_T_414, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_415, UInt<1>(0h1), "") : assert_17 node _T_419 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_419, UInt<1>(0h1), "") : assert_18 node _T_423 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_423 : node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_428 = shr(io.in.a.bits.source, 2) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_25) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_433 = and(_T_431, _T_432) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_434 = shr(io.in.a.bits.source, 2) node _T_435 = eq(_T_434, UInt<1>(0h1)) node _T_436 = leq(UInt<1>(0h0), uncommonBits_26) node _T_437 = and(_T_435, _T_436) node _T_438 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_439 = and(_T_437, _T_438) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<2>(0h2)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_27) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<2>(0h3)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_28) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_452 = shr(io.in.a.bits.source, 3) node _T_453 = eq(_T_452, UInt<3>(0h4)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_29) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_460 = or(_T_427, _T_433) node _T_461 = or(_T_460, _T_439) node _T_462 = or(_T_461, _T_445) node _T_463 = or(_T_462, _T_451) node _T_464 = or(_T_463, _T_457) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = and(_T_426, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_468, UInt<1>(0h1), "") : assert_19 node _T_472 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_473 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_474 = and(_T_472, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<17>(0h101c0))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_482 = cvt(_T_481) node _T_483 = and(_T_482, asSInt(UInt<29>(0h100001c0))) node _T_484 = asSInt(_T_483) node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0))) node _T_486 = or(_T_480, _T_485) node _T_487 = and(_T_475, _T_486) node _T_488 = or(UInt<1>(0h0), _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_488, UInt<1>(0h1), "") : assert_20 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(source_ok, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_498 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_498, UInt<1>(0h1), "") : assert_23 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_502, UInt<1>(0h1), "") : assert_24 node _T_506 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_T_506, UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_506, UInt<1>(0h1), "") : assert_25 node _T_510 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_510 : node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_512 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_30) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<1>(0h1)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_31) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h2)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_32) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_533 = shr(io.in.a.bits.source, 2) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_33) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<3>(0h4)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_34) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_547 = or(_T_514, _T_520) node _T_548 = or(_T_547, _T_526) node _T_549 = or(_T_548, _T_532) node _T_550 = or(_T_549, _T_538) node _T_551 = or(_T_550, _T_544) node _T_552 = or(_T_551, _T_545) node _T_553 = or(_T_552, _T_546) node _T_554 = and(_T_513, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_557 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_561 = cvt(_T_560) node _T_562 = and(_T_561, asSInt(UInt<17>(0h101c0))) node _T_563 = asSInt(_T_562) node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0))) node _T_565 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_566 = cvt(_T_565) node _T_567 = and(_T_566, asSInt(UInt<29>(0h100001c0))) node _T_568 = asSInt(_T_567) node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0))) node _T_570 = or(_T_564, _T_569) node _T_571 = and(_T_559, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = and(_T_555, _T_572) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_573, UInt<1>(0h1), "") : assert_26 node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(source_ok, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(is_aligned, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_583, UInt<1>(0h1), "") : assert_29 node _T_587 = eq(io.in.a.bits.mask, mask) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_587, UInt<1>(0h1), "") : assert_30 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_35) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_620 = shr(io.in.a.bits.source, 3) node _T_621 = eq(_T_620, UInt<3>(0h4)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_625 = and(_T_623, _T_624) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_625) node _T_633 = or(_T_632, _T_626) node _T_634 = or(_T_633, _T_627) node _T_635 = and(_T_594, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_639 = and(_T_637, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_642 = cvt(_T_641) node _T_643 = and(_T_642, asSInt(UInt<17>(0h101c0))) node _T_644 = asSInt(_T_643) node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0))) node _T_646 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<29>(0h100001c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = or(_T_645, _T_650) node _T_652 = and(_T_640, _T_651) node _T_653 = or(UInt<1>(0h0), _T_652) node _T_654 = and(_T_636, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_654, UInt<1>(0h1), "") : assert_31 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(source_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(is_aligned, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(_T_664, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_664, UInt<1>(0h1), "") : assert_34 node _T_668 = not(mask) node _T_669 = and(io.in.a.bits.mask, _T_668) node _T_670 = eq(_T_669, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_670, UInt<1>(0h1), "") : assert_35 node _T_674 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_674 : node _T_675 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_676 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_679 = shr(io.in.a.bits.source, 2) node _T_680 = eq(_T_679, UInt<1>(0h0)) node _T_681 = leq(UInt<1>(0h0), uncommonBits_40) node _T_682 = and(_T_680, _T_681) node _T_683 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_684 = and(_T_682, _T_683) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h1)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_41) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<2>(0h2)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_42) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h3)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_43) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_703 = shr(io.in.a.bits.source, 3) node _T_704 = eq(_T_703, UInt<3>(0h4)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_44) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_711 = or(_T_678, _T_684) node _T_712 = or(_T_711, _T_690) node _T_713 = or(_T_712, _T_696) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_708) node _T_716 = or(_T_715, _T_709) node _T_717 = or(_T_716, _T_710) node _T_718 = and(_T_677, _T_717) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_721 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_722 = and(_T_720, _T_721) node _T_723 = or(UInt<1>(0h0), _T_722) node _T_724 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_725 = cvt(_T_724) node _T_726 = and(_T_725, asSInt(UInt<17>(0h101c0))) node _T_727 = asSInt(_T_726) node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) node _T_729 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<29>(0h100001c0))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = or(_T_728, _T_733) node _T_735 = and(_T_723, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = and(_T_719, _T_736) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_737, UInt<1>(0h1), "") : assert_36 node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(source_ok, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(is_aligned, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_747 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_747, UInt<1>(0h1), "") : assert_39 node _T_751 = eq(io.in.a.bits.mask, mask) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_751, UInt<1>(0h1), "") : assert_40 node _T_755 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_755 : node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_45) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<1>(0h1)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_46) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<2>(0h2)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_47) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<2>(0h3)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_48) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_784 = shr(io.in.a.bits.source, 3) node _T_785 = eq(_T_784, UInt<3>(0h4)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_49) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_792 = or(_T_759, _T_765) node _T_793 = or(_T_792, _T_771) node _T_794 = or(_T_793, _T_777) node _T_795 = or(_T_794, _T_783) node _T_796 = or(_T_795, _T_789) node _T_797 = or(_T_796, _T_790) node _T_798 = or(_T_797, _T_791) node _T_799 = and(_T_758, _T_798) node _T_800 = or(UInt<1>(0h0), _T_799) node _T_801 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_802 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_803 = and(_T_801, _T_802) node _T_804 = or(UInt<1>(0h0), _T_803) node _T_805 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h101c0))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<29>(0h100001c0))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = or(_T_809, _T_814) node _T_816 = and(_T_804, _T_815) node _T_817 = or(UInt<1>(0h0), _T_816) node _T_818 = and(_T_800, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(source_ok, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_841 = shr(io.in.a.bits.source, 2) node _T_842 = eq(_T_841, UInt<1>(0h0)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_50) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_846 = and(_T_844, _T_845) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h1)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_51) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<2>(0h2)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_52) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h3)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_53) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_865 = shr(io.in.a.bits.source, 3) node _T_866 = eq(_T_865, UInt<3>(0h4)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_54) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_873 = or(_T_840, _T_846) node _T_874 = or(_T_873, _T_852) node _T_875 = or(_T_874, _T_858) node _T_876 = or(_T_875, _T_864) node _T_877 = or(_T_876, _T_870) node _T_878 = or(_T_877, _T_871) node _T_879 = or(_T_878, _T_872) node _T_880 = and(_T_839, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_883 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_884 = and(_T_882, _T_883) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000180)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<17>(0h101c0))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<32>(0h80000180)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<29>(0h100001c0))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = or(_T_890, _T_895) node _T_897 = and(_T_885, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_881, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_40 = shr(io.in.d.bits.source, 2) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_46 = shr(io.in.d.bits.source, 2) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 3) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_39 connect _source_ok_WIRE_1[1], _source_ok_T_45 connect _source_ok_WIRE_1[2], _source_ok_T_51 connect _source_ok_WIRE_1[3], _source_ok_T_57 connect _source_ok_WIRE_1[4], _source_ok_T_63 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h1), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h1), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h1), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h1), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h1), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1054 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 node _T_1058 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) node _T_1060 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1061 = cvt(_T_1060) node _T_1062 = and(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = asSInt(_T_1062) node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0))) node _T_1065 = or(_T_1059, _T_1064) node _uncommonBits_T_55 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1066 = shr(io.in.b.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = or(_T_1072, _T_1077) node _uncommonBits_T_56 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1079 = shr(io.in.b.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h1)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<1>(0h0))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1085, _T_1090) node _uncommonBits_T_57 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1092 = shr(io.in.b.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) node _T_1099 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1100 = cvt(_T_1099) node _T_1101 = and(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = asSInt(_T_1101) node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0))) node _T_1104 = or(_T_1098, _T_1103) node _uncommonBits_T_58 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1105 = shr(io.in.b.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = or(_T_1111, _T_1116) node _uncommonBits_T_59 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1118 = shr(io.in.b.bits.source, 3) node _T_1119 = eq(_T_1118, UInt<3>(0h4)) node _T_1120 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = leq(uncommonBits_59, UInt<3>(0h7)) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) node _T_1125 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<1>(0h0))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1124, _T_1129) node _T_1131 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) node _T_1133 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1134 = cvt(_T_1133) node _T_1135 = and(_T_1134, asSInt(UInt<1>(0h0))) node _T_1136 = asSInt(_T_1135) node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0))) node _T_1138 = or(_T_1132, _T_1137) node _T_1139 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) node _T_1141 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = or(_T_1140, _T_1145) node _T_1147 = and(_T_1065, _T_1078) node _T_1148 = and(_T_1147, _T_1091) node _T_1149 = and(_T_1148, _T_1104) node _T_1150 = and(_T_1149, _T_1117) node _T_1151 = and(_T_1150, _T_1130) node _T_1152 = and(_T_1151, _T_1138) node _T_1153 = and(_T_1152, _T_1146) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0) node _legal_source_T_25 = shr(io.in.b.bits.source, 3) node _legal_source_T_26 = eq(_legal_source_T_25, UInt<3>(0h4)) node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4) node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27) node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7)) node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _legal_source_WIRE : UInt<1>[8] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_30 connect _legal_source_WIRE[6], _legal_source_T_31 connect _legal_source_WIRE[7], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_41 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_35) node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_36) node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_37) node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_38) node _legal_source_T_46 = or(_legal_source_T_45, _legal_source_T_39) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_40) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_47 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1157 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1157 : node _T_1158 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1159 = shr(io.in.b.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_61 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1165 = shr(io.in.b.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_62 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1171 = shr(io.in.b.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_63 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1177 = shr(io.in.b.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _uncommonBits_T_64 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1183 = shr(io.in.b.bits.source, 3) node _T_1184 = eq(_T_1183, UInt<3>(0h4)) node _T_1185 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = leq(uncommonBits_64, UInt<3>(0h7)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1190 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _WIRE_4 : UInt<1>[8] connect _WIRE_4[0], _T_1158 connect _WIRE_4[1], _T_1164 connect _WIRE_4[2], _T_1170 connect _WIRE_4[3], _T_1176 connect _WIRE_4[4], _T_1182 connect _WIRE_4[5], _T_1188 connect _WIRE_4[6], _T_1189 connect _WIRE_4[7], _T_1190 node _T_1191 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1192 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1194 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1195 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1196 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1197 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1198 = mux(_WIRE_4[6], _T_1191, UInt<1>(0h0)) node _T_1199 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1200 = or(_T_1192, _T_1193) node _T_1201 = or(_T_1200, _T_1194) node _T_1202 = or(_T_1201, _T_1195) node _T_1203 = or(_T_1202, _T_1196) node _T_1204 = or(_T_1203, _T_1197) node _T_1205 = or(_T_1204, _T_1198) node _T_1206 = or(_T_1205, _T_1199) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1206 node _T_1207 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1208 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = or(UInt<1>(0h0), _T_1209) node _T_1211 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1212 = cvt(_T_1211) node _T_1213 = and(_T_1212, asSInt(UInt<17>(0h101c0))) node _T_1214 = asSInt(_T_1213) node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0))) node _T_1216 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1217 = cvt(_T_1216) node _T_1218 = and(_T_1217, asSInt(UInt<29>(0h100001c0))) node _T_1219 = asSInt(_T_1218) node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = or(_T_1215, _T_1220) node _T_1222 = and(_T_1210, _T_1221) node _T_1223 = or(UInt<1>(0h0), _T_1222) node _T_1224 = and(_WIRE_5, _T_1223) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_86 node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(address_ok, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(legal_source, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1237 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_90 node _T_1241 = eq(io.in.b.bits.mask, mask_1) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_91 node _T_1245 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_92 node _T_1249 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1249 : node _T_1250 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1251 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1252 = and(_T_1250, _T_1251) node _T_1253 = or(UInt<1>(0h0), _T_1252) node _T_1254 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<17>(0h101c0))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1260 = cvt(_T_1259) node _T_1261 = and(_T_1260, asSInt(UInt<29>(0h100001c0))) node _T_1262 = asSInt(_T_1261) node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0))) node _T_1264 = or(_T_1258, _T_1263) node _T_1265 = and(_T_1253, _T_1264) node _T_1266 = or(UInt<1>(0h0), _T_1265) node _T_1267 = and(UInt<1>(0h0), _T_1266) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_93 node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(address_ok, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(legal_source, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1280 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_97 node _T_1284 = eq(io.in.b.bits.mask, mask_1) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_98 node _T_1288 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_99 node _T_1292 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1292 : node _T_1293 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1294 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<17>(0h101c0))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<29>(0h100001c0))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = or(_T_1301, _T_1306) node _T_1308 = and(_T_1296, _T_1307) node _T_1309 = or(UInt<1>(0h0), _T_1308) node _T_1310 = and(UInt<1>(0h0), _T_1309) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_100 node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(address_ok, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(legal_source, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1323 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_104 node _T_1327 = eq(io.in.b.bits.mask, mask_1) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_105 node _T_1331 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1331 : node _T_1332 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1333 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = or(UInt<1>(0h0), _T_1334) node _T_1336 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1337 = cvt(_T_1336) node _T_1338 = and(_T_1337, asSInt(UInt<17>(0h101c0))) node _T_1339 = asSInt(_T_1338) node _T_1340 = eq(_T_1339, asSInt(UInt<1>(0h0))) node _T_1341 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<29>(0h100001c0))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = or(_T_1340, _T_1345) node _T_1347 = and(_T_1335, _T_1346) node _T_1348 = or(UInt<1>(0h0), _T_1347) node _T_1349 = and(UInt<1>(0h0), _T_1348) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_106 node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(address_ok, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(legal_source, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1362 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_110 node _T_1366 = not(mask_1) node _T_1367 = and(io.in.b.bits.mask, _T_1366) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_111 node _T_1372 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1372 : node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1375 = and(_T_1373, _T_1374) node _T_1376 = or(UInt<1>(0h0), _T_1375) node _T_1377 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h101c0))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<29>(0h100001c0))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = or(_T_1381, _T_1386) node _T_1388 = and(_T_1376, _T_1387) node _T_1389 = or(UInt<1>(0h0), _T_1388) node _T_1390 = and(UInt<1>(0h0), _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112 node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(address_ok, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(legal_source, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1403 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_116 node _T_1407 = eq(io.in.b.bits.mask, mask_1) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_117 node _T_1411 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1411 : node _T_1412 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1413 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = or(UInt<1>(0h0), _T_1414) node _T_1416 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<17>(0h101c0))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<29>(0h100001c0))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = or(_T_1420, _T_1425) node _T_1427 = and(_T_1415, _T_1426) node _T_1428 = or(UInt<1>(0h0), _T_1427) node _T_1429 = and(UInt<1>(0h0), _T_1428) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_118 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(address_ok, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(legal_source, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1442 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_122 node _T_1446 = eq(io.in.b.bits.mask, mask_1) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_123 node _T_1450 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1450 : node _T_1451 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1452 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1453 = and(_T_1451, _T_1452) node _T_1454 = or(UInt<1>(0h0), _T_1453) node _T_1455 = xor(io.in.b.bits.address, UInt<28>(0h8000180)) node _T_1456 = cvt(_T_1455) node _T_1457 = and(_T_1456, asSInt(UInt<17>(0h101c0))) node _T_1458 = asSInt(_T_1457) node _T_1459 = eq(_T_1458, asSInt(UInt<1>(0h0))) node _T_1460 = xor(io.in.b.bits.address, UInt<32>(0h80000180)) node _T_1461 = cvt(_T_1460) node _T_1462 = and(_T_1461, asSInt(UInt<29>(0h100001c0))) node _T_1463 = asSInt(_T_1462) node _T_1464 = eq(_T_1463, asSInt(UInt<1>(0h0))) node _T_1465 = or(_T_1459, _T_1464) node _T_1466 = and(_T_1454, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1466) node _T_1468 = and(UInt<1>(0h0), _T_1467) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_124 node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(address_ok, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(legal_source, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1481 = eq(io.in.b.bits.mask, mask_1) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_128 node _T_1485 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1489 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_130 node _source_ok_T_78 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_79 = shr(io.in.c.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_85 = shr(io.in.c.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_91 = shr(io.in.c.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_97 = shr(io.in.c.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 2, 0) node _source_ok_T_103 = shr(io.in.c.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<3>(0h7)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_110 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_2 : UInt<1>[8] connect _source_ok_WIRE_2[0], _source_ok_T_78 connect _source_ok_WIRE_2[1], _source_ok_T_84 connect _source_ok_WIRE_2[2], _source_ok_T_90 connect _source_ok_WIRE_2[3], _source_ok_T_96 connect _source_ok_WIRE_2[4], _source_ok_T_102 connect _source_ok_WIRE_2[5], _source_ok_T_108 connect _source_ok_WIRE_2[6], _source_ok_T_109 connect _source_ok_WIRE_2[7], _source_ok_T_110 node _source_ok_T_111 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_2[2]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_2[3]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_2[4]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_2[5]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_2[6]) node source_ok_2 = or(_source_ok_T_116, _source_ok_WIRE_2[7]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1493 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = or(_T_1494, _T_1499) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1501 = shr(io.in.c.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) node _T_1508 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = or(_T_1507, _T_1512) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1514 = shr(io.in.c.bits.source, 2) node _T_1515 = eq(_T_1514, UInt<1>(0h1)) node _T_1516 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1519 = and(_T_1517, _T_1518) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) node _T_1521 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1520, _T_1525) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_1527 = shr(io.in.c.bits.source, 2) node _T_1528 = eq(_T_1527, UInt<2>(0h2)) node _T_1529 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_1532 = and(_T_1530, _T_1531) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<1>(0h0))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = or(_T_1533, _T_1538) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_1540 = shr(io.in.c.bits.source, 2) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_1545 = and(_T_1543, _T_1544) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) node _T_1547 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1546, _T_1551) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1553 = shr(io.in.c.bits.source, 3) node _T_1554 = eq(_T_1553, UInt<3>(0h4)) node _T_1555 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1556 = and(_T_1554, _T_1555) node _T_1557 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = or(_T_1559, _T_1564) node _T_1566 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) node _T_1568 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<1>(0h0))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = or(_T_1567, _T_1572) node _T_1574 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) node _T_1576 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1577 = cvt(_T_1576) node _T_1578 = and(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = asSInt(_T_1578) node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = or(_T_1575, _T_1580) node _T_1582 = and(_T_1500, _T_1513) node _T_1583 = and(_T_1582, _T_1526) node _T_1584 = and(_T_1583, _T_1539) node _T_1585 = and(_T_1584, _T_1552) node _T_1586 = and(_T_1585, _T_1565) node _T_1587 = and(_T_1586, _T_1573) node _T_1588 = and(_T_1587, _T_1581) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_131 node _T_1592 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1592 : node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(address_ok_1, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(source_ok_2, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1599 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_134 node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1606 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_136 node _T_1610 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(_T_1610, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1610, UInt<1>(0h1), "") : assert_137 node _T_1614 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1614 : node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(address_ok_1, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(source_ok_2, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1621 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_140 node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1628 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1629 = asUInt(reset) node _T_1630 = eq(_T_1629, UInt<1>(0h0)) when _T_1630 : node _T_1631 = eq(_T_1628, UInt<1>(0h0)) when _T_1631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1628, UInt<1>(0h1), "") : assert_142 node _T_1632 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1632 : node _T_1633 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1634 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1637 = shr(io.in.c.bits.source, 2) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) node _T_1639 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1640 = and(_T_1638, _T_1639) node _T_1641 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1642 = and(_T_1640, _T_1641) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1643 = shr(io.in.c.bits.source, 2) node _T_1644 = eq(_T_1643, UInt<1>(0h1)) node _T_1645 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1646 = and(_T_1644, _T_1645) node _T_1647 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1648 = and(_T_1646, _T_1647) node _uncommonBits_T_72 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1649 = shr(io.in.c.bits.source, 2) node _T_1650 = eq(_T_1649, UInt<2>(0h2)) node _T_1651 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1652 = and(_T_1650, _T_1651) node _T_1653 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1654 = and(_T_1652, _T_1653) node _uncommonBits_T_73 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1655 = shr(io.in.c.bits.source, 2) node _T_1656 = eq(_T_1655, UInt<2>(0h3)) node _T_1657 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1658 = and(_T_1656, _T_1657) node _T_1659 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1660 = and(_T_1658, _T_1659) node _uncommonBits_T_74 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1661 = shr(io.in.c.bits.source, 3) node _T_1662 = eq(_T_1661, UInt<3>(0h4)) node _T_1663 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1664 = and(_T_1662, _T_1663) node _T_1665 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1666 = and(_T_1664, _T_1665) node _T_1667 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1669 = or(_T_1636, _T_1642) node _T_1670 = or(_T_1669, _T_1648) node _T_1671 = or(_T_1670, _T_1654) node _T_1672 = or(_T_1671, _T_1660) node _T_1673 = or(_T_1672, _T_1666) node _T_1674 = or(_T_1673, _T_1667) node _T_1675 = or(_T_1674, _T_1668) node _T_1676 = and(_T_1635, _T_1675) node _T_1677 = or(UInt<1>(0h0), _T_1676) node _T_1678 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1679 = or(UInt<1>(0h0), _T_1678) node _T_1680 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<17>(0h101c0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1686 = cvt(_T_1685) node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h100001c0))) node _T_1688 = asSInt(_T_1687) node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0))) node _T_1690 = or(_T_1684, _T_1689) node _T_1691 = and(_T_1679, _T_1690) node _T_1692 = or(UInt<1>(0h0), _T_1691) node _T_1693 = and(_T_1677, _T_1692) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_143 node _T_1697 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_75 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1698 = shr(io.in.c.bits.source, 2) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1703 = and(_T_1701, _T_1702) node _uncommonBits_T_76 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 1, 0) node _T_1704 = shr(io.in.c.bits.source, 2) node _T_1705 = eq(_T_1704, UInt<1>(0h1)) node _T_1706 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = leq(uncommonBits_76, UInt<2>(0h3)) node _T_1709 = and(_T_1707, _T_1708) node _uncommonBits_T_77 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0) node _T_1710 = shr(io.in.c.bits.source, 2) node _T_1711 = eq(_T_1710, UInt<2>(0h2)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_77, UInt<2>(0h3)) node _T_1715 = and(_T_1713, _T_1714) node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_1716 = shr(io.in.c.bits.source, 2) node _T_1717 = eq(_T_1716, UInt<2>(0h3)) node _T_1718 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1719 = and(_T_1717, _T_1718) node _T_1720 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_1721 = and(_T_1719, _T_1720) node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 2, 0) node _T_1722 = shr(io.in.c.bits.source, 3) node _T_1723 = eq(_T_1722, UInt<3>(0h4)) node _T_1724 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1725 = and(_T_1723, _T_1724) node _T_1726 = leq(uncommonBits_79, UInt<3>(0h7)) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_6 : UInt<1>[8] connect _WIRE_6[0], _T_1697 connect _WIRE_6[1], _T_1703 connect _WIRE_6[2], _T_1709 connect _WIRE_6[3], _T_1715 connect _WIRE_6[4], _T_1721 connect _WIRE_6[5], _T_1727 connect _WIRE_6[6], _T_1728 connect _WIRE_6[7], _T_1729 node _T_1730 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1731 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1732 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1733 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1734 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1735 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1736 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1737 = mux(_WIRE_6[6], _T_1730, UInt<1>(0h0)) node _T_1738 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1739 = or(_T_1731, _T_1732) node _T_1740 = or(_T_1739, _T_1733) node _T_1741 = or(_T_1740, _T_1734) node _T_1742 = or(_T_1741, _T_1735) node _T_1743 = or(_T_1742, _T_1736) node _T_1744 = or(_T_1743, _T_1737) node _T_1745 = or(_T_1744, _T_1738) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1745 node _T_1746 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1747 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1748 = and(_T_1746, _T_1747) node _T_1749 = or(UInt<1>(0h0), _T_1748) node _T_1750 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<17>(0h101c0))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1756 = cvt(_T_1755) node _T_1757 = and(_T_1756, asSInt(UInt<29>(0h100001c0))) node _T_1758 = asSInt(_T_1757) node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0))) node _T_1760 = or(_T_1754, _T_1759) node _T_1761 = and(_T_1749, _T_1760) node _T_1762 = or(UInt<1>(0h0), _T_1761) node _T_1763 = and(_WIRE_7, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_144 node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(source_ok_2, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1770 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1771 = asUInt(reset) node _T_1772 = eq(_T_1771, UInt<1>(0h0)) when _T_1772 : node _T_1773 = eq(_T_1770, UInt<1>(0h0)) when _T_1773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1770, UInt<1>(0h1), "") : assert_146 node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1777 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1778 = asUInt(reset) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) when _T_1779 : node _T_1780 = eq(_T_1777, UInt<1>(0h0)) when _T_1780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1777, UInt<1>(0h1), "") : assert_148 node _T_1781 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_149 node _T_1785 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1785 : node _T_1786 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1787 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1788 = and(_T_1786, _T_1787) node _T_1789 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0) node _T_1790 = shr(io.in.c.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_80, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0) node _T_1796 = shr(io.in.c.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<1>(0h1)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_81, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 1, 0) node _T_1802 = shr(io.in.c.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<2>(0h2)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_82, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 1, 0) node _T_1808 = shr(io.in.c.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<2>(0h3)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_83, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 2, 0) node _T_1814 = shr(io.in.c.bits.source, 3) node _T_1815 = eq(_T_1814, UInt<3>(0h4)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_84, UInt<3>(0h7)) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1821 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1822 = or(_T_1789, _T_1795) node _T_1823 = or(_T_1822, _T_1801) node _T_1824 = or(_T_1823, _T_1807) node _T_1825 = or(_T_1824, _T_1813) node _T_1826 = or(_T_1825, _T_1819) node _T_1827 = or(_T_1826, _T_1820) node _T_1828 = or(_T_1827, _T_1821) node _T_1829 = and(_T_1788, _T_1828) node _T_1830 = or(UInt<1>(0h0), _T_1829) node _T_1831 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1832 = or(UInt<1>(0h0), _T_1831) node _T_1833 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1834 = cvt(_T_1833) node _T_1835 = and(_T_1834, asSInt(UInt<17>(0h101c0))) node _T_1836 = asSInt(_T_1835) node _T_1837 = eq(_T_1836, asSInt(UInt<1>(0h0))) node _T_1838 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1839 = cvt(_T_1838) node _T_1840 = and(_T_1839, asSInt(UInt<29>(0h100001c0))) node _T_1841 = asSInt(_T_1840) node _T_1842 = eq(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = or(_T_1837, _T_1842) node _T_1844 = and(_T_1832, _T_1843) node _T_1845 = or(UInt<1>(0h0), _T_1844) node _T_1846 = and(_T_1830, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_150 node _T_1850 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1851 = shr(io.in.c.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1857 = shr(io.in.c.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<1>(0h1)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1863 = shr(io.in.c.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<2>(0h2)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_1869 = shr(io.in.c.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<2>(0h3)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0) node _T_1875 = shr(io.in.c.bits.source, 3) node _T_1876 = eq(_T_1875, UInt<3>(0h4)) node _T_1877 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1878 = and(_T_1876, _T_1877) node _T_1879 = leq(uncommonBits_89, UInt<3>(0h7)) node _T_1880 = and(_T_1878, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1882 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_8 : UInt<1>[8] connect _WIRE_8[0], _T_1850 connect _WIRE_8[1], _T_1856 connect _WIRE_8[2], _T_1862 connect _WIRE_8[3], _T_1868 connect _WIRE_8[4], _T_1874 connect _WIRE_8[5], _T_1880 connect _WIRE_8[6], _T_1881 connect _WIRE_8[7], _T_1882 node _T_1883 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1884 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1885 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1886 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1887 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1888 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1889 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1890 = mux(_WIRE_8[6], _T_1883, UInt<1>(0h0)) node _T_1891 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1892 = or(_T_1884, _T_1885) node _T_1893 = or(_T_1892, _T_1886) node _T_1894 = or(_T_1893, _T_1887) node _T_1895 = or(_T_1894, _T_1888) node _T_1896 = or(_T_1895, _T_1889) node _T_1897 = or(_T_1896, _T_1890) node _T_1898 = or(_T_1897, _T_1891) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1898 node _T_1899 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1900 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = or(UInt<1>(0h0), _T_1901) node _T_1903 = xor(io.in.c.bits.address, UInt<28>(0h8000180)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h101c0))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.c.bits.address, UInt<32>(0h80000180)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<29>(0h100001c0))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = or(_T_1907, _T_1912) node _T_1914 = and(_T_1902, _T_1913) node _T_1915 = or(UInt<1>(0h0), _T_1914) node _T_1916 = and(_WIRE_9, _T_1915) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_151 node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(source_ok_2, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1923 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_153 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1930 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_155 node _T_1934 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1941 = asUInt(reset) node _T_1942 = eq(_T_1941, UInt<1>(0h0)) when _T_1942 : node _T_1943 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1944 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_159 node _T_1948 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_160 node _T_1952 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(address_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(source_ok_2, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1962 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_164 node _T_1966 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1966 : node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(address_ok_1, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_2, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1976 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_168 node _T_1980 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1987 = eq(a_first, UInt<1>(0h0)) node _T_1988 = and(io.in.a.valid, _T_1987) when _T_1988 : node _T_1989 = eq(io.in.a.bits.opcode, opcode) node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(_T_1989, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1989, UInt<1>(0h1), "") : assert_171 node _T_1993 = eq(io.in.a.bits.param, param) node _T_1994 = asUInt(reset) node _T_1995 = eq(_T_1994, UInt<1>(0h0)) when _T_1995 : node _T_1996 = eq(_T_1993, UInt<1>(0h0)) when _T_1996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1993, UInt<1>(0h1), "") : assert_172 node _T_1997 = eq(io.in.a.bits.size, size) node _T_1998 = asUInt(reset) node _T_1999 = eq(_T_1998, UInt<1>(0h0)) when _T_1999 : node _T_2000 = eq(_T_1997, UInt<1>(0h0)) when _T_2000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1997, UInt<1>(0h1), "") : assert_173 node _T_2001 = eq(io.in.a.bits.source, source) node _T_2002 = asUInt(reset) node _T_2003 = eq(_T_2002, UInt<1>(0h0)) when _T_2003 : node _T_2004 = eq(_T_2001, UInt<1>(0h0)) when _T_2004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2001, UInt<1>(0h1), "") : assert_174 node _T_2005 = eq(io.in.a.bits.address, address) node _T_2006 = asUInt(reset) node _T_2007 = eq(_T_2006, UInt<1>(0h0)) when _T_2007 : node _T_2008 = eq(_T_2005, UInt<1>(0h0)) when _T_2008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2005, UInt<1>(0h1), "") : assert_175 node _T_2009 = and(io.in.a.ready, io.in.a.valid) node _T_2010 = and(_T_2009, a_first) when _T_2010 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2011 = eq(d_first, UInt<1>(0h0)) node _T_2012 = and(io.in.d.valid, _T_2011) when _T_2012 : node _T_2013 = eq(io.in.d.bits.opcode, opcode_1) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_176 node _T_2017 = eq(io.in.d.bits.param, param_1) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_177 node _T_2021 = eq(io.in.d.bits.size, size_1) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_178 node _T_2025 = eq(io.in.d.bits.source, source_1) node _T_2026 = asUInt(reset) node _T_2027 = eq(_T_2026, UInt<1>(0h0)) when _T_2027 : node _T_2028 = eq(_T_2025, UInt<1>(0h0)) when _T_2028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2025, UInt<1>(0h1), "") : assert_179 node _T_2029 = eq(io.in.d.bits.sink, sink) node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(_T_2029, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2029, UInt<1>(0h1), "") : assert_180 node _T_2033 = eq(io.in.d.bits.denied, denied) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_181 node _T_2037 = and(io.in.d.ready, io.in.d.valid) node _T_2038 = and(_T_2037, d_first) when _T_2038 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2039 = eq(b_first, UInt<1>(0h0)) node _T_2040 = and(io.in.b.valid, _T_2039) when _T_2040 : node _T_2041 = eq(io.in.b.bits.opcode, opcode_2) node _T_2042 = asUInt(reset) node _T_2043 = eq(_T_2042, UInt<1>(0h0)) when _T_2043 : node _T_2044 = eq(_T_2041, UInt<1>(0h0)) when _T_2044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2041, UInt<1>(0h1), "") : assert_182 node _T_2045 = eq(io.in.b.bits.param, param_2) node _T_2046 = asUInt(reset) node _T_2047 = eq(_T_2046, UInt<1>(0h0)) when _T_2047 : node _T_2048 = eq(_T_2045, UInt<1>(0h0)) when _T_2048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2045, UInt<1>(0h1), "") : assert_183 node _T_2049 = eq(io.in.b.bits.size, size_2) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_184 node _T_2053 = eq(io.in.b.bits.source, source_2) node _T_2054 = asUInt(reset) node _T_2055 = eq(_T_2054, UInt<1>(0h0)) when _T_2055 : node _T_2056 = eq(_T_2053, UInt<1>(0h0)) when _T_2056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2053, UInt<1>(0h1), "") : assert_185 node _T_2057 = eq(io.in.b.bits.address, address_1) node _T_2058 = asUInt(reset) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) when _T_2059 : node _T_2060 = eq(_T_2057, UInt<1>(0h0)) when _T_2060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2057, UInt<1>(0h1), "") : assert_186 node _T_2061 = and(io.in.b.ready, io.in.b.valid) node _T_2062 = and(_T_2061, b_first) when _T_2062 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2063 = eq(c_first, UInt<1>(0h0)) node _T_2064 = and(io.in.c.valid, _T_2063) when _T_2064 : node _T_2065 = eq(io.in.c.bits.opcode, opcode_3) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_187 node _T_2069 = eq(io.in.c.bits.param, param_3) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_188 node _T_2073 = eq(io.in.c.bits.size, size_3) node _T_2074 = asUInt(reset) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) when _T_2075 : node _T_2076 = eq(_T_2073, UInt<1>(0h0)) when _T_2076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2073, UInt<1>(0h1), "") : assert_189 node _T_2077 = eq(io.in.c.bits.source, source_3) node _T_2078 = asUInt(reset) node _T_2079 = eq(_T_2078, UInt<1>(0h0)) when _T_2079 : node _T_2080 = eq(_T_2077, UInt<1>(0h0)) when _T_2080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2077, UInt<1>(0h1), "") : assert_190 node _T_2081 = eq(io.in.c.bits.address, address_2) node _T_2082 = asUInt(reset) node _T_2083 = eq(_T_2082, UInt<1>(0h0)) when _T_2083 : node _T_2084 = eq(_T_2081, UInt<1>(0h0)) when _T_2084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2081, UInt<1>(0h1), "") : assert_191 node _T_2085 = and(io.in.c.ready, io.in.c.valid) node _T_2086 = and(_T_2085, c_first) when _T_2086 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes : UInt<172>, clock, reset, UInt<172>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<43> connect a_set, UInt<43>(0h0) wire a_set_wo_ready : UInt<43> connect a_set_wo_ready, UInt<43>(0h0) wire a_opcodes_set : UInt<172> connect a_opcodes_set, UInt<172>(0h0) wire a_sizes_set : UInt<172> connect a_sizes_set, UInt<172>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2087 = and(io.in.a.valid, a_first_1) node _T_2088 = and(_T_2087, UInt<1>(0h1)) when _T_2088 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2089 = and(io.in.a.ready, io.in.a.valid) node _T_2090 = and(_T_2089, a_first_1) node _T_2091 = and(_T_2090, UInt<1>(0h1)) when _T_2091 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2092 = dshr(inflight, io.in.a.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<43> connect d_clr, UInt<43>(0h0) wire d_clr_wo_ready : UInt<43> connect d_clr_wo_ready, UInt<43>(0h0) wire d_opcodes_clr : UInt<172> connect d_opcodes_clr, UInt<172>(0h0) wire d_sizes_clr : UInt<172> connect d_sizes_clr, UInt<172>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2098 = and(io.in.d.valid, d_first_1) node _T_2099 = and(_T_2098, UInt<1>(0h1)) node _T_2100 = eq(d_release_ack, UInt<1>(0h0)) node _T_2101 = and(_T_2099, _T_2100) when _T_2101 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2102 = and(io.in.d.ready, io.in.d.valid) node _T_2103 = and(_T_2102, d_first_1) node _T_2104 = and(_T_2103, UInt<1>(0h1)) node _T_2105 = eq(d_release_ack, UInt<1>(0h0)) node _T_2106 = and(_T_2104, _T_2105) when _T_2106 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2107 = and(io.in.d.valid, d_first_1) node _T_2108 = and(_T_2107, UInt<1>(0h1)) node _T_2109 = eq(d_release_ack, UInt<1>(0h0)) node _T_2110 = and(_T_2108, _T_2109) when _T_2110 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2111 = dshr(inflight, io.in.d.bits.source) node _T_2112 = bits(_T_2111, 0, 0) node _T_2113 = or(_T_2112, same_cycle_resp) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2119 = or(_T_2117, _T_2118) node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(_T_2119, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2119, UInt<1>(0h1), "") : assert_194 node _T_2123 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_195 else : node _T_2127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2129 = or(_T_2127, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_196 node _T_2133 = eq(io.in.d.bits.size, a_size_lookup) node _T_2134 = asUInt(reset) node _T_2135 = eq(_T_2134, UInt<1>(0h0)) when _T_2135 : node _T_2136 = eq(_T_2133, UInt<1>(0h0)) when _T_2136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2133, UInt<1>(0h1), "") : assert_197 node _T_2137 = and(io.in.d.valid, d_first_1) node _T_2138 = and(_T_2137, a_first_1) node _T_2139 = and(_T_2138, io.in.a.valid) node _T_2140 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2141 = and(_T_2139, _T_2140) node _T_2142 = eq(d_release_ack, UInt<1>(0h0)) node _T_2143 = and(_T_2141, _T_2142) when _T_2143 : node _T_2144 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2145 = or(_T_2144, io.in.a.ready) node _T_2146 = asUInt(reset) node _T_2147 = eq(_T_2146, UInt<1>(0h0)) when _T_2147 : node _T_2148 = eq(_T_2145, UInt<1>(0h0)) when _T_2148 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2145, UInt<1>(0h1), "") : assert_198 node _T_2149 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2150 = orr(a_set_wo_ready) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) node _T_2152 = or(_T_2149, _T_2151) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_112 node _T_2156 = orr(inflight) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2159 = or(_T_2157, _T_2158) node _T_2160 = lt(watchdog, plusarg_reader.out) node _T_2161 = or(_T_2159, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2165 = and(io.in.a.ready, io.in.a.valid) node _T_2166 = and(io.in.d.ready, io.in.d.valid) node _T_2167 = or(_T_2165, _T_2166) when _T_2167 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes_1 : UInt<172>, clock, reset, UInt<172>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<43> connect c_set, UInt<43>(0h0) wire c_set_wo_ready : UInt<43> connect c_set_wo_ready, UInt<43>(0h0) wire c_opcodes_set : UInt<172> connect c_opcodes_set, UInt<172>(0h0) wire c_sizes_set : UInt<172> connect c_sizes_set, UInt<172>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2168 = and(io.in.c.valid, c_first_1) node _T_2169 = bits(io.in.c.bits.opcode, 2, 2) node _T_2170 = bits(io.in.c.bits.opcode, 1, 1) node _T_2171 = and(_T_2169, _T_2170) node _T_2172 = and(_T_2168, _T_2171) when _T_2172 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2173 = and(io.in.c.ready, io.in.c.valid) node _T_2174 = and(_T_2173, c_first_1) node _T_2175 = bits(io.in.c.bits.opcode, 2, 2) node _T_2176 = bits(io.in.c.bits.opcode, 1, 1) node _T_2177 = and(_T_2175, _T_2176) node _T_2178 = and(_T_2174, _T_2177) when _T_2178 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2179 = dshr(inflight_1, io.in.c.bits.source) node _T_2180 = bits(_T_2179, 0, 0) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = asUInt(reset) node _T_2183 = eq(_T_2182, UInt<1>(0h0)) when _T_2183 : node _T_2184 = eq(_T_2181, UInt<1>(0h0)) when _T_2184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2181, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<43> connect d_clr_1, UInt<43>(0h0) wire d_clr_wo_ready_1 : UInt<43> connect d_clr_wo_ready_1, UInt<43>(0h0) wire d_opcodes_clr_1 : UInt<172> connect d_opcodes_clr_1, UInt<172>(0h0) wire d_sizes_clr_1 : UInt<172> connect d_sizes_clr_1, UInt<172>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2185 = and(io.in.d.valid, d_first_2) node _T_2186 = and(_T_2185, UInt<1>(0h1)) node _T_2187 = and(_T_2186, d_release_ack_1) when _T_2187 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2188 = and(io.in.d.ready, io.in.d.valid) node _T_2189 = and(_T_2188, d_first_2) node _T_2190 = and(_T_2189, UInt<1>(0h1)) node _T_2191 = and(_T_2190, d_release_ack_1) when _T_2191 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2192 = and(io.in.d.valid, d_first_2) node _T_2193 = and(_T_2192, UInt<1>(0h1)) node _T_2194 = and(_T_2193, d_release_ack_1) when _T_2194 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2195 = dshr(inflight_1, io.in.d.bits.source) node _T_2196 = bits(_T_2195, 0, 0) node _T_2197 = or(_T_2196, same_cycle_resp_1) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2201 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_203 else : node _T_2205 = eq(io.in.d.bits.size, c_size_lookup) node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(_T_2205, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2205, UInt<1>(0h1), "") : assert_204 node _T_2209 = and(io.in.d.valid, d_first_2) node _T_2210 = and(_T_2209, c_first_1) node _T_2211 = and(_T_2210, io.in.c.valid) node _T_2212 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2213 = and(_T_2211, _T_2212) node _T_2214 = and(_T_2213, d_release_ack_1) node _T_2215 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2216 = and(_T_2214, _T_2215) when _T_2216 : node _T_2217 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2218 = or(_T_2217, io.in.c.ready) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(_T_2218, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2218, UInt<1>(0h1), "") : assert_205 node _T_2222 = orr(c_set_wo_ready) when _T_2222 : node _T_2223 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(_T_2223, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2223, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_113 node _T_2227 = orr(inflight_1) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) node _T_2229 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2230 = or(_T_2228, _T_2229) node _T_2231 = lt(watchdog_1, plusarg_reader_1.out) node _T_2232 = or(_T_2230, _T_2231) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2236 = and(io.in.c.ready, io.in.c.valid) node _T_2237 = and(io.in.d.ready, io.in.d.valid) node _T_2238 = or(_T_2236, _T_2237) when _T_2238 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<12> connect d_set, UInt<12>(0h0) node _T_2239 = and(io.in.d.ready, io.in.d.valid) node _T_2240 = and(_T_2239, d_first_3) node _T_2241 = bits(io.in.d.bits.opcode, 2, 2) node _T_2242 = bits(io.in.d.bits.opcode, 1, 1) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) node _T_2244 = and(_T_2241, _T_2243) node _T_2245 = and(_T_2240, _T_2244) when _T_2245 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2246 = dshr(inflight_2, io.in.d.bits.sink) node _T_2247 = bits(_T_2246, 0, 0) node _T_2248 = eq(_T_2247, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<12> connect e_clr, UInt<12>(0h0) node _T_2252 = and(io.in.e.ready, io.in.e.valid) node _T_2253 = and(_T_2252, UInt<1>(0h1)) node _T_2254 = and(_T_2253, UInt<1>(0h1)) when _T_2254 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2255 = or(d_set, inflight_2) node _T_2256 = dshr(_T_2255, io.in.e.bits.sink) node _T_2257 = bits(_T_2256, 0, 0) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_114 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_115 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_6 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] io_in_b_bits_source = 6'h28; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_56 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_57 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_58 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_59 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_1 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_2 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_3 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_4 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_T_39 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_46 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_47 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _uncommonBits_T_60 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_61 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_62 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_63 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_64 = 6'h28; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _legal_source_T_25 = 3'h5; // @[Parameters.scala:54:10] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_35 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_40 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] _legal_source_T_33 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_43 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_44 = 5'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_37 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_1 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_7 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_13 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_19 = 4'hA; // @[Parameters.scala:54:10] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000180; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000180; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_78 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_97 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_103 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_104 = _source_ok_T_103 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_116 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000180; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000180; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31] wire _T_2165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2165; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2165; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2239 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2239; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [1:0] b_first_counter; // @[Edges.scala:229:27] wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2236 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2236; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2236; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [42:0] inflight; // @[Monitor.scala:614:27] reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [171:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] a_set; // @[Monitor.scala:626:34] wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [171:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [171:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [171:0] _a_size_lookup_T_6 = {168'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [171:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[171:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2091 = _T_2165 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2091 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2091 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2091 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2091 ? _a_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [42:0] d_clr; // @[Monitor.scala:664:34] wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [171:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2137 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2106 = _T_2239 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2106 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2106 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2106 ? _d_sizes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [42:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [171:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [171:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [171:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [171:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [42:0] inflight_1; // @[Monitor.scala:726:35] reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [171:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] c_set; // @[Monitor.scala:738:34] wire [42:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [171:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [171:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [171:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [171:0] _c_size_lookup_T_6 = {168'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [171:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[171:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2178 = _T_2236 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2178 ? _c_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2178 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2178 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2178 ? _c_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2178 ? _c_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [42:0] d_clr_1; // @[Monitor.scala:774:34] wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [171:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2191 = _T_2239 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2191 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2191 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2191 ? _d_sizes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [42:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [171:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [171:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [171:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [11:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_set; // @[Monitor.scala:833:25] wire _T_2245 = _T_2239 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2245 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35] wire [11:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = or(UInt<1>(0h0), _T_70) node _T_72 = and(_T_21, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<14>(0h2000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<13>(0h1000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<17>(0h10000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<18>(0h2f000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<17>(0h10000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<13>(0h1000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<13>(0h1000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = or(_T_84, _T_89) node _T_121 = or(_T_120, _T_94) node _T_122 = or(_T_121, _T_99) node _T_123 = or(_T_122, _T_104) node _T_124 = or(_T_123, _T_109) node _T_125 = or(_T_124, _T_114) node _T_126 = or(_T_125, _T_119) node _T_127 = and(_T_79, _T_126) node _T_128 = or(UInt<1>(0h0), _T_127) node _T_129 = and(UInt<1>(0h0), _T_128) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_129, UInt<1>(0h1), "") : assert_3 node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_136 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_136, UInt<1>(0h1), "") : assert_5 node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(is_aligned, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_143 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_143, UInt<1>(0h1), "") : assert_7 node _T_147 = not(io.in.a.bits.mask) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_148, UInt<1>(0h1), "") : assert_8 node _T_152 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_152, UInt<1>(0h1), "") : assert_9 node _T_156 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_156 : node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<27>(0h4000000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<13>(0h1000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = or(_T_168, _T_173) node _T_205 = or(_T_204, _T_178) node _T_206 = or(_T_205, _T_183) node _T_207 = or(_T_206, _T_188) node _T_208 = or(_T_207, _T_193) node _T_209 = or(_T_208, _T_198) node _T_210 = or(_T_209, _T_203) node _T_211 = and(_T_163, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = and(_T_162, _T_212) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_213, UInt<1>(0h1), "") : assert_10 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<14>(0h2000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<18>(0h2f000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<27>(0h4000000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_225, _T_230) node _T_262 = or(_T_261, _T_235) node _T_263 = or(_T_262, _T_240) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_250) node _T_266 = or(_T_265, _T_255) node _T_267 = or(_T_266, _T_260) node _T_268 = and(_T_220, _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = and(UInt<1>(0h0), _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_270, UInt<1>(0h1), "") : assert_11 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_277, UInt<1>(0h1), "") : assert_13 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(is_aligned, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_284, UInt<1>(0h1), "") : assert_15 node _T_288 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_288, UInt<1>(0h1), "") : assert_16 node _T_292 = not(io.in.a.bits.mask) node _T_293 = eq(_T_292, UInt<1>(0h0)) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_293, UInt<1>(0h1), "") : assert_17 node _T_297 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_297, UInt<1>(0h1), "") : assert_18 node _T_301 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_301 : node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_307, UInt<1>(0h1), "") : assert_19 node _T_311 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_312 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(UInt<1>(0h0), _T_313) node _T_315 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = and(_T_314, _T_319) node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_323 = and(_T_321, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<14>(0h2000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = or(_T_329, _T_334) node _T_361 = or(_T_360, _T_339) node _T_362 = or(_T_361, _T_344) node _T_363 = or(_T_362, _T_349) node _T_364 = or(_T_363, _T_354) node _T_365 = or(_T_364, _T_359) node _T_366 = and(_T_324, _T_365) node _T_367 = or(UInt<1>(0h0), _T_320) node _T_368 = or(_T_367, _T_366) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_398 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_399 = and(_T_397, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = and(_T_400, _T_405) node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_409 = and(_T_407, _T_408) node _T_410 = or(UInt<1>(0h0), _T_409) node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<27>(0h4000000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = or(_T_415, _T_420) node _T_442 = or(_T_441, _T_425) node _T_443 = or(_T_442, _T_430) node _T_444 = or(_T_443, _T_435) node _T_445 = or(_T_444, _T_440) node _T_446 = and(_T_410, _T_445) node _T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = or(UInt<1>(0h0), _T_406) node _T_455 = or(_T_454, _T_446) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_396, _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_457, UInt<1>(0h1), "") : assert_26 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(is_aligned, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_467 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_467, UInt<1>(0h1), "") : assert_29 node _T_471 = eq(io.in.a.bits.mask, mask) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_471, UInt<1>(0h1), "") : assert_30 node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_475 : node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_483 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_484 = and(_T_482, _T_483) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<13>(0h1000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = and(_T_485, _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<14>(0h2000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<18>(0h2f000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = or(_T_500, _T_505) node _T_527 = or(_T_526, _T_510) node _T_528 = or(_T_527, _T_515) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_525) node _T_531 = and(_T_495, _T_530) node _T_532 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = and(_T_532, _T_537) node _T_539 = or(UInt<1>(0h0), _T_491) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_538) node _T_542 = and(_T_481, _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_542, UInt<1>(0h1), "") : assert_31 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_552, UInt<1>(0h1), "") : assert_34 node _T_556 = not(mask) node _T_557 = and(io.in.a.bits.mask, _T_556) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_558, UInt<1>(0h1), "") : assert_35 node _T_562 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_562 : node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<14>(0h2000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<13>(0h1000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<18>(0h2f000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<13>(0h1000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<27>(0h4000000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = or(_T_577, _T_582) node _T_609 = or(_T_608, _T_587) node _T_610 = or(_T_609, _T_592) node _T_611 = or(_T_610, _T_597) node _T_612 = or(_T_611, _T_602) node _T_613 = or(_T_612, _T_607) node _T_614 = and(_T_572, _T_613) node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = and(_T_615, _T_620) node _T_622 = or(UInt<1>(0h0), _T_614) node _T_623 = or(_T_622, _T_621) node _T_624 = and(_T_568, _T_623) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_624, UInt<1>(0h1), "") : assert_36 node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(is_aligned, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_634 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_634, UInt<1>(0h1), "") : assert_39 node _T_638 = eq(io.in.a.bits.mask, mask) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_638, UInt<1>(0h1), "") : assert_40 node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_642 : node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_645 = and(_T_643, _T_644) node _T_646 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_647 = and(_T_645, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<18>(0h2f000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<13>(0h1000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = or(_T_657, _T_662) node _T_689 = or(_T_688, _T_667) node _T_690 = or(_T_689, _T_672) node _T_691 = or(_T_690, _T_677) node _T_692 = or(_T_691, _T_682) node _T_693 = or(_T_692, _T_687) node _T_694 = and(_T_652, _T_693) node _T_695 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = or(UInt<1>(0h0), _T_694) node _T_703 = or(_T_702, _T_701) node _T_704 = and(_T_648, _T_703) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_704, UInt<1>(0h1), "") : assert_41 node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(is_aligned, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_714 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_714, UInt<1>(0h1), "") : assert_44 node _T_718 = eq(io.in.a.bits.mask, mask) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_718, UInt<1>(0h1), "") : assert_45 node _T_722 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_722 : node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = and(_T_725, _T_726) node _T_728 = or(UInt<1>(0h0), _T_727) node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = and(_T_732, _T_737) node _T_739 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_740 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<14>(0h2000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<18>(0h2f000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<17>(0h10000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<27>(0h4000000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<13>(0h1000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = or(_T_744, _T_749) node _T_776 = or(_T_775, _T_754) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_764) node _T_779 = or(_T_778, _T_769) node _T_780 = or(_T_779, _T_774) node _T_781 = and(_T_739, _T_780) node _T_782 = or(UInt<1>(0h0), _T_738) node _T_783 = or(_T_782, _T_781) node _T_784 = and(_T_728, _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_784, UInt<1>(0h1), "") : assert_46 node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(is_aligned, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_794 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_794, UInt<1>(0h1), "") : assert_49 node _T_798 = eq(io.in.a.bits.mask, mask) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_798, UInt<1>(0h1), "") : assert_50 node _T_802 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_802, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_806 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_806, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_810 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_810 : node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_814 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_814, UInt<1>(0h1), "") : assert_54 node _T_818 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_818, UInt<1>(0h1), "") : assert_55 node _T_822 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_822, UInt<1>(0h1), "") : assert_56 node _T_826 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_826, UInt<1>(0h1), "") : assert_57 node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(sink_ok, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_837 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_837, UInt<1>(0h1), "") : assert_60 node _T_841 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_841, UInt<1>(0h1), "") : assert_61 node _T_845 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_845, UInt<1>(0h1), "") : assert_62 node _T_849 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_849, UInt<1>(0h1), "") : assert_63 node _T_853 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_854 = or(UInt<1>(0h1), _T_853) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_854, UInt<1>(0h1), "") : assert_64 node _T_858 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_858 : node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(sink_ok, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_865, UInt<1>(0h1), "") : assert_67 node _T_869 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_869, UInt<1>(0h1), "") : assert_68 node _T_873 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_873, UInt<1>(0h1), "") : assert_69 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = or(_T_877, io.in.d.bits.corrupt) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_878, UInt<1>(0h1), "") : assert_70 node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_883 = or(UInt<1>(0h1), _T_882) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_883, UInt<1>(0h1), "") : assert_71 node _T_887 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_887 : node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_891 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_891, UInt<1>(0h1), "") : assert_73 node _T_895 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_895, UInt<1>(0h1), "") : assert_74 node _T_899 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_900 = or(UInt<1>(0h1), _T_899) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_900, UInt<1>(0h1), "") : assert_75 node _T_904 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_904 : node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_908 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_908, UInt<1>(0h1), "") : assert_77 node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_913 = or(_T_912, io.in.d.bits.corrupt) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_913, UInt<1>(0h1), "") : assert_78 node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_918 = or(UInt<1>(0h1), _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_918, UInt<1>(0h1), "") : assert_79 node _T_922 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_926, UInt<1>(0h1), "") : assert_81 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_930, UInt<1>(0h1), "") : assert_82 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h1), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_935, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_939 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_939, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_943 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_943, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_947 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_947, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_951 = eq(a_first, UInt<1>(0h0)) node _T_952 = and(io.in.a.valid, _T_951) when _T_952 : node _T_953 = eq(io.in.a.bits.opcode, opcode) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_953, UInt<1>(0h1), "") : assert_87 node _T_957 = eq(io.in.a.bits.param, param) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_957, UInt<1>(0h1), "") : assert_88 node _T_961 = eq(io.in.a.bits.size, size) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_961, UInt<1>(0h1), "") : assert_89 node _T_965 = eq(io.in.a.bits.source, source) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_965, UInt<1>(0h1), "") : assert_90 node _T_969 = eq(io.in.a.bits.address, address) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_969, UInt<1>(0h1), "") : assert_91 node _T_973 = and(io.in.a.ready, io.in.a.valid) node _T_974 = and(_T_973, a_first) when _T_974 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_975 = eq(d_first, UInt<1>(0h0)) node _T_976 = and(io.in.d.valid, _T_975) when _T_976 : node _T_977 = eq(io.in.d.bits.opcode, opcode_1) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_977, UInt<1>(0h1), "") : assert_92 node _T_981 = eq(io.in.d.bits.param, param_1) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_981, UInt<1>(0h1), "") : assert_93 node _T_985 = eq(io.in.d.bits.size, size_1) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_985, UInt<1>(0h1), "") : assert_94 node _T_989 = eq(io.in.d.bits.source, source_1) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_989, UInt<1>(0h1), "") : assert_95 node _T_993 = eq(io.in.d.bits.sink, sink) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_993, UInt<1>(0h1), "") : assert_96 node _T_997 = eq(io.in.d.bits.denied, denied) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_997, UInt<1>(0h1), "") : assert_97 node _T_1001 = and(io.in.d.ready, io.in.d.valid) node _T_1002 = and(_T_1001, d_first) when _T_1002 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1003 = and(io.in.a.valid, a_first_1) node _T_1004 = and(_T_1003, UInt<1>(0h1)) when _T_1004 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1005 = and(io.in.a.ready, io.in.a.valid) node _T_1006 = and(_T_1005, a_first_1) node _T_1007 = and(_T_1006, UInt<1>(0h1)) when _T_1007 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1008 = dshr(inflight, io.in.a.bits.source) node _T_1009 = bits(_T_1008, 0, 0) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1014 = and(io.in.d.valid, d_first_1) node _T_1015 = and(_T_1014, UInt<1>(0h1)) node _T_1016 = eq(d_release_ack, UInt<1>(0h0)) node _T_1017 = and(_T_1015, _T_1016) when _T_1017 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1018 = and(io.in.d.ready, io.in.d.valid) node _T_1019 = and(_T_1018, d_first_1) node _T_1020 = and(_T_1019, UInt<1>(0h1)) node _T_1021 = eq(d_release_ack, UInt<1>(0h0)) node _T_1022 = and(_T_1020, _T_1021) when _T_1022 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1023 = and(io.in.d.valid, d_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1027 = dshr(inflight, io.in.d.bits.source) node _T_1028 = bits(_T_1027, 0, 0) node _T_1029 = or(_T_1028, same_cycle_resp) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1033 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1034 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_100 node _T_1039 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_101 else : node _T_1043 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1044 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1045 = or(_T_1043, _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_102 node _T_1049 = eq(io.in.d.bits.size, a_size_lookup) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_103 node _T_1053 = and(io.in.d.valid, d_first_1) node _T_1054 = and(_T_1053, a_first_1) node _T_1055 = and(_T_1054, io.in.a.valid) node _T_1056 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = eq(d_release_ack, UInt<1>(0h0)) node _T_1059 = and(_T_1057, _T_1058) when _T_1059 : node _T_1060 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1061 = or(_T_1060, io.in.a.ready) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_104 node _T_1065 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1066 = orr(a_set_wo_ready) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = or(_T_1065, _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_66 node _T_1072 = orr(inflight) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) node _T_1074 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1075 = or(_T_1073, _T_1074) node _T_1076 = lt(watchdog, plusarg_reader.out) node _T_1077 = or(_T_1075, _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1081 = and(io.in.a.ready, io.in.a.valid) node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = or(_T_1081, _T_1082) when _T_1083 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1084 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1085 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1086 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1087 = and(_T_1085, _T_1086) node _T_1088 = and(_T_1084, _T_1087) when _T_1088 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1089 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1090 = and(_T_1089, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1091 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1092 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1093 = and(_T_1091, _T_1092) node _T_1094 = and(_T_1090, _T_1093) when _T_1094 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1095 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1096 = bits(_T_1095, 0, 0) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1101 = and(io.in.d.valid, d_first_2) node _T_1102 = and(_T_1101, UInt<1>(0h1)) node _T_1103 = and(_T_1102, d_release_ack_1) when _T_1103 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1104 = and(io.in.d.ready, io.in.d.valid) node _T_1105 = and(_T_1104, d_first_2) node _T_1106 = and(_T_1105, UInt<1>(0h1)) node _T_1107 = and(_T_1106, d_release_ack_1) when _T_1107 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1108 = and(io.in.d.valid, d_first_2) node _T_1109 = and(_T_1108, UInt<1>(0h1)) node _T_1110 = and(_T_1109, d_release_ack_1) when _T_1110 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1111 = dshr(inflight_1, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp_1) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1117 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_109 else : node _T_1121 = eq(io.in.d.bits.size, c_size_lookup) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_110 node _T_1125 = and(io.in.d.valid, d_first_2) node _T_1126 = and(_T_1125, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1127 = and(_T_1126, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1128 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = and(_T_1129, d_release_ack_1) node _T_1131 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _T_1133 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1134 = or(_T_1133, _WIRE_23.ready) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_111 node _T_1138 = orr(c_set_wo_ready) when _T_1138 : node _T_1139 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_67 node _T_1143 = orr(inflight_1) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) node _T_1145 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1146 = or(_T_1144, _T_1145) node _T_1147 = lt(watchdog_1, plusarg_reader_1.out) node _T_1148 = or(_T_1146, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1152 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = or(_T_1152, _T_1153) when _T_1154 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h0; // @[Edges.scala:92:37] wire _a_first_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire a_first_beats1_opdata = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire a_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h2; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] io_in_a_bits_mask = 8'hF; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:657:53] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:657:61] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [4:0] _a_sizes_set_interm_T_1 = 5'h5; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'h4; // @[Monitor.scala:658:51] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [28:0] _is_aligned_T = {27'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_0_1 = _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_0_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire mask_sub_1_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_1 = _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_3_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [28:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = {3'h0, a_set}; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'h5 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1053 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_mbus_i1_o2_a32d64s5k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_33 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<5>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<5>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<5>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<5>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<5>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<5>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<5>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<5>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<28>(0h0) connect _WIRE_50.bits.source, UInt<5>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<5>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<28>(0h0) connect _WIRE_54.bits.source, UInt<5>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<5>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<28>(0h0) connect _WIRE_58.bits.source, UInt<5>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<5>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<28>(0h0) connect _WIRE_62.bits.source, UInt<5>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<5>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 5) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 4, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 5) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<5>(0h1f)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) node _requestDOI_T = shr(out[0].d.bits.source, 5) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 4, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 5) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<5>(0h1f)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<5>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<5>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<5>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<5>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<5>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<5>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<5>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<5>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<32>(0h0) connect _WIRE_80.bits.source, UInt<5>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<5> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)

module TLXbar_mbus_i1_o2_a32d64s5k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [4:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [4:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [4:0] _addressC_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _addressC_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _requestBOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _requestBOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _requestBOI_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29] wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _requestBOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _requestBOI_uncommonBits_T_1 = 5'h0; // @[Parameters.scala:52:29] wire [4:0] requestBOI_uncommonBits_1 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _beatsBO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _beatsBO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _beatsBO_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _beatsBO_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _beatsCI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _beatsCI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _portsBIO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _portsBIO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] portsBIO_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsBIO_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _portsBIO_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] portsBIO_filtered_1_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsCOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _portsCOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] portsCOI_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] portsCOI_filtered_1_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [27:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [4:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [4:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [4:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [4:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [4:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [4:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [4:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [4:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [31:0] _requestAIO_T = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d32s1k3z4u_3 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_44 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d32s1k3z4u_2 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d32s1k3z4u_2 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLBuffer_a32d32s1k3z4u_3( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_44 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d32s1k3z4u_2 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d32s1k3z4u_2 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_316 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_316( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_2 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<17> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<6> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_38_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_7_2, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_34_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_12_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_10_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_12_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_22_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_12_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_7_6, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_29_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_10_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_12_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_12_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_7_8, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_28_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_12_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_7_9, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_37_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_10_10, decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_12_8) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_12, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_9_10) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_30_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_10_11, decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_12_9) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_7_13, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_6_13) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_10_12, decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_12_10) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_14, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_9_12) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_6_14) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_39_2 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_10_13, decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_andMatrixInput_12_11) node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_7_15, decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_9_13) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_4_15, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_andMatrixInput_6_15) node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_15) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_11) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_21_2 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_33_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_15_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_10_16, decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_12_12) node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_7_18, decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_andMatrixInput_9_16) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_6_18) node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_2_18, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_12) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_31_2 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_10_17, decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_andMatrixInput_12_13) node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_7_19, decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_9_17) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_4_19, decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_andMatrixInput_6_19) node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_2_19, decoded_andMatrixOutputs_andMatrixInput_3_19) node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_hi_hi_lo_13) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_20_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_10_18, decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_12_14) node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_9_18) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_4_20, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_6_20) node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_20) node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_14) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_32_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_10_19, decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_12_15) node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_7_21, decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_9_19) node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21) node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_4_21, decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_6_21) node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_2_21, decoded_andMatrixOutputs_andMatrixInput_3_21) node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_15) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21) node decoded_andMatrixOutputs_17_2 = andr(_decoded_andMatrixOutputs_T_21) node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_10_20, decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_12_16) node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_7_22, decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_9_20) node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22) node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_4_22, decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_6_22) node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_22, decoded_andMatrixOutputs_andMatrixInput_3_22) node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_hi_hi_lo_16) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_10_21, decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_lo_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_12_17) node decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_7_23, decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_9_21) node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23) node decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_4_23, decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_hi_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_6_23) node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_2_23, decoded_andMatrixOutputs_andMatrixInput_3_23) node decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_hi_hi_lo_17) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23) node decoded_andMatrixOutputs_25_2 = andr(_decoded_andMatrixOutputs_T_23) node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_andMatrixOutputs_lo_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_andMatrixOutputs_lo_24 = cat(decoded_andMatrixOutputs_lo_hi_24, decoded_andMatrixOutputs_lo_lo_24) node decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_andMatrixOutputs_hi_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_andMatrixOutputs_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_24, decoded_andMatrixOutputs_hi_lo_24) node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_24, decoded_andMatrixOutputs_lo_24) node decoded_andMatrixOutputs_18_2 = andr(_decoded_andMatrixOutputs_T_24) node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_andMatrixOutputs_lo_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_andMatrixOutputs_lo_25 = cat(decoded_andMatrixOutputs_lo_hi_25, decoded_andMatrixOutputs_lo_lo_25) node decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_andMatrixOutputs_hi_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_andMatrixOutputs_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_25, decoded_andMatrixOutputs_hi_lo_25) node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_25, decoded_andMatrixOutputs_lo_25) node decoded_andMatrixOutputs_24_2 = andr(_decoded_andMatrixOutputs_T_25) node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_7_26, decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_5_26, decoded_andMatrixOutputs_andMatrixInput_6_26) node decoded_andMatrixOutputs_lo_26 = cat(decoded_andMatrixOutputs_lo_hi_26, decoded_andMatrixOutputs_lo_lo_26) node decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_24, decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_andMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_26, decoded_andMatrixOutputs_hi_lo_26) node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_26, decoded_andMatrixOutputs_lo_26) node decoded_andMatrixOutputs_36_2 = andr(_decoded_andMatrixOutputs_T_26) node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_7_27, decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_5_27, decoded_andMatrixOutputs_andMatrixInput_6_27) node decoded_andMatrixOutputs_lo_27 = cat(decoded_andMatrixOutputs_lo_hi_27, decoded_andMatrixOutputs_lo_lo_27) node decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_25, decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_andMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_27, decoded_andMatrixOutputs_hi_lo_27) node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_hi_27, decoded_andMatrixOutputs_lo_27) node decoded_andMatrixOutputs_16_2 = andr(_decoded_andMatrixOutputs_T_27) node decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_7_28, decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_5_28, decoded_andMatrixOutputs_andMatrixInput_6_28) node decoded_andMatrixOutputs_lo_28 = cat(decoded_andMatrixOutputs_lo_hi_28, decoded_andMatrixOutputs_lo_lo_28) node decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_26, decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_andMatrixOutputs_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_28, decoded_andMatrixOutputs_hi_lo_28) node _decoded_andMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_hi_28, decoded_andMatrixOutputs_lo_28) node decoded_andMatrixOutputs_35_2 = andr(_decoded_andMatrixOutputs_T_28) node decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_7_29, decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_5_29, decoded_andMatrixOutputs_andMatrixInput_6_29) node decoded_andMatrixOutputs_lo_29 = cat(decoded_andMatrixOutputs_lo_hi_29, decoded_andMatrixOutputs_lo_lo_29) node decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_hi_27, decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_andMatrixOutputs_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_29, decoded_andMatrixOutputs_hi_lo_29) node _decoded_andMatrixOutputs_T_29 = cat(decoded_andMatrixOutputs_hi_29, decoded_andMatrixOutputs_lo_29) node decoded_andMatrixOutputs_27_2 = andr(_decoded_andMatrixOutputs_T_29) node decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_7_30, decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_5_30, decoded_andMatrixOutputs_andMatrixInput_6_30) node decoded_andMatrixOutputs_lo_30 = cat(decoded_andMatrixOutputs_lo_hi_30, decoded_andMatrixOutputs_lo_lo_30) node decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_hi_28, decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_andMatrixOutputs_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_30, decoded_andMatrixOutputs_hi_lo_30) node _decoded_andMatrixOutputs_T_30 = cat(decoded_andMatrixOutputs_hi_30, decoded_andMatrixOutputs_lo_30) node decoded_andMatrixOutputs_26_2 = andr(_decoded_andMatrixOutputs_T_30) node decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_7_31, decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_5_31, decoded_andMatrixOutputs_andMatrixInput_6_31) node decoded_andMatrixOutputs_lo_31 = cat(decoded_andMatrixOutputs_lo_hi_31, decoded_andMatrixOutputs_lo_lo_31) node decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_hi_29, decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_andMatrixOutputs_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_31, decoded_andMatrixOutputs_hi_lo_31) node _decoded_andMatrixOutputs_T_31 = cat(decoded_andMatrixOutputs_hi_31, decoded_andMatrixOutputs_lo_31) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_31) node decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_2_32, decoded_andMatrixOutputs_andMatrixInput_3_32) node decoded_andMatrixOutputs_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_andMatrixOutputs_andMatrixInput_1_32) node _decoded_andMatrixOutputs_T_32 = cat(decoded_andMatrixOutputs_hi_32, decoded_andMatrixOutputs_lo_32) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_32) node decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_2_33, decoded_andMatrixOutputs_andMatrixInput_3_33) node decoded_andMatrixOutputs_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_andMatrixOutputs_andMatrixInput_1_33) node _decoded_andMatrixOutputs_T_33 = cat(decoded_andMatrixOutputs_hi_33, decoded_andMatrixOutputs_lo_33) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_33) node decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_7_32, decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_5_32, decoded_andMatrixOutputs_andMatrixInput_6_32) node decoded_andMatrixOutputs_lo_34 = cat(decoded_andMatrixOutputs_lo_hi_32, decoded_andMatrixOutputs_lo_lo_32) node decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_hi_30, decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_andMatrixOutputs_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_32, decoded_andMatrixOutputs_hi_lo_32) node _decoded_andMatrixOutputs_T_34 = cat(decoded_andMatrixOutputs_hi_34, decoded_andMatrixOutputs_lo_34) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_34) node decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_7_33, decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_5_33, decoded_andMatrixOutputs_andMatrixInput_6_33) node decoded_andMatrixOutputs_lo_35 = cat(decoded_andMatrixOutputs_lo_hi_33, decoded_andMatrixOutputs_lo_lo_33) node decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_hi_31, decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_andMatrixOutputs_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_33, decoded_andMatrixOutputs_hi_lo_33) node _decoded_andMatrixOutputs_T_35 = cat(decoded_andMatrixOutputs_hi_35, decoded_andMatrixOutputs_lo_35) node decoded_andMatrixOutputs_23_2 = andr(_decoded_andMatrixOutputs_T_35) node decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_7_34, decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_5_34, decoded_andMatrixOutputs_andMatrixInput_6_34) node decoded_andMatrixOutputs_lo_36 = cat(decoded_andMatrixOutputs_lo_hi_34, decoded_andMatrixOutputs_lo_lo_34) node decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_hi_32, decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_andMatrixOutputs_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_34, decoded_andMatrixOutputs_hi_lo_34) node _decoded_andMatrixOutputs_T_36 = cat(decoded_andMatrixOutputs_hi_36, decoded_andMatrixOutputs_lo_36) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_36) node decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_7_35, decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_5_35, decoded_andMatrixOutputs_andMatrixInput_6_35) node decoded_andMatrixOutputs_lo_37 = cat(decoded_andMatrixOutputs_lo_hi_35, decoded_andMatrixOutputs_lo_lo_35) node decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_hi_33, decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_andMatrixOutputs_hi_37 = cat(decoded_andMatrixOutputs_hi_hi_35, decoded_andMatrixOutputs_hi_lo_35) node _decoded_andMatrixOutputs_T_37 = cat(decoded_andMatrixOutputs_hi_37, decoded_andMatrixOutputs_lo_37) node decoded_andMatrixOutputs_19_2 = andr(_decoded_andMatrixOutputs_T_37) node decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_7_36, decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_5_36, decoded_andMatrixOutputs_andMatrixInput_6_36) node decoded_andMatrixOutputs_lo_38 = cat(decoded_andMatrixOutputs_lo_hi_36, decoded_andMatrixOutputs_lo_lo_36) node decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_hi_34, decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_andMatrixOutputs_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_36, decoded_andMatrixOutputs_hi_lo_36) node _decoded_andMatrixOutputs_T_38 = cat(decoded_andMatrixOutputs_hi_38, decoded_andMatrixOutputs_lo_38) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_38) node decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_7_37, decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_5_37, decoded_andMatrixOutputs_andMatrixInput_6_37) node decoded_andMatrixOutputs_lo_39 = cat(decoded_andMatrixOutputs_lo_hi_37, decoded_andMatrixOutputs_lo_lo_37) node decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_andMatrixOutputs_hi_hi_hi_35, decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_andMatrixOutputs_hi_39 = cat(decoded_andMatrixOutputs_hi_hi_37, decoded_andMatrixOutputs_hi_lo_37) node _decoded_andMatrixOutputs_T_39 = cat(decoded_andMatrixOutputs_hi_39, decoded_andMatrixOutputs_lo_39) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_39) node decoded_orMatrixOutputs_lo = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_4_2) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_5_2, decoded_andMatrixOutputs_19_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_26_2, decoded_andMatrixOutputs_11_2) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_35_2, decoded_andMatrixOutputs_27_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_14_2, decoded_andMatrixOutputs_23_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_36_2, decoded_andMatrixOutputs_16_2) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_13_2, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_18_2) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_andMatrixOutputs_24_2) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_andMatrixOutputs_32_2, decoded_andMatrixOutputs_17_2) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_andMatrixOutputs_15_2, decoded_andMatrixOutputs_31_2) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_andMatrixOutputs_20_2) node decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_andMatrixOutputs_21_2, decoded_andMatrixOutputs_33_2) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_39_2) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_andMatrixOutputs_37_2, decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_andMatrixOutputs_30_2) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_28_2) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_andMatrixOutputs_2_2) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_22_2) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_andMatrixOutputs_29_2) node decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_34_2) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_38_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_1, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_1, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 3, 0) node _decoded_T_1 = bits(_decoded_T, 1, 0) node _decoded_T_2 = bits(_decoded_T_1, 0, 0) node _decoded_T_3 = bits(_decoded_T_1, 1, 1) node _decoded_T_4 = cat(_decoded_T_2, _decoded_T_3) node _decoded_T_5 = bits(_decoded_T, 3, 2) node _decoded_T_6 = bits(_decoded_T_5, 0, 0) node _decoded_T_7 = bits(_decoded_T_5, 1, 1) node _decoded_T_8 = cat(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = cat(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(decoded_plaOutput, 5, 4) node _decoded_T_11 = bits(_decoded_T_10, 0, 0) node _decoded_T_12 = bits(_decoded_T_10, 1, 1) node _decoded_T_13 = cat(_decoded_T_11, _decoded_T_12) node decoded = cat(_decoded_T_9, _decoded_T_13) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<17> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<6> node decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_10_24, decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_andMatrixOutputs_lo_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_12_18) node decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_7_38, decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_andMatrixOutputs_lo_hi_hi_24, decoded_andMatrixOutputs_andMatrixInput_9_24) node decoded_andMatrixOutputs_lo_40 = cat(decoded_andMatrixOutputs_lo_hi_38, decoded_andMatrixOutputs_lo_lo_38) node decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_4_38, decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_andMatrixOutputs_hi_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_6_38) node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_2_40, decoded_andMatrixOutputs_andMatrixInput_3_40) node decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_hi_36, decoded_andMatrixOutputs_hi_hi_lo_18) node decoded_andMatrixOutputs_hi_40 = cat(decoded_andMatrixOutputs_hi_hi_38, decoded_andMatrixOutputs_hi_lo_38) node _decoded_andMatrixOutputs_T_40 = cat(decoded_andMatrixOutputs_hi_40, decoded_andMatrixOutputs_lo_40) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_40) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_2, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 5, 5) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_14 = bits(decoded_plaOutput_1, 3, 0) node _decoded_T_15 = bits(_decoded_T_14, 1, 0) node _decoded_T_16 = bits(_decoded_T_15, 0, 0) node _decoded_T_17 = bits(_decoded_T_15, 1, 1) node _decoded_T_18 = cat(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = bits(_decoded_T_14, 3, 2) node _decoded_T_20 = bits(_decoded_T_19, 0, 0) node _decoded_T_21 = bits(_decoded_T_19, 1, 1) node _decoded_T_22 = cat(_decoded_T_20, _decoded_T_21) node _decoded_T_23 = cat(_decoded_T_18, _decoded_T_22) node _decoded_T_24 = bits(decoded_plaOutput_1, 5, 4) node _decoded_T_25 = bits(_decoded_T_24, 0, 0) node _decoded_T_26 = bits(_decoded_T_24, 1, 1) node _decoded_T_27 = cat(_decoded_T_25, _decoded_T_26) node decoded_1 = cat(_decoded_T_23, _decoded_T_27) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<17> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<6> node _decoded_orMatrixOutputs_T_13 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_hi_3 = cat(_decoded_orMatrixOutputs_T_13, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_2, 5, 5) node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_28 = bits(decoded_plaOutput_2, 3, 0) node _decoded_T_29 = bits(_decoded_T_28, 1, 0) node _decoded_T_30 = bits(_decoded_T_29, 0, 0) node _decoded_T_31 = bits(_decoded_T_29, 1, 1) node _decoded_T_32 = cat(_decoded_T_30, _decoded_T_31) node _decoded_T_33 = bits(_decoded_T_28, 3, 2) node _decoded_T_34 = bits(_decoded_T_33, 0, 0) node _decoded_T_35 = bits(_decoded_T_33, 1, 1) node _decoded_T_36 = cat(_decoded_T_34, _decoded_T_35) node _decoded_T_37 = cat(_decoded_T_32, _decoded_T_36) node _decoded_T_38 = bits(decoded_plaOutput_2, 5, 4) node _decoded_T_39 = bits(_decoded_T_38, 0, 0) node _decoded_T_40 = bits(_decoded_T_38, 1, 1) node _decoded_T_41 = cat(_decoded_T_39, _decoded_T_40) node decoded_2 = cat(_decoded_T_37, _decoded_T_41) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T connect io.resp.`2`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_20 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20

module RouteComputer_2( // @[RouteComputer.scala:29:7] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_5 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [25:0] _decoded_orMatrixOutputs_T_10 = {&{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_3 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_4 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_5 = &{~(io_req_1_bits_flow_egress_node_id[1]), io_req_1_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :98:{53,70}] assign io_resp_0_vc_sel_0_0 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_0_1 = |{&{decoded_invInputs[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_2 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_3 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_4 = |{&{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}, &{decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_5 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}, &{decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[21] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[10]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[11]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[12]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[13]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[14]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[15]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[16]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[17]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[18]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[19]) node source_ok = or(_source_ok_T_59, _source_ok_WIRE[20]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = and(_T_11, _T_24) node _T_193 = and(_T_192, _T_37) node _T_194 = and(_T_193, _T_50) node _T_195 = and(_T_194, _T_63) node _T_196 = and(_T_195, _T_71) node _T_197 = and(_T_196, _T_79) node _T_198 = and(_T_197, _T_87) node _T_199 = and(_T_198, _T_95) node _T_200 = and(_T_199, _T_103) node _T_201 = and(_T_200, _T_111) node _T_202 = and(_T_201, _T_119) node _T_203 = and(_T_202, _T_127) node _T_204 = and(_T_203, _T_135) node _T_205 = and(_T_204, _T_143) node _T_206 = and(_T_205, _T_151) node _T_207 = and(_T_206, _T_159) node _T_208 = and(_T_207, _T_167) node _T_209 = and(_T_208, _T_175) node _T_210 = and(_T_209, _T_183) node _T_211 = and(_T_210, _T_191) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_211, UInt<1>(0h1), "") : assert_1 node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_215 : node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_4) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<1>(0h1)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_5) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h2)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_6) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_238 = shr(io.in.a.bits.source, 2) node _T_239 = eq(_T_238, UInt<2>(0h3)) node _T_240 = leq(UInt<1>(0h0), uncommonBits_7) node _T_241 = and(_T_239, _T_240) node _T_242 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_249 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_250 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_251 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_252 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_253 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_257 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_258 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_259 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_260 = or(_T_219, _T_225) node _T_261 = or(_T_260, _T_231) node _T_262 = or(_T_261, _T_237) node _T_263 = or(_T_262, _T_243) node _T_264 = or(_T_263, _T_244) node _T_265 = or(_T_264, _T_245) node _T_266 = or(_T_265, _T_246) node _T_267 = or(_T_266, _T_247) node _T_268 = or(_T_267, _T_248) node _T_269 = or(_T_268, _T_249) node _T_270 = or(_T_269, _T_250) node _T_271 = or(_T_270, _T_251) node _T_272 = or(_T_271, _T_252) node _T_273 = or(_T_272, _T_253) node _T_274 = or(_T_273, _T_254) node _T_275 = or(_T_274, _T_255) node _T_276 = or(_T_275, _T_256) node _T_277 = or(_T_276, _T_257) node _T_278 = or(_T_277, _T_258) node _T_279 = or(_T_278, _T_259) node _T_280 = and(_T_218, _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<17>(0h100c0))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_290 = cvt(_T_289) node _T_291 = and(_T_290, asSInt(UInt<29>(0h100000c0))) node _T_292 = asSInt(_T_291) node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0))) node _T_294 = or(_T_288, _T_293) node _T_295 = and(_T_283, _T_294) node _T_296 = or(UInt<1>(0h0), _T_295) node _T_297 = and(_T_281, _T_296) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_297, UInt<1>(0h1), "") : assert_2 node _T_301 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_302 = shr(io.in.a.bits.source, 2) node _T_303 = eq(_T_302, UInt<1>(0h0)) node _T_304 = leq(UInt<1>(0h0), uncommonBits_8) node _T_305 = and(_T_303, _T_304) node _T_306 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_307 = and(_T_305, _T_306) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_308 = shr(io.in.a.bits.source, 2) node _T_309 = eq(_T_308, UInt<1>(0h1)) node _T_310 = leq(UInt<1>(0h0), uncommonBits_9) node _T_311 = and(_T_309, _T_310) node _T_312 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_313 = and(_T_311, _T_312) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_314 = shr(io.in.a.bits.source, 2) node _T_315 = eq(_T_314, UInt<2>(0h2)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_10) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_319 = and(_T_317, _T_318) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_320 = shr(io.in.a.bits.source, 2) node _T_321 = eq(_T_320, UInt<2>(0h3)) node _T_322 = leq(UInt<1>(0h0), uncommonBits_11) node _T_323 = and(_T_321, _T_322) node _T_324 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_325 = and(_T_323, _T_324) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[21] connect _WIRE[0], _T_301 connect _WIRE[1], _T_307 connect _WIRE[2], _T_313 connect _WIRE[3], _T_319 connect _WIRE[4], _T_325 connect _WIRE[5], _T_326 connect _WIRE[6], _T_327 connect _WIRE[7], _T_328 connect _WIRE[8], _T_329 connect _WIRE[9], _T_330 connect _WIRE[10], _T_331 connect _WIRE[11], _T_332 connect _WIRE[12], _T_333 connect _WIRE[13], _T_334 connect _WIRE[14], _T_335 connect _WIRE[15], _T_336 connect _WIRE[16], _T_337 connect _WIRE[17], _T_338 connect _WIRE[18], _T_339 connect _WIRE[19], _T_340 connect _WIRE[20], _T_341 node _T_342 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_343 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_344 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_345 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_346 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_347 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_349 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_350 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE[5], _T_342, UInt<1>(0h0)) node _T_356 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE[7], _T_343, UInt<1>(0h0)) node _T_358 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE[9], _T_344, UInt<1>(0h0)) node _T_360 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE[11], _T_345, UInt<1>(0h0)) node _T_362 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE[13], _T_346, UInt<1>(0h0)) node _T_364 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE[15], _T_347, UInt<1>(0h0)) node _T_366 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_367 = mux(_WIRE[17], _T_348, UInt<1>(0h0)) node _T_368 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_369 = mux(_WIRE[19], _T_349, UInt<1>(0h0)) node _T_370 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_371 = or(_T_350, _T_351) node _T_372 = or(_T_371, _T_352) node _T_373 = or(_T_372, _T_353) node _T_374 = or(_T_373, _T_354) node _T_375 = or(_T_374, _T_355) node _T_376 = or(_T_375, _T_356) node _T_377 = or(_T_376, _T_357) node _T_378 = or(_T_377, _T_358) node _T_379 = or(_T_378, _T_359) node _T_380 = or(_T_379, _T_360) node _T_381 = or(_T_380, _T_361) node _T_382 = or(_T_381, _T_362) node _T_383 = or(_T_382, _T_363) node _T_384 = or(_T_383, _T_364) node _T_385 = or(_T_384, _T_365) node _T_386 = or(_T_385, _T_366) node _T_387 = or(_T_386, _T_367) node _T_388 = or(_T_387, _T_368) node _T_389 = or(_T_388, _T_369) node _T_390 = or(_T_389, _T_370) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_390 node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h100c0))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<29>(0h100000c0))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = or(_T_399, _T_404) node _T_406 = and(_T_394, _T_405) node _T_407 = or(UInt<1>(0h0), _T_406) node _T_408 = and(_WIRE_1, _T_407) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_408, UInt<1>(0h1), "") : assert_3 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(source_ok, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_415, UInt<1>(0h1), "") : assert_5 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_422, UInt<1>(0h1), "") : assert_7 node _T_426 = not(io.in.a.bits.mask) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_427, UInt<1>(0h1), "") : assert_8 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_431, UInt<1>(0h1), "") : assert_9 node _T_435 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_12) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<1>(0h1)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_13) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_452 = shr(io.in.a.bits.source, 2) node _T_453 = eq(_T_452, UInt<2>(0h2)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_14) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<2>(0h3)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_15) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_473 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_480 = or(_T_439, _T_445) node _T_481 = or(_T_480, _T_451) node _T_482 = or(_T_481, _T_457) node _T_483 = or(_T_482, _T_463) node _T_484 = or(_T_483, _T_464) node _T_485 = or(_T_484, _T_465) node _T_486 = or(_T_485, _T_466) node _T_487 = or(_T_486, _T_467) node _T_488 = or(_T_487, _T_468) node _T_489 = or(_T_488, _T_469) node _T_490 = or(_T_489, _T_470) node _T_491 = or(_T_490, _T_471) node _T_492 = or(_T_491, _T_472) node _T_493 = or(_T_492, _T_473) node _T_494 = or(_T_493, _T_474) node _T_495 = or(_T_494, _T_475) node _T_496 = or(_T_495, _T_476) node _T_497 = or(_T_496, _T_477) node _T_498 = or(_T_497, _T_478) node _T_499 = or(_T_498, _T_479) node _T_500 = and(_T_438, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<17>(0h100c0))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<29>(0h100000c0))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = or(_T_508, _T_513) node _T_515 = and(_T_503, _T_514) node _T_516 = or(UInt<1>(0h0), _T_515) node _T_517 = and(_T_501, _T_516) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_517, UInt<1>(0h1), "") : assert_10 node _T_521 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<1>(0h0)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_16) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<1>(0h1)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_17) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_533 = and(_T_531, _T_532) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_534 = shr(io.in.a.bits.source, 2) node _T_535 = eq(_T_534, UInt<2>(0h2)) node _T_536 = leq(UInt<1>(0h0), uncommonBits_18) node _T_537 = and(_T_535, _T_536) node _T_538 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_539 = and(_T_537, _T_538) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_540 = shr(io.in.a.bits.source, 2) node _T_541 = eq(_T_540, UInt<2>(0h3)) node _T_542 = leq(UInt<1>(0h0), uncommonBits_19) node _T_543 = and(_T_541, _T_542) node _T_544 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_545 = and(_T_543, _T_544) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_547 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_548 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_549 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_550 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_551 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_552 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_553 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_554 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_557 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_558 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_559 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_560 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_561 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[21] connect _WIRE_2[0], _T_521 connect _WIRE_2[1], _T_527 connect _WIRE_2[2], _T_533 connect _WIRE_2[3], _T_539 connect _WIRE_2[4], _T_545 connect _WIRE_2[5], _T_546 connect _WIRE_2[6], _T_547 connect _WIRE_2[7], _T_548 connect _WIRE_2[8], _T_549 connect _WIRE_2[9], _T_550 connect _WIRE_2[10], _T_551 connect _WIRE_2[11], _T_552 connect _WIRE_2[12], _T_553 connect _WIRE_2[13], _T_554 connect _WIRE_2[14], _T_555 connect _WIRE_2[15], _T_556 connect _WIRE_2[16], _T_557 connect _WIRE_2[17], _T_558 connect _WIRE_2[18], _T_559 connect _WIRE_2[19], _T_560 connect _WIRE_2[20], _T_561 node _T_562 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_563 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_564 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_565 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_566 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_567 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_568 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_569 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_570 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_572 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_573 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_574 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_575 = mux(_WIRE_2[5], _T_562, UInt<1>(0h0)) node _T_576 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_577 = mux(_WIRE_2[7], _T_563, UInt<1>(0h0)) node _T_578 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_579 = mux(_WIRE_2[9], _T_564, UInt<1>(0h0)) node _T_580 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_581 = mux(_WIRE_2[11], _T_565, UInt<1>(0h0)) node _T_582 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_583 = mux(_WIRE_2[13], _T_566, UInt<1>(0h0)) node _T_584 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_585 = mux(_WIRE_2[15], _T_567, UInt<1>(0h0)) node _T_586 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_587 = mux(_WIRE_2[17], _T_568, UInt<1>(0h0)) node _T_588 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_589 = mux(_WIRE_2[19], _T_569, UInt<1>(0h0)) node _T_590 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_591 = or(_T_570, _T_571) node _T_592 = or(_T_591, _T_572) node _T_593 = or(_T_592, _T_573) node _T_594 = or(_T_593, _T_574) node _T_595 = or(_T_594, _T_575) node _T_596 = or(_T_595, _T_576) node _T_597 = or(_T_596, _T_577) node _T_598 = or(_T_597, _T_578) node _T_599 = or(_T_598, _T_579) node _T_600 = or(_T_599, _T_580) node _T_601 = or(_T_600, _T_581) node _T_602 = or(_T_601, _T_582) node _T_603 = or(_T_602, _T_583) node _T_604 = or(_T_603, _T_584) node _T_605 = or(_T_604, _T_585) node _T_606 = or(_T_605, _T_586) node _T_607 = or(_T_606, _T_587) node _T_608 = or(_T_607, _T_588) node _T_609 = or(_T_608, _T_589) node _T_610 = or(_T_609, _T_590) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_610 node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_613 = and(_T_611, _T_612) node _T_614 = or(UInt<1>(0h0), _T_613) node _T_615 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<17>(0h100c0))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<29>(0h100000c0))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = or(_T_619, _T_624) node _T_626 = and(_T_614, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = and(_WIRE_3, _T_627) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_628, UInt<1>(0h1), "") : assert_11 node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(source_ok, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_635 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_635, UInt<1>(0h1), "") : assert_13 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_642 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_642, UInt<1>(0h1), "") : assert_15 node _T_646 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_646, UInt<1>(0h1), "") : assert_16 node _T_650 = not(io.in.a.bits.mask) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_651, UInt<1>(0h1), "") : assert_17 node _T_655 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_655, UInt<1>(0h1), "") : assert_18 node _T_659 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_659 : node _T_660 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_661 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_662 = and(_T_660, _T_661) node _T_663 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_20) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_670 = shr(io.in.a.bits.source, 2) node _T_671 = eq(_T_670, UInt<1>(0h1)) node _T_672 = leq(UInt<1>(0h0), uncommonBits_21) node _T_673 = and(_T_671, _T_672) node _T_674 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_675 = and(_T_673, _T_674) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_676 = shr(io.in.a.bits.source, 2) node _T_677 = eq(_T_676, UInt<2>(0h2)) node _T_678 = leq(UInt<1>(0h0), uncommonBits_22) node _T_679 = and(_T_677, _T_678) node _T_680 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_681 = and(_T_679, _T_680) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<2>(0h3)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_23) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_702 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_703 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_704 = or(_T_663, _T_669) node _T_705 = or(_T_704, _T_675) node _T_706 = or(_T_705, _T_681) node _T_707 = or(_T_706, _T_687) node _T_708 = or(_T_707, _T_688) node _T_709 = or(_T_708, _T_689) node _T_710 = or(_T_709, _T_690) node _T_711 = or(_T_710, _T_691) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_693) node _T_714 = or(_T_713, _T_694) node _T_715 = or(_T_714, _T_695) node _T_716 = or(_T_715, _T_696) node _T_717 = or(_T_716, _T_697) node _T_718 = or(_T_717, _T_698) node _T_719 = or(_T_718, _T_699) node _T_720 = or(_T_719, _T_700) node _T_721 = or(_T_720, _T_701) node _T_722 = or(_T_721, _T_702) node _T_723 = or(_T_722, _T_703) node _T_724 = and(_T_662, _T_723) node _T_725 = or(UInt<1>(0h0), _T_724) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_725, UInt<1>(0h1), "") : assert_19 node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<17>(0h100c0))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h100000c0))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_737, _T_742) node _T_744 = and(_T_732, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_745, UInt<1>(0h1), "") : assert_20 node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(source_ok, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(is_aligned, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_755 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_755, UInt<1>(0h1), "") : assert_23 node _T_759 = eq(io.in.a.bits.mask, mask) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_759, UInt<1>(0h1), "") : assert_24 node _T_763 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_763, UInt<1>(0h1), "") : assert_25 node _T_767 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_767 : node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_770 = and(_T_768, _T_769) node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_24) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_25) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_26) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_27) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_806 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_809 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_810 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_811 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_812 = or(_T_771, _T_777) node _T_813 = or(_T_812, _T_783) node _T_814 = or(_T_813, _T_789) node _T_815 = or(_T_814, _T_795) node _T_816 = or(_T_815, _T_796) node _T_817 = or(_T_816, _T_797) node _T_818 = or(_T_817, _T_798) node _T_819 = or(_T_818, _T_799) node _T_820 = or(_T_819, _T_800) node _T_821 = or(_T_820, _T_801) node _T_822 = or(_T_821, _T_802) node _T_823 = or(_T_822, _T_803) node _T_824 = or(_T_823, _T_804) node _T_825 = or(_T_824, _T_805) node _T_826 = or(_T_825, _T_806) node _T_827 = or(_T_826, _T_807) node _T_828 = or(_T_827, _T_808) node _T_829 = or(_T_828, _T_809) node _T_830 = or(_T_829, _T_810) node _T_831 = or(_T_830, _T_811) node _T_832 = and(_T_770, _T_831) node _T_833 = or(UInt<1>(0h0), _T_832) node _T_834 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_835 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_836 = and(_T_834, _T_835) node _T_837 = or(UInt<1>(0h0), _T_836) node _T_838 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<17>(0h100c0))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<29>(0h100000c0))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = or(_T_842, _T_847) node _T_849 = and(_T_837, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = and(_T_833, _T_850) node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(_T_851, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_851, UInt<1>(0h1), "") : assert_26 node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(source_ok, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(is_aligned, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_861 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_861, UInt<1>(0h1), "") : assert_29 node _T_865 = eq(io.in.a.bits.mask, mask) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_865, UInt<1>(0h1), "") : assert_30 node _T_869 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_869 : node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_872 = and(_T_870, _T_871) node _T_873 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<1>(0h0)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_28) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h1)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_29) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_886 = shr(io.in.a.bits.source, 2) node _T_887 = eq(_T_886, UInt<2>(0h2)) node _T_888 = leq(UInt<1>(0h0), uncommonBits_30) node _T_889 = and(_T_887, _T_888) node _T_890 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_891 = and(_T_889, _T_890) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_892 = shr(io.in.a.bits.source, 2) node _T_893 = eq(_T_892, UInt<2>(0h3)) node _T_894 = leq(UInt<1>(0h0), uncommonBits_31) node _T_895 = and(_T_893, _T_894) node _T_896 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_897 = and(_T_895, _T_896) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_902 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_903 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_904 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_911 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_912 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_913 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_914 = or(_T_873, _T_879) node _T_915 = or(_T_914, _T_885) node _T_916 = or(_T_915, _T_891) node _T_917 = or(_T_916, _T_897) node _T_918 = or(_T_917, _T_898) node _T_919 = or(_T_918, _T_899) node _T_920 = or(_T_919, _T_900) node _T_921 = or(_T_920, _T_901) node _T_922 = or(_T_921, _T_902) node _T_923 = or(_T_922, _T_903) node _T_924 = or(_T_923, _T_904) node _T_925 = or(_T_924, _T_905) node _T_926 = or(_T_925, _T_906) node _T_927 = or(_T_926, _T_907) node _T_928 = or(_T_927, _T_908) node _T_929 = or(_T_928, _T_909) node _T_930 = or(_T_929, _T_910) node _T_931 = or(_T_930, _T_911) node _T_932 = or(_T_931, _T_912) node _T_933 = or(_T_932, _T_913) node _T_934 = and(_T_872, _T_933) node _T_935 = or(UInt<1>(0h0), _T_934) node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_938 = and(_T_936, _T_937) node _T_939 = or(UInt<1>(0h0), _T_938) node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<17>(0h100c0))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<29>(0h100000c0))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_944, _T_949) node _T_951 = and(_T_939, _T_950) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = and(_T_935, _T_952) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_953, UInt<1>(0h1), "") : assert_31 node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(source_ok, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(is_aligned, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_963 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_963, UInt<1>(0h1), "") : assert_34 node _T_967 = not(mask) node _T_968 = and(io.in.a.bits.mask, _T_967) node _T_969 = eq(_T_968, UInt<1>(0h0)) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_969, UInt<1>(0h1), "") : assert_35 node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_973 : node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_976 = and(_T_974, _T_975) node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<1>(0h0)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_32) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<1>(0h1)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_33) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_990 = shr(io.in.a.bits.source, 2) node _T_991 = eq(_T_990, UInt<2>(0h2)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_34) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<2>(0h3)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_35) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1018 = or(_T_977, _T_983) node _T_1019 = or(_T_1018, _T_989) node _T_1020 = or(_T_1019, _T_995) node _T_1021 = or(_T_1020, _T_1001) node _T_1022 = or(_T_1021, _T_1002) node _T_1023 = or(_T_1022, _T_1003) node _T_1024 = or(_T_1023, _T_1004) node _T_1025 = or(_T_1024, _T_1005) node _T_1026 = or(_T_1025, _T_1006) node _T_1027 = or(_T_1026, _T_1007) node _T_1028 = or(_T_1027, _T_1008) node _T_1029 = or(_T_1028, _T_1009) node _T_1030 = or(_T_1029, _T_1010) node _T_1031 = or(_T_1030, _T_1011) node _T_1032 = or(_T_1031, _T_1012) node _T_1033 = or(_T_1032, _T_1013) node _T_1034 = or(_T_1033, _T_1014) node _T_1035 = or(_T_1034, _T_1015) node _T_1036 = or(_T_1035, _T_1016) node _T_1037 = or(_T_1036, _T_1017) node _T_1038 = and(_T_976, _T_1037) node _T_1039 = or(UInt<1>(0h0), _T_1038) node _T_1040 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1041 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = or(UInt<1>(0h0), _T_1042) node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<17>(0h100c0))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<29>(0h100000c0))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = or(_T_1048, _T_1053) node _T_1055 = and(_T_1043, _T_1054) node _T_1056 = or(UInt<1>(0h0), _T_1055) node _T_1057 = and(_T_1039, _T_1056) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_36 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(source_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(is_aligned, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_39 node _T_1071 = eq(io.in.a.bits.mask, mask) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_40 node _T_1075 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1075 : node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1080 = shr(io.in.a.bits.source, 2) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) node _T_1082 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1085 = and(_T_1083, _T_1084) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1086 = shr(io.in.a.bits.source, 2) node _T_1087 = eq(_T_1086, UInt<1>(0h1)) node _T_1088 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1091 = and(_T_1089, _T_1090) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1092 = shr(io.in.a.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1098 = shr(io.in.a.bits.source, 2) node _T_1099 = eq(_T_1098, UInt<2>(0h3)) node _T_1100 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1103 = and(_T_1101, _T_1102) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1120 = or(_T_1079, _T_1085) node _T_1121 = or(_T_1120, _T_1091) node _T_1122 = or(_T_1121, _T_1097) node _T_1123 = or(_T_1122, _T_1103) node _T_1124 = or(_T_1123, _T_1104) node _T_1125 = or(_T_1124, _T_1105) node _T_1126 = or(_T_1125, _T_1106) node _T_1127 = or(_T_1126, _T_1107) node _T_1128 = or(_T_1127, _T_1108) node _T_1129 = or(_T_1128, _T_1109) node _T_1130 = or(_T_1129, _T_1110) node _T_1131 = or(_T_1130, _T_1111) node _T_1132 = or(_T_1131, _T_1112) node _T_1133 = or(_T_1132, _T_1113) node _T_1134 = or(_T_1133, _T_1114) node _T_1135 = or(_T_1134, _T_1115) node _T_1136 = or(_T_1135, _T_1116) node _T_1137 = or(_T_1136, _T_1117) node _T_1138 = or(_T_1137, _T_1118) node _T_1139 = or(_T_1138, _T_1119) node _T_1140 = and(_T_1078, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1140) node _T_1142 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1143 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _T_1145 = or(UInt<1>(0h0), _T_1144) node _T_1146 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1147 = cvt(_T_1146) node _T_1148 = and(_T_1147, asSInt(UInt<17>(0h100c0))) node _T_1149 = asSInt(_T_1148) node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0))) node _T_1151 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1152 = cvt(_T_1151) node _T_1153 = and(_T_1152, asSInt(UInt<29>(0h100000c0))) node _T_1154 = asSInt(_T_1153) node _T_1155 = eq(_T_1154, asSInt(UInt<1>(0h0))) node _T_1156 = or(_T_1150, _T_1155) node _T_1157 = and(_T_1145, _T_1156) node _T_1158 = or(UInt<1>(0h0), _T_1157) node _T_1159 = and(_T_1141, _T_1158) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_41 node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(source_ok, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(is_aligned, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1169 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_44 node _T_1173 = eq(io.in.a.bits.mask, mask) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_45 node _T_1177 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1177 : node _T_1178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1179 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1182 = shr(io.in.a.bits.source, 2) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) node _T_1184 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1185 = and(_T_1183, _T_1184) node _T_1186 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1187 = and(_T_1185, _T_1186) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1188 = shr(io.in.a.bits.source, 2) node _T_1189 = eq(_T_1188, UInt<1>(0h1)) node _T_1190 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1193 = and(_T_1191, _T_1192) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<2>(0h2)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<2>(0h3)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1207 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1208 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1209 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1210 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1211 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1212 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1213 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1214 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1215 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1216 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1219 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1220 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1221 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1222 = or(_T_1181, _T_1187) node _T_1223 = or(_T_1222, _T_1193) node _T_1224 = or(_T_1223, _T_1199) node _T_1225 = or(_T_1224, _T_1205) node _T_1226 = or(_T_1225, _T_1206) node _T_1227 = or(_T_1226, _T_1207) node _T_1228 = or(_T_1227, _T_1208) node _T_1229 = or(_T_1228, _T_1209) node _T_1230 = or(_T_1229, _T_1210) node _T_1231 = or(_T_1230, _T_1211) node _T_1232 = or(_T_1231, _T_1212) node _T_1233 = or(_T_1232, _T_1213) node _T_1234 = or(_T_1233, _T_1214) node _T_1235 = or(_T_1234, _T_1215) node _T_1236 = or(_T_1235, _T_1216) node _T_1237 = or(_T_1236, _T_1217) node _T_1238 = or(_T_1237, _T_1218) node _T_1239 = or(_T_1238, _T_1219) node _T_1240 = or(_T_1239, _T_1220) node _T_1241 = or(_T_1240, _T_1221) node _T_1242 = and(_T_1180, _T_1241) node _T_1243 = or(UInt<1>(0h0), _T_1242) node _T_1244 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1245 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1246 = and(_T_1244, _T_1245) node _T_1247 = or(UInt<1>(0h0), _T_1246) node _T_1248 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<17>(0h100c0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<29>(0h100000c0))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = or(_T_1252, _T_1257) node _T_1259 = and(_T_1247, _T_1258) node _T_1260 = or(UInt<1>(0h0), _T_1259) node _T_1261 = and(_T_1243, _T_1260) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_46 node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(source_ok, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(is_aligned, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1271 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_49 node _T_1275 = eq(io.in.a.bits.mask, mask) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_50 node _T_1279 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1283 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_52 node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[21] connect _source_ok_WIRE_1[0], _source_ok_T_60 connect _source_ok_WIRE_1[1], _source_ok_T_66 connect _source_ok_WIRE_1[2], _source_ok_T_72 connect _source_ok_WIRE_1[3], _source_ok_T_78 connect _source_ok_WIRE_1[4], _source_ok_T_84 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_86 connect _source_ok_WIRE_1[7], _source_ok_T_87 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 connect _source_ok_WIRE_1[11], _source_ok_T_91 connect _source_ok_WIRE_1[12], _source_ok_T_92 connect _source_ok_WIRE_1[13], _source_ok_T_93 connect _source_ok_WIRE_1[14], _source_ok_T_94 connect _source_ok_WIRE_1[15], _source_ok_T_95 connect _source_ok_WIRE_1[16], _source_ok_T_96 connect _source_ok_WIRE_1[17], _source_ok_T_97 connect _source_ok_WIRE_1[18], _source_ok_T_98 connect _source_ok_WIRE_1[19], _source_ok_T_99 connect _source_ok_WIRE_1[20], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[11]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[12]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[13]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[14]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[15]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[16]) node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[17]) node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[18]) node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[19]) node source_ok_1 = or(_source_ok_T_119, _source_ok_WIRE_1[20]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1287 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1287 : node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(source_ok_1, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1291 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_54 node _T_1295 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_55 node _T_1299 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_56 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_57 node _T_1307 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1307 : node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok_1, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(sink_ok, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1314 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_60 node _T_1318 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_61 node _T_1322 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_62 node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_63 node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1331 = or(UInt<1>(0h1), _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_64 node _T_1335 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1335 : node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(source_ok_1, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(sink_ok, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1342 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_67 node _T_1346 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(_T_1346, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1346, UInt<1>(0h1), "") : assert_68 node _T_1350 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_69 node _T_1354 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1355 = or(_T_1354, io.in.d.bits.corrupt) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_70 node _T_1359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1360 = or(UInt<1>(0h1), _T_1359) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_71 node _T_1364 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1364 : node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(source_ok_1, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1368 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_73 node _T_1372 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_74 node _T_1376 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1377 = or(UInt<1>(0h1), _T_1376) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_75 node _T_1381 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1381 : node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(source_ok_1, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1385 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_77 node _T_1389 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1390 = or(_T_1389, io.in.d.bits.corrupt) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_78 node _T_1394 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1395 = or(UInt<1>(0h1), _T_1394) node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(_T_1395, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1395, UInt<1>(0h1), "") : assert_79 node _T_1399 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1399 : node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(source_ok_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_81 node _T_1407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_82 node _T_1411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1412 = or(UInt<1>(0h1), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1416 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_84 node _T_1420 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) node _T_1422 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1423 = cvt(_T_1422) node _T_1424 = and(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = asSInt(_T_1424) node _T_1426 = eq(_T_1425, asSInt(UInt<1>(0h0))) node _T_1427 = or(_T_1421, _T_1426) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1428 = shr(io.in.b.bits.source, 2) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) node _T_1435 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<1>(0h0))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1434, _T_1439) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1441 = shr(io.in.b.bits.source, 2) node _T_1442 = eq(_T_1441, UInt<1>(0h1)) node _T_1443 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1444 = and(_T_1442, _T_1443) node _T_1445 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1446 = and(_T_1444, _T_1445) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) node _T_1448 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = or(_T_1447, _T_1452) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1454 = shr(io.in.b.bits.source, 2) node _T_1455 = eq(_T_1454, UInt<2>(0h2)) node _T_1456 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1457 = and(_T_1455, _T_1456) node _T_1458 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) node _T_1461 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = or(_T_1460, _T_1465) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1467 = shr(io.in.b.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<2>(0h3)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) node _T_1474 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = or(_T_1473, _T_1478) node _T_1480 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) node _T_1482 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<1>(0h0))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = or(_T_1481, _T_1486) node _T_1488 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) node _T_1490 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1491 = cvt(_T_1490) node _T_1492 = and(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = asSInt(_T_1492) node _T_1494 = eq(_T_1493, asSInt(UInt<1>(0h0))) node _T_1495 = or(_T_1489, _T_1494) node _T_1496 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) node _T_1498 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = or(_T_1497, _T_1502) node _T_1504 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) node _T_1506 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<1>(0h0))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = or(_T_1505, _T_1510) node _T_1512 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) node _T_1514 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1515 = cvt(_T_1514) node _T_1516 = and(_T_1515, asSInt(UInt<1>(0h0))) node _T_1517 = asSInt(_T_1516) node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0))) node _T_1519 = or(_T_1513, _T_1518) node _T_1520 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1523 = cvt(_T_1522) node _T_1524 = and(_T_1523, asSInt(UInt<1>(0h0))) node _T_1525 = asSInt(_T_1524) node _T_1526 = eq(_T_1525, asSInt(UInt<1>(0h0))) node _T_1527 = or(_T_1521, _T_1526) node _T_1528 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) node _T_1530 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1531 = cvt(_T_1530) node _T_1532 = and(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = asSInt(_T_1532) node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0))) node _T_1535 = or(_T_1529, _T_1534) node _T_1536 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) node _T_1538 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1537, _T_1542) node _T_1544 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) node _T_1546 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1547 = cvt(_T_1546) node _T_1548 = and(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = asSInt(_T_1548) node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0))) node _T_1551 = or(_T_1545, _T_1550) node _T_1552 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) node _T_1554 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<1>(0h0))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = or(_T_1553, _T_1558) node _T_1560 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) node _T_1562 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1563 = cvt(_T_1562) node _T_1564 = and(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = asSInt(_T_1564) node _T_1566 = eq(_T_1565, asSInt(UInt<1>(0h0))) node _T_1567 = or(_T_1561, _T_1566) node _T_1568 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) node _T_1570 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1571 = cvt(_T_1570) node _T_1572 = and(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = asSInt(_T_1572) node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0))) node _T_1575 = or(_T_1569, _T_1574) node _T_1576 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) node _T_1578 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = or(_T_1577, _T_1582) node _T_1584 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) node _T_1586 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1587 = cvt(_T_1586) node _T_1588 = and(_T_1587, asSInt(UInt<1>(0h0))) node _T_1589 = asSInt(_T_1588) node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0))) node _T_1591 = or(_T_1585, _T_1590) node _T_1592 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) node _T_1594 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1595 = cvt(_T_1594) node _T_1596 = and(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = asSInt(_T_1596) node _T_1598 = eq(_T_1597, asSInt(UInt<1>(0h0))) node _T_1599 = or(_T_1593, _T_1598) node _T_1600 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) node _T_1602 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<1>(0h0))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = or(_T_1601, _T_1606) node _T_1608 = and(_T_1427, _T_1440) node _T_1609 = and(_T_1608, _T_1453) node _T_1610 = and(_T_1609, _T_1466) node _T_1611 = and(_T_1610, _T_1479) node _T_1612 = and(_T_1611, _T_1487) node _T_1613 = and(_T_1612, _T_1495) node _T_1614 = and(_T_1613, _T_1503) node _T_1615 = and(_T_1614, _T_1511) node _T_1616 = and(_T_1615, _T_1519) node _T_1617 = and(_T_1616, _T_1527) node _T_1618 = and(_T_1617, _T_1535) node _T_1619 = and(_T_1618, _T_1543) node _T_1620 = and(_T_1619, _T_1551) node _T_1621 = and(_T_1620, _T_1559) node _T_1622 = and(_T_1621, _T_1567) node _T_1623 = and(_T_1622, _T_1575) node _T_1624 = and(_T_1623, _T_1583) node _T_1625 = and(_T_1624, _T_1591) node _T_1626 = and(_T_1625, _T_1599) node _T_1627 = and(_T_1626, _T_1607) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _legal_source_T_33 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_34 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_35 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_36 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_37 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_39 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_40 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[21] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 connect _legal_source_WIRE[13], _legal_source_T_33 connect _legal_source_WIRE[14], _legal_source_T_34 connect _legal_source_WIRE[15], _legal_source_T_35 connect _legal_source_WIRE[16], _legal_source_T_36 connect _legal_source_WIRE[17], _legal_source_T_37 connect _legal_source_WIRE[18], _legal_source_T_38 connect _legal_source_WIRE[19], _legal_source_T_39 connect _legal_source_WIRE[20], _legal_source_T_40 node _legal_source_T_41 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_46 = mux(_legal_source_WIRE[5], UInt<6>(0h3c), UInt<1>(0h0)) node _legal_source_T_47 = mux(_legal_source_WIRE[6], UInt<6>(0h3e), UInt<1>(0h0)) node _legal_source_T_48 = mux(_legal_source_WIRE[7], UInt<6>(0h38), UInt<1>(0h0)) node _legal_source_T_49 = mux(_legal_source_WIRE[8], UInt<6>(0h3a), UInt<1>(0h0)) node _legal_source_T_50 = mux(_legal_source_WIRE[9], UInt<6>(0h34), UInt<1>(0h0)) node _legal_source_T_51 = mux(_legal_source_WIRE[10], UInt<6>(0h36), UInt<1>(0h0)) node _legal_source_T_52 = mux(_legal_source_WIRE[11], UInt<6>(0h30), UInt<1>(0h0)) node _legal_source_T_53 = mux(_legal_source_WIRE[12], UInt<6>(0h32), UInt<1>(0h0)) node _legal_source_T_54 = mux(_legal_source_WIRE[13], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_55 = mux(_legal_source_WIRE[14], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_56 = mux(_legal_source_WIRE[15], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_57 = mux(_legal_source_WIRE[16], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_58 = mux(_legal_source_WIRE[17], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_59 = mux(_legal_source_WIRE[18], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_60 = mux(_legal_source_WIRE[19], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_61 = mux(_legal_source_WIRE[20], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_62 = or(_legal_source_T_41, _legal_source_T_42) node _legal_source_T_63 = or(_legal_source_T_62, _legal_source_T_43) node _legal_source_T_64 = or(_legal_source_T_63, _legal_source_T_44) node _legal_source_T_65 = or(_legal_source_T_64, _legal_source_T_45) node _legal_source_T_66 = or(_legal_source_T_65, _legal_source_T_46) node _legal_source_T_67 = or(_legal_source_T_66, _legal_source_T_47) node _legal_source_T_68 = or(_legal_source_T_67, _legal_source_T_48) node _legal_source_T_69 = or(_legal_source_T_68, _legal_source_T_49) node _legal_source_T_70 = or(_legal_source_T_69, _legal_source_T_50) node _legal_source_T_71 = or(_legal_source_T_70, _legal_source_T_51) node _legal_source_T_72 = or(_legal_source_T_71, _legal_source_T_52) node _legal_source_T_73 = or(_legal_source_T_72, _legal_source_T_53) node _legal_source_T_74 = or(_legal_source_T_73, _legal_source_T_54) node _legal_source_T_75 = or(_legal_source_T_74, _legal_source_T_55) node _legal_source_T_76 = or(_legal_source_T_75, _legal_source_T_56) node _legal_source_T_77 = or(_legal_source_T_76, _legal_source_T_57) node _legal_source_T_78 = or(_legal_source_T_77, _legal_source_T_58) node _legal_source_T_79 = or(_legal_source_T_78, _legal_source_T_59) node _legal_source_T_80 = or(_legal_source_T_79, _legal_source_T_60) node _legal_source_T_81 = or(_legal_source_T_80, _legal_source_T_61) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_81 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1631 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1631 : node _T_1632 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1633 = shr(io.in.b.bits.source, 2) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) node _T_1635 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1636 = and(_T_1634, _T_1635) node _T_1637 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1638 = and(_T_1636, _T_1637) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1639 = shr(io.in.b.bits.source, 2) node _T_1640 = eq(_T_1639, UInt<1>(0h1)) node _T_1641 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1642 = and(_T_1640, _T_1641) node _T_1643 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1644 = and(_T_1642, _T_1643) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1645 = shr(io.in.b.bits.source, 2) node _T_1646 = eq(_T_1645, UInt<2>(0h2)) node _T_1647 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1648 = and(_T_1646, _T_1647) node _T_1649 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1650 = and(_T_1648, _T_1649) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1651 = shr(io.in.b.bits.source, 2) node _T_1652 = eq(_T_1651, UInt<2>(0h3)) node _T_1653 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1654 = and(_T_1652, _T_1653) node _T_1655 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1656 = and(_T_1654, _T_1655) node _T_1657 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1658 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1659 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1660 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1661 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1662 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1663 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_1664 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_1665 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1666 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1667 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1669 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1670 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1671 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1672 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[21] connect _WIRE_4[0], _T_1632 connect _WIRE_4[1], _T_1638 connect _WIRE_4[2], _T_1644 connect _WIRE_4[3], _T_1650 connect _WIRE_4[4], _T_1656 connect _WIRE_4[5], _T_1657 connect _WIRE_4[6], _T_1658 connect _WIRE_4[7], _T_1659 connect _WIRE_4[8], _T_1660 connect _WIRE_4[9], _T_1661 connect _WIRE_4[10], _T_1662 connect _WIRE_4[11], _T_1663 connect _WIRE_4[12], _T_1664 connect _WIRE_4[13], _T_1665 connect _WIRE_4[14], _T_1666 connect _WIRE_4[15], _T_1667 connect _WIRE_4[16], _T_1668 connect _WIRE_4[17], _T_1669 connect _WIRE_4[18], _T_1670 connect _WIRE_4[19], _T_1671 connect _WIRE_4[20], _T_1672 node _T_1673 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1674 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1675 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1676 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1677 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1678 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1679 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1680 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1681 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1682 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1683 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1684 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1685 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1686 = mux(_WIRE_4[5], _T_1673, UInt<1>(0h0)) node _T_1687 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1688 = mux(_WIRE_4[7], _T_1674, UInt<1>(0h0)) node _T_1689 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1690 = mux(_WIRE_4[9], _T_1675, UInt<1>(0h0)) node _T_1691 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1692 = mux(_WIRE_4[11], _T_1676, UInt<1>(0h0)) node _T_1693 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1694 = mux(_WIRE_4[13], _T_1677, UInt<1>(0h0)) node _T_1695 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_1696 = mux(_WIRE_4[15], _T_1678, UInt<1>(0h0)) node _T_1697 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1698 = mux(_WIRE_4[17], _T_1679, UInt<1>(0h0)) node _T_1699 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1700 = mux(_WIRE_4[19], _T_1680, UInt<1>(0h0)) node _T_1701 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_1702 = or(_T_1681, _T_1682) node _T_1703 = or(_T_1702, _T_1683) node _T_1704 = or(_T_1703, _T_1684) node _T_1705 = or(_T_1704, _T_1685) node _T_1706 = or(_T_1705, _T_1686) node _T_1707 = or(_T_1706, _T_1687) node _T_1708 = or(_T_1707, _T_1688) node _T_1709 = or(_T_1708, _T_1689) node _T_1710 = or(_T_1709, _T_1690) node _T_1711 = or(_T_1710, _T_1691) node _T_1712 = or(_T_1711, _T_1692) node _T_1713 = or(_T_1712, _T_1693) node _T_1714 = or(_T_1713, _T_1694) node _T_1715 = or(_T_1714, _T_1695) node _T_1716 = or(_T_1715, _T_1696) node _T_1717 = or(_T_1716, _T_1697) node _T_1718 = or(_T_1717, _T_1698) node _T_1719 = or(_T_1718, _T_1699) node _T_1720 = or(_T_1719, _T_1700) node _T_1721 = or(_T_1720, _T_1701) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1721 node _T_1722 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1723 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1724 = and(_T_1722, _T_1723) node _T_1725 = or(UInt<1>(0h0), _T_1724) node _T_1726 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1727 = cvt(_T_1726) node _T_1728 = and(_T_1727, asSInt(UInt<17>(0h100c0))) node _T_1729 = asSInt(_T_1728) node _T_1730 = eq(_T_1729, asSInt(UInt<1>(0h0))) node _T_1731 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1732 = cvt(_T_1731) node _T_1733 = and(_T_1732, asSInt(UInt<29>(0h100000c0))) node _T_1734 = asSInt(_T_1733) node _T_1735 = eq(_T_1734, asSInt(UInt<1>(0h0))) node _T_1736 = or(_T_1730, _T_1735) node _T_1737 = and(_T_1725, _T_1736) node _T_1738 = or(UInt<1>(0h0), _T_1737) node _T_1739 = and(_WIRE_5, _T_1738) node _T_1740 = asUInt(reset) node _T_1741 = eq(_T_1740, UInt<1>(0h0)) when _T_1741 : node _T_1742 = eq(_T_1739, UInt<1>(0h0)) when _T_1742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1739, UInt<1>(0h1), "") : assert_86 node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(address_ok, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1746 = asUInt(reset) node _T_1747 = eq(_T_1746, UInt<1>(0h0)) when _T_1747 : node _T_1748 = eq(legal_source, UInt<1>(0h0)) when _T_1748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1752 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_90 node _T_1756 = eq(io.in.b.bits.mask, mask_1) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_91 node _T_1760 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1761 = asUInt(reset) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) when _T_1762 : node _T_1763 = eq(_T_1760, UInt<1>(0h0)) when _T_1763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1760, UInt<1>(0h1), "") : assert_92 node _T_1764 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1764 : node _T_1765 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1766 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1767 = and(_T_1765, _T_1766) node _T_1768 = or(UInt<1>(0h0), _T_1767) node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1770 = cvt(_T_1769) node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h100c0))) node _T_1772 = asSInt(_T_1771) node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0))) node _T_1774 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1775 = cvt(_T_1774) node _T_1776 = and(_T_1775, asSInt(UInt<29>(0h100000c0))) node _T_1777 = asSInt(_T_1776) node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = or(_T_1773, _T_1778) node _T_1780 = and(_T_1768, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = and(UInt<1>(0h0), _T_1781) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_93 node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(address_ok, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1789 = asUInt(reset) node _T_1790 = eq(_T_1789, UInt<1>(0h0)) when _T_1790 : node _T_1791 = eq(legal_source, UInt<1>(0h0)) when _T_1791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1795 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_97 node _T_1799 = eq(io.in.b.bits.mask, mask_1) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_98 node _T_1803 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(_T_1803, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1803, UInt<1>(0h1), "") : assert_99 node _T_1807 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1807 : node _T_1808 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1809 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1810 = and(_T_1808, _T_1809) node _T_1811 = or(UInt<1>(0h0), _T_1810) node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h100c0))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<29>(0h100000c0))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = or(_T_1816, _T_1821) node _T_1823 = and(_T_1811, _T_1822) node _T_1824 = or(UInt<1>(0h0), _T_1823) node _T_1825 = and(UInt<1>(0h0), _T_1824) node _T_1826 = asUInt(reset) node _T_1827 = eq(_T_1826, UInt<1>(0h0)) when _T_1827 : node _T_1828 = eq(_T_1825, UInt<1>(0h0)) when _T_1828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1825, UInt<1>(0h1), "") : assert_100 node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(address_ok, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1832 = asUInt(reset) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) when _T_1833 : node _T_1834 = eq(legal_source, UInt<1>(0h0)) when _T_1834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1838 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_104 node _T_1842 = eq(io.in.b.bits.mask, mask_1) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_105 node _T_1846 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1846 : node _T_1847 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1848 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = or(UInt<1>(0h0), _T_1849) node _T_1851 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1852 = cvt(_T_1851) node _T_1853 = and(_T_1852, asSInt(UInt<17>(0h100c0))) node _T_1854 = asSInt(_T_1853) node _T_1855 = eq(_T_1854, asSInt(UInt<1>(0h0))) node _T_1856 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1857 = cvt(_T_1856) node _T_1858 = and(_T_1857, asSInt(UInt<29>(0h100000c0))) node _T_1859 = asSInt(_T_1858) node _T_1860 = eq(_T_1859, asSInt(UInt<1>(0h0))) node _T_1861 = or(_T_1855, _T_1860) node _T_1862 = and(_T_1850, _T_1861) node _T_1863 = or(UInt<1>(0h0), _T_1862) node _T_1864 = and(UInt<1>(0h0), _T_1863) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_106 node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(address_ok, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(legal_source, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1874 = asUInt(reset) node _T_1875 = eq(_T_1874, UInt<1>(0h0)) when _T_1875 : node _T_1876 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1877 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1878 = asUInt(reset) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) when _T_1879 : node _T_1880 = eq(_T_1877, UInt<1>(0h0)) when _T_1880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1877, UInt<1>(0h1), "") : assert_110 node _T_1881 = not(mask_1) node _T_1882 = and(io.in.b.bits.mask, _T_1881) node _T_1883 = eq(_T_1882, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_111 node _T_1887 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1887 : node _T_1888 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1889 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1890 = and(_T_1888, _T_1889) node _T_1891 = or(UInt<1>(0h0), _T_1890) node _T_1892 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1893 = cvt(_T_1892) node _T_1894 = and(_T_1893, asSInt(UInt<17>(0h100c0))) node _T_1895 = asSInt(_T_1894) node _T_1896 = eq(_T_1895, asSInt(UInt<1>(0h0))) node _T_1897 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1898 = cvt(_T_1897) node _T_1899 = and(_T_1898, asSInt(UInt<29>(0h100000c0))) node _T_1900 = asSInt(_T_1899) node _T_1901 = eq(_T_1900, asSInt(UInt<1>(0h0))) node _T_1902 = or(_T_1896, _T_1901) node _T_1903 = and(_T_1891, _T_1902) node _T_1904 = or(UInt<1>(0h0), _T_1903) node _T_1905 = and(UInt<1>(0h0), _T_1904) node _T_1906 = asUInt(reset) node _T_1907 = eq(_T_1906, UInt<1>(0h0)) when _T_1907 : node _T_1908 = eq(_T_1905, UInt<1>(0h0)) when _T_1908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1905, UInt<1>(0h1), "") : assert_112 node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(address_ok, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1912 = asUInt(reset) node _T_1913 = eq(_T_1912, UInt<1>(0h0)) when _T_1913 : node _T_1914 = eq(legal_source, UInt<1>(0h0)) when _T_1914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1918 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(_T_1918, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1918, UInt<1>(0h1), "") : assert_116 node _T_1922 = eq(io.in.b.bits.mask, mask_1) node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(_T_1922, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1922, UInt<1>(0h1), "") : assert_117 node _T_1926 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1926 : node _T_1927 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1928 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1929 = and(_T_1927, _T_1928) node _T_1930 = or(UInt<1>(0h0), _T_1929) node _T_1931 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<17>(0h100c0))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h100000c0))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1935, _T_1940) node _T_1942 = and(_T_1930, _T_1941) node _T_1943 = or(UInt<1>(0h0), _T_1942) node _T_1944 = and(UInt<1>(0h0), _T_1943) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_118 node _T_1948 = asUInt(reset) node _T_1949 = eq(_T_1948, UInt<1>(0h0)) when _T_1949 : node _T_1950 = eq(address_ok, UInt<1>(0h0)) when _T_1950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1951 = asUInt(reset) node _T_1952 = eq(_T_1951, UInt<1>(0h0)) when _T_1952 : node _T_1953 = eq(legal_source, UInt<1>(0h0)) when _T_1953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1957 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_122 node _T_1961 = eq(io.in.b.bits.mask, mask_1) node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(_T_1961, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1961, UInt<1>(0h1), "") : assert_123 node _T_1965 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1965 : node _T_1966 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1967 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1968 = and(_T_1966, _T_1967) node _T_1969 = or(UInt<1>(0h0), _T_1968) node _T_1970 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<17>(0h100c0))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<29>(0h100000c0))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = or(_T_1974, _T_1979) node _T_1981 = and(_T_1969, _T_1980) node _T_1982 = or(UInt<1>(0h0), _T_1981) node _T_1983 = and(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_124 node _T_1987 = asUInt(reset) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) when _T_1988 : node _T_1989 = eq(address_ok, UInt<1>(0h0)) when _T_1989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(legal_source, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1993 = asUInt(reset) node _T_1994 = eq(_T_1993, UInt<1>(0h0)) when _T_1994 : node _T_1995 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1996 = eq(io.in.b.bits.mask, mask_1) node _T_1997 = asUInt(reset) node _T_1998 = eq(_T_1997, UInt<1>(0h0)) when _T_1998 : node _T_1999 = eq(_T_1996, UInt<1>(0h0)) when _T_1999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1996, UInt<1>(0h1), "") : assert_128 node _T_2000 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_2004 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_130 node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_121 = shr(io.in.c.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h0)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_127 = shr(io.in.c.bits.source, 2) node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h1)) node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129) node _source_ok_T_131 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_133 = shr(io.in.c.bits.source, 2) node _source_ok_T_134 = eq(_source_ok_T_133, UInt<2>(0h2)) node _source_ok_T_135 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_136 = and(_source_ok_T_134, _source_ok_T_135) node _source_ok_T_137 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_138 = and(_source_ok_T_136, _source_ok_T_137) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_139 = shr(io.in.c.bits.source, 2) node _source_ok_T_140 = eq(_source_ok_T_139, UInt<2>(0h3)) node _source_ok_T_141 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_142 = and(_source_ok_T_140, _source_ok_T_141) node _source_ok_T_143 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_144 = and(_source_ok_T_142, _source_ok_T_143) node _source_ok_T_145 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _source_ok_T_146 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _source_ok_T_147 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _source_ok_T_148 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _source_ok_T_149 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _source_ok_T_150 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _source_ok_T_151 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _source_ok_T_152 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _source_ok_T_153 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_154 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_155 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_156 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_159 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_160 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[21] connect _source_ok_WIRE_2[0], _source_ok_T_120 connect _source_ok_WIRE_2[1], _source_ok_T_126 connect _source_ok_WIRE_2[2], _source_ok_T_132 connect _source_ok_WIRE_2[3], _source_ok_T_138 connect _source_ok_WIRE_2[4], _source_ok_T_144 connect _source_ok_WIRE_2[5], _source_ok_T_145 connect _source_ok_WIRE_2[6], _source_ok_T_146 connect _source_ok_WIRE_2[7], _source_ok_T_147 connect _source_ok_WIRE_2[8], _source_ok_T_148 connect _source_ok_WIRE_2[9], _source_ok_T_149 connect _source_ok_WIRE_2[10], _source_ok_T_150 connect _source_ok_WIRE_2[11], _source_ok_T_151 connect _source_ok_WIRE_2[12], _source_ok_T_152 connect _source_ok_WIRE_2[13], _source_ok_T_153 connect _source_ok_WIRE_2[14], _source_ok_T_154 connect _source_ok_WIRE_2[15], _source_ok_T_155 connect _source_ok_WIRE_2[16], _source_ok_T_156 connect _source_ok_WIRE_2[17], _source_ok_T_157 connect _source_ok_WIRE_2[18], _source_ok_T_158 connect _source_ok_WIRE_2[19], _source_ok_T_159 connect _source_ok_WIRE_2[20], _source_ok_T_160 node _source_ok_T_161 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_162 = or(_source_ok_T_161, _source_ok_WIRE_2[2]) node _source_ok_T_163 = or(_source_ok_T_162, _source_ok_WIRE_2[3]) node _source_ok_T_164 = or(_source_ok_T_163, _source_ok_WIRE_2[4]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_2[5]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_2[6]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_2[7]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_2[8]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_2[9]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_2[10]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_2[11]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_2[12]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_2[13]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_2[14]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_2[15]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_2[16]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_2[17]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_2[18]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_2[19]) node source_ok_2 = or(_source_ok_T_179, _source_ok_WIRE_2[20]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_2008 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_2009 = eq(_T_2008, UInt<1>(0h0)) node _T_2010 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<1>(0h0))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_2009, _T_2014) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_2016 = shr(io.in.c.bits.source, 2) node _T_2017 = eq(_T_2016, UInt<1>(0h0)) node _T_2018 = leq(UInt<1>(0h0), uncommonBits_52) node _T_2019 = and(_T_2017, _T_2018) node _T_2020 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_2021 = and(_T_2019, _T_2020) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) node _T_2023 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2024 = cvt(_T_2023) node _T_2025 = and(_T_2024, asSInt(UInt<1>(0h0))) node _T_2026 = asSInt(_T_2025) node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0))) node _T_2028 = or(_T_2022, _T_2027) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_2029 = shr(io.in.c.bits.source, 2) node _T_2030 = eq(_T_2029, UInt<1>(0h1)) node _T_2031 = leq(UInt<1>(0h0), uncommonBits_53) node _T_2032 = and(_T_2030, _T_2031) node _T_2033 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_2034 = and(_T_2032, _T_2033) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) node _T_2036 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2037 = cvt(_T_2036) node _T_2038 = and(_T_2037, asSInt(UInt<1>(0h0))) node _T_2039 = asSInt(_T_2038) node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0))) node _T_2041 = or(_T_2035, _T_2040) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_2042 = shr(io.in.c.bits.source, 2) node _T_2043 = eq(_T_2042, UInt<2>(0h2)) node _T_2044 = leq(UInt<1>(0h0), uncommonBits_54) node _T_2045 = and(_T_2043, _T_2044) node _T_2046 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_2047 = and(_T_2045, _T_2046) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<1>(0h0))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = or(_T_2048, _T_2053) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_2055 = shr(io.in.c.bits.source, 2) node _T_2056 = eq(_T_2055, UInt<2>(0h3)) node _T_2057 = leq(UInt<1>(0h0), uncommonBits_55) node _T_2058 = and(_T_2056, _T_2057) node _T_2059 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_2060 = and(_T_2058, _T_2059) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) node _T_2062 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2063 = cvt(_T_2062) node _T_2064 = and(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = asSInt(_T_2064) node _T_2066 = eq(_T_2065, asSInt(UInt<1>(0h0))) node _T_2067 = or(_T_2061, _T_2066) node _T_2068 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) node _T_2070 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<1>(0h0))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = or(_T_2069, _T_2074) node _T_2076 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) node _T_2078 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2079 = cvt(_T_2078) node _T_2080 = and(_T_2079, asSInt(UInt<1>(0h0))) node _T_2081 = asSInt(_T_2080) node _T_2082 = eq(_T_2081, asSInt(UInt<1>(0h0))) node _T_2083 = or(_T_2077, _T_2082) node _T_2084 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = or(_T_2085, _T_2090) node _T_2092 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2093 = eq(_T_2092, UInt<1>(0h0)) node _T_2094 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<1>(0h0))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2093, _T_2098) node _T_2100 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2101 = eq(_T_2100, UInt<1>(0h0)) node _T_2102 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2103 = cvt(_T_2102) node _T_2104 = and(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = asSInt(_T_2104) node _T_2106 = eq(_T_2105, asSInt(UInt<1>(0h0))) node _T_2107 = or(_T_2101, _T_2106) node _T_2108 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2109 = eq(_T_2108, UInt<1>(0h0)) node _T_2110 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<1>(0h0))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = or(_T_2109, _T_2114) node _T_2116 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2117 = eq(_T_2116, UInt<1>(0h0)) node _T_2118 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2119 = cvt(_T_2118) node _T_2120 = and(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = asSInt(_T_2120) node _T_2122 = eq(_T_2121, asSInt(UInt<1>(0h0))) node _T_2123 = or(_T_2117, _T_2122) node _T_2124 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) node _T_2126 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2127 = cvt(_T_2126) node _T_2128 = and(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = asSInt(_T_2128) node _T_2130 = eq(_T_2129, asSInt(UInt<1>(0h0))) node _T_2131 = or(_T_2125, _T_2130) node _T_2132 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2133 = eq(_T_2132, UInt<1>(0h0)) node _T_2134 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2135 = cvt(_T_2134) node _T_2136 = and(_T_2135, asSInt(UInt<1>(0h0))) node _T_2137 = asSInt(_T_2136) node _T_2138 = eq(_T_2137, asSInt(UInt<1>(0h0))) node _T_2139 = or(_T_2133, _T_2138) node _T_2140 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2141 = eq(_T_2140, UInt<1>(0h0)) node _T_2142 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2143 = cvt(_T_2142) node _T_2144 = and(_T_2143, asSInt(UInt<1>(0h0))) node _T_2145 = asSInt(_T_2144) node _T_2146 = eq(_T_2145, asSInt(UInt<1>(0h0))) node _T_2147 = or(_T_2141, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) node _T_2150 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<1>(0h0))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = or(_T_2149, _T_2154) node _T_2156 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2159 = cvt(_T_2158) node _T_2160 = and(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = asSInt(_T_2160) node _T_2162 = eq(_T_2161, asSInt(UInt<1>(0h0))) node _T_2163 = or(_T_2157, _T_2162) node _T_2164 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2165 = eq(_T_2164, UInt<1>(0h0)) node _T_2166 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = or(_T_2165, _T_2170) node _T_2172 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) node _T_2174 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<1>(0h0))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = or(_T_2173, _T_2178) node _T_2180 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2183 = cvt(_T_2182) node _T_2184 = and(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = asSInt(_T_2184) node _T_2186 = eq(_T_2185, asSInt(UInt<1>(0h0))) node _T_2187 = or(_T_2181, _T_2186) node _T_2188 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) node _T_2190 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<1>(0h0))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2189, _T_2194) node _T_2196 = and(_T_2015, _T_2028) node _T_2197 = and(_T_2196, _T_2041) node _T_2198 = and(_T_2197, _T_2054) node _T_2199 = and(_T_2198, _T_2067) node _T_2200 = and(_T_2199, _T_2075) node _T_2201 = and(_T_2200, _T_2083) node _T_2202 = and(_T_2201, _T_2091) node _T_2203 = and(_T_2202, _T_2099) node _T_2204 = and(_T_2203, _T_2107) node _T_2205 = and(_T_2204, _T_2115) node _T_2206 = and(_T_2205, _T_2123) node _T_2207 = and(_T_2206, _T_2131) node _T_2208 = and(_T_2207, _T_2139) node _T_2209 = and(_T_2208, _T_2147) node _T_2210 = and(_T_2209, _T_2155) node _T_2211 = and(_T_2210, _T_2163) node _T_2212 = and(_T_2211, _T_2171) node _T_2213 = and(_T_2212, _T_2179) node _T_2214 = and(_T_2213, _T_2187) node _T_2215 = and(_T_2214, _T_2195) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_131 node _T_2219 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_2219 : node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(address_ok_1, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(source_ok_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2226 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_134 node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2233 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(_T_2233, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2233, UInt<1>(0h1), "") : assert_136 node _T_2237 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_137 node _T_2241 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2241 : node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(address_ok_1, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(source_ok_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2248 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_140 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2255 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(_T_2255, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2255, UInt<1>(0h1), "") : assert_142 node _T_2259 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2259 : node _T_2260 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2261 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2262 = and(_T_2260, _T_2261) node _T_2263 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_2264 = shr(io.in.c.bits.source, 2) node _T_2265 = eq(_T_2264, UInt<1>(0h0)) node _T_2266 = leq(UInt<1>(0h0), uncommonBits_56) node _T_2267 = and(_T_2265, _T_2266) node _T_2268 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_2269 = and(_T_2267, _T_2268) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_2270 = shr(io.in.c.bits.source, 2) node _T_2271 = eq(_T_2270, UInt<1>(0h1)) node _T_2272 = leq(UInt<1>(0h0), uncommonBits_57) node _T_2273 = and(_T_2271, _T_2272) node _T_2274 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_2275 = and(_T_2273, _T_2274) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_2276 = shr(io.in.c.bits.source, 2) node _T_2277 = eq(_T_2276, UInt<2>(0h2)) node _T_2278 = leq(UInt<1>(0h0), uncommonBits_58) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_2281 = and(_T_2279, _T_2280) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_2282 = shr(io.in.c.bits.source, 2) node _T_2283 = eq(_T_2282, UInt<2>(0h3)) node _T_2284 = leq(UInt<1>(0h0), uncommonBits_59) node _T_2285 = and(_T_2283, _T_2284) node _T_2286 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_2287 = and(_T_2285, _T_2286) node _T_2288 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2289 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2290 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2291 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2292 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2293 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2294 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2295 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2296 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2297 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2298 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2299 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2300 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2301 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2302 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2303 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2304 = or(_T_2263, _T_2269) node _T_2305 = or(_T_2304, _T_2275) node _T_2306 = or(_T_2305, _T_2281) node _T_2307 = or(_T_2306, _T_2287) node _T_2308 = or(_T_2307, _T_2288) node _T_2309 = or(_T_2308, _T_2289) node _T_2310 = or(_T_2309, _T_2290) node _T_2311 = or(_T_2310, _T_2291) node _T_2312 = or(_T_2311, _T_2292) node _T_2313 = or(_T_2312, _T_2293) node _T_2314 = or(_T_2313, _T_2294) node _T_2315 = or(_T_2314, _T_2295) node _T_2316 = or(_T_2315, _T_2296) node _T_2317 = or(_T_2316, _T_2297) node _T_2318 = or(_T_2317, _T_2298) node _T_2319 = or(_T_2318, _T_2299) node _T_2320 = or(_T_2319, _T_2300) node _T_2321 = or(_T_2320, _T_2301) node _T_2322 = or(_T_2321, _T_2302) node _T_2323 = or(_T_2322, _T_2303) node _T_2324 = and(_T_2262, _T_2323) node _T_2325 = or(UInt<1>(0h0), _T_2324) node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = or(UInt<1>(0h0), _T_2326) node _T_2328 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2329 = cvt(_T_2328) node _T_2330 = and(_T_2329, asSInt(UInt<17>(0h100c0))) node _T_2331 = asSInt(_T_2330) node _T_2332 = eq(_T_2331, asSInt(UInt<1>(0h0))) node _T_2333 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2334 = cvt(_T_2333) node _T_2335 = and(_T_2334, asSInt(UInt<29>(0h100000c0))) node _T_2336 = asSInt(_T_2335) node _T_2337 = eq(_T_2336, asSInt(UInt<1>(0h0))) node _T_2338 = or(_T_2332, _T_2337) node _T_2339 = and(_T_2327, _T_2338) node _T_2340 = or(UInt<1>(0h0), _T_2339) node _T_2341 = and(_T_2325, _T_2340) node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(_T_2341, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2341, UInt<1>(0h1), "") : assert_143 node _T_2345 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_2346 = shr(io.in.c.bits.source, 2) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) node _T_2348 = leq(UInt<1>(0h0), uncommonBits_60) node _T_2349 = and(_T_2347, _T_2348) node _T_2350 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_2351 = and(_T_2349, _T_2350) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_2352 = shr(io.in.c.bits.source, 2) node _T_2353 = eq(_T_2352, UInt<1>(0h1)) node _T_2354 = leq(UInt<1>(0h0), uncommonBits_61) node _T_2355 = and(_T_2353, _T_2354) node _T_2356 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_2357 = and(_T_2355, _T_2356) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_2358 = shr(io.in.c.bits.source, 2) node _T_2359 = eq(_T_2358, UInt<2>(0h2)) node _T_2360 = leq(UInt<1>(0h0), uncommonBits_62) node _T_2361 = and(_T_2359, _T_2360) node _T_2362 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_2363 = and(_T_2361, _T_2362) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_2364 = shr(io.in.c.bits.source, 2) node _T_2365 = eq(_T_2364, UInt<2>(0h3)) node _T_2366 = leq(UInt<1>(0h0), uncommonBits_63) node _T_2367 = and(_T_2365, _T_2366) node _T_2368 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_2369 = and(_T_2367, _T_2368) node _T_2370 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2371 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2372 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2373 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2374 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2375 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2376 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2377 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2378 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2379 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2380 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2381 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2382 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2383 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2384 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2385 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[21] connect _WIRE_6[0], _T_2345 connect _WIRE_6[1], _T_2351 connect _WIRE_6[2], _T_2357 connect _WIRE_6[3], _T_2363 connect _WIRE_6[4], _T_2369 connect _WIRE_6[5], _T_2370 connect _WIRE_6[6], _T_2371 connect _WIRE_6[7], _T_2372 connect _WIRE_6[8], _T_2373 connect _WIRE_6[9], _T_2374 connect _WIRE_6[10], _T_2375 connect _WIRE_6[11], _T_2376 connect _WIRE_6[12], _T_2377 connect _WIRE_6[13], _T_2378 connect _WIRE_6[14], _T_2379 connect _WIRE_6[15], _T_2380 connect _WIRE_6[16], _T_2381 connect _WIRE_6[17], _T_2382 connect _WIRE_6[18], _T_2383 connect _WIRE_6[19], _T_2384 connect _WIRE_6[20], _T_2385 node _T_2386 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2387 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2388 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2389 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2390 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2391 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2392 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2393 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2394 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2395 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2396 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2397 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2398 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2399 = mux(_WIRE_6[5], _T_2386, UInt<1>(0h0)) node _T_2400 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2401 = mux(_WIRE_6[7], _T_2387, UInt<1>(0h0)) node _T_2402 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2403 = mux(_WIRE_6[9], _T_2388, UInt<1>(0h0)) node _T_2404 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2405 = mux(_WIRE_6[11], _T_2389, UInt<1>(0h0)) node _T_2406 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2407 = mux(_WIRE_6[13], _T_2390, UInt<1>(0h0)) node _T_2408 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2409 = mux(_WIRE_6[15], _T_2391, UInt<1>(0h0)) node _T_2410 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2411 = mux(_WIRE_6[17], _T_2392, UInt<1>(0h0)) node _T_2412 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2413 = mux(_WIRE_6[19], _T_2393, UInt<1>(0h0)) node _T_2414 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2415 = or(_T_2394, _T_2395) node _T_2416 = or(_T_2415, _T_2396) node _T_2417 = or(_T_2416, _T_2397) node _T_2418 = or(_T_2417, _T_2398) node _T_2419 = or(_T_2418, _T_2399) node _T_2420 = or(_T_2419, _T_2400) node _T_2421 = or(_T_2420, _T_2401) node _T_2422 = or(_T_2421, _T_2402) node _T_2423 = or(_T_2422, _T_2403) node _T_2424 = or(_T_2423, _T_2404) node _T_2425 = or(_T_2424, _T_2405) node _T_2426 = or(_T_2425, _T_2406) node _T_2427 = or(_T_2426, _T_2407) node _T_2428 = or(_T_2427, _T_2408) node _T_2429 = or(_T_2428, _T_2409) node _T_2430 = or(_T_2429, _T_2410) node _T_2431 = or(_T_2430, _T_2411) node _T_2432 = or(_T_2431, _T_2412) node _T_2433 = or(_T_2432, _T_2413) node _T_2434 = or(_T_2433, _T_2414) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2434 node _T_2435 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2436 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = or(UInt<1>(0h0), _T_2437) node _T_2439 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2440 = cvt(_T_2439) node _T_2441 = and(_T_2440, asSInt(UInt<17>(0h100c0))) node _T_2442 = asSInt(_T_2441) node _T_2443 = eq(_T_2442, asSInt(UInt<1>(0h0))) node _T_2444 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2445 = cvt(_T_2444) node _T_2446 = and(_T_2445, asSInt(UInt<29>(0h100000c0))) node _T_2447 = asSInt(_T_2446) node _T_2448 = eq(_T_2447, asSInt(UInt<1>(0h0))) node _T_2449 = or(_T_2443, _T_2448) node _T_2450 = and(_T_2438, _T_2449) node _T_2451 = or(UInt<1>(0h0), _T_2450) node _T_2452 = and(_WIRE_7, _T_2451) node _T_2453 = asUInt(reset) node _T_2454 = eq(_T_2453, UInt<1>(0h0)) when _T_2454 : node _T_2455 = eq(_T_2452, UInt<1>(0h0)) when _T_2455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2452, UInt<1>(0h1), "") : assert_144 node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(source_ok_2, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2459 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_146 node _T_2463 = asUInt(reset) node _T_2464 = eq(_T_2463, UInt<1>(0h0)) when _T_2464 : node _T_2465 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2466 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_148 node _T_2470 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(_T_2470, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2470, UInt<1>(0h1), "") : assert_149 node _T_2474 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2474 : node _T_2475 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2476 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2477 = and(_T_2475, _T_2476) node _T_2478 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2479 = shr(io.in.c.bits.source, 2) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2482 = and(_T_2480, _T_2481) node _T_2483 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2484 = and(_T_2482, _T_2483) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2485 = shr(io.in.c.bits.source, 2) node _T_2486 = eq(_T_2485, UInt<1>(0h1)) node _T_2487 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2488 = and(_T_2486, _T_2487) node _T_2489 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2490 = and(_T_2488, _T_2489) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2491 = shr(io.in.c.bits.source, 2) node _T_2492 = eq(_T_2491, UInt<2>(0h2)) node _T_2493 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2494 = and(_T_2492, _T_2493) node _T_2495 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2496 = and(_T_2494, _T_2495) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2497 = shr(io.in.c.bits.source, 2) node _T_2498 = eq(_T_2497, UInt<2>(0h3)) node _T_2499 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2500 = and(_T_2498, _T_2499) node _T_2501 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2502 = and(_T_2500, _T_2501) node _T_2503 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2504 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2505 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2506 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2507 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2508 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2509 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2510 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2511 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2512 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2513 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2514 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2515 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2516 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2517 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2518 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2519 = or(_T_2478, _T_2484) node _T_2520 = or(_T_2519, _T_2490) node _T_2521 = or(_T_2520, _T_2496) node _T_2522 = or(_T_2521, _T_2502) node _T_2523 = or(_T_2522, _T_2503) node _T_2524 = or(_T_2523, _T_2504) node _T_2525 = or(_T_2524, _T_2505) node _T_2526 = or(_T_2525, _T_2506) node _T_2527 = or(_T_2526, _T_2507) node _T_2528 = or(_T_2527, _T_2508) node _T_2529 = or(_T_2528, _T_2509) node _T_2530 = or(_T_2529, _T_2510) node _T_2531 = or(_T_2530, _T_2511) node _T_2532 = or(_T_2531, _T_2512) node _T_2533 = or(_T_2532, _T_2513) node _T_2534 = or(_T_2533, _T_2514) node _T_2535 = or(_T_2534, _T_2515) node _T_2536 = or(_T_2535, _T_2516) node _T_2537 = or(_T_2536, _T_2517) node _T_2538 = or(_T_2537, _T_2518) node _T_2539 = and(_T_2477, _T_2538) node _T_2540 = or(UInt<1>(0h0), _T_2539) node _T_2541 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2542 = or(UInt<1>(0h0), _T_2541) node _T_2543 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2544 = cvt(_T_2543) node _T_2545 = and(_T_2544, asSInt(UInt<17>(0h100c0))) node _T_2546 = asSInt(_T_2545) node _T_2547 = eq(_T_2546, asSInt(UInt<1>(0h0))) node _T_2548 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2549 = cvt(_T_2548) node _T_2550 = and(_T_2549, asSInt(UInt<29>(0h100000c0))) node _T_2551 = asSInt(_T_2550) node _T_2552 = eq(_T_2551, asSInt(UInt<1>(0h0))) node _T_2553 = or(_T_2547, _T_2552) node _T_2554 = and(_T_2542, _T_2553) node _T_2555 = or(UInt<1>(0h0), _T_2554) node _T_2556 = and(_T_2540, _T_2555) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_150 node _T_2560 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2561 = shr(io.in.c.bits.source, 2) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) node _T_2563 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2564 = and(_T_2562, _T_2563) node _T_2565 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2566 = and(_T_2564, _T_2565) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2567 = shr(io.in.c.bits.source, 2) node _T_2568 = eq(_T_2567, UInt<1>(0h1)) node _T_2569 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2570 = and(_T_2568, _T_2569) node _T_2571 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2572 = and(_T_2570, _T_2571) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2573 = shr(io.in.c.bits.source, 2) node _T_2574 = eq(_T_2573, UInt<2>(0h2)) node _T_2575 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2576 = and(_T_2574, _T_2575) node _T_2577 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2578 = and(_T_2576, _T_2577) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2579 = shr(io.in.c.bits.source, 2) node _T_2580 = eq(_T_2579, UInt<2>(0h3)) node _T_2581 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2582 = and(_T_2580, _T_2581) node _T_2583 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2584 = and(_T_2582, _T_2583) node _T_2585 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2586 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2587 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2588 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2589 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2590 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2591 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2592 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2593 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2594 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2595 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2596 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2597 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2598 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2599 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2600 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[21] connect _WIRE_8[0], _T_2560 connect _WIRE_8[1], _T_2566 connect _WIRE_8[2], _T_2572 connect _WIRE_8[3], _T_2578 connect _WIRE_8[4], _T_2584 connect _WIRE_8[5], _T_2585 connect _WIRE_8[6], _T_2586 connect _WIRE_8[7], _T_2587 connect _WIRE_8[8], _T_2588 connect _WIRE_8[9], _T_2589 connect _WIRE_8[10], _T_2590 connect _WIRE_8[11], _T_2591 connect _WIRE_8[12], _T_2592 connect _WIRE_8[13], _T_2593 connect _WIRE_8[14], _T_2594 connect _WIRE_8[15], _T_2595 connect _WIRE_8[16], _T_2596 connect _WIRE_8[17], _T_2597 connect _WIRE_8[18], _T_2598 connect _WIRE_8[19], _T_2599 connect _WIRE_8[20], _T_2600 node _T_2601 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2602 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2603 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2604 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2605 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2606 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2607 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2608 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2609 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2610 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2611 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2612 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2613 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2614 = mux(_WIRE_8[5], _T_2601, UInt<1>(0h0)) node _T_2615 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2616 = mux(_WIRE_8[7], _T_2602, UInt<1>(0h0)) node _T_2617 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2618 = mux(_WIRE_8[9], _T_2603, UInt<1>(0h0)) node _T_2619 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2620 = mux(_WIRE_8[11], _T_2604, UInt<1>(0h0)) node _T_2621 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2622 = mux(_WIRE_8[13], _T_2605, UInt<1>(0h0)) node _T_2623 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2624 = mux(_WIRE_8[15], _T_2606, UInt<1>(0h0)) node _T_2625 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2626 = mux(_WIRE_8[17], _T_2607, UInt<1>(0h0)) node _T_2627 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2628 = mux(_WIRE_8[19], _T_2608, UInt<1>(0h0)) node _T_2629 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2630 = or(_T_2609, _T_2610) node _T_2631 = or(_T_2630, _T_2611) node _T_2632 = or(_T_2631, _T_2612) node _T_2633 = or(_T_2632, _T_2613) node _T_2634 = or(_T_2633, _T_2614) node _T_2635 = or(_T_2634, _T_2615) node _T_2636 = or(_T_2635, _T_2616) node _T_2637 = or(_T_2636, _T_2617) node _T_2638 = or(_T_2637, _T_2618) node _T_2639 = or(_T_2638, _T_2619) node _T_2640 = or(_T_2639, _T_2620) node _T_2641 = or(_T_2640, _T_2621) node _T_2642 = or(_T_2641, _T_2622) node _T_2643 = or(_T_2642, _T_2623) node _T_2644 = or(_T_2643, _T_2624) node _T_2645 = or(_T_2644, _T_2625) node _T_2646 = or(_T_2645, _T_2626) node _T_2647 = or(_T_2646, _T_2627) node _T_2648 = or(_T_2647, _T_2628) node _T_2649 = or(_T_2648, _T_2629) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2649 node _T_2650 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2651 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2652 = and(_T_2650, _T_2651) node _T_2653 = or(UInt<1>(0h0), _T_2652) node _T_2654 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2655 = cvt(_T_2654) node _T_2656 = and(_T_2655, asSInt(UInt<17>(0h100c0))) node _T_2657 = asSInt(_T_2656) node _T_2658 = eq(_T_2657, asSInt(UInt<1>(0h0))) node _T_2659 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2660 = cvt(_T_2659) node _T_2661 = and(_T_2660, asSInt(UInt<29>(0h100000c0))) node _T_2662 = asSInt(_T_2661) node _T_2663 = eq(_T_2662, asSInt(UInt<1>(0h0))) node _T_2664 = or(_T_2658, _T_2663) node _T_2665 = and(_T_2653, _T_2664) node _T_2666 = or(UInt<1>(0h0), _T_2665) node _T_2667 = and(_WIRE_9, _T_2666) node _T_2668 = asUInt(reset) node _T_2669 = eq(_T_2668, UInt<1>(0h0)) when _T_2669 : node _T_2670 = eq(_T_2667, UInt<1>(0h0)) when _T_2670 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2667, UInt<1>(0h1), "") : assert_151 node _T_2671 = asUInt(reset) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) when _T_2672 : node _T_2673 = eq(source_ok_2, UInt<1>(0h0)) when _T_2673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2674 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2675 = asUInt(reset) node _T_2676 = eq(_T_2675, UInt<1>(0h0)) when _T_2676 : node _T_2677 = eq(_T_2674, UInt<1>(0h0)) when _T_2677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2674, UInt<1>(0h1), "") : assert_153 node _T_2678 = asUInt(reset) node _T_2679 = eq(_T_2678, UInt<1>(0h0)) when _T_2679 : node _T_2680 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2681 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2682 = asUInt(reset) node _T_2683 = eq(_T_2682, UInt<1>(0h0)) when _T_2683 : node _T_2684 = eq(_T_2681, UInt<1>(0h0)) when _T_2684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2681, UInt<1>(0h1), "") : assert_155 node _T_2685 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2685 : node _T_2686 = asUInt(reset) node _T_2687 = eq(_T_2686, UInt<1>(0h0)) when _T_2687 : node _T_2688 = eq(address_ok_1, UInt<1>(0h0)) when _T_2688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(source_ok_2, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2692 = asUInt(reset) node _T_2693 = eq(_T_2692, UInt<1>(0h0)) when _T_2693 : node _T_2694 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2695 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2696 = asUInt(reset) node _T_2697 = eq(_T_2696, UInt<1>(0h0)) when _T_2697 : node _T_2698 = eq(_T_2695, UInt<1>(0h0)) when _T_2698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2695, UInt<1>(0h1), "") : assert_159 node _T_2699 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2700 = asUInt(reset) node _T_2701 = eq(_T_2700, UInt<1>(0h0)) when _T_2701 : node _T_2702 = eq(_T_2699, UInt<1>(0h0)) when _T_2702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2699, UInt<1>(0h1), "") : assert_160 node _T_2703 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2703 : node _T_2704 = asUInt(reset) node _T_2705 = eq(_T_2704, UInt<1>(0h0)) when _T_2705 : node _T_2706 = eq(address_ok_1, UInt<1>(0h0)) when _T_2706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2707 = asUInt(reset) node _T_2708 = eq(_T_2707, UInt<1>(0h0)) when _T_2708 : node _T_2709 = eq(source_ok_2, UInt<1>(0h0)) when _T_2709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2713 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2714 = asUInt(reset) node _T_2715 = eq(_T_2714, UInt<1>(0h0)) when _T_2715 : node _T_2716 = eq(_T_2713, UInt<1>(0h0)) when _T_2716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2713, UInt<1>(0h1), "") : assert_164 node _T_2717 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2717 : node _T_2718 = asUInt(reset) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) when _T_2719 : node _T_2720 = eq(address_ok_1, UInt<1>(0h0)) when _T_2720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2721 = asUInt(reset) node _T_2722 = eq(_T_2721, UInt<1>(0h0)) when _T_2722 : node _T_2723 = eq(source_ok_2, UInt<1>(0h0)) when _T_2723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2727 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2728 = asUInt(reset) node _T_2729 = eq(_T_2728, UInt<1>(0h0)) when _T_2729 : node _T_2730 = eq(_T_2727, UInt<1>(0h0)) when _T_2730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2727, UInt<1>(0h1), "") : assert_168 node _T_2731 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2732 = asUInt(reset) node _T_2733 = eq(_T_2732, UInt<1>(0h0)) when _T_2733 : node _T_2734 = eq(_T_2731, UInt<1>(0h0)) when _T_2734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2731, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2735 = asUInt(reset) node _T_2736 = eq(_T_2735, UInt<1>(0h0)) when _T_2736 : node _T_2737 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2738 = eq(a_first, UInt<1>(0h0)) node _T_2739 = and(io.in.a.valid, _T_2738) when _T_2739 : node _T_2740 = eq(io.in.a.bits.opcode, opcode) node _T_2741 = asUInt(reset) node _T_2742 = eq(_T_2741, UInt<1>(0h0)) when _T_2742 : node _T_2743 = eq(_T_2740, UInt<1>(0h0)) when _T_2743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2740, UInt<1>(0h1), "") : assert_171 node _T_2744 = eq(io.in.a.bits.param, param) node _T_2745 = asUInt(reset) node _T_2746 = eq(_T_2745, UInt<1>(0h0)) when _T_2746 : node _T_2747 = eq(_T_2744, UInt<1>(0h0)) when _T_2747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2744, UInt<1>(0h1), "") : assert_172 node _T_2748 = eq(io.in.a.bits.size, size) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_173 node _T_2752 = eq(io.in.a.bits.source, source) node _T_2753 = asUInt(reset) node _T_2754 = eq(_T_2753, UInt<1>(0h0)) when _T_2754 : node _T_2755 = eq(_T_2752, UInt<1>(0h0)) when _T_2755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2752, UInt<1>(0h1), "") : assert_174 node _T_2756 = eq(io.in.a.bits.address, address) node _T_2757 = asUInt(reset) node _T_2758 = eq(_T_2757, UInt<1>(0h0)) when _T_2758 : node _T_2759 = eq(_T_2756, UInt<1>(0h0)) when _T_2759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2756, UInt<1>(0h1), "") : assert_175 node _T_2760 = and(io.in.a.ready, io.in.a.valid) node _T_2761 = and(_T_2760, a_first) when _T_2761 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2762 = eq(d_first, UInt<1>(0h0)) node _T_2763 = and(io.in.d.valid, _T_2762) when _T_2763 : node _T_2764 = eq(io.in.d.bits.opcode, opcode_1) node _T_2765 = asUInt(reset) node _T_2766 = eq(_T_2765, UInt<1>(0h0)) when _T_2766 : node _T_2767 = eq(_T_2764, UInt<1>(0h0)) when _T_2767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2764, UInt<1>(0h1), "") : assert_176 node _T_2768 = eq(io.in.d.bits.param, param_1) node _T_2769 = asUInt(reset) node _T_2770 = eq(_T_2769, UInt<1>(0h0)) when _T_2770 : node _T_2771 = eq(_T_2768, UInt<1>(0h0)) when _T_2771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2768, UInt<1>(0h1), "") : assert_177 node _T_2772 = eq(io.in.d.bits.size, size_1) node _T_2773 = asUInt(reset) node _T_2774 = eq(_T_2773, UInt<1>(0h0)) when _T_2774 : node _T_2775 = eq(_T_2772, UInt<1>(0h0)) when _T_2775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2772, UInt<1>(0h1), "") : assert_178 node _T_2776 = eq(io.in.d.bits.source, source_1) node _T_2777 = asUInt(reset) node _T_2778 = eq(_T_2777, UInt<1>(0h0)) when _T_2778 : node _T_2779 = eq(_T_2776, UInt<1>(0h0)) when _T_2779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2776, UInt<1>(0h1), "") : assert_179 node _T_2780 = eq(io.in.d.bits.sink, sink) node _T_2781 = asUInt(reset) node _T_2782 = eq(_T_2781, UInt<1>(0h0)) when _T_2782 : node _T_2783 = eq(_T_2780, UInt<1>(0h0)) when _T_2783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2780, UInt<1>(0h1), "") : assert_180 node _T_2784 = eq(io.in.d.bits.denied, denied) node _T_2785 = asUInt(reset) node _T_2786 = eq(_T_2785, UInt<1>(0h0)) when _T_2786 : node _T_2787 = eq(_T_2784, UInt<1>(0h0)) when _T_2787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2784, UInt<1>(0h1), "") : assert_181 node _T_2788 = and(io.in.d.ready, io.in.d.valid) node _T_2789 = and(_T_2788, d_first) when _T_2789 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2790 = eq(b_first, UInt<1>(0h0)) node _T_2791 = and(io.in.b.valid, _T_2790) when _T_2791 : node _T_2792 = eq(io.in.b.bits.opcode, opcode_2) node _T_2793 = asUInt(reset) node _T_2794 = eq(_T_2793, UInt<1>(0h0)) when _T_2794 : node _T_2795 = eq(_T_2792, UInt<1>(0h0)) when _T_2795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2792, UInt<1>(0h1), "") : assert_182 node _T_2796 = eq(io.in.b.bits.param, param_2) node _T_2797 = asUInt(reset) node _T_2798 = eq(_T_2797, UInt<1>(0h0)) when _T_2798 : node _T_2799 = eq(_T_2796, UInt<1>(0h0)) when _T_2799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2796, UInt<1>(0h1), "") : assert_183 node _T_2800 = eq(io.in.b.bits.size, size_2) node _T_2801 = asUInt(reset) node _T_2802 = eq(_T_2801, UInt<1>(0h0)) when _T_2802 : node _T_2803 = eq(_T_2800, UInt<1>(0h0)) when _T_2803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2800, UInt<1>(0h1), "") : assert_184 node _T_2804 = eq(io.in.b.bits.source, source_2) node _T_2805 = asUInt(reset) node _T_2806 = eq(_T_2805, UInt<1>(0h0)) when _T_2806 : node _T_2807 = eq(_T_2804, UInt<1>(0h0)) when _T_2807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2804, UInt<1>(0h1), "") : assert_185 node _T_2808 = eq(io.in.b.bits.address, address_1) node _T_2809 = asUInt(reset) node _T_2810 = eq(_T_2809, UInt<1>(0h0)) when _T_2810 : node _T_2811 = eq(_T_2808, UInt<1>(0h0)) when _T_2811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2808, UInt<1>(0h1), "") : assert_186 node _T_2812 = and(io.in.b.ready, io.in.b.valid) node _T_2813 = and(_T_2812, b_first) when _T_2813 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2814 = eq(c_first, UInt<1>(0h0)) node _T_2815 = and(io.in.c.valid, _T_2814) when _T_2815 : node _T_2816 = eq(io.in.c.bits.opcode, opcode_3) node _T_2817 = asUInt(reset) node _T_2818 = eq(_T_2817, UInt<1>(0h0)) when _T_2818 : node _T_2819 = eq(_T_2816, UInt<1>(0h0)) when _T_2819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2816, UInt<1>(0h1), "") : assert_187 node _T_2820 = eq(io.in.c.bits.param, param_3) node _T_2821 = asUInt(reset) node _T_2822 = eq(_T_2821, UInt<1>(0h0)) when _T_2822 : node _T_2823 = eq(_T_2820, UInt<1>(0h0)) when _T_2823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2820, UInt<1>(0h1), "") : assert_188 node _T_2824 = eq(io.in.c.bits.size, size_3) node _T_2825 = asUInt(reset) node _T_2826 = eq(_T_2825, UInt<1>(0h0)) when _T_2826 : node _T_2827 = eq(_T_2824, UInt<1>(0h0)) when _T_2827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2824, UInt<1>(0h1), "") : assert_189 node _T_2828 = eq(io.in.c.bits.source, source_3) node _T_2829 = asUInt(reset) node _T_2830 = eq(_T_2829, UInt<1>(0h0)) when _T_2830 : node _T_2831 = eq(_T_2828, UInt<1>(0h0)) when _T_2831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2828, UInt<1>(0h1), "") : assert_190 node _T_2832 = eq(io.in.c.bits.address, address_2) node _T_2833 = asUInt(reset) node _T_2834 = eq(_T_2833, UInt<1>(0h0)) when _T_2834 : node _T_2835 = eq(_T_2832, UInt<1>(0h0)) when _T_2835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2832, UInt<1>(0h1), "") : assert_191 node _T_2836 = and(io.in.c.ready, io.in.c.valid) node _T_2837 = and(_T_2836, c_first) when _T_2837 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<63>, clock, reset, UInt<63>(0h0) regreset inflight_opcodes : UInt<252>, clock, reset, UInt<252>(0h0) regreset inflight_sizes : UInt<252>, clock, reset, UInt<252>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<63> connect a_set, UInt<63>(0h0) wire a_set_wo_ready : UInt<63> connect a_set_wo_ready, UInt<63>(0h0) wire a_opcodes_set : UInt<252> connect a_opcodes_set, UInt<252>(0h0) wire a_sizes_set : UInt<252> connect a_sizes_set, UInt<252>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2838 = and(io.in.a.valid, a_first_1) node _T_2839 = and(_T_2838, UInt<1>(0h1)) when _T_2839 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2840 = and(io.in.a.ready, io.in.a.valid) node _T_2841 = and(_T_2840, a_first_1) node _T_2842 = and(_T_2841, UInt<1>(0h1)) when _T_2842 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2843 = dshr(inflight, io.in.a.bits.source) node _T_2844 = bits(_T_2843, 0, 0) node _T_2845 = eq(_T_2844, UInt<1>(0h0)) node _T_2846 = asUInt(reset) node _T_2847 = eq(_T_2846, UInt<1>(0h0)) when _T_2847 : node _T_2848 = eq(_T_2845, UInt<1>(0h0)) when _T_2848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2845, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<63> connect d_clr, UInt<63>(0h0) wire d_clr_wo_ready : UInt<63> connect d_clr_wo_ready, UInt<63>(0h0) wire d_opcodes_clr : UInt<252> connect d_opcodes_clr, UInt<252>(0h0) wire d_sizes_clr : UInt<252> connect d_sizes_clr, UInt<252>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2849 = and(io.in.d.valid, d_first_1) node _T_2850 = and(_T_2849, UInt<1>(0h1)) node _T_2851 = eq(d_release_ack, UInt<1>(0h0)) node _T_2852 = and(_T_2850, _T_2851) when _T_2852 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2853 = and(io.in.d.ready, io.in.d.valid) node _T_2854 = and(_T_2853, d_first_1) node _T_2855 = and(_T_2854, UInt<1>(0h1)) node _T_2856 = eq(d_release_ack, UInt<1>(0h0)) node _T_2857 = and(_T_2855, _T_2856) when _T_2857 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2858 = and(io.in.d.valid, d_first_1) node _T_2859 = and(_T_2858, UInt<1>(0h1)) node _T_2860 = eq(d_release_ack, UInt<1>(0h0)) node _T_2861 = and(_T_2859, _T_2860) when _T_2861 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2862 = dshr(inflight, io.in.d.bits.source) node _T_2863 = bits(_T_2862, 0, 0) node _T_2864 = or(_T_2863, same_cycle_resp) node _T_2865 = asUInt(reset) node _T_2866 = eq(_T_2865, UInt<1>(0h0)) when _T_2866 : node _T_2867 = eq(_T_2864, UInt<1>(0h0)) when _T_2867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2864, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2868 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2869 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2870 = or(_T_2868, _T_2869) node _T_2871 = asUInt(reset) node _T_2872 = eq(_T_2871, UInt<1>(0h0)) when _T_2872 : node _T_2873 = eq(_T_2870, UInt<1>(0h0)) when _T_2873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2870, UInt<1>(0h1), "") : assert_194 node _T_2874 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2875 = asUInt(reset) node _T_2876 = eq(_T_2875, UInt<1>(0h0)) when _T_2876 : node _T_2877 = eq(_T_2874, UInt<1>(0h0)) when _T_2877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2874, UInt<1>(0h1), "") : assert_195 else : node _T_2878 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2879 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2880 = or(_T_2878, _T_2879) node _T_2881 = asUInt(reset) node _T_2882 = eq(_T_2881, UInt<1>(0h0)) when _T_2882 : node _T_2883 = eq(_T_2880, UInt<1>(0h0)) when _T_2883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2880, UInt<1>(0h1), "") : assert_196 node _T_2884 = eq(io.in.d.bits.size, a_size_lookup) node _T_2885 = asUInt(reset) node _T_2886 = eq(_T_2885, UInt<1>(0h0)) when _T_2886 : node _T_2887 = eq(_T_2884, UInt<1>(0h0)) when _T_2887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2884, UInt<1>(0h1), "") : assert_197 node _T_2888 = and(io.in.d.valid, d_first_1) node _T_2889 = and(_T_2888, a_first_1) node _T_2890 = and(_T_2889, io.in.a.valid) node _T_2891 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2892 = and(_T_2890, _T_2891) node _T_2893 = eq(d_release_ack, UInt<1>(0h0)) node _T_2894 = and(_T_2892, _T_2893) when _T_2894 : node _T_2895 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2896 = or(_T_2895, io.in.a.ready) node _T_2897 = asUInt(reset) node _T_2898 = eq(_T_2897, UInt<1>(0h0)) when _T_2898 : node _T_2899 = eq(_T_2896, UInt<1>(0h0)) when _T_2899 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2896, UInt<1>(0h1), "") : assert_198 node _T_2900 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2901 = orr(a_set_wo_ready) node _T_2902 = eq(_T_2901, UInt<1>(0h0)) node _T_2903 = or(_T_2900, _T_2902) node _T_2904 = asUInt(reset) node _T_2905 = eq(_T_2904, UInt<1>(0h0)) when _T_2905 : node _T_2906 = eq(_T_2903, UInt<1>(0h0)) when _T_2906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2903, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_169 node _T_2907 = orr(inflight) node _T_2908 = eq(_T_2907, UInt<1>(0h0)) node _T_2909 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2910 = or(_T_2908, _T_2909) node _T_2911 = lt(watchdog, plusarg_reader.out) node _T_2912 = or(_T_2910, _T_2911) node _T_2913 = asUInt(reset) node _T_2914 = eq(_T_2913, UInt<1>(0h0)) when _T_2914 : node _T_2915 = eq(_T_2912, UInt<1>(0h0)) when _T_2915 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2912, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2916 = and(io.in.a.ready, io.in.a.valid) node _T_2917 = and(io.in.d.ready, io.in.d.valid) node _T_2918 = or(_T_2916, _T_2917) when _T_2918 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<63>, clock, reset, UInt<63>(0h0) regreset inflight_opcodes_1 : UInt<252>, clock, reset, UInt<252>(0h0) regreset inflight_sizes_1 : UInt<252>, clock, reset, UInt<252>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<63> connect c_set, UInt<63>(0h0) wire c_set_wo_ready : UInt<63> connect c_set_wo_ready, UInt<63>(0h0) wire c_opcodes_set : UInt<252> connect c_opcodes_set, UInt<252>(0h0) wire c_sizes_set : UInt<252> connect c_sizes_set, UInt<252>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2919 = and(io.in.c.valid, c_first_1) node _T_2920 = bits(io.in.c.bits.opcode, 2, 2) node _T_2921 = bits(io.in.c.bits.opcode, 1, 1) node _T_2922 = and(_T_2920, _T_2921) node _T_2923 = and(_T_2919, _T_2922) when _T_2923 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2924 = and(io.in.c.ready, io.in.c.valid) node _T_2925 = and(_T_2924, c_first_1) node _T_2926 = bits(io.in.c.bits.opcode, 2, 2) node _T_2927 = bits(io.in.c.bits.opcode, 1, 1) node _T_2928 = and(_T_2926, _T_2927) node _T_2929 = and(_T_2925, _T_2928) when _T_2929 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2930 = dshr(inflight_1, io.in.c.bits.source) node _T_2931 = bits(_T_2930, 0, 0) node _T_2932 = eq(_T_2931, UInt<1>(0h0)) node _T_2933 = asUInt(reset) node _T_2934 = eq(_T_2933, UInt<1>(0h0)) when _T_2934 : node _T_2935 = eq(_T_2932, UInt<1>(0h0)) when _T_2935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2932, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<63> connect d_clr_1, UInt<63>(0h0) wire d_clr_wo_ready_1 : UInt<63> connect d_clr_wo_ready_1, UInt<63>(0h0) wire d_opcodes_clr_1 : UInt<252> connect d_opcodes_clr_1, UInt<252>(0h0) wire d_sizes_clr_1 : UInt<252> connect d_sizes_clr_1, UInt<252>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2936 = and(io.in.d.valid, d_first_2) node _T_2937 = and(_T_2936, UInt<1>(0h1)) node _T_2938 = and(_T_2937, d_release_ack_1) when _T_2938 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2939 = and(io.in.d.ready, io.in.d.valid) node _T_2940 = and(_T_2939, d_first_2) node _T_2941 = and(_T_2940, UInt<1>(0h1)) node _T_2942 = and(_T_2941, d_release_ack_1) when _T_2942 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2943 = and(io.in.d.valid, d_first_2) node _T_2944 = and(_T_2943, UInt<1>(0h1)) node _T_2945 = and(_T_2944, d_release_ack_1) when _T_2945 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2946 = dshr(inflight_1, io.in.d.bits.source) node _T_2947 = bits(_T_2946, 0, 0) node _T_2948 = or(_T_2947, same_cycle_resp_1) node _T_2949 = asUInt(reset) node _T_2950 = eq(_T_2949, UInt<1>(0h0)) when _T_2950 : node _T_2951 = eq(_T_2948, UInt<1>(0h0)) when _T_2951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2948, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2952 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2953 = asUInt(reset) node _T_2954 = eq(_T_2953, UInt<1>(0h0)) when _T_2954 : node _T_2955 = eq(_T_2952, UInt<1>(0h0)) when _T_2955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2952, UInt<1>(0h1), "") : assert_203 else : node _T_2956 = eq(io.in.d.bits.size, c_size_lookup) node _T_2957 = asUInt(reset) node _T_2958 = eq(_T_2957, UInt<1>(0h0)) when _T_2958 : node _T_2959 = eq(_T_2956, UInt<1>(0h0)) when _T_2959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2956, UInt<1>(0h1), "") : assert_204 node _T_2960 = and(io.in.d.valid, d_first_2) node _T_2961 = and(_T_2960, c_first_1) node _T_2962 = and(_T_2961, io.in.c.valid) node _T_2963 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2964 = and(_T_2962, _T_2963) node _T_2965 = and(_T_2964, d_release_ack_1) node _T_2966 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2967 = and(_T_2965, _T_2966) when _T_2967 : node _T_2968 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2969 = or(_T_2968, io.in.c.ready) node _T_2970 = asUInt(reset) node _T_2971 = eq(_T_2970, UInt<1>(0h0)) when _T_2971 : node _T_2972 = eq(_T_2969, UInt<1>(0h0)) when _T_2972 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2969, UInt<1>(0h1), "") : assert_205 node _T_2973 = orr(c_set_wo_ready) when _T_2973 : node _T_2974 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2975 = asUInt(reset) node _T_2976 = eq(_T_2975, UInt<1>(0h0)) when _T_2976 : node _T_2977 = eq(_T_2974, UInt<1>(0h0)) when _T_2977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2974, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_170 node _T_2978 = orr(inflight_1) node _T_2979 = eq(_T_2978, UInt<1>(0h0)) node _T_2980 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2981 = or(_T_2979, _T_2980) node _T_2982 = lt(watchdog_1, plusarg_reader_1.out) node _T_2983 = or(_T_2981, _T_2982) node _T_2984 = asUInt(reset) node _T_2985 = eq(_T_2984, UInt<1>(0h0)) when _T_2985 : node _T_2986 = eq(_T_2983, UInt<1>(0h0)) when _T_2986 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2983, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2987 = and(io.in.c.ready, io.in.c.valid) node _T_2988 = and(io.in.d.ready, io.in.d.valid) node _T_2989 = or(_T_2987, _T_2988) when _T_2989 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2990 = and(io.in.d.ready, io.in.d.valid) node _T_2991 = and(_T_2990, d_first_3) node _T_2992 = bits(io.in.d.bits.opcode, 2, 2) node _T_2993 = bits(io.in.d.bits.opcode, 1, 1) node _T_2994 = eq(_T_2993, UInt<1>(0h0)) node _T_2995 = and(_T_2992, _T_2994) node _T_2996 = and(_T_2991, _T_2995) when _T_2996 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2997 = dshr(inflight_2, io.in.d.bits.sink) node _T_2998 = bits(_T_2997, 0, 0) node _T_2999 = eq(_T_2998, UInt<1>(0h0)) node _T_3000 = asUInt(reset) node _T_3001 = eq(_T_3000, UInt<1>(0h0)) when _T_3001 : node _T_3002 = eq(_T_2999, UInt<1>(0h0)) when _T_3002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2999, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_3003 = and(io.in.e.ready, io.in.e.valid) node _T_3004 = and(_T_3003, UInt<1>(0h1)) node _T_3005 = and(_T_3004, UInt<1>(0h1)) when _T_3005 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_3006 = or(d_set, inflight_2) node _T_3007 = dshr(_T_3006, io.in.e.bits.sink) node _T_3008 = bits(_T_3007, 0, 0) node _T_3009 = asUInt(reset) node _T_3010 = eq(_T_3009, UInt<1>(0h0)) when _T_3010 : node _T_3011 = eq(_T_3008, UInt<1>(0h0)) when _T_3011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_3008, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [62:0] inflight; // @[Monitor.scala:614:27] reg [251:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [251:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [62:0] inflight_1; // @[Monitor.scala:726:35] reg [251:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_80 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_80( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_3 : output auto : { flip rerocc_tile_ctrl_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rerocc_tile_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip rerocc_tile_re_ro_cc_in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, flip rerocc_tile_rerocc_manager_id_sink_in : UInt<7>, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst rerocc_tile of ReRoCCManagerTile_1 connect rerocc_tile.clock, childClock connect rerocc_tile.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect rerocc_tile.auto.rerocc_manager_id_sink_in, auto.rerocc_tile_rerocc_manager_id_sink_in connect rerocc_tile.auto.re_ro_cc_in, auto.rerocc_tile_re_ro_cc_in connect auto.rerocc_tile_buffer_out.e.bits, rerocc_tile.auto.buffer_out.e.bits connect auto.rerocc_tile_buffer_out.e.valid, rerocc_tile.auto.buffer_out.e.valid connect rerocc_tile.auto.buffer_out.e.ready, auto.rerocc_tile_buffer_out.e.ready connect rerocc_tile.auto.buffer_out.d, auto.rerocc_tile_buffer_out.d connect auto.rerocc_tile_buffer_out.c.bits, rerocc_tile.auto.buffer_out.c.bits connect auto.rerocc_tile_buffer_out.c.valid, rerocc_tile.auto.buffer_out.c.valid connect rerocc_tile.auto.buffer_out.c.ready, auto.rerocc_tile_buffer_out.c.ready connect rerocc_tile.auto.buffer_out.b, auto.rerocc_tile_buffer_out.b connect auto.rerocc_tile_buffer_out.a.bits, rerocc_tile.auto.buffer_out.a.bits connect auto.rerocc_tile_buffer_out.a.valid, rerocc_tile.auto.buffer_out.a.valid connect rerocc_tile.auto.buffer_out.a.ready, auto.rerocc_tile_buffer_out.a.ready connect rerocc_tile.auto.ctrl_ctrl_in, auto.rerocc_tile_ctrl_ctrl_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset

module ClockSinkDomain_3( // @[ClockDomain.scala:14:9] output auto_rerocc_tile_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_rerocc_tile_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_rerocc_tile_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire auto_rerocc_tile_ctrl_ctrl_in_a_valid_0 = auto_rerocc_tile_ctrl_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_ready_0 = auto_rerocc_tile_ctrl_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_ready_0 = auto_rerocc_tile_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_valid_0 = auto_rerocc_tile_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode_0 = auto_rerocc_tile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_b_bits_param_0 = auto_rerocc_tile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_b_bits_size_0 = auto_rerocc_tile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_source_0 = auto_rerocc_tile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_b_bits_address_0 = auto_rerocc_tile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_b_bits_mask_0 = auto_rerocc_tile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_b_bits_data_0 = auto_rerocc_tile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_corrupt_0 = auto_rerocc_tile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_ready_0 = auto_rerocc_tile_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_valid_0 = auto_rerocc_tile_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode_0 = auto_rerocc_tile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_d_bits_param_0 = auto_rerocc_tile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_d_bits_size_0 = auto_rerocc_tile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_source_0 = auto_rerocc_tile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_sink_0 = auto_rerocc_tile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_denied_0 = auto_rerocc_tile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_d_bits_data_0 = auto_rerocc_tile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_corrupt_0 = auto_rerocc_tile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_ready_0 = auto_rerocc_tile_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_valid_0 = auto_rerocc_tile_re_ro_cc_in_req_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_opcode; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_client_id; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_ready_0 = auto_rerocc_tile_re_ro_cc_in_resp_ready; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in_0 = auto_rerocc_tile_rerocc_manager_id_sink_in; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] ReRoCCManagerTile_1 rerocc_tile ( // @[Integration.scala:45:54] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrl_ctrl_in_a_ready (auto_rerocc_tile_ctrl_ctrl_in_a_ready_0), .auto_ctrl_ctrl_in_a_valid (auto_rerocc_tile_ctrl_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_param (auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_size (auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_source (auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_address (auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_mask (auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_data (auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_corrupt (auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_ready (auto_rerocc_tile_ctrl_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_valid (auto_rerocc_tile_ctrl_ctrl_in_d_valid_0), .auto_ctrl_ctrl_in_d_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0), .auto_ctrl_ctrl_in_d_bits_size (auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0), .auto_ctrl_ctrl_in_d_bits_source (auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0), .auto_ctrl_ctrl_in_d_bits_data (auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0), .auto_buffer_out_a_ready (auto_rerocc_tile_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_rerocc_tile_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_rerocc_tile_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_rerocc_tile_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_rerocc_tile_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_rerocc_tile_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_rerocc_tile_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_rerocc_tile_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_rerocc_tile_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_rerocc_tile_buffer_out_a_bits_corrupt_0), .auto_buffer_out_b_ready (auto_rerocc_tile_buffer_out_b_ready_0), .auto_buffer_out_b_valid (auto_rerocc_tile_buffer_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (auto_rerocc_tile_buffer_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (auto_rerocc_tile_buffer_out_b_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (auto_rerocc_tile_buffer_out_b_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (auto_rerocc_tile_buffer_out_b_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (auto_rerocc_tile_buffer_out_b_bits_address_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (auto_rerocc_tile_buffer_out_b_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (auto_rerocc_tile_buffer_out_b_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (auto_rerocc_tile_buffer_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (auto_rerocc_tile_buffer_out_c_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (auto_rerocc_tile_buffer_out_c_valid_0), .auto_buffer_out_c_bits_opcode (auto_rerocc_tile_buffer_out_c_bits_opcode_0), .auto_buffer_out_c_bits_param (auto_rerocc_tile_buffer_out_c_bits_param_0), .auto_buffer_out_c_bits_size (auto_rerocc_tile_buffer_out_c_bits_size_0), .auto_buffer_out_c_bits_source (auto_rerocc_tile_buffer_out_c_bits_source_0), .auto_buffer_out_c_bits_address (auto_rerocc_tile_buffer_out_c_bits_address_0), .auto_buffer_out_c_bits_data (auto_rerocc_tile_buffer_out_c_bits_data_0), .auto_buffer_out_c_bits_corrupt (auto_rerocc_tile_buffer_out_c_bits_corrupt_0), .auto_buffer_out_d_ready (auto_rerocc_tile_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_rerocc_tile_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_rerocc_tile_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (auto_rerocc_tile_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_rerocc_tile_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_rerocc_tile_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (auto_rerocc_tile_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (auto_rerocc_tile_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_rerocc_tile_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (auto_rerocc_tile_buffer_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (auto_rerocc_tile_buffer_out_e_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (auto_rerocc_tile_buffer_out_e_valid_0), .auto_buffer_out_e_bits_sink (auto_rerocc_tile_buffer_out_e_bits_sink_0), .auto_re_ro_cc_in_req_ready (auto_rerocc_tile_re_ro_cc_in_req_ready_0), .auto_re_ro_cc_in_req_valid (auto_rerocc_tile_re_ro_cc_in_req_valid_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_opcode (auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_client_id (auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_data (auto_rerocc_tile_re_ro_cc_in_req_bits_data_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_ready (auto_rerocc_tile_re_ro_cc_in_resp_ready_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_valid (auto_rerocc_tile_re_ro_cc_in_resp_valid_0), .auto_re_ro_cc_in_resp_bits_opcode (auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0), .auto_re_ro_cc_in_resp_bits_client_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0), .auto_re_ro_cc_in_resp_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0), .auto_re_ro_cc_in_resp_bits_data (auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0), .auto_rerocc_manager_id_sink_in (auto_rerocc_tile_rerocc_manager_id_sink_in_0) // @[ClockDomain.scala:14:9] ); // @[Integration.scala:45:54] assign auto_rerocc_tile_ctrl_ctrl_in_a_ready = auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_valid = auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode = auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_size = auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_source = auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_data = auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_valid = auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_opcode = auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_param = auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_size = auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_source = auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_address = auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_mask = auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_data = auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_corrupt = auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_b_ready = auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_valid = auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_opcode = auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_param = auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_size = auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_source = auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_address = auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_data = auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_corrupt = auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_d_ready = auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_valid = auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_bits_sink = auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_req_ready = auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_valid = auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode = auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_data = auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_20 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_276 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_20( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_276 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_79 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_79( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DTLB_4 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}, flip kill : UInt<1>} node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_70 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_4 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.prv, mpu_priv inst pma of PMAChecker_5 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<18>(0h20000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<15>(0h4000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<18>(0h24000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<13>(0h1000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<13>(0h1000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<17>(0h10000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_51 = cvt(_homogeneous_T_50) node _homogeneous_T_52 = and(_homogeneous_T_51, asSInt(UInt<13>(0h1000))) node _homogeneous_T_53 = asSInt(_homogeneous_T_52) node _homogeneous_T_54 = eq(_homogeneous_T_53, asSInt(UInt<1>(0h0))) node _homogeneous_T_55 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_56 = cvt(_homogeneous_T_55) node _homogeneous_T_57 = and(_homogeneous_T_56, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_58 = asSInt(_homogeneous_T_57) node _homogeneous_T_59 = eq(_homogeneous_T_58, asSInt(UInt<1>(0h0))) node _homogeneous_T_60 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_61 = or(_homogeneous_T_60, _homogeneous_T_9) node _homogeneous_T_62 = or(_homogeneous_T_61, _homogeneous_T_14) node _homogeneous_T_63 = or(_homogeneous_T_62, _homogeneous_T_19) node _homogeneous_T_64 = or(_homogeneous_T_63, _homogeneous_T_24) node _homogeneous_T_65 = or(_homogeneous_T_64, _homogeneous_T_29) node _homogeneous_T_66 = or(_homogeneous_T_65, _homogeneous_T_34) node _homogeneous_T_67 = or(_homogeneous_T_66, _homogeneous_T_39) node _homogeneous_T_68 = or(_homogeneous_T_67, _homogeneous_T_44) node _homogeneous_T_69 = or(_homogeneous_T_68, _homogeneous_T_49) node _homogeneous_T_70 = or(_homogeneous_T_69, _homogeneous_T_54) node homogeneous = or(_homogeneous_T_70, _homogeneous_T_59) node _homogeneous_T_71 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = or(UInt<1>(0h0), _homogeneous_T_76) node _homogeneous_T_78 = eq(_homogeneous_T_77, UInt<1>(0h0)) node _homogeneous_T_79 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_80 = cvt(_homogeneous_T_79) node _homogeneous_T_81 = and(_homogeneous_T_80, asSInt(UInt<33>(0hffff3000))) node _homogeneous_T_82 = asSInt(_homogeneous_T_81) node _homogeneous_T_83 = eq(_homogeneous_T_82, asSInt(UInt<1>(0h0))) node _homogeneous_T_84 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_85 = cvt(_homogeneous_T_84) node _homogeneous_T_86 = and(_homogeneous_T_85, asSInt(UInt<33>(0hffff3000))) node _homogeneous_T_87 = asSInt(_homogeneous_T_86) node _homogeneous_T_88 = eq(_homogeneous_T_87, asSInt(UInt<1>(0h0))) node _homogeneous_T_89 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_90 = cvt(_homogeneous_T_89) node _homogeneous_T_91 = and(_homogeneous_T_90, asSInt(UInt<33>(0hffff0000))) node _homogeneous_T_92 = asSInt(_homogeneous_T_91) node _homogeneous_T_93 = eq(_homogeneous_T_92, asSInt(UInt<1>(0h0))) node _homogeneous_T_94 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_95 = cvt(_homogeneous_T_94) node _homogeneous_T_96 = and(_homogeneous_T_95, asSInt(UInt<33>(0hffff0000))) node _homogeneous_T_97 = asSInt(_homogeneous_T_96) node _homogeneous_T_98 = eq(_homogeneous_T_97, asSInt(UInt<1>(0h0))) node _homogeneous_T_99 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_100 = cvt(_homogeneous_T_99) node _homogeneous_T_101 = and(_homogeneous_T_100, asSInt(UInt<33>(0hf0000000))) node _homogeneous_T_102 = asSInt(_homogeneous_T_101) node _homogeneous_T_103 = eq(_homogeneous_T_102, asSInt(UInt<1>(0h0))) node _homogeneous_T_104 = or(UInt<1>(0h0), _homogeneous_T_83) node _homogeneous_T_105 = or(_homogeneous_T_104, _homogeneous_T_88) node _homogeneous_T_106 = or(_homogeneous_T_105, _homogeneous_T_93) node _homogeneous_T_107 = or(_homogeneous_T_106, _homogeneous_T_98) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_103) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8e020000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_115 = cvt(_homogeneous_T_114) node _homogeneous_T_116 = and(_homogeneous_T_115, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_117 = asSInt(_homogeneous_T_116) node _homogeneous_T_118 = eq(_homogeneous_T_117, asSInt(UInt<1>(0h0))) node _homogeneous_T_119 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_120 = or(_homogeneous_T_119, _homogeneous_T_118) node _homogeneous_T_121 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_122 = cvt(_homogeneous_T_121) node _homogeneous_T_123 = and(_homogeneous_T_122, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_124 = asSInt(_homogeneous_T_123) node _homogeneous_T_125 = eq(_homogeneous_T_124, asSInt(UInt<1>(0h0))) node _homogeneous_T_126 = or(UInt<1>(0h0), _homogeneous_T_125) node _homogeneous_T_127 = eq(_homogeneous_T_126, UInt<1>(0h0)) node _homogeneous_T_128 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_129 = cvt(_homogeneous_T_128) node _homogeneous_T_130 = and(_homogeneous_T_129, asSInt(UInt<33>(0h8a130000))) node _homogeneous_T_131 = asSInt(_homogeneous_T_130) node _homogeneous_T_132 = eq(_homogeneous_T_131, asSInt(UInt<1>(0h0))) node _homogeneous_T_133 = or(UInt<1>(0h0), _homogeneous_T_132) node _homogeneous_T_134 = eq(_homogeneous_T_133, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_71 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_72 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_73 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_74 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_75 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_76 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_77 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_78 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_79 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_80 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_81 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_82 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_83 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, UInt<1>(0h0)) node pal_array_if_cached = or(pal_array, UInt<1>(0h0)) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h0), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h0), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h0), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)

module DTLB_4( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input io_req_bits_passthrough, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_st, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_st, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_ma_st, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_must_alloc, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] output [1:0] io_resp_size, // @[TLB.scala:320:14] output [4:0] io_resp_cmd, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [15:0] io_ptw_ptbr_asid, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [15:0] io_ptw_ptbr_asid_0 = io_ptw_ptbr_asid; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _homogeneous_T_71 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire _io_req_ready_T; // @[TLB.scala:631:25] wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [15:0] satp_asid = io_ptw_ptbr_asid_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_st_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_st_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_ma_st_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_must_alloc_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64] wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_79 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T = do_refill | io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_60 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_84; // @[Parameters.scala:137:31] assign _homogeneous_T_84 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_89; // @[Parameters.scala:137:31] assign _homogeneous_T_89 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_121; // @[Parameters.scala:137:31] assign _homogeneous_T_121 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_128; // @[Parameters.scala:137:31] assign _homogeneous_T_128 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h20000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFFC000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h24000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_30 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_40; // @[Parameters.scala:137:31] assign _homogeneous_T_40 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_94; // @[Parameters.scala:137:31] assign _homogeneous_T_94 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_45 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_50 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_51 = {1'h0, _homogeneous_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_52 = _homogeneous_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_53 = _homogeneous_T_52; // @[Parameters.scala:137:46] wire _homogeneous_T_54 = _homogeneous_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_55; // @[Parameters.scala:137:31] assign _homogeneous_T_55 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_99; // @[Parameters.scala:137:31] assign _homogeneous_T_99 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_114; // @[Parameters.scala:137:31] assign _homogeneous_T_114 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_56 = {1'h0, _homogeneous_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_57 = _homogeneous_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_58 = _homogeneous_T_57; // @[Parameters.scala:137:46] wire _homogeneous_T_59 = _homogeneous_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_61 = _homogeneous_T_60 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_62 = _homogeneous_T_61 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_63 = _homogeneous_T_62 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_64 = _homogeneous_T_63 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_65 = _homogeneous_T_64 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_66 = _homogeneous_T_65 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_67 = _homogeneous_T_66 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_68 = _homogeneous_T_67 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_69 = _homogeneous_T_68 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_70 = _homogeneous_T_69 | _homogeneous_T_54; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_70 | _homogeneous_T_59; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_77 = _homogeneous_T_76; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_78 = ~_homogeneous_T_77; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_80 = {1'h0, _homogeneous_T_79}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_81 = _homogeneous_T_80 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_82 = _homogeneous_T_81; // @[Parameters.scala:137:46] wire _homogeneous_T_83 = _homogeneous_T_82 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_104 = _homogeneous_T_83; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_85 = {1'h0, _homogeneous_T_84}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_86 = _homogeneous_T_85 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_87 = _homogeneous_T_86; // @[Parameters.scala:137:46] wire _homogeneous_T_88 = _homogeneous_T_87 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_90 = {1'h0, _homogeneous_T_89}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_91 = _homogeneous_T_90 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_92 = _homogeneous_T_91; // @[Parameters.scala:137:46] wire _homogeneous_T_93 = _homogeneous_T_92 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_95 = {1'h0, _homogeneous_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_96 = _homogeneous_T_95 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_97 = _homogeneous_T_96; // @[Parameters.scala:137:46] wire _homogeneous_T_98 = _homogeneous_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_100 = {1'h0, _homogeneous_T_99}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_101 = _homogeneous_T_100 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_102 = _homogeneous_T_101; // @[Parameters.scala:137:46] wire _homogeneous_T_103 = _homogeneous_T_102 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_105 = _homogeneous_T_104 | _homogeneous_T_88; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_106 = _homogeneous_T_105 | _homogeneous_T_93; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_107 = _homogeneous_T_106 | _homogeneous_T_98; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_103; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8E020000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_119 = _homogeneous_T_113; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_115 = {1'h0, _homogeneous_T_114}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_116 = _homogeneous_T_115 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_117 = _homogeneous_T_116; // @[Parameters.scala:137:46] wire _homogeneous_T_118 = _homogeneous_T_117 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_120 = _homogeneous_T_119 | _homogeneous_T_118; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_122 = {1'h0, _homogeneous_T_121}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_123 = _homogeneous_T_122 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_124 = _homogeneous_T_123; // @[Parameters.scala:137:46] wire _homogeneous_T_125 = _homogeneous_T_124 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_126 = _homogeneous_T_125; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_127 = ~_homogeneous_T_126; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_129 = {1'h0, _homogeneous_T_128}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_130 = _homogeneous_T_129 & 41'h8A130000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_131 = _homogeneous_T_130; // @[Parameters.scala:137:46] wire _homogeneous_T_132 = _homogeneous_T_131 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_133 = _homogeneous_T_132; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_134 = ~_homogeneous_T_133; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1; // @[TLB.scala:429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1; // @[TLB.scala:430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1; // @[TLB.scala:434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [13:0] paa_array_if_cached = paa_array; // @[TLB.scala:541:22, :545:39] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pal_array_if_cached = pal_array; // @[TLB.scala:543:22, :546:39] wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47] wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5; // @[TLB.scala:588:53, :589:53] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] ae_st_array = _ae_st_array_T_8; // @[TLB.scala:589:53, :590:53] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1; // @[TLB.scala:593:{8,43}] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4; // @[TLB.scala:593:43, :594:43] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] must_alloc_array = _must_alloc_array_T_7; // @[TLB.scala:594:43, :595:46] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_32 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg

module AsyncResetRegVec_w1_i0_32( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h1)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h8)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 4) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<4>(0h8)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_13 node _source_ok_T_14 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_15 = or(_source_ok_T_14, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_15, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h1)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h8)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_25 = shr(io.in.a.bits.source, 4) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<4>(0h8)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _T_38 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = or(_T_39, _T_44) node _T_46 = and(_T_16, _T_24) node _T_47 = and(_T_46, _T_37) node _T_48 = and(_T_47, _T_45) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_48, UInt<1>(0h1), "") : assert_1 node _T_52 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_52 : node _T_53 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_54 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_55 = and(_T_53, _T_54) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_56 = shr(io.in.a.bits.source, 4) node _T_57 = eq(_T_56, UInt<1>(0h1)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_2) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_2, UInt<4>(0h8)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_63 = shr(io.in.a.bits.source, 4) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = leq(UInt<1>(0h0), uncommonBits_3) node _T_66 = and(_T_64, _T_65) node _T_67 = leq(uncommonBits_3, UInt<4>(0h8)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_70 = or(_T_61, _T_62) node _T_71 = or(_T_70, _T_68) node _T_72 = or(_T_71, _T_69) node _T_73 = and(_T_55, _T_72) node _T_74 = or(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<13>(0h1000))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_82 = cvt(_T_81) node _T_83 = and(_T_82, asSInt(UInt<18>(0h2f000))) node _T_84 = asSInt(_T_83) node _T_85 = eq(_T_84, asSInt(UInt<1>(0h0))) node _T_86 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<13>(0h1000))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = or(_T_80, _T_85) node _T_92 = or(_T_91, _T_90) node _T_93 = and(_T_75, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = and(_T_74, _T_94) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_95, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_99 = shr(io.in.a.bits.source, 4) node _T_100 = eq(_T_99, UInt<1>(0h1)) node _T_101 = leq(UInt<1>(0h0), uncommonBits_4) node _T_102 = and(_T_100, _T_101) node _T_103 = leq(uncommonBits_4, UInt<4>(0h8)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_106 = shr(io.in.a.bits.source, 4) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = leq(UInt<1>(0h0), uncommonBits_5) node _T_109 = and(_T_107, _T_108) node _T_110 = leq(uncommonBits_5, UInt<4>(0h8)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE : UInt<1>[4] connect _WIRE[0], _T_104 connect _WIRE[1], _T_105 connect _WIRE[2], _T_111 connect _WIRE[3], _T_112 node _T_113 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_114 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_115 = mux(_WIRE[0], _T_113, UInt<1>(0h0)) node _T_116 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_117 = mux(_WIRE[2], _T_114, UInt<1>(0h0)) node _T_118 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = or(_T_115, _T_116) node _T_120 = or(_T_119, _T_117) node _T_121 = or(_T_120, _T_118) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<18>(0h2f000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<13>(0h1000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = or(_T_130, _T_135) node _T_142 = or(_T_141, _T_140) node _T_143 = and(_T_125, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = and(_WIRE_1, _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_145, UInt<1>(0h1), "") : assert_3 node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(source_ok, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_152 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_152, UInt<1>(0h1), "") : assert_5 node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(is_aligned, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_159 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_159, UInt<1>(0h1), "") : assert_7 node _T_163 = not(io.in.a.bits.mask) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_164, UInt<1>(0h1), "") : assert_8 node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_168, UInt<1>(0h1), "") : assert_9 node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_172 : node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_176 = shr(io.in.a.bits.source, 4) node _T_177 = eq(_T_176, UInt<1>(0h1)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_6) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_6, UInt<4>(0h8)) node _T_181 = and(_T_179, _T_180) node _T_182 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_183 = shr(io.in.a.bits.source, 4) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = leq(UInt<1>(0h0), uncommonBits_7) node _T_186 = and(_T_184, _T_185) node _T_187 = leq(uncommonBits_7, UInt<4>(0h8)) node _T_188 = and(_T_186, _T_187) node _T_189 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_190 = or(_T_181, _T_182) node _T_191 = or(_T_190, _T_188) node _T_192 = or(_T_191, _T_189) node _T_193 = and(_T_175, _T_192) node _T_194 = or(UInt<1>(0h0), _T_193) node _T_195 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<18>(0h2f000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<13>(0h1000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = or(_T_200, _T_205) node _T_212 = or(_T_211, _T_210) node _T_213 = and(_T_195, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_194, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_215, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_219 = shr(io.in.a.bits.source, 4) node _T_220 = eq(_T_219, UInt<1>(0h1)) node _T_221 = leq(UInt<1>(0h0), uncommonBits_8) node _T_222 = and(_T_220, _T_221) node _T_223 = leq(uncommonBits_8, UInt<4>(0h8)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_226 = shr(io.in.a.bits.source, 4) node _T_227 = eq(_T_226, UInt<1>(0h0)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_9) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_9, UInt<4>(0h8)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], _T_224 connect _WIRE_2[1], _T_225 connect _WIRE_2[2], _T_231 connect _WIRE_2[3], _T_232 node _T_233 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_234 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_235 = mux(_WIRE_2[0], _T_233, UInt<1>(0h0)) node _T_236 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE_2[2], _T_234, UInt<1>(0h0)) node _T_238 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = or(_T_235, _T_236) node _T_240 = or(_T_239, _T_237) node _T_241 = or(_T_240, _T_238) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_241 node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<18>(0h2f000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_250, _T_255) node _T_262 = or(_T_261, _T_260) node _T_263 = and(_T_245, _T_262) node _T_264 = or(UInt<1>(0h0), _T_263) node _T_265 = and(_WIRE_3, _T_264) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_265, UInt<1>(0h1), "") : assert_11 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(source_ok, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_272 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_272, UInt<1>(0h1), "") : assert_13 node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(is_aligned, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_279 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_280 = asUInt(reset) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(_T_279, UInt<1>(0h0)) when _T_282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_279, UInt<1>(0h1), "") : assert_15 node _T_283 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_284 = asUInt(reset) node _T_285 = eq(_T_284, UInt<1>(0h0)) when _T_285 : node _T_286 = eq(_T_283, UInt<1>(0h0)) when _T_286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_283, UInt<1>(0h1), "") : assert_16 node _T_287 = not(io.in.a.bits.mask) node _T_288 = eq(_T_287, UInt<1>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_288, UInt<1>(0h1), "") : assert_17 node _T_292 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_292, UInt<1>(0h1), "") : assert_18 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_300 = shr(io.in.a.bits.source, 4) node _T_301 = eq(_T_300, UInt<1>(0h1)) node _T_302 = leq(UInt<1>(0h0), uncommonBits_10) node _T_303 = and(_T_301, _T_302) node _T_304 = leq(uncommonBits_10, UInt<4>(0h8)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_307 = shr(io.in.a.bits.source, 4) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_11) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_11, UInt<4>(0h8)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_314 = or(_T_305, _T_306) node _T_315 = or(_T_314, _T_312) node _T_316 = or(_T_315, _T_313) node _T_317 = and(_T_299, _T_316) node _T_318 = or(UInt<1>(0h0), _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_318, UInt<1>(0h1), "") : assert_19 node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = and(_T_325, _T_330) node _T_332 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_333 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_334 = and(_T_332, _T_333) node _T_335 = or(UInt<1>(0h0), _T_334) node _T_336 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<18>(0h2f000))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<13>(0h1000))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = or(_T_340, _T_345) node _T_347 = and(_T_335, _T_346) node _T_348 = or(UInt<1>(0h0), _T_331) node _T_349 = or(_T_348, _T_347) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_349, UInt<1>(0h1), "") : assert_20 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(source_ok, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(is_aligned, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_359 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_359, UInt<1>(0h1), "") : assert_23 node _T_363 = eq(io.in.a.bits.mask, mask) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_363, UInt<1>(0h1), "") : assert_24 node _T_367 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_367, UInt<1>(0h1), "") : assert_25 node _T_371 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_371 : node _T_372 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_373 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_374 = and(_T_372, _T_373) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_375 = shr(io.in.a.bits.source, 4) node _T_376 = eq(_T_375, UInt<1>(0h1)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_12) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_12, UInt<4>(0h8)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_382 = shr(io.in.a.bits.source, 4) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_13) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_13, UInt<4>(0h8)) node _T_387 = and(_T_385, _T_386) node _T_388 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_389 = or(_T_380, _T_381) node _T_390 = or(_T_389, _T_387) node _T_391 = or(_T_390, _T_388) node _T_392 = and(_T_374, _T_391) node _T_393 = or(UInt<1>(0h0), _T_392) node _T_394 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_395 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_396 = and(_T_394, _T_395) node _T_397 = or(UInt<1>(0h0), _T_396) node _T_398 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_399 = cvt(_T_398) node _T_400 = and(_T_399, asSInt(UInt<13>(0h1000))) node _T_401 = asSInt(_T_400) node _T_402 = eq(_T_401, asSInt(UInt<1>(0h0))) node _T_403 = and(_T_397, _T_402) node _T_404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_405 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_406 = and(_T_404, _T_405) node _T_407 = or(UInt<1>(0h0), _T_406) node _T_408 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_409 = cvt(_T_408) node _T_410 = and(_T_409, asSInt(UInt<18>(0h2f000))) node _T_411 = asSInt(_T_410) node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0))) node _T_413 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_414 = cvt(_T_413) node _T_415 = and(_T_414, asSInt(UInt<13>(0h1000))) node _T_416 = asSInt(_T_415) node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0))) node _T_418 = or(_T_412, _T_417) node _T_419 = and(_T_407, _T_418) node _T_420 = or(UInt<1>(0h0), _T_403) node _T_421 = or(_T_420, _T_419) node _T_422 = and(_T_393, _T_421) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_422, UInt<1>(0h1), "") : assert_26 node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(source_ok, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(is_aligned, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_432 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_432, UInt<1>(0h1), "") : assert_29 node _T_436 = eq(io.in.a.bits.mask, mask) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_436, UInt<1>(0h1), "") : assert_30 node _T_440 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_440 : node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_444 = shr(io.in.a.bits.source, 4) node _T_445 = eq(_T_444, UInt<1>(0h1)) node _T_446 = leq(UInt<1>(0h0), uncommonBits_14) node _T_447 = and(_T_445, _T_446) node _T_448 = leq(uncommonBits_14, UInt<4>(0h8)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_451 = shr(io.in.a.bits.source, 4) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = leq(UInt<1>(0h0), uncommonBits_15) node _T_454 = and(_T_452, _T_453) node _T_455 = leq(uncommonBits_15, UInt<4>(0h8)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_458 = or(_T_449, _T_450) node _T_459 = or(_T_458, _T_456) node _T_460 = or(_T_459, _T_457) node _T_461 = and(_T_443, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<18>(0h2f000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<13>(0h1000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = or(_T_481, _T_486) node _T_488 = and(_T_476, _T_487) node _T_489 = or(UInt<1>(0h0), _T_472) node _T_490 = or(_T_489, _T_488) node _T_491 = and(_T_462, _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_491, UInt<1>(0h1), "") : assert_31 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(source_ok, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(is_aligned, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_501 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_501, UInt<1>(0h1), "") : assert_34 node _T_505 = not(mask) node _T_506 = and(io.in.a.bits.mask, _T_505) node _T_507 = eq(_T_506, UInt<1>(0h0)) node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_T_507, UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_507, UInt<1>(0h1), "") : assert_35 node _T_511 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_511 : node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_515 = shr(io.in.a.bits.source, 4) node _T_516 = eq(_T_515, UInt<1>(0h1)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_16) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_16, UInt<4>(0h8)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_522 = shr(io.in.a.bits.source, 4) node _T_523 = eq(_T_522, UInt<1>(0h0)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_17) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_17, UInt<4>(0h8)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_529 = or(_T_520, _T_521) node _T_530 = or(_T_529, _T_527) node _T_531 = or(_T_530, _T_528) node _T_532 = and(_T_514, _T_531) node _T_533 = or(UInt<1>(0h0), _T_532) node _T_534 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_535 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_536 = and(_T_534, _T_535) node _T_537 = or(UInt<1>(0h0), _T_536) node _T_538 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_539 = cvt(_T_538) node _T_540 = and(_T_539, asSInt(UInt<13>(0h1000))) node _T_541 = asSInt(_T_540) node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0))) node _T_543 = and(_T_537, _T_542) node _T_544 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_546 = cvt(_T_545) node _T_547 = and(_T_546, asSInt(UInt<18>(0h2f000))) node _T_548 = asSInt(_T_547) node _T_549 = eq(_T_548, asSInt(UInt<1>(0h0))) node _T_550 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_551 = cvt(_T_550) node _T_552 = and(_T_551, asSInt(UInt<13>(0h1000))) node _T_553 = asSInt(_T_552) node _T_554 = eq(_T_553, asSInt(UInt<1>(0h0))) node _T_555 = or(_T_549, _T_554) node _T_556 = and(_T_544, _T_555) node _T_557 = or(UInt<1>(0h0), _T_543) node _T_558 = or(_T_557, _T_556) node _T_559 = and(_T_533, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_559, UInt<1>(0h1), "") : assert_36 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_569 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_569, UInt<1>(0h1), "") : assert_39 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_573, UInt<1>(0h1), "") : assert_40 node _T_577 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_577 : node _T_578 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_579 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 3, 0) node _T_581 = shr(io.in.a.bits.source, 4) node _T_582 = eq(_T_581, UInt<1>(0h1)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_18) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_18, UInt<4>(0h8)) node _T_586 = and(_T_584, _T_585) node _T_587 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 3, 0) node _T_588 = shr(io.in.a.bits.source, 4) node _T_589 = eq(_T_588, UInt<1>(0h0)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_19) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_19, UInt<4>(0h8)) node _T_593 = and(_T_591, _T_592) node _T_594 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_595 = or(_T_586, _T_587) node _T_596 = or(_T_595, _T_593) node _T_597 = or(_T_596, _T_594) node _T_598 = and(_T_580, _T_597) node _T_599 = or(UInt<1>(0h0), _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = and(_T_603, _T_608) node _T_610 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_611 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_612 = cvt(_T_611) node _T_613 = and(_T_612, asSInt(UInt<18>(0h2f000))) node _T_614 = asSInt(_T_613) node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0))) node _T_616 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<13>(0h1000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = or(_T_615, _T_620) node _T_622 = and(_T_610, _T_621) node _T_623 = or(UInt<1>(0h0), _T_609) node _T_624 = or(_T_623, _T_622) node _T_625 = and(_T_599, _T_624) node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(_T_625, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_625, UInt<1>(0h1), "") : assert_41 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(source_ok, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(is_aligned, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_635 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_635, UInt<1>(0h1), "") : assert_44 node _T_639 = eq(io.in.a.bits.mask, mask) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_639, UInt<1>(0h1), "") : assert_45 node _T_643 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_643 : node _T_644 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_645 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_646 = and(_T_644, _T_645) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 3, 0) node _T_647 = shr(io.in.a.bits.source, 4) node _T_648 = eq(_T_647, UInt<1>(0h1)) node _T_649 = leq(UInt<1>(0h0), uncommonBits_20) node _T_650 = and(_T_648, _T_649) node _T_651 = leq(uncommonBits_20, UInt<4>(0h8)) node _T_652 = and(_T_650, _T_651) node _T_653 = eq(io.in.a.bits.source, UInt<5>(0h19)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 3, 0) node _T_654 = shr(io.in.a.bits.source, 4) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_21) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_21, UInt<4>(0h8)) node _T_659 = and(_T_657, _T_658) node _T_660 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_661 = or(_T_652, _T_653) node _T_662 = or(_T_661, _T_659) node _T_663 = or(_T_662, _T_660) node _T_664 = and(_T_646, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<13>(0h1000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = and(_T_669, _T_674) node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<18>(0h2f000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_683 = cvt(_T_682) node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000))) node _T_685 = asSInt(_T_684) node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0))) node _T_687 = or(_T_681, _T_686) node _T_688 = and(_T_676, _T_687) node _T_689 = or(UInt<1>(0h0), _T_675) node _T_690 = or(_T_689, _T_688) node _T_691 = and(_T_665, _T_690) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_691, UInt<1>(0h1), "") : assert_46 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(source_ok, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(is_aligned, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_701 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_701, UInt<1>(0h1), "") : assert_49 node _T_705 = eq(io.in.a.bits.mask, mask) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_705, UInt<1>(0h1), "") : assert_50 node _T_709 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_709, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_713 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_713, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_16 = shr(io.in.d.bits.source, 4) node _source_ok_T_17 = eq(_source_ok_T_16, UInt<1>(0h1)) node _source_ok_T_18 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = leq(source_ok_uncommonBits_2, UInt<4>(0h8)) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = eq(io.in.d.bits.source, UInt<5>(0h19)) node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0) node _source_ok_T_23 = shr(io.in.d.bits.source, 4) node _source_ok_T_24 = eq(_source_ok_T_23, UInt<1>(0h0)) node _source_ok_T_25 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_26 = and(_source_ok_T_24, _source_ok_T_25) node _source_ok_T_27 = leq(source_ok_uncommonBits_3, UInt<4>(0h8)) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = eq(io.in.d.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_21 connect _source_ok_WIRE_1[1], _source_ok_T_22 connect _source_ok_WIRE_1[2], _source_ok_T_28 connect _source_ok_WIRE_1[3], _source_ok_T_29 node _source_ok_T_30 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_31, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_717 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_717 : node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(source_ok_1, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_721 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_721, UInt<1>(0h1), "") : assert_54 node _T_725 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_725, UInt<1>(0h1), "") : assert_55 node _T_729 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_729, UInt<1>(0h1), "") : assert_56 node _T_733 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_734 = asUInt(reset) node _T_735 = eq(_T_734, UInt<1>(0h0)) when _T_735 : node _T_736 = eq(_T_733, UInt<1>(0h0)) when _T_736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_733, UInt<1>(0h1), "") : assert_57 node _T_737 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_737 : node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(source_ok_1, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(sink_ok, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_744 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_744, UInt<1>(0h1), "") : assert_60 node _T_748 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_748, UInt<1>(0h1), "") : assert_61 node _T_752 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(_T_752, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_752, UInt<1>(0h1), "") : assert_62 node _T_756 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(_T_756, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_756, UInt<1>(0h1), "") : assert_63 node _T_760 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_761 = or(UInt<1>(0h1), _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_761, UInt<1>(0h1), "") : assert_64 node _T_765 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_765 : node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(source_ok_1, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(sink_ok, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_772 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_772, UInt<1>(0h1), "") : assert_67 node _T_776 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(_T_776, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_776, UInt<1>(0h1), "") : assert_68 node _T_780 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_780, UInt<1>(0h1), "") : assert_69 node _T_784 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_785 = or(_T_784, io.in.d.bits.corrupt) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_785, UInt<1>(0h1), "") : assert_70 node _T_789 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_790 = or(UInt<1>(0h1), _T_789) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_790, UInt<1>(0h1), "") : assert_71 node _T_794 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_794 : node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(source_ok_1, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_798 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_798, UInt<1>(0h1), "") : assert_73 node _T_802 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_802, UInt<1>(0h1), "") : assert_74 node _T_806 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_807 = or(UInt<1>(0h1), _T_806) node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(_T_807, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_807, UInt<1>(0h1), "") : assert_75 node _T_811 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_811 : node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(source_ok_1, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_815 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(_T_815, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_815, UInt<1>(0h1), "") : assert_77 node _T_819 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_820 = or(_T_819, io.in.d.bits.corrupt) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_820, UInt<1>(0h1), "") : assert_78 node _T_824 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_825 = or(UInt<1>(0h1), _T_824) node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_T_825, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_825, UInt<1>(0h1), "") : assert_79 node _T_829 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_829 : node _T_830 = asUInt(reset) node _T_831 = eq(_T_830, UInt<1>(0h0)) when _T_831 : node _T_832 = eq(source_ok_1, UInt<1>(0h0)) when _T_832 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_833 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(_T_833, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_833, UInt<1>(0h1), "") : assert_81 node _T_837 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_837, UInt<1>(0h1), "") : assert_82 node _T_841 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_842 = or(UInt<1>(0h1), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_842, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_846 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_846, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_850 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_850, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_854 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_854, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_858 = eq(a_first, UInt<1>(0h0)) node _T_859 = and(io.in.a.valid, _T_858) when _T_859 : node _T_860 = eq(io.in.a.bits.opcode, opcode) node _T_861 = asUInt(reset) node _T_862 = eq(_T_861, UInt<1>(0h0)) when _T_862 : node _T_863 = eq(_T_860, UInt<1>(0h0)) when _T_863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_860, UInt<1>(0h1), "") : assert_87 node _T_864 = eq(io.in.a.bits.param, param) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_864, UInt<1>(0h1), "") : assert_88 node _T_868 = eq(io.in.a.bits.size, size) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_868, UInt<1>(0h1), "") : assert_89 node _T_872 = eq(io.in.a.bits.source, source) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_872, UInt<1>(0h1), "") : assert_90 node _T_876 = eq(io.in.a.bits.address, address) node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(_T_876, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_876, UInt<1>(0h1), "") : assert_91 node _T_880 = and(io.in.a.ready, io.in.a.valid) node _T_881 = and(_T_880, a_first) when _T_881 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_882 = eq(d_first, UInt<1>(0h0)) node _T_883 = and(io.in.d.valid, _T_882) when _T_883 : node _T_884 = eq(io.in.d.bits.opcode, opcode_1) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_884, UInt<1>(0h1), "") : assert_92 node _T_888 = eq(io.in.d.bits.param, param_1) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_888, UInt<1>(0h1), "") : assert_93 node _T_892 = eq(io.in.d.bits.size, size_1) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_892, UInt<1>(0h1), "") : assert_94 node _T_896 = eq(io.in.d.bits.source, source_1) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_896, UInt<1>(0h1), "") : assert_95 node _T_900 = eq(io.in.d.bits.sink, sink) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_900, UInt<1>(0h1), "") : assert_96 node _T_904 = eq(io.in.d.bits.denied, denied) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_904, UInt<1>(0h1), "") : assert_97 node _T_908 = and(io.in.d.ready, io.in.d.valid) node _T_909 = and(_T_908, d_first) when _T_909 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<26>, clock, reset, UInt<26>(0h0) regreset inflight_opcodes : UInt<104>, clock, reset, UInt<104>(0h0) regreset inflight_sizes : UInt<208>, clock, reset, UInt<208>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<26> connect a_set, UInt<26>(0h0) wire a_set_wo_ready : UInt<26> connect a_set_wo_ready, UInt<26>(0h0) wire a_opcodes_set : UInt<104> connect a_opcodes_set, UInt<104>(0h0) wire a_sizes_set : UInt<208> connect a_sizes_set, UInt<208>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_910 = and(io.in.a.valid, a_first_1) node _T_911 = and(_T_910, UInt<1>(0h1)) when _T_911 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_912 = and(io.in.a.ready, io.in.a.valid) node _T_913 = and(_T_912, a_first_1) node _T_914 = and(_T_913, UInt<1>(0h1)) when _T_914 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_915 = dshr(inflight, io.in.a.bits.source) node _T_916 = bits(_T_915, 0, 0) node _T_917 = eq(_T_916, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_917, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<26> connect d_clr, UInt<26>(0h0) wire d_clr_wo_ready : UInt<26> connect d_clr_wo_ready, UInt<26>(0h0) wire d_opcodes_clr : UInt<104> connect d_opcodes_clr, UInt<104>(0h0) wire d_sizes_clr : UInt<208> connect d_sizes_clr, UInt<208>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_921 = and(io.in.d.valid, d_first_1) node _T_922 = and(_T_921, UInt<1>(0h1)) node _T_923 = eq(d_release_ack, UInt<1>(0h0)) node _T_924 = and(_T_922, _T_923) when _T_924 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_925 = and(io.in.d.ready, io.in.d.valid) node _T_926 = and(_T_925, d_first_1) node _T_927 = and(_T_926, UInt<1>(0h1)) node _T_928 = eq(d_release_ack, UInt<1>(0h0)) node _T_929 = and(_T_927, _T_928) when _T_929 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_930 = and(io.in.d.valid, d_first_1) node _T_931 = and(_T_930, UInt<1>(0h1)) node _T_932 = eq(d_release_ack, UInt<1>(0h0)) node _T_933 = and(_T_931, _T_932) when _T_933 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_934 = dshr(inflight, io.in.d.bits.source) node _T_935 = bits(_T_934, 0, 0) node _T_936 = or(_T_935, same_cycle_resp) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_936, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_940 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_941 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_942 = or(_T_940, _T_941) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_942, UInt<1>(0h1), "") : assert_100 node _T_946 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_946, UInt<1>(0h1), "") : assert_101 else : node _T_950 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_951 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_952 = or(_T_950, _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_952, UInt<1>(0h1), "") : assert_102 node _T_956 = eq(io.in.d.bits.size, a_size_lookup) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_956, UInt<1>(0h1), "") : assert_103 node _T_960 = and(io.in.d.valid, d_first_1) node _T_961 = and(_T_960, a_first_1) node _T_962 = and(_T_961, io.in.a.valid) node _T_963 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_964 = and(_T_962, _T_963) node _T_965 = eq(d_release_ack, UInt<1>(0h0)) node _T_966 = and(_T_964, _T_965) when _T_966 : node _T_967 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_968 = or(_T_967, io.in.a.ready) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_968, UInt<1>(0h1), "") : assert_104 node _T_972 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_973 = orr(a_set_wo_ready) node _T_974 = eq(_T_973, UInt<1>(0h0)) node _T_975 = or(_T_972, _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_975, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_979 = orr(inflight) node _T_980 = eq(_T_979, UInt<1>(0h0)) node _T_981 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_982 = or(_T_980, _T_981) node _T_983 = lt(watchdog, plusarg_reader.out) node _T_984 = or(_T_982, _T_983) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_984, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_988 = and(io.in.a.ready, io.in.a.valid) node _T_989 = and(io.in.d.ready, io.in.d.valid) node _T_990 = or(_T_988, _T_989) when _T_990 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<26>, clock, reset, UInt<26>(0h0) regreset inflight_opcodes_1 : UInt<104>, clock, reset, UInt<104>(0h0) regreset inflight_sizes_1 : UInt<208>, clock, reset, UInt<208>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<26> connect c_set, UInt<26>(0h0) wire c_set_wo_ready : UInt<26> connect c_set_wo_ready, UInt<26>(0h0) wire c_opcodes_set : UInt<104> connect c_opcodes_set, UInt<104>(0h0) wire c_sizes_set : UInt<208> connect c_sizes_set, UInt<208>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_991 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_992 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_993 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_994 = and(_T_992, _T_993) node _T_995 = and(_T_991, _T_994) when _T_995 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_996 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_997 = and(_T_996, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_998 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_999 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1000 = and(_T_998, _T_999) node _T_1001 = and(_T_997, _T_1000) when _T_1001 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1002 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1003 = bits(_T_1002, 0, 0) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<26> connect d_clr_1, UInt<26>(0h0) wire d_clr_wo_ready_1 : UInt<26> connect d_clr_wo_ready_1, UInt<26>(0h0) wire d_opcodes_clr_1 : UInt<104> connect d_opcodes_clr_1, UInt<104>(0h0) wire d_sizes_clr_1 : UInt<208> connect d_sizes_clr_1, UInt<208>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1008 = and(io.in.d.valid, d_first_2) node _T_1009 = and(_T_1008, UInt<1>(0h1)) node _T_1010 = and(_T_1009, d_release_ack_1) when _T_1010 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1011 = and(io.in.d.ready, io.in.d.valid) node _T_1012 = and(_T_1011, d_first_2) node _T_1013 = and(_T_1012, UInt<1>(0h1)) node _T_1014 = and(_T_1013, d_release_ack_1) when _T_1014 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1015 = and(io.in.d.valid, d_first_2) node _T_1016 = and(_T_1015, UInt<1>(0h1)) node _T_1017 = and(_T_1016, d_release_ack_1) when _T_1017 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1018 = dshr(inflight_1, io.in.d.bits.source) node _T_1019 = bits(_T_1018, 0, 0) node _T_1020 = or(_T_1019, same_cycle_resp_1) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1024 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_109 else : node _T_1028 = eq(io.in.d.bits.size, c_size_lookup) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_110 node _T_1032 = and(io.in.d.valid, d_first_2) node _T_1033 = and(_T_1032, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1034 = and(_T_1033, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1035 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = and(_T_1036, d_release_ack_1) node _T_1038 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1039 = and(_T_1037, _T_1038) when _T_1039 : node _T_1040 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<5>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1041 = or(_T_1040, _WIRE_27.ready) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_111 node _T_1045 = orr(c_set_wo_ready) when _T_1045 : node _T_1046 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1050 = orr(inflight_1) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) node _T_1052 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1053 = or(_T_1051, _T_1052) node _T_1054 = lt(watchdog_1, plusarg_reader_1.out) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<5>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1059 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1060 = and(io.in.d.ready, io.in.d.valid) node _T_1061 = or(_T_1059, _T_1060) when _T_1061 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_18 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_25 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] c_set = 26'h0; // @[Monitor.scala:738:34] wire [25:0] c_set_wo_ready = 26'h0; // @[Monitor.scala:739:34] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [207:0] c_sizes_set = 208'h0; // @[Monitor.scala:741:34] wire [103:0] c_opcodes_set = 104'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_7 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 5'h19; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = ~_source_ok_T_7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_10 & _source_ok_T_11; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_a_bits_source_0 == 5'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_3 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire _source_ok_T_14 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_15 = _source_ok_T_14 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_15 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_16 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_23 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_19 = _source_ok_T_17; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_20 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_21 = _source_ok_T_19 & _source_ok_T_20; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_21; // @[Parameters.scala:1138:31] wire _source_ok_T_22 = io_in_d_bits_source_0 == 5'h19; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_22; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_24 = ~_source_ok_T_23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_26 = _source_ok_T_24; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_27 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_28 = _source_ok_T_26 & _source_ok_T_27; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_2 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_d_bits_source_0 == 5'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_3 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_31 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_988 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_988; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_988; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_1061 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1061; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1061; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1061; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [25:0] inflight; // @[Monitor.scala:614:27] reg [103:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [207:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [25:0] a_set; // @[Monitor.scala:626:34] wire [25:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [103:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [207:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [103:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [103:0] _a_opcode_lookup_T_6 = {100'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [103:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [207:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [207:0] _a_size_lookup_T_6 = {200'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [207:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[207:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_914 = _T_988 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_914 ? _a_set_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_914 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_914 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_914 ? _a_opcodes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_914 ? _a_sizes_set_T_1[207:0] : 208'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [25:0] d_clr; // @[Monitor.scala:664:34] wire [25:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [103:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [207:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_960 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_960 & ~d_release_ack ? _d_clr_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_929 = _T_1061 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_929 ? _d_clr_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_929 ? _d_opcodes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_929 ? _d_sizes_clr_T_5[207:0] : 208'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [25:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [25:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [25:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [103:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [103:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [103:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [207:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [207:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [207:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [25:0] inflight_1; // @[Monitor.scala:726:35] wire [25:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [103:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [103:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [207:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [207:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [103:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [103:0] _c_opcode_lookup_T_6 = {100'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [103:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [207:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [207:0] _c_size_lookup_T_6 = {200'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [207:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[207:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [25:0] d_clr_1; // @[Monitor.scala:774:34] wire [25:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [103:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [207:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1032 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1032 & d_release_ack_1 ? _d_clr_wo_ready_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_1014 = _T_1061 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1014 ? _d_clr_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1014 ? _d_opcodes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1014 ? _d_sizes_clr_T_11[207:0] : 208'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [25:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [25:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [103:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [103:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [207:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [207:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MSHR_62 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_62( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_57 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_117 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_118 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]